A method, system, electronic device and storage medium for efficiently simplifying digital logic circuits based on deep learning

Abstract

The application discloses a kind of based on deep learning's efficient simplified digital logic circuit method, system, electronic equipment and storage medium, comprising: constructing logic synthesis dataset, the logic synthesis dataset includes training set and test set, input data in the logic synthesis dataset is the circuit of RTL verilog description;Logic synthesis environment is constructed to input data is preprocessed, and efficient simplified digital logic circuit model based on deep learning is constructed;Efficient simplified digital logic circuit model based on deep learning is trained using the circuit of preprocessed training set, until efficient simplified digital logic circuit model converges;Using the efficient simplified digital logic circuit model based on deep learning that is trained, and logic optimization is carried out on test set, to test the logic optimization capability of efficient simplified digital logic circuit model.The application can efficiently optimize circuit, and its effect is better than the method of traditional node-by-node application single optimization algorithm.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic design automation, and particularly relates to a method and system for efficiently simplifying a digital logic circuit based on deep learning, an electronic device and a storage medium. BACKGROUND

[0002] With the continuous expansion of the design scale of modern very large scale integrated circuits, logic synthesis as a key step in the electronic design automation (EDA) process has an important influence on chip performance and resource utilization. The main goal of logic synthesis is to convert the RTL (Register Transfer Level) level description of the circuit into a gate level netlist and optimize its area, power consumption and timing performance. Logic synthesis usually includes three stages of translation, logic optimization and mapping, wherein the logic optimization stage simplifies the logic representation of the circuit to reduce the circuit size and optimize its performance.

[0003] In the logic optimization process, the optimization algorithms (such as rewriting, replacement, etc.) in the open source tool ABC are usually used to optimize the circuit node by node to achieve the purpose of simplifying the logic of the circuit. However, the use of a single algorithm for each node usually leads to a local optimal situation of the circuit, which ultimately affects the performance of the circuit, so it is important to select a suitable optimization algorithm for each node, but it is a difficult problem to select which algorithm to optimize the nodes in the circuit. SUMMARY

[0004] The purpose of the present application is to provide a method and system for efficiently simplifying a digital logic circuit based on deep learning, an electronic device and a storage medium to solve one or more technical problems existing in the prior art and at least provide a beneficial choice or create conditions.

[0005] The present application adopts the following technical solutions to achieve the above-mentioned application purposes:

[0006] The present application provides a method for efficiently simplifying a digital logic circuit based on deep learning, comprising:

[0007] Constructing a logic synthesis data set, wherein the logic synthesis data set includes a training set and a test set, and the input data in the logic synthesis data set is a circuit described in RTL verilog;

[0008] Construct a logic synthesis environment and an action space, and preprocess input data, construct an efficient simplified digital logic circuit model based on deep learning, the efficient simplified digital logic circuit model includes a circuit feature extraction module and an action selection module, the circuit feature extraction module is used to learn the complete structure and local structure of the circuit, and the complete structure feature and the local structure feature after learning are spliced to generate the mixed structure feature of the circuit, the action selection module selects a suitable optimization algorithm for analyzing the mixed structure feature of the circuit;

[0009] Train the efficient simplified digital logic circuit model based on deep learning using the preprocessed training set until the efficient simplified digital logic circuit model converges;

[0010] Use the trained efficient simplified digital logic circuit model based on deep learning, and perform logic optimization on the test set to test the logic optimization capability of the efficient simplified digital logic circuit model.

[0011] Further, the logic synthesis environment and the action space are constructed, and the input data is preprocessed, including:

[0012] The logic synthesis environment is constructed by using an open source logic synthesis tool ABC, and the circuit described by verilog is converted into an AIG format circuit;

[0013] A directed acyclic graph is constructed according to the AIG format circuit As The initial graph structure of the circuit, wherein is a set of nodes, including logical and gate nodes and logical not gate nodes; is a set of edges, wherein each edge represents the directed connection of the corresponding two nodes;

[0014] The action space is constructed, three logic circuit optimization algorithms including rewriting, replacing and extracting are selected in the synthesis tool ABC, and skip is used to represent that the current node does not perform any optimization action, the action space includes skip, rewriting, replacing and extracting, each action is recorded as numbers 0~3, representing the four actions respectively.

[0015] Further, wherein the circuit feature extraction module is composed of a GraphSAGE graph neural network, including a first SAGE layer, a first ReLU layer, a second SAGE layer, a second ReLU layer and a third SAGE layer;

[0016] The local structure feature is the fan-in cone of the node to be optimized, the fan-in cone is the set of paths passed by all input signals of the node, including the entire circuit structure from the input end of the logic unit to all possible standard inputs;

[0017] The input of the first SAGE layer adopts an initial circuit structure feature, the input of the second SAGE layer adopts the result output by the first ReLU layer, and the third SAGE layer adopts the result output by the second ReLU layer.

[0018] The first SAGE layer, the second SAGE layer and the third SAGE layer aggregate the sampled neighbor node features into a vector through a neighbor sampling and an aggregation function, and then combine the vector with the own feature to update the own node feature.

[0019] Further, the neighbor sampling and the aggregation function are used to aggregate the sampled neighbor node features into a vector, and then the vector is combined with the own feature to update the own node feature, including:

[0020] sampling a fixed number of neighbor nodes from a neighbor set of a node , using an aggregation function to aggregate the features of the sampled neighbors:

[0021] ;

[0022] wherein, the number of the fixed number of neighbor nodes sampled is , denotes the feature of the node , denotes the final result of neighbor aggregation, and AGGREGATE is an aggregation function that concatenates the feature of the node itself with the aggregated neighbor features , and transforms and nonlinearly activates the features through a learnable weight matrix:

[0023] ;

[0024] wherein, denotes the updated feature vector of the node , is a nonlinear activation function, is a feature transformation weight matrix, denotes a concatenation operation.

[0025] Further, the action selection module includes a first linear layer, a first ReLU layer, a second linear layer, a second ReLU layer and a third linear layer.

[0026] ​The hybrid structural features are input into the action selection module, and are sequentially processed by the first linear layer for dimension mapping, the first ReLU layer for activation, the second linear layer for further extraction of abstract features, the second ReLU layer for reactivation, and finally the third linear layer outputs an action probability vector, which corresponds to the selection probability of four actions.

[0027] The vector with a selection probability of 1*4 has a sum of probabilities of 100% for all actions.

[0028] Each time, the action corresponding to the maximum value among the four probabilities is selected as the optimization action of that node. The four probabilities are numbered 0, 1, 2, and 3 respectively, where 0 means that the node does not use any optimization algorithm, and 1, 2, and 3 mean that the node uses rewriting, replacement, and extraction algorithms for logical optimization respectively.

[0029] Furthermore, the circuits on the preprocessed training set are used to train a deep learning-based efficient simplified digital logic circuit model until the efficient simplified digital logic circuit model converges, including:

[0030] S1, Select a circuit from the circuits in the training set and read it into the logic synthesis environment;

[0031] S2, starting from the input node of the circuit, efficiently simplifies the digital logic circuit model each time the global structure of the input circuit and the local structure of the node are obtained, and outputs the optimized action of the node.

[0032] S3 calculates the corresponding loss by using a loss function to obtain the optimized action selected from the efficient simplified digital logic circuit model and the optimal optimized action, and then updates the efficient simplified digital logic circuit model.

[0033] S4: Repeat steps S2-S3 until the efficient simplified digital logic circuit model has been trained to complete all nodes of the circuit. This completes one round of training.

[0034] S5: Restore this circuit to its original state, and repeat steps S2-S4 until the efficient simplified digital logic circuit model converges on this circuit.

[0035] S6: Repeat steps S1-S5 until the efficient simplified digital logic circuit model has been trained and converged on all circuits in the training set, thus obtaining the trained efficient simplified digital logic circuit model.

[0036] Furthermore, the loss function is the cross-entropy loss, expressed as follows:

[0037] ;

[0038] in, Indicates the optimal action number at this node. One-hot encoding, This represents the loss function value corresponding to the selected action at this node. This represents the probability of the action of that node as output by deep learning. Represents probability The logarithm of .

[0039] This application provides a system for efficiently simplifying digital logic circuits based on deep learning, comprising:

[0040] The first construction unit is used to construct a logic synthesis dataset, which includes a training set and a test set. The input data in the logic synthesis dataset is a circuit described by RTL Verilog.

[0041] The second construction unit is used to construct a logic synthesis environment and action space, and to preprocess the input data to construct an efficient simplified digital logic circuit model based on deep learning. The efficient simplified digital logic circuit model includes a circuit feature extraction module and an action selection module. The circuit feature extraction module is used to learn the complete structure and local structure of the circuit, and to use the learned complete structure features and local structure features to splice together the mixed structure features of the circuit. The action selection module selects an appropriate optimization algorithm to analyze the mixed structure features of the circuit.

[0042] The training unit is used to train a deep learning-based efficient simplified digital logic circuit model using circuits from a preprocessed training set until the efficient simplified digital logic circuit model converges.

[0043] The test unit is used to utilize a trained, deep learning-based, efficient simplified digital logic circuit model and perform logic optimization on a test set to test the logic optimization capability of the efficient simplified digital logic circuit model.

[0044] This application provides an electronic device, including a memory and a processor;

[0045] The memory is used to store instructions;

[0046] The processor is configured to operate according to the instructions to perform the steps according to the method described above.

[0047] This application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method.

[0048] The beneficial effects of this application are as follows:

[0049] The circuit feature extraction module of this application analyzes the complete and local structures of logic circuits to generate hybrid circuit structure features. This improves the ability of the deep learning-based efficient simplified digital logic circuit model to understand different regions of the circuit. By utilizing the hybrid circuit structure features, the deep learning-based efficient simplified digital logic circuit model can intelligently guide the selection of the optimal optimization strategy for each local structure of the circuit. Through training until convergence, the final deep learning-based efficient simplified digital logic circuit model can efficiently optimize the circuit, and its performance is better than the traditional method of applying a single optimization algorithm node by node. Attached Figure Description

[0050] Figure 1 This is an overall flowchart of a method for efficiently simplifying digital logic circuits based on deep learning, according to an embodiment of this application.

[0051] Figure 2 This is a diagram of a deep learning-based efficient simplified digital logic circuit model in a method for efficiently simplifying digital logic circuits based on deep learning, provided according to an embodiment of this application.

[0052] Figure 3 This is a circuit feature extraction module diagram in a method for efficiently simplifying digital logic circuits based on deep learning, provided according to an embodiment of this application.

[0053] Figure 4 This is a schematic diagram of the circuit, complete AIG structure, and partial AIG structure transformation in a method for efficiently simplifying digital logic circuits based on deep learning, according to an embodiment of this application.

[0054] Figure 5 This is a diagram of the action selection module in a method for efficiently simplifying digital logic circuits based on deep learning, according to an embodiment of this application. Detailed Implementation

[0055] Deep learning (DL) has been introduced into logic synthesis optimization to automatically learn hierarchical feature representations of data, thereby providing optimization guidance for complex circuits. The core advantage of deep learning lies in its ability to automatically learn complex and deep-level correlations and patterns between circuit structure, logic function, and their optimal optimization strategies from massive amounts of circuit data. Using a well-trained, efficient, and simplified digital logic circuit model based on deep learning, it can quickly recommend strategies that are most likely to bring global performance improvements to each node in the specific circuit to be optimized. This approach aims to overcome the bottleneck of "local optima" in traditional methods, making more coordinated and forward-looking optimization decisions for different nodes through the model's "understanding" of the overall circuit state and comprehensive evaluation of optimization effects. The ultimate goal is to significantly improve the overall performance of chips in key indicators such as area, power consumption, and timing through this data-driven intelligent optimization guidance, thus driving the advancement of logic synthesis technology.

[0056] The circuit feature extraction module of this application employs a GraphSAGE graph neural network to simultaneously analyze the complete and local structures of the logic circuit, generating hybrid circuit structure features. This improves the ability of the efficient and simplified digital logic circuit model based on deep learning to understand different regions of the circuit. Utilizing these hybrid circuit structure features, the model can intelligently guide the selection of the optimal optimization strategy for each local circuit structure. Through training until convergence, the final model can efficiently optimize the circuit, outperforming traditional methods that apply a single optimization algorithm node-by-node.

[0057] Example 1

[0058] like Figure 1 As shown, this application provides a method for efficiently simplifying digital logic circuits based on deep learning, which specifically includes the following steps:

[0059] S100: Construct a logic synthesis dataset, which includes a training set and a test set. The input data in the logic synthesis dataset is a circuit described by RTL Verilog.

[0060] Specifically, S100 is:

[0061] A logic synthesis dataset is constructed by pre-dividing the circuits into two groups, a training set and a test set, in a 7:3 ratio. The training set circuits are used to train the model, and the test set circuits serve as new circuits to test the effect of model optimization. The dataset contains input data, which are circuits described by RTL Verilog.

[0062] S200: Constructs a logic synthesis environment and action space, preprocesses input data, and builds an efficient and simplified digital logic circuit model based on deep learning;

[0063] Specifically, S200 is:

[0064] S201: Construct the logic synthesis environment and action space, and preprocess the input data;

[0065] A logic synthesis environment was built using the open-source logic synthesis tool ABC, and the circuit described in Verilog was converted into an AIG (And-Inverter Graph) format circuit. The circuit described in AIG was then read into the logic synthesis tool ABC to obtain the initial graph structure of the AIG circuit.

[0066] Construct a directed acyclic graph based on the AIG format circuit. As The initial circuit diagram structure, in which It is a collection of nodes, each node has corresponding node attributes, including node type, number of fan-in gates, and number of NOT gates; Let be the set of edges, where each edge represents a directed connection between two corresponding nodes;

[0067] The node type is numbered 0, 1, and 2, where 0 represents a standard input node, 1 represents a logical AND gate node, and 2 represents a standard output node; the number of fan-in inputs refers to the number of inputs to the node; and the number of NOT gates refers to the number of NOT gates in the node's inputs.

[0068] Construct the action space; select three commonly used logic circuit optimization algorithms in the synthesis tool ABC, namely rewrite, resub, and refactor, and use skip to indicate that the current node does not perform any optimization action; the action space is {skip, rewrite, substitute, refactor}, and each action is numbered 0~3 to represent these four actions respectively.

[0069] S202: Construct a model for efficient and simplified digital logic circuits based on deep learning;

[0070] The efficient and simplified digital logic circuit model based on deep learning is as follows: Figure 2 It includes a circuit feature extraction module and an action selection module;

[0071] The circuit feature extraction module, such as Figure 3 As shown, it consists of a GraphSAGE (Graph Sample and Aggregate) graph neural network;

[0072] Preferably, the GraphSAGE network input is the local structure and global structure of the circuit, and the two structural features are spliced ​​together after neural network processing to form the hybrid structural features of the circuit. Specifically, it includes a first SAGE layer, a first ReLU (Rectified Linear Unit) layer, a second SAGE layer, a second ReLU layer, and a third SAGE layer.

[0073] The schematic diagrams of the local and global structures of the circuit are as follows: Figure 4 .in Figure 4 In the diagram, 'a' represents the original circuit. Figure 4 In the diagram, 'b' represents the AIG representation of the circuit, i.e., the global structure. Figure 4 In this circuit, c represents the fan-in cone of a certain node, i.e., the local structure.

[0074] The fan-in cone of a node refers to the set of paths traversed by all input signals of that node. It includes the entire circuit structure starting from the input of the logic unit and tracing downwards to all possible standard inputs.

[0075] The first, second, and third SAGE layers all use neighbor sampling and aggregation functions to aggregate the sampled neighbor node features into a vector, which is then combined with the model's own features to update its own node features. The only structural difference between the three SAGE layers is the input and output dimensions. Furthermore, the first SAGE layer uses the mean aggregation function, allowing the model to stably fuse neighbor information, effectively capturing local neighborhood structures and improving the model's generalization ability. The mathematical description is as follows:

[0076] First, starting from the nodes Neighbor set A fixed number of neighboring nodes are sampled. Then, use an aggregation function to aggregate the features of the sampled neighbors:

[0077]

[0078] Here, a fixed number of neighboring nodes are sampled. The number is , Represents a node Features This represents the final result of neighbor aggregation; AGGREGATE is the aggregation function. Then, the nodes... Its own characteristics Features of aggregated neighbors The components are concatenated and transformed using a learnable weight matrix, followed by nonlinear activation.

[0079] ;

[0080] in, Represents a node Updated feature vectors It is a non-linear activation function. It is the feature transformation weight matrix. This indicates a splicing operation; the input of the first GraphSAGE layer uses the initial circuit structure features, the input of the second GraphSAGE layer uses the output of the first ReLU layer, and the input of the third GraphSAGE layer uses the output of the second ReLU layer.

[0081] The action selection module is as follows: Figure 5 As shown, it consists of linear layers;

[0082] Preferably, the action selection module is used to analyze the hybrid structure features of the circuit and select a suitable optimization algorithm, specifically including a first linear layer, a first ReLU layer, a second linear layer, a second ReLU layer, and a third linear layer. The hybrid structure features are input into the action selection module, and are sequentially processed by the first linear layer for dimension mapping, the first ReLU layer for activation, the second linear layer for further extraction of abstract features, the second ReLU layer for reactivation, and finally the third linear layer outputs an action probability vector, which corresponds to the selection probability of four actions.

[0083] Based on the hybrid structure characteristics of the circuit, the selection probability of different optimization algorithms is derived from the model of efficient simplified digital logic circuit based on deep learning. The optimization algorithm refers to one of the three optimization algorithms mentioned above: rewriting, replacement, and extraction.

[0084] The selection probability is a 1*4 vector with a total sum of 1, meaning the sum of the probabilities of all actions is 100%. Each time, the action corresponding to the maximum value among the four probabilities is selected as the optimized action for that node. The four probabilities are numbered 0, 1, 2, and 3, respectively, corresponding to the four types of actions in the aforementioned action space.

[0085] S300: Train a deep learning-based efficient simplified digital logic circuit model using the preprocessed training set of circuits until the efficient simplified digital logic circuit model converges.

[0086] Specifically, S300 is:

[0087] S301: Select a circuit from the training set and read it into the logic synthesis environment;

[0088] S302: Starting from the input node of the circuit, the model of the efficient simplified digital logic circuit based on deep learning is used to input the global structure of the circuit and the local structure of the node at each time, and output the optimized action of the node.

[0089] S303: Calculate the corresponding loss by combining the optimized action selected by the model with the optimal optimized action using the loss function, and then update the model accordingly;

[0090] The optimal optimization action is obtained by the following method: performing one of four optimization actions on the node in sequence. After each action is completed, the quality of the circuit is immediately judged according to the circuit evaluation criteria. After comparing the effects of all optimization actions, the action with the best optimization result is taken as the best optimization action.

[0091] The evaluation criteria for the circuit refer to the number of nodes and layers of the logic circuit;

[0092] The loss function is the cross-entropy loss, and its specific calculation expression is as follows:

[0093] ;

[0094] in, Indicates the optimal action number at this node. One-hot encoding (one-hot vector), This represents the loss function value corresponding to the selected action at this node. This represents the probability of the action of that node as output by deep learning. Represents probability The logarithm of ;

[0095] S304: Repeat steps S302-S303 until the model has trained all nodes of the circuit. This is considered as one round of training completed.

[0096] S305: Restore this circuit to its original state, and repeat steps S302-S304 until the model converges on this circuit;

[0097] S306: Repeat steps S301-S305 until the model has been trained and converged on all circuits in the training set, and the trained model is obtained.

[0098] S400: Utilizes a trained, high-efficiency simplified digital logic circuit model based on deep learning, and performs logic optimization on a test set to test the logic optimization capability of the high-efficiency simplified digital logic circuit model.

[0099] Example 2

[0100] This application provides a system for efficiently simplifying digital logic circuits based on deep learning, comprising:

[0101] The first construction unit is used to construct a logic synthesis dataset, which includes a training set and a test set. The input data in the logic synthesis dataset is a circuit described by RTL Verilog.

[0102] The second construction unit is used to construct a logic synthesis environment and action space, and to preprocess the input data to construct an efficient simplified digital logic circuit model based on deep learning. The efficient simplified digital logic circuit model includes a circuit feature extraction module and an action selection module. The circuit feature extraction module is used to learn the complete structure and local structure of the circuit, and to use the learned complete structure features and local structure features to splice together the mixed structure features of the circuit. The action selection module selects an appropriate optimization algorithm to analyze the mixed structure features of the circuit.

[0103] The training unit is used to train a deep learning-based efficient simplified digital logic circuit model using circuits from a preprocessed training set until the efficient simplified digital logic circuit model converges.

[0104] The test unit is used to utilize a trained, deep learning-based, efficient simplified digital logic circuit model and perform logic optimization on a test set to test the logic optimization capability of the efficient simplified digital logic circuit model.

[0105] Example 3

[0106] This application also provides an electronic device that may include a memory and a processor; the memory is used to store instructions.

[0107] The processor is configured to operate according to the instructions to execute the steps of the aforementioned method for efficiently simplifying digital logic circuits based on deep learning.

[0108] Example 4

[0109] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the aforementioned method for efficiently simplifying digital logic circuits based on deep learning.

[0110] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0111] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0112] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0113] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0114] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A method for efficiently simplifying digital logic circuits based on deep learning, characterized in that, include: Construct a logic synthesis dataset, which includes a training set and a test set. The input data in the logic synthesis dataset is a circuit described by RTL Verilog. A logic synthesis environment and action space are constructed, and the input data is preprocessed to construct an efficient simplified digital logic circuit model based on deep learning. The efficient simplified digital logic circuit model includes a circuit feature extraction module and an action selection module. The circuit feature extraction module is used to learn the complete structure and local structure of the circuit, and uses the learned complete structure features and local structure features to splice together the mixed structure features of the circuit. The action selection module selects an appropriate optimization algorithm to analyze the mixed structure features of the circuit. The circuits of the preprocessed training set are used to train an efficient simplified digital logic circuit model based on deep learning until the efficient simplified digital logic circuit model converges. We used a well-trained, high-efficiency simplified digital logic circuit model based on deep learning and performed logic optimization on a test set to test the logic optimization capability of the high-efficiency simplified digital logic circuit model. The circuit feature extraction module is composed of a GraphSAGE graph neural network, and the input of the GraphSAGE graph neural network is the local structure and global structure of the circuit; The local structural feature is the fan-in cone of the node to be optimized. The fan-in cone is the set of paths traversed by all input signals of the node, including the entire circuit structure starting from the input of the logic unit and tracing down to all possible standard inputs. The GraphSAGE graph neural network includes a first SAGE layer, a first ReLU layer, a second SAGE layer, a second ReLU layer, and a third SAGE layer; The input of the first SAGE layer adopts the initial circuit structure features, the input of the second SAGE layer adopts the output of the first ReLU layer, and the input of the third SAGE layer adopts the output of the second ReLU layer. The first SAGE layer, the second SAGE layer, and the third SAGE layer use neighbor sampling and aggregation functions to aggregate the sampled neighbor node features into a vector, and then combine it with their own features to update their own node features.

2. The method for efficiently simplifying digital logic circuits based on deep learning according to claim 1, characterized in that, Construct a logic synthesis environment and action space, and preprocess the input data, including: A logic synthesis environment was built using the open-source logic synthesis tool ABC, and the circuit described in Verilog was converted into an AIG format circuit. Construct a directed acyclic graph based on the AIG format circuit. As the initial diagram structure of the AIG circuit, in which It is a set of nodes, including logical AND gate nodes and logical NOT gate nodes; Let be the set of edges, where each edge represents a directed connection between two corresponding nodes; Construct an action space, select three logic circuit optimization algorithms in the synthesis tool ABC, including rewrite, replacement and extraction, and use skip to indicate that the current node does not perform any optimization action. The action space includes skip, rewrite, replacement and extraction, and each action is numbered 0 to 3 to represent these four actions respectively.

3. The method for efficiently simplifying digital logic circuits based on deep learning according to claim 2, characterized in that, By using neighbor sampling and aggregation functions, the sampled neighbor node features are aggregated into a vector, which is then combined with the node's own features to update the node's own features, including: From node Neighbor set A fixed number of neighboring nodes are sampled. Aggregate the features of sampled neighbors using aggregation functions: Here, a fixed number of neighboring nodes are sampled. The number is , Represents a node Features This represents the final result of neighbor aggregation. AGGREGATE is the aggregation function that aggregates nodes... Its own characteristics Features of aggregated neighbors The components are concatenated and transformed using a learnable weight matrix, followed by nonlinear activation. in, Represents a node Updated feature vectors It is a non-linear activation function. It is the feature transformation weight matrix, and CONCAT represents the concatenation operation.

4. The method for efficiently simplifying digital logic circuits based on deep learning according to claim 2, characterized in that, in, The action selection module includes a first linear layer, a first ReLU layer, a second linear layer, a second ReLU layer, and a third linear layer; The hybrid structural features are input into the action selection module, and are sequentially processed by the first linear layer for dimension mapping, the first ReLU layer for activation, the second linear layer for further extraction of abstract features, the second ReLU layer for reactivation, and finally the third linear layer outputs an action probability vector, which corresponds to the selection probability of four actions. The vector with a selection probability of 1*4 has a sum of probabilities of 100% for all actions. Each time, the action corresponding to the maximum value among the four probabilities is selected as the optimization action of that node. The four probabilities are numbered 0, 1, 2, and 3 respectively, where 0 means that the node does not use any optimization algorithm, and 1, 2, and 3 mean that the node uses rewriting, replacement, and extraction algorithms for logical optimization respectively.

5. The method for efficiently simplifying digital logic circuits based on deep learning according to claim 1, characterized in that, Train a deep learning-based efficient simplified digital logic circuit model using the preprocessed training set until the efficient simplified digital logic circuit model converges, including: S1, Select a circuit from the circuits in the training set and read it into the logic synthesis environment; S2, starting from the input node of the circuit, efficiently simplifies the digital logic circuit model each time the global structure of the input circuit and the local structure of the node are obtained, and outputs the optimized action of the node. S3 calculates the corresponding loss by using a loss function to obtain the optimized action selected from the efficient simplified digital logic circuit model and the optimal optimized action, and then updates the efficient simplified digital logic circuit model. S4: Repeat steps S2-S3 until the efficient simplified digital logic circuit model has been trained to complete all nodes of the circuit. This completes one round of training. S5: Restore this circuit to its original state, and repeat steps S2-S4 until the efficient simplified digital logic circuit model converges on this circuit. S6: Repeat steps S1-S5 until the efficient simplified digital logic circuit model has been trained and converged on all circuits in the training set, thus obtaining the trained efficient simplified digital logic circuit model.

6. The method for efficiently simplifying digital logic circuits based on deep learning according to claim 5, characterized in that, The loss function is the cross-entropy loss, and its expression is as follows: in, Indicates the optimal action number at this node. One-hot encoding, This represents the loss function value corresponding to the selected action at this node. This represents the probability of the action of that node as output by deep learning. Represents probability The logarithm of .

7. A system for efficiently simplifying digital logic circuits based on deep learning, characterized in that, The method described in any one of claims 1-6 includes: The first construction unit is used to construct a logic synthesis dataset, which includes a training set and a test set. The input data in the logic synthesis dataset is a circuit described by RTL Verilog. The second construction unit is used to construct a logic synthesis environment and action space, and to preprocess the input data to construct an efficient simplified digital logic circuit model based on deep learning. The efficient simplified digital logic circuit model includes a circuit feature extraction module and an action selection module. The circuit feature extraction module is used to learn the complete structure and local structure of the circuit, and to use the learned complete structure features and local structure features to splice together the mixed structure features of the circuit. The action selection module selects an appropriate optimization algorithm to analyze the mixed structure features of the circuit. The training unit is used to train a deep learning-based efficient simplified digital logic circuit model using circuits from a preprocessed training set until the efficient simplified digital logic circuit model converges. The test unit is used to utilize a trained, deep learning-based, efficient simplified digital logic circuit model and perform logic optimization on a test set to test the logic optimization capability of the efficient simplified digital logic circuit model.

8. An electronic device, characterized in that, Including memory and processor; The memory is used to store instructions; The processor is configured to operate according to the instructions to perform the steps of the method according to any one of claims 1-6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the program implements the steps of the method according to any one of claims 1-6.

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