Logic synthesis method and device for logic circuit design and storage medium
By decomposing the logic circuit design into sub-circuit designs and performing bottom-up traversal and constant transfer optimization, combined with a machine learning scoring model, the problem of excessive resource area in logic circuit design is solved, achieving a more efficient synthesis process and lower resource overhead.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-25
- Publication Date
- 2026-04-07
AI Technical Summary
In existing technologies, the overall resource area of logic circuit design far exceeds the overall requirements, resulting in excessive resource overhead that is difficult to reduce effectively.
By obtaining the abstract syntax tree of the logic circuit design, it is decomposed into multiple sub-logic circuit designs, and bottom-up traversal and constant transfer optimization are performed. Combined with a machine learning scoring model, operator thresholds and constant transfer are optimized, and parallel synthesis is performed to obtain a comprehensive netlist.
It effectively reduces the overall resource area of logic circuit design, improves synthesis efficiency, avoids the existence of redundant logic, and improves the quality of the synthesized netlist.
Smart Images
Figure CN121809356A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the fields of chip development and chip testing, and in particular to a logic synthesis method, apparatus and storage medium for logic circuit design. Background Technology
[0002] As chip functionality continues to improve, the scale of logic circuit design within chips is also increasing. How to quickly synthesize ultra-large-scale logic circuit designs within chips has become a key focus for designers.
[0003] Logic verification refers to the verification process of converting Register-Transfer Level (RTL) code into a gate-level netlist. In the existing technology, for the rapid synthesis of large-scale logic circuit designs, designers usually break down the logic circuit design into multiple smaller-scale logic circuit designs, and then synthesize the smaller-scale logic circuit designs.
[0004] However, this logic synthesis method results in a large amount of redundant logic in the synthesized netlist, which makes the resource area of the synthesis result far exceed the resource overhead of the overall synthesis result of the logic circuit design, greatly increasing the synthesis resource area of the logic circuit design. Summary of the Invention
[0005] This invention provides a logic synthesis method, apparatus, electronic device, and storage medium for logic circuit design to solve the problem of excessive synthesis resource area in logic circuit design.
[0006] According to another aspect of the present invention, a logic synthesis method for logic circuit design is provided, comprising:
[0007] Obtain the abstract syntax tree corresponding to the logic circuit design, and obtain the number of operators for each functional module based on the abstract syntax tree;
[0008] By using a bottom-up exploration approach, the abstract syntax tree is traversed based on operator thresholds to obtain multiple sub-logic circuit designs.
[0009] In each of the sub-logic circuit designs, a constant search is performed, and the searched constants are transmitted to the adjacent sub-logic circuit designs so as to optimize the logic and signals of each sub-logic circuit design based on the constant transmission results.
[0010] The sub-logic circuit designs are synthesized in parallel to obtain a synthesized netlist of the logic circuit designs.
[0011] Before obtaining the number of operators for each functional module based on the abstract syntax tree, the method further includes: traversing the abstract syntax tree to obtain high-level operator nodes; obtaining the logical expression of the high-level operator node, and replacing the high-level operators in the logical expression with low-level operators to perform downgrade processing on the abstract syntax tree.
[0012] The step of obtaining the number of operators for each functional module based on the abstract syntax tree specifically includes: assigning matching resource weights to different operators according to the operator type, and obtaining the weighted number of operators for each functional module based on the number of operators in each functional module and the resource weight of each operator.
[0013] The method of traversing the abstract syntax tree based on operator thresholds through a bottom-up exploration approach to obtain multiple sub-logic circuit designs includes: obtaining the operator threshold corresponding to the current functional module based on the topology density, fan-out number, timing critical path distribution status, and cross-module interaction frequency of the current functional module.
[0014] The step of obtaining the operator threshold corresponding to the current functional module based on the topology density, fan-out number, temporal critical path distribution status, and cross-module interaction frequency of the current functional module includes: obtaining the feature vector of the current functional module based on the topology density, fan-out number, temporal critical path distribution status, and cross-module interaction frequency of the current functional module, and inputting the feature vector into the machine learning scoring model to obtain the operator threshold corresponding to the current functional module through the machine learning scoring model.
[0015] The step of transmitting the searched constants to adjacent sub-logic circuit designs to perform logic and signal optimization on each sub-logic circuit design based on the constant transmission results includes: transmitting the searched constants to adjacent sub-logic circuit designs and recording the newly added constants in a constant list; if it is determined that the number of newly added constants in the constant list is greater than a preset threshold, continuing to transmit the searched constants to adjacent sub-logic circuit designs until the number of newly added constants in the constant list is less than or equal to the preset threshold, or the number of constant transmissions reaches a preset threshold, and then performing logic and signal optimization on each sub-logic circuit design based on the constant transmission results.
[0016] According to another aspect of the present invention, a logic synthesis apparatus for logic circuit design is provided, comprising:
[0017] The operator count acquisition module is used to acquire the abstract syntax tree corresponding to the logic circuit design, and to acquire the operator count of each functional module based on the abstract syntax tree;
[0018] The sub-circuit design acquisition module is used to traverse the abstract syntax tree based on operator thresholds in a bottom-up exploration manner to obtain multiple sub-logic circuit designs.
[0019] The design optimization execution module is used to perform constant search in each of the sub-logic circuit designs and transmit the searched constants to the adjacent sub-logic circuit designs, so as to perform logic optimization and signal optimization on each of the sub-logic circuit designs based on the constant transmission results.
[0020] The integrated netlist acquisition module is used to perform parallel synthesis of each of the sub-logic circuit designs to obtain the integrated netlist of the logic circuit designs.
[0021] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform a logic synthesis method for logic circuit design according to any embodiment of the present invention.
[0022] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the logic synthesis method for logic circuit design according to any embodiment of the present invention.
[0023] According to another aspect of the present invention, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the logic synthesis method for logic circuit design as described in any embodiment of the present invention.
[0024] The technical solution of this invention first obtains the abstract syntax tree corresponding to the logic circuit design, and then obtains the number of operators for each functional module based on the abstract syntax tree. Next, it traverses the abstract syntax tree from the bottom up, based on operator thresholds, to obtain multiple sub-logic circuit designs. Then, it performs constant search in each sub-logic circuit design and transmits the searched constants to adjacent sub-logic circuit designs to optimize logic and signals based on the constant transmission results. Finally, it performs parallel synthesis of each sub-logic circuit design to obtain a synthesis netlist of the logic circuit design. Thus, by splitting and concurrently synthesizing multiple obtained sub-logic circuit designs, the synthesis efficiency of the logic circuit design is improved, while avoiding redundant logic in the synthesis netlist and reducing the synthesis resource area of the logic circuit design.
[0025] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description
[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0027] Figure 1 This is a flowchart of a logic synthesis method for logic circuit design provided in Embodiment 1 of the present invention;
[0028] Figure 2 This is a schematic diagram showing the breakdown result of the logic circuit design provided in Embodiment 1 of the present invention;
[0029] Figure 3 This is a schematic diagram of a cross-boundary transmission constant scenario provided by Embodiment 1 of the present invention;
[0030] Figure 4 This is a flowchart of another logic synthesis method for logic circuit design provided in Embodiment 2 of the present invention;
[0031] Figure 5 This is a flowchart of another logic synthesis method for logic circuit design provided in Embodiment 3 of the present invention;
[0032] Figure 6 This is a schematic diagram of the structure of a logic synthesis device for logic circuit design according to Embodiment 4 of the present invention;
[0033] Figure 7 This is a schematic diagram of the structure of an electronic device that implements the logic synthesis method for logic circuit design in the embodiments of the present invention. Detailed Implementation
[0034] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0035] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0036] Example 1
[0037] Figure 1 This is a flowchart of a logic synthesis method for logic circuit design provided in Embodiment 1 of the present invention. This embodiment is applicable to obtaining a synthesized netlist of a logic circuit design by optimizing the logic and signals of each sub-logic circuit design. This method can be executed by the logic synthesis device for logic circuit design in any embodiment of the present invention. The logic synthesis device for logic circuit design can be implemented in hardware and / or software and can be configured in an electronic device. Figure 1 As shown, the method includes:
[0038] S101. Obtain the abstract syntax tree corresponding to the logic circuit design, and obtain the number of operators for each functional module based on the abstract syntax tree.
[0039] Logic circuit design refers to the circuit modules formed by combining and connecting electronic components on a chip according to certain logical rules. Logic circuit design can be represented in the form of register-transfer level code. Abstract Syntax Tree (AST) is an abstract tree-like representation of the syntactic structure of source code. It transforms the logical composition of code into a tree-like data structure, where each node corresponds to a syntactic unit in the source code (e.g., variable declaration, function, expression, literal, etc.). Existing syntax parsing tools can be used to perform lexical and syntactic analysis on logic circuit design, thereby generating an abstract syntax hierarchy tree.
[0040] A functional module refers to a code unit in an abstract syntax tree that has a specific semantic or logical function. In fact, it is also a sub-module or sub-unit used in logic circuit design to implement a specified function. For example, based on the syntax structure, each subtree in the abstract syntax tree can be regarded as a functional module, and the root node of the subtree represents the module type. Alternatively, based on semantic logic, modules containing flow control nodes such as branches or loops can be regarded as control flow modules, and modules containing expression subtrees such as variable declarations, assignments, or arithmetic operations can be regarded as data processing modules. Based on this, the number of operators of each functional module can be obtained by traversing the abstract syntax tree.
[0041] Optionally, in this embodiment of the invention, obtaining the number of operators for each functional module based on the abstract syntax tree specifically includes: assigning matching resource weights to different operators according to the operator type, and obtaining the weighted number of operators for each functional module based on the number of operators in each functional module and the resource weight of each operator.
[0042] Specifically, resource weights reflect the resource consumption of different operators. The more resources consumed, the higher the resource weight; the less resources consumed, the lower the resource weight. For example, the resource weight of basic operators (e.g., AND, OR) can be configured to 1; the weight of medium operators (e.g., select, bitwise shift) can be configured to 2; and the weight of complex operators (e.g., read port, write port) can be configured to 5. These complex operators involve the use of storage resources.
[0043] The weighted number of operators for each functional module is equal to the sum of the products of each operator and its corresponding resource weight. Compared to simply counting the number of operators in a functional module, the weighted number of operators calculated based on the number of operators and resource weights ensures the accuracy of the operator scale for each functional module and more intuitively reflects the amount of system resources used by different functional modules.
[0044] S102. By using a bottom-up exploration method, the abstract syntax tree is traversed based on the operator threshold to obtain multiple sub-logic circuit designs.
[0045] The operator threshold (e.g., 10,000 operators) represents the maximum capacity of a sub-logic circuit design. Starting from the leaf nodes of the AST, the AST is traversed in a bottom-up manner. When the total number of operators in the sub-level trees reaches the operator threshold, it is split into independent sub-logic circuit designs. Each sub-logic circuit design may include one or more functional modules, or it may only include a part of a functional module. When a sub-logic circuit design includes multiple functional modules, at most one functional module is allowed to lack a complete logical structure, while other functional modules must include a complete logical structure.
[0046] by Figure 2 For example, after the logic circuit design is broken down, it forms three sub-logic circuit designs: sub-logic circuit design A, sub-logic circuit design B, and sub-logic circuit design C. Sub-logic circuit design A specifically includes functional modules a, c, f, and h; sub-logic circuit design B specifically includes functional modules b, d, e, and i; and sub-logic circuit design C specifically includes functional modules g, j, and k.
[0047] Optionally, in this embodiment of the invention, the step of traversing the abstract syntax tree based on operator thresholds through a bottom-up exploration method to obtain multiple sub-logic circuit designs includes: obtaining the operator threshold corresponding to the current functional module based on the topology density, fan-out number, timing critical path distribution status, and cross-module interaction frequency of the current functional module.
[0048] Specifically, when a functional module has a large number of operators, it may be split into multiple sub-logic circuit designs. In this case, the splitting of the functional module can be based on a dynamic operator threshold. Topology density refers to the density of physical connections between the internal logic units of the functional module. The higher the density, the lower the operator threshold, which promotes the splitting of the functional module and reduces the competition for local resources. Fan-out refers to the number of lower-level modules driven by a single signal output. The more fan-out modules there are, the greater the signal propagation delay and the lower the operator threshold, which allows high-fan-out modules to be split into multi-level buffer structures.
[0049] The timing critical path refers to the path with the greatest signal delay in the system, and its delay determines the system's highest operating frequency. The distribution state of the timing critical path is also the physical distribution state of the timing critical path. If the timing critical path is concentrated, that is, the timing critical path is concentrated in a certain area, splitting it may disrupt the original timing, in which case the operator threshold should be increased. If the timing critical path is dispersed, that is, the timing critical path is dispersed in different areas, in which case the operator threshold can be decreased to ensure the optimization of local paths.
[0050] Cross-module interaction frequency refers to the frequency of data exchange and control signal exchange between the current functional module and other functional modules. The more frequent these interactions, the more constant the communication overhead will be due to fragmentation. In this case, it is necessary to increase the operator threshold to avoid excessive fragmentation and maintain communication locality. Based on this, the operator threshold corresponding to the current functional module can be calculated according to the topology density, fan-out number, timing critical path distribution, cross-module interaction frequency, and their respective weight coefficients. This ensures both the logical integrity of each sub-logic circuit design and a larger number of sub-logic circuit designs to improve the efficiency of obtaining the synthesized netlist.
[0051] Optionally, in this embodiment of the invention, obtaining the operator threshold corresponding to the current functional module based on the topology density, fan-out number, temporal critical path distribution status, and cross-module interaction frequency of the current functional module includes: obtaining the feature vector of the current functional module based on the topology density, fan-out number, temporal critical path distribution status, and cross-module interaction frequency of the current functional module, and inputting the feature vector into a machine learning scoring model to obtain the operator threshold corresponding to the current functional module through the machine learning scoring model.
[0052] Specifically, the machine learning scoring model can include an XGBoost (eXtreme Gradient Boosting) model or a graph neural network model, which is trained using historical chip design projects as training samples. It obtains quantized values corresponding to topology density, fan-out number, temporal critical path distribution state, and cross-module interaction frequency, and constructs feature vectors based on these values. These feature vectors are then input into the machine learning scoring model to obtain the recommendation splitting granularity output by the machine learning scoring model. Through multi-dimensional feature linkage and with the help of the recommendation function of the machine learning scoring model, a more accurate operator threshold for the current functional module can be obtained, avoiding over-segmentation and under-segmentation.
[0053] S103. Perform constant search in each of the sub-logic circuit designs and transmit the searched constants to the adjacent sub-logic circuit designs so as to optimize the logic and signals of each sub-logic circuit design based on the constant transmission results.
[0054] In addition to logic values 0 and 1, the constants also include unknown state X and high impedance Z. Unknown state X represents an uncertain logic state, such as an unknown voltage, which may be due to reasons such as uninitialized circuit, signal collision, or race conditions. High impedance Z represents a high impedance state, such as no-drive output, which may be due to the extremely high resistance presented by the output terminal being disconnected from the power supply. Thus, by statistically analyzing the distribution of 0 or 1, it is possible to confirm whether the circuit is working properly (e.g., whether the counter output is within the expected range). Statistics on X can locate uninitialized registers or signal collisions. Statistics on Z can check whether the enable logic of tri-state gates is correct (e.g., whether multiple devices are driving the bus simultaneously).
[0055] Within each sub-logic circuit design, all signals and operators are scanned to identify constant values; for example, in sub-logic circuit design A, "signal G is always 0" is searched; through the interconnect boundary ports (i.e., input port INPUT and output port OUTPUT) of adjacent sub-logic circuit designs, the constants in each sub-logic circuit design are transmitted to the adjacent sub-logic circuit designs.
[0056] by Figure 3 For example, if the constants 0, 1, X, and Z in sub-logic circuit design A need to be passed to the adjacent sub-logic circuit design B, they need to be passed through the interconnection boundary port between the two. At the same time, if the constants 0, 1, X, and Z in sub-logic circuit design B need to be passed to the adjacent sub-logic circuit design A, they also need to be passed through the interconnection boundary port between the two.
[0057] The constants 0, 1, X, and Z within sub-logic circuit design B need to be passed to the adjacent sub-logic circuit design C through the interconnection boundary port between them; similarly, the constants 0, 1, X, and Z within sub-logic circuit design C also need to be passed to the adjacent sub-logic circuit design B through the interconnection boundary port between them.
[0058] The constants 0, 1, X, and Z within sub-logic circuit design C need to be passed to the adjacent sub-logic circuit design A through the interconnection boundary port between them.
[0059] Based on this, the large-scale logic circuit design is broken down into multiple smaller sub-logic circuit designs. After cross-boundary data transfer, each sub-logic circuit design is locally simplified. For example, if signal G is ANDed with a constant 0, the result will always be 0, so signal G and the AND logic can be optimized and removed. If signal G is ANDed with a constant 1, the result will still be signal G, so the AND logic can be optimized and removed. If signal G is ORed with a constant 0, the result will still be signal G, so the OR logic can be optimized and removed. If signal G is ORed with a constant 1, the result will always be 1, so signal G and the OR logic can be optimized and removed. By removing redundant logic and signals, the resource area of the synthesized netlist is reduced.
[0060] S104. Perform parallel synthesis on each of the sub-logic circuit designs to obtain a synthesized netlist of the logic circuit designs.
[0061] The optimized sub-logic circuit designs are assigned to independent synthesis processes, and the processes are started concurrently through a task scheduling tool. Compared with directly synthesizing the logic circuit design, concurrent synthesis of multiple sub-logic circuit designs obviously improves the synthesis efficiency of the logic circuit design. After completing the netlist merging, the cross-boundary ports (e.g., signals from sub-logic circuit design A to sub-logic circuit design B) are reconnected, and timing and functional equivalence are verified, thereby completing the synthesis netlist acquisition of the logic circuit design.
[0062] The technical solution of this invention first obtains the abstract syntax tree corresponding to the logic circuit design, and then obtains the number of operators for each functional module based on the abstract syntax tree. Next, it traverses the abstract syntax tree from the bottom up, based on operator thresholds, to obtain multiple sub-logic circuit designs. Then, it performs constant search in each sub-logic circuit design and transmits the searched constants to adjacent sub-logic circuit designs to optimize logic and signals based on the constant transmission results. Finally, it performs parallel synthesis of each sub-logic circuit design to obtain a synthesis netlist of the logic circuit design. Thus, by splitting and concurrently synthesizing multiple obtained sub-logic circuit designs, the synthesis efficiency of the logic circuit design is improved, while avoiding redundant logic in the synthesis netlist and reducing the synthesis resource area of the logic circuit design.
[0063] Example 2
[0064] Figure 4 This is a flowchart of a logic synthesis method for logic circuit design provided in Embodiment 2 of the present invention. The relationship between this embodiment and the above embodiments is that constant transmission is completed through iterative transmission, such as... Figure 4 As shown, the method includes:
[0065] S201. Obtain the abstract syntax tree corresponding to the logic circuit design, and obtain the number of operators for each functional module based on the abstract syntax tree.
[0066] S202. By using a bottom-up exploration method, the abstract syntax tree is traversed based on the operator threshold to obtain multiple sub-logic circuit designs.
[0067] S203. Perform constant search in each of the sub-logic circuit designs, and transmit the searched constants to the adjacent sub-logic circuit designs, and record the newly added constants through the constant list.
[0068] When a transmission constant is detected between sub-logic circuit designs, the newly added constant for this transmission is recorded in the constant list.
[0069] S204. If it is determined that the number of newly added constants in the constant list is greater than a preset number threshold, the searched constants are continued to be transmitted to the adjacent sub-logic circuit designs until the number of newly added constants in the constant list is less than or equal to the preset number threshold, or the number of constant transmissions reaches the preset number threshold. Then, logic optimization and signal optimization are performed on each of the sub-logic circuit designs based on the constant transmission results.
[0070] After each constant transfer is completed, the number of newly added constants is counted. If the number of newly added constants is greater than the preset threshold, it indicates that the constants in each sub-logic circuit design are still changing. If logic optimization and signal optimization are performed on each sub-logic circuit design based on the constant transfer results at this time, constant loss will occur, which will result in the logic and signals of the sub-logic circuit design not being fully optimized, and redundant logic and redundant signals still exist.
[0071] If the number of newly added constants is less than or equal to the preset number threshold, it indicates that the constants in each sub-logic circuit design have become stable. At this time, logic optimization and signal optimization can be performed on each sub-logic circuit design based on the constant transmission results. In particular, the preset number threshold can be configured to a value of 0, which means that when there are no new constants in the constant list, constant transmission is stopped, further ensuring the complete optimization of logic and signals in each sub-logic circuit design.
[0072] Meanwhile, when there are no new constants in some sub-logic circuit designs, the constant inflow of that sub-logic circuit design can be paused, and constant transmission iteration can only be continued for other sub-logic circuit designs until the number of new constants in all sub-logic circuit designs is less than or equal to a preset number threshold. In addition, by setting a preset number threshold, the phenomenon of infinite loop in constant transmission can be avoided, thereby improving the optimization efficiency of sub-logic circuit designs.
[0073] S205. Perform parallel synthesis on each of the sub-logic circuit designs to obtain a synthesized netlist of the logic circuit designs.
[0074] The technical solution of this invention involves transmitting the searched constants to adjacent sub-logic circuit designs and recording the newly added constants in a constant list. If the number of newly added constants in the constant list is greater than a preset threshold, the searched constants are continued to be transmitted to adjacent sub-logic circuit designs until the number of newly added constants in the constant list is less than or equal to the preset threshold, or the number of constant transmissions reaches a preset threshold. Based on the constant transmission results, logic and signal optimization are performed on each sub-logic circuit design. Thus, by configuring the preset threshold, complete optimization of logic and signals in each sub-logic circuit design is ensured. By configuring the preset threshold, infinite loops in constant transmission are avoided, improving the optimization efficiency of the sub-logic circuit designs.
[0075] Example 3
[0076] Figure 5 This is a flowchart of a logic synthesis method for logic circuit design provided in Embodiment 3 of the present invention. The relationship between this embodiment and the above embodiments is that the abstract syntax tree is downgraded, such as... Figure 5 As shown, the method includes:
[0077] S301. Obtain the abstract syntax tree corresponding to the logic circuit design, and traverse the abstract syntax tree to obtain the high-level operator nodes.
[0078] Advanced operator nodes can include module call nodes and advanced operator nodes; among them, module call nodes include module import nodes and module export nodes. Module import nodes represent the syntax structure for importing external modules, and module export nodes describe the syntax structure for export statements; advanced operator nodes can include various types of operators such as control cohesion operators, optional chaining operators, spread operators, and type assertions.
[0079] S302. Obtain the logical expression of the high-level operator node, and replace the high-level operators in the logical expression with low-level operators to perform downgrade processing on the abstract syntax tree.
[0080] After traversing the abstract syntax tree to obtain the high-level operator nodes, the logical expressions of the high-level operator nodes are extracted. For example, the logical expression of a full adder consists of three XOR operators, while the exception operator itself is a high-level operator. The logical expression represented by the high-level operators is replaced with a logical expression represented by low-level operators. For example, the logical expression of the full adder after replacement contains only three low-level operators (i.e., AND, OR, and NOT).
[0081] By replacing high-level operators in the abstract syntax tree with low-level operators, a downgrading process is achieved, refining the abstract syntax tree from a more abstract, general, and high-level abstract syntax tree to a more specific and lower-level operator syntax tree. In other words, the description level of the syntax tree is reduced, which greatly improves the parsing efficiency when parsing the syntax tree, thereby reducing the time consumed in the subsequent synthesis process.
[0082] S303. Obtain the number of operators for each functional module based on the abstract syntax tree.
[0083] S304. By using a bottom-up exploration method, the abstract syntax tree is traversed based on the operator threshold to obtain multiple sub-logic circuit designs.
[0084] S305. Perform constant search in each of the sub-logic circuit designs and transmit the searched constants to the adjacent sub-logic circuit designs to optimize the logic and signals of each sub-logic circuit design based on the constant transmission results.
[0085] S306. Perform parallel synthesis on each of the sub-logic circuit designs to obtain a synthesized netlist of the logic circuit designs.
[0086] The technical solution of this invention traverses the abstract syntax tree to obtain high-level operator nodes, then obtains the logical expressions of the high-level operator nodes, and replaces the high-level operators in the logical expressions with low-level operators to perform a downgrading process on the abstract syntax tree. This achieves a downgrading process from a more abstract, generalized, and higher-level abstract syntax tree to a more specific and lower-level operator syntax tree, greatly improving parsing efficiency and reducing the time consumed in subsequent synthesis processes.
[0087] Example 4
[0088] Figure 6 This is a structural block diagram of a logic synthesis device for logic circuit design provided in Embodiment 4 of the present invention. The device specifically includes:
[0089] Operator count acquisition module 401 is used to acquire the abstract syntax tree corresponding to the logic circuit design, and to acquire the number of operators of each functional module according to the abstract syntax tree;
[0090] The sub-circuit design acquisition module 402 is used to traverse the abstract syntax tree based on operator thresholds in a bottom-up exploration manner to obtain multiple sub-logic circuit designs.
[0091] The design optimization execution module 403 is used to perform constant search in each of the sub-logic circuit designs and transmit the searched constants to the adjacent sub-logic circuit designs, so as to perform logic optimization and signal optimization on each of the sub-logic circuit designs based on the constant transmission results.
[0092] The integrated netlist acquisition module 404 is used to perform parallel synthesis of each of the sub-logic circuit designs to obtain the integrated netlist of the logic circuit designs.
[0093] The technical solution of this invention first obtains the abstract syntax tree corresponding to the logic circuit design, and then obtains the number of operators for each functional module based on the abstract syntax tree. Next, it traverses the abstract syntax tree from the bottom up, based on operator thresholds, to obtain multiple sub-logic circuit designs. Then, it performs constant search in each sub-logic circuit design and transmits the searched constants to adjacent sub-logic circuit designs to optimize logic and signals based on the constant transmission results. Finally, it performs parallel synthesis of each sub-logic circuit design to obtain a synthesis netlist of the logic circuit design. Thus, by splitting and concurrently synthesizing multiple obtained sub-logic circuit designs, the synthesis efficiency of the logic circuit design is improved, while avoiding redundant logic in the synthesis netlist and reducing the synthesis resource area of the logic circuit design.
[0094] Optionally, the logic synthesis device for logic circuit design is further configured to traverse the abstract syntax tree to obtain high-level operator nodes; obtain the logical expressions of the high-level operator nodes, and replace the high-level operators in the logical expressions with low-level operators to perform downgrade processing on the abstract syntax tree.
[0095] Optionally, the operator quantity acquisition module 401 is specifically used to assign matching resource weights to different operators according to the operator type, and to obtain the weighted number of operators for each functional module according to the number of operators in each functional module and the resource weight of each operator.
[0096] Optionally, the sub-circuit design acquisition module 402 is specifically used to acquire the operator threshold corresponding to the current functional module based on the topology density, fan-out number, timing critical path distribution status, and cross-module interaction frequency of the current functional module.
[0097] Optionally, the sub-circuit design acquisition module 402 is further configured to acquire the feature vector of the current functional module based on the topology density, fan-out number, timing critical path distribution status and cross-module interaction frequency of the current functional module, and input the feature vector to the machine learning scoring model to obtain the operator threshold corresponding to the current functional module through the machine learning scoring model.
[0098] Optionally, the design optimization execution module 403 is specifically used to transmit the searched constants to adjacent sub-logic circuit designs and record the newly added constants through a constant list; if it is determined that the number of newly added constants in the constant list is greater than a preset number threshold, the searched constants are continued to be transmitted to adjacent sub-logic circuit designs until the number of newly added constants in the constant list is less than or equal to the preset number threshold, or the number of constant transmissions reaches a preset number threshold, and then logic optimization and signal optimization are performed on each of the sub-logic circuit designs based on the constant transmission results.
[0099] The above-described apparatus can execute the logic synthesis method for logic circuit design provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the method. Technical details not described in detail in this embodiment can be found in the logic synthesis method for logic circuit design provided in any embodiment of the present invention.
[0100] Example 5
[0101] Figure 7A schematic diagram of an electronic device 10, which can be used to implement embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, electronic devices, blade electronic devices, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (such as helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.
[0102] like Figure 7 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.
[0103] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.
[0104] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as logic synthesis methods for logic circuit design.
[0105] In some embodiments, the logic synthesis method for logic circuit design can be implemented as a computer program tangibly contained in a computer-readable storage medium, such as a memory cell. In some embodiments, part or all of the computer program can be loaded and / or installed on a heterogeneous hardware accelerator via ROM and / or a communication unit. When the computer program is loaded into RAM and executed by a processor, one or more steps of the logic synthesis method for logic circuit design described above can be performed. Alternatively, in other embodiments, the processor can be configured to perform the logic synthesis method for logic circuit design by any other suitable means (e.g., by means of firmware).
[0106] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.
[0107] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.
[0108] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.
[0109] To provide user interaction, the systems and techniques described herein can be implemented on a heterogeneous hardware accelerator, which includes: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the heterogeneous hardware accelerator. Other types of devices can also be used to provide user interaction; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or haptic feedback); and input from the user can be received in any form (including sound input, voice input, or haptic input).
[0110] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.
[0111] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.
[0112] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.
[0113] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.
Claims
1. A logic synthesis method for logic circuit design, characterized in that, include: Obtain the abstract syntax tree corresponding to the logic circuit design, and obtain the number of operators for each functional module based on the abstract syntax tree; By using a bottom-up exploration approach, the abstract syntax tree is traversed based on operator thresholds to obtain multiple sub-logic circuit designs. In each of the sub-logic circuit designs, a constant search is performed, and the searched constants are transmitted to the adjacent sub-logic circuit designs so as to optimize the logic and signals of each sub-logic circuit design based on the constant transmission results. The sub-logic circuit designs are synthesized in parallel to obtain a synthesized netlist of the logic circuit designs.
2. The logic synthesis method for logic circuit design according to claim 1, characterized in that, Before obtaining the number of operators for each functional module based on the abstract syntax tree, the process also includes: Traverse the abstract syntax tree to obtain high-level operator nodes; Obtain the logical expression of the high-level operator node, and replace the high-level operators in the logical expression with low-level operators to perform downgrade processing on the abstract syntax tree.
3. The logic synthesis method for logic circuit design according to claim 1, characterized in that, The step of obtaining the number of operators for each functional module based on the abstract syntax tree specifically includes: Based on the operator type, assign matching resource weights to different operators, and obtain the weighted number of operators for each functional module according to the number of operators in each functional module and the resource weight of each operator.
4. The logic synthesis method for logic circuit design according to claim 1, characterized in that, The process involves traversing the abstract syntax tree using a bottom-up approach, based on operator thresholds, to obtain multiple sub-logic circuit designs, including: Based on the topology density, fan-out number, timing critical path distribution status, and cross-module interaction frequency of the current functional module, obtain the operator threshold corresponding to the current functional module.
5. The logic synthesis method for logic circuit design according to claim 4, characterized in that, The step of obtaining the operator threshold corresponding to the current functional module based on the current functional module's topology density, fan-out number, temporal critical path distribution status, and cross-module interaction frequency includes: Based on the topology density, fan-out number, temporal critical path distribution status, and cross-module interaction frequency of the current functional module, the feature vector of the current functional module is obtained, and the feature vector is input into the machine learning scoring model to obtain the operator threshold corresponding to the current functional module through the machine learning scoring model.
6. The logic synthesis method for logic circuit design according to claim 1, characterized in that, The step of transmitting the searched constants to adjacent sub-logic circuit designs to perform logic and signal optimization on each sub-logic circuit design based on the constant transmission results includes: The searched constants are transferred to the adjacent sub-logic circuit designs, and the newly added constants are recorded in the constant list; If the number of newly added constants in the constant list is determined to be greater than a preset threshold, the searched constants are continued to be transmitted to the adjacent sub-logic circuit designs until the number of newly added constants in the constant list is less than or equal to the preset threshold, or the number of constant transmissions reaches the preset threshold. Then, logic optimization and signal optimization are performed on each of the sub-logic circuit designs based on the constant transmission results.
7. A logic synthesis device for logic circuit design, characterized in that, include: The operator count acquisition module is used to acquire the abstract syntax tree corresponding to the logic circuit design, and to acquire the operator count of each functional module based on the abstract syntax tree; The sub-circuit design acquisition module is used to traverse the abstract syntax tree based on operator thresholds in a bottom-up exploration manner to obtain multiple sub-logic circuit designs. The design optimization execution module is used to perform constant search in each of the sub-logic circuit designs and transmit the searched constants to the adjacent sub-logic circuit designs, so as to perform logic optimization and signal optimization on each of the sub-logic circuit designs based on the constant transmission results. The integrated netlist acquisition module is used to perform parallel synthesis of each of the sub-logic circuit designs to obtain the integrated netlist of the logic circuit designs.
8. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the logic synthesis method for the logic circuit design according to any one of claims 1-6.
9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed by a processor, implement the logic synthesis method for the logic circuit design according to any one of claims 1-6.
10. A computer program product comprising a computer program that, when executed by a processor, implements the logic synthesis method for the logic circuit design according to any one of claims 1-6.