Defect prediction method, device and system after chip grinding and medium

Abstract

The invention provides a defect prediction method, device and system after chip grinding and a medium. A graphics processor is used for rendering; obtaining vertex data of the new polygons by utilizing Roberts filtering; according to the vertex data of each new polygon, calculating to obtain each equivalent length and each equivalent width of each new polygon, and calculating to obtain a target layer equivalent line width of a chip layout target layer; according to the total area of the new polygon and the total area of the target layer of the chip layout, calculating the target layer graph density of the target layer of the chip layout; and inputting the equivalent line width of the target layer and the graph density of the target layer into the pre-trained multi-layer perceptron model to obtain a predicted defect of the target layer of the chip layout. According to the method, the new polygon is obtained through rendering of the graphics processor, traditional polygon contact judgment and intersection and union operation with the large calculation amount are avoided, the complex interaction and nonlinear effect in the grinding process can be captured by pre-training the multi-layer perceptron model, and accurate and rapid prediction of defects after chip grinding is achieved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit simulation technology, and particularly to a method, device, system and medium for predicting defects after chip grinding. Background Art

[0002] Chemical mechanical polishing (CMP) is applied in the front-end process, middle-end process and back-end process of integrated circuits, and is an important means to ensure the flatness of wafers.

[0003] The surface topography of the wafer after chemical mechanical polishing is not only related to process parameters such as pressure, rotation speed and polishing solution composition, but also related to the patterns on the wafer.

[0004] Patterns with different characteristics have different effects on the surface height of the wafer after grinding. In the entire manufacturing process of integrated circuits, there are more than ten chemical mechanical polishing steps. The surface undulations of the lower-layer wafers will accumulate and exacerbate the surface height fluctuations of the upper layer, affecting the performance and manufacturing yield of the chips.

[0005] In order to avoid the influence of layout patterns on the surface height fluctuations of the chip after chemical mechanical polishing, it is necessary to perform chemical mechanical polishing simulation in the design stage to predict defects after chip grinding. Chemical mechanical polishing simulation first needs to read and parse the chip layout, then extract layout features, and input the layout feature parameters into the chemical mechanical polishing simulation model, and then the surface height of the wafer corresponding to the layout can be calculated.

[0006] In this process, feature extraction is an important task for extracting the parameters required for subsequent analysis from the chip layout patterns.

[0007] Chemical mechanical polishing simulation requires the extraction of the equivalent line width and pattern density at each part of the layout. These two parameters have a significant impact on the surface topography of the wafer after chemical mechanical polishing. Traditional very large scale integration (VLSI) layout feature extraction methods are often inefficient when dealing with complex and large-scale layouts, requiring a large amount of computing resources and time, which restricts the efficiency of chip design.

[0008] Specifically, the current mainstream layout file formats are GDSII (Graphic Design System Ⅱ) and OASIS (Open Artwork System Interchange Standard), both of which store the design information of the chip by recording the vertices of polygons. Therefore, the process of feature extraction for chip layout data is a process of performing operations such as intersection and union on the polygons in the chip layout. The processing of polygons in the layout consumes a large amount of time. First, the complexity of polygon operations is relatively high. Each polygon consists of numerous vertices and edges, and calculating its area, perimeter, intersection relationships, etc. requires complex mathematical operations and algorithms. Second, as the number of polygons increases, the computational complexity increases exponentially, resulting in a significant increase in the operation time. Especially in chip layouts, there are often hundreds of thousands of polygons in a single interconnect layer. In addition, EDA (Electronic Design Automation) algorithms with different functions have different computational requirements for polygons, increasing the difficulty of processing polygon data in the layout. Therefore, when dealing with a large number of polygons, a large amount of computing resources and time are required to complete these complex geometric computing tasks.

[0009] In addition, it is equally crucial to establish an accurate CMP model. There is currently no completely accurate and reliable CMP simulation model. Whether it is a physics-based model or a data-driven model, both contain undetermined parameters that require test data support. The conventional approach is to produce test layouts, collect data from the test layouts, use the data to calibrate the parameters of the model and test the accuracy of the model, which is less efficient.

[0010] Therefore, how to accurately and quickly predict the defects after chip grinding is a technical problem that needs to be solved in this field. Summary of the Invention

[0011] In view of this, this Summary of the Invention section is provided to introduce the concepts in a brief form. These concepts will be described in detail in the following Detailed Implementation section. This Summary of the Invention section is not intended to identify the key features or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0012] The purpose of this application is to provide a method, device, system, and medium for predicting defects after chip grinding, which can accurately and quickly predict the defects after chip grinding.

[0013] To achieve the above purpose, this application has the following technical solutions:

[0014] In the first aspect, an embodiment of this application provides a method for predicting defects after chip grinding, including:

[0015] Obtain the vertex data of each initial polygon in the target layer of the chip layout;

[0016] Use the graphics processing unit to render each of the initial polygons according to the vertex data of each of the initial polygons;

[0017] Use Roberts filtering to re-divide the boundaries and extract vertices of the rendered initial polygons to obtain the vertex data of each new polygon;

[0018] Calculate the areas and perimeters of each of the new polygons based on the vertex data of each of the new polygons; calculate the equivalent lengths and equivalent widths of each of the new polygons based on the areas and perimeters of each of the new polygons;

[0019] Calculate the target layer equivalent line width of the target layer of the chip layout based on the equivalent widths of each of the new polygons, the areas of each of the new polygons, and the total area of the new polygons; calculate the target layer graphic density of the target layer of the chip layout based on the total area of the new polygons and the total area of the target layer of the chip layout;

[0020] Input the target layer equivalent line width and the target layer graphic density into a pre-trained multi-layer perceptron model to obtain the predicted defects of the target layer of the chip layout.

[0021] In a possible implementation, the using the graphics processing unit to render each of the initial polygons according to the vertex data of each of the initial polygons includes:

[0022] Use the bandwidth of the interconnection between the graphics processing unit and the central processing unit to obtain the vertex data of each of the initial polygons from the central processing unit and store it in the global memory of the graphics processing unit;

[0023] According to the stored vertex data of each of the initial polygons, allocate threads of the graphics processing unit to separately render the regions enclosed by each of the initial polygons.

[0024] In a possible implementation, the pre-trained multi-layer perceptron model includes a first multi-layer perceptron model and a second multi-layer perceptron model. The inputting the target layer equivalent line width and the target layer graphic density into the pre-trained multi-layer perceptron model to obtain the predicted defects of the target layer of the chip layout includes:

[0025] Input the target layer equivalent line width and the target layer graphic density into the first multi-layer perceptron model to obtain the predicted metal dish defects of the target layer of the chip layout;

[0026] Input the equivalent line width of the target layer and the pattern density of the target layer into the second multi-layer perceptron model to obtain the predicted dielectric erosion defects of the target layer of the chip layout; the predicted defects include the predicted metal dishing defects and the predicted dielectric erosion defects.

[0027] In a possible implementation, calculating the equivalent length and equivalent width of each new polygon based on the areas and perimeters of each new polygon is specifically solved through the following equations:

[0028]

[0029]

[0030] where the value of x1 is the equivalent length of each new polygon, the value of x2 is the equivalent width of each new polygon, x1 > x2, C i is the perimeter of each new polygon, and S i is the area of each new polygon.

[0031] In a second aspect, an embodiment of the present application provides a defect prediction device after chip grinding, including:

[0032] An acquisition unit, configured to acquire vertex data of each initial polygon in the target layer of the chip layout;

[0033] A rendering unit, configured to render each initial polygon using a graphics processing unit according to the vertex data of each initial polygon;

[0034] A partitioning unit, configured to re-partition the boundaries and extract vertices of the rendered initial polygons using Roberts filtering to obtain vertex data of each new polygon;

[0035] A first calculation unit, configured to calculate the areas and perimeters of each new polygon according to the vertex data of each new polygon; calculate the equivalent length and equivalent width of each new polygon according to the areas and perimeters of each new polygon;

[0036] A second calculation unit, configured to calculate the equivalent line width of the target layer of the chip layout according to the equivalent width of each new polygon, the areas of each new polygon, and the total area of the new polygons; calculate the pattern density of the target layer of the chip layout according to the total area of the new polygons and the total area of the target layer of the chip layout;

[0037] A prediction unit, configured to input the equivalent line width of the target layer and the pattern density of the target layer into a pre-trained multi-layer perceptron model to obtain the predicted defects of the target layer of the chip layout.

[0038] In a possible implementation, the rendering unit is specifically configured to:

[0039] Utilize the bandwidth of the interconnection between the graphics processing unit and the central processing unit to obtain the vertex data of each initial polygon from the central processing unit and store it in the global memory of the graphics processing unit;

[0040] According to the stored vertex data of each initial polygon, allocate threads of the graphics processing unit to separately render the regions enclosed by each initial polygon.

[0041] In a possible implementation, the pre-trained multi-layer perceptron model includes a first multi-layer perceptron model and a second multi-layer perceptron model. The prediction unit is specifically configured to:

[0042] Input the equivalent line width of the target layer and the graphic density of the target layer into the first multi-layer perceptron model to obtain the predicted metal dishing defects of the target layer of the chip layout;

[0043] Input the equivalent line width of the target layer and the graphic density of the target layer into the second multi-layer perceptron model to obtain the predicted dielectric erosion defects of the target layer of the chip layout; the predicted defects include the predicted metal dishing defects and the predicted dielectric erosion defects.

[0044] In a possible implementation, the first calculation unit is specifically configured to solve for the equivalent lengths and equivalent widths of each new polygon through the following equation:

[0045]

[0046]

[0047] where the value of x1 is the equivalent lengths of each new polygon, the value of x2 is the equivalent widths of each new polygon, x1 > x2, C i is the perimeter of each new polygon, and S i is the area of each new polygon.

[0048] In a third aspect, an embodiment of the present application provides a system for predicting defects after chip grinding, including:

[0049] A memory for storing a computer program;

[0050] A processor for implementing the steps of the method for predicting defects after chip grinding as described above when executing the computer program.

[0051] Fourthly, an embodiment of the present application provides a computer-readable medium, on which a computer program is stored. When the computer program is processed and executed, the steps of the defect prediction method after chip grinding as described above are implemented.

[0052] Compared with the prior art, the embodiment of the present application has the following beneficial effects:

[0053] The embodiment of the present application provides a defect prediction method, device, system and medium after chip grinding. The method includes: obtaining vertex data of each initial polygon in the target layer of the chip layout; using a graphics processor to render each initial polygon according to the vertex data of each initial polygon; using Roberts filtering to re-divide the boundaries and extract vertices of the rendered initial polygons to obtain vertex data of each new polygon; calculating the areas and perimeters of each new polygon according to the vertex data of each new polygon; calculating the equivalent lengths and equivalent widths of each new polygon according to the areas and perimeters of each new polygon; calculating the equivalent line width of the target layer of the chip layout target layer according to the equivalent widths of each new polygon, the areas of each new polygon and the total area of the new polygon; calculating the target layer graphic density of the chip layout target layer according to the total area of the new polygon and the total area of the chip layout target layer; inputting the target layer equivalent line width and the target layer graphic density into a pre-trained multi-layer perceptron model to obtain the predicted defects of the chip layout target layer. The present application renders new polygons through a graphics processor, avoiding the extremely computationally intensive polygon contact determination and intersection and union operations in the traditional method. Through the pre-trained multi-layer perceptron model, complex interactions and non-linear effects during the grinding process can be captured, so as to realize accurate and rapid prediction of defects after chip grinding. Description of the Drawings

[0054] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.

[0055] Combined with the drawings and referring to the following specific embodiments, the above and other features, advantages and aspects of the various embodiments of the present disclosure will become more obvious. Throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic, and the original components and elements are not necessarily drawn to scale.

[0056] Figure 1 Shows a flowchart of a defect prediction method after chip grinding provided by an embodiment of the present application;

[0057] Figure 2Shows a schematic diagram of an initial polygon after rendering provided by an embodiment of the present application;

[0058] Figure 3 Shows a schematic diagram of a new polygon after Roberts filtering provided by an embodiment of the present application;

[0059] Figure 4 Shows a schematic diagram with the upper left vertex of the new polygon as the traversal starting point provided by an embodiment of the present application;

[0060] Figure 5 Shows a schematic diagram of the thread corresponding to the initial polygon provided by an embodiment of the present application;

[0061] Figure 6 Shows a schematic diagram of a chip grinding defect prediction device provided by an embodiment of the present application. Detailed implementation manners

[0062] To make the above objects, features, and advantages of the present application more obvious and understandable, the following will describe the detailed implementation manners of the present application in conjunction with the accompanying drawings.

[0063] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar generalizations without departing from the connotation of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0064] As described in the background art, through research by the applicant, it is found that chemical mechanical polishing (CMP) is applied in the front-end process, middle-end process, and back-end process of integrated circuits and is an important means to ensure the flatness of wafers.

[0065] The surface topography of the wafer after chemical mechanical polishing is not only related to process parameters such as pressure, rotation speed, and polishing solution composition, but also related to the patterns on the wafer.

[0066] Patterns with different characteristics have different effects on the surface height of the polished wafer. In the entire manufacturing process of integrated circuits, there are more than ten chemical mechanical polishing steps. The surface undulations of the lower-layer wafers will accumulate and exacerbate the surface height fluctuations of the upper layer, affecting the performance and manufacturing yield of the chips.

[0067] In order to avoid the influence of layout patterns on the height fluctuation of the chip surface after chemical mechanical polishing (CMP), it is necessary to perform CMP simulation in the design stage to predict the defects on the polished chip. The CMP simulation first reads and parses the chip layout, then extracts the layout features, and inputs the layout feature parameters into the CMP simulation model, and then the surface height of the wafer corresponding to this layout after CMP can be calculated.

[0068] In this process, feature extraction is an important task, which is used to extract the parameters required for subsequent analysis from the chip layout patterns.

[0069] CMP simulation requires the extraction of the equivalent line width and pattern density at each location of the layout. These two parameters have a significant impact on the surface topography of the wafer after CMP. Traditional methods for extracting layout features of very large scale integration (VLSI) circuits are often inefficient when dealing with complex and large-scale layouts, requiring a large amount of computing resources and time, which restricts the efficiency of chip design.

[0070] Specifically, the current mainstream layout file formats are GDSII (Graphic Design System Ⅱ) and OASIS (Open Artwork System Interchange Standard), both of which store the design information of the chip by recording the vertices of polygons. Therefore, the process of extracting features from chip layout data is a process of performing operations such as intersection and union on the polygons in the chip layout. The processing of polygons in the layout consumes a large amount of time. First, the complexity of polygon operations is relatively high. Each polygon consists of numerous vertices and edges, and calculating its area, perimeter, intersection relationship, etc. requires complex mathematical operations and algorithms. Second, as the number of polygons increases, the complexity of the calculation increases exponentially, resulting in a significant increase in the operation time. Especially in chip layouts, there are often hundreds of thousands of polygons in a single interconnect layer. In addition, different functions of EDA (Electronic Design Automation) algorithms have different requirements for polygon calculations, which increases the difficulty of processing polygon data in the layout. Therefore, when dealing with a large number of polygons, a large amount of computing resources and time are required to complete these complex geometric calculation tasks.

[0071] Meanwhile, in the chip layout, polygons are allowed to overlap and contact each other, and adjacent polygons are counted as a single polygon during manufacturing. During the process of layout feature extraction, it is necessary to prevent the overlapping parts of such polygons from being double-counted. In the first step of performing feature extraction, it is necessary to determine the contact situation of all polygons and perform a "union" operation on adjacent polygons. It is obviously not realistic to determine the contact situation of all polygons. Introducing a location-based polygon indexing system can alleviate this problem, but it will also cause a larger storage space occupation, and the intersection and union operations of polygons still consume a large amount of time.

[0072] In addition, it is also crucial to establish an accurate CMP model. At present, there is no completely accurate and reliable CMP simulation model. Whether it is a physics-based model or a data-driven model, both contain undetermined parameters that require test data support. The conventional approach is to produce test layouts, collect data from the test layouts, use the data to calibrate the parameters of the model and test the accuracy of the model, which is inefficient.

[0073] The CMP process involves complex physical phenomena, including the interaction between abrasive particles and the surface, hydrodynamics, and chemical reactions, etc. These physical phenomena are difficult to accurately model. In addition, physics-based CMP models usually require a large amount of computing resources, which may limit their application in the actual production environment. AI-based CMP modeling requires a large amount of training data, and these data may require a large number of experiments or simulations to obtain, especially for complex CMP systems.

[0074] If there is not enough data or the model is too complex, AI-based models are prone to overfitting, resulting in poor performance on new data. When facing conditions or changes different from the training data, AI models may not be able to generalize well, resulting in inaccurate predictions.

[0075] Therefore, how to achieve accurate and rapid prediction of defects after chip polishing is a technical problem that needs to be solved in this field.

[0076] To solve the above technical problems, the embodiments of the present application provide a method, apparatus, system and medium for predicting defects after chip grinding. The method includes: obtaining vertex data of each initial polygon in the target layer of the chip layout; using a graphics processing unit to render each initial polygon according to the vertex data of each initial polygon; using Roberts filtering to re-divide the boundaries and extract vertices of the rendered initial polygons to obtain vertex data of each new polygon; calculating the areas and perimeters of each new polygon according to the vertex data of each new polygon; calculating the equivalent lengths and equivalent widths of each new polygon according to the areas and perimeters of each new polygon; calculating the equivalent line width of the target layer of the chip layout according to the equivalent widths of each new polygon, the areas of each new polygon and the total area of the new polygons; calculating the target layer graphic density of the chip layout according to the total area of the new polygons and the total area of the target layer of the chip layout; inputting the equivalent line width of the target layer and the target layer graphic density into a pre-trained multi-layer perceptron model to obtain the predicted defects of the target layer of the chip layout. The present application renders new polygons through a graphics processing unit, avoiding the traditional extremely computationally intensive polygon contact determination and intersection and union operations. Through the pre-trained multi-layer perceptron model, complex interactions and non-linear effects during the grinding process can be captured, thus realizing accurate and rapid prediction of defects after chip grinding.

[0077] Exemplary method

[0078] See Figure 1 As shown, it is a flowchart of a method for predicting defects after chip grinding provided by the embodiments of the present application, including:

[0079] S101: Obtain vertex data of each initial polygon in the target layer of the chip layout.

[0080] In the embodiments of the present application, in order to determine the area enclosed by each initial polygon in the target layer of the chip layout, the vertex data of each initial polygon needs to be obtained.

[0081] First, the chip layout file in GDSII or OASIS format can be read, and the vertex coordinate data of all initial polygons in the target layer of the chip layout (such as the first metal layer in the chip layout, etc.) can be parsed and stored.

[0082] Specifically, the embodiments of the present application can load the chip layout file in GDSII or OASIS format from a hard disk or other storage media and verify the legality and format of the file. When the verification passes, the user specifies the target layer to be parsed in the form of a layer number, and filters out the relevant data of each initial polygon in the target layer to improve the execution efficiency.

[0083] Then, according to the specifications of the GDSII or OASIS file, each initial polygon object of the target layer can be parsed item by item, and the vertex coordinate data of each initial polygon can be extracted. At the same time, the vertex data of each initial polygon obtained by parsing can be stored in a file according to the sequential structure, for example, it can be stored in the memory of the CPU (Central Processing Unit) for subsequent processing.

[0084] S102: Render each of the initial polygons using a graphics processing unit according to the vertex data of each of the initial polygons.

[0085] In the embodiments of the present application, mainly by utilizing the high concurrency and large bandwidth characteristics of the GPU (graphics processing unit), a space is allocated in the globally shared memory area of the GPU, and the area enclosed by all the initial polygons is rendered, so as to draw the target layer of the chip layout as a graph in the memory.

[0086] This step is equivalent to taking a photo of the layout in the memory. And the initial polygons that are in contact in the layout will naturally form a new polygon, and the overlapping part is set to 1 twice, avoiding the situation of being calculated twice.

[0087] For example, see Figure 2 shown, which is a schematic diagram of an initial polygon after rendering provided by the embodiments of the present application. Figure 2 In, the initial polygon areas are all set to 1, and the rest are 0 to distinguish the initial polygon areas. It should be noted that the data exists in a one-dimensional form in the memory.

[0088] S103: Use Roberts filtering to re-divide the boundaries and extract the vertices of the rendered initial polygons to obtain the vertex data of each new polygon.

[0089] In the embodiments of the present application, after rendering each initial polygon, only the areas occupied by each initial polygon are determined, but the boundaries and vertex data of the formed new polygons are not divided. For example, two mutually contacting initial polygons will become a new polygon after rendering and boundary division.

[0090] The convolution filtering based on the Roberts operator (Roberts operator) in the embodiments of the present application is called Roberts filtering. Roberts filtering can effectively extract the boundaries and vertices of new polygons. Roberts filtering is a basic convolution filter for edge detection, commonly used in grayscale images or binary images, and consists of two 2x2 convolution kernels, which are respectively used to detect horizontal and vertical edges in the image.

[0091] The convolution filtering result of Roberts filtering can be calculated by the following formula:

[0092]

[0093] Result = ABS(d x ) + ABS(d y );

[0094] Where d x is the convolution kernel in the horizontal direction of the new polygon, d y is the convolution kernel in the vertical direction of the new polygon, and ABS (absolute value) is an absolute value function. Result is the convolution filtering result of Roberts filtering.

[0095] Since Roberts filtering only involves small convolution kernels, its computational cost is very low and it is particularly suitable for scenarios with high-speed processing. Although Roberts filtering is sensitive to noise, there will be no noise pollution in the memory map based on polygon drawing. Therefore, using Roberts filtering can not only ensure the extraction of the boundaries of all new polygons, but also improve the operation speed as much as possible.

[0096] In addition, by applying an additional memory space to store the convolution results, there is no data coupling between the threads performing convolution filtering. Therefore, this step has a very high degree of concurrency.

[0097] See Figure 3 shown in the figure, which is a schematic diagram of a new polygon after Roberts filtering provided by the embodiment of the present application.

[0098] For example, by performing convolution on the memory map, the convolution result corresponding to the vertex position of the new polygon in the figure is 1, the convolution result at the boundary position is 2, and the convolution result inside the polygon is 0.

[0099] S104: Calculate the areas and perimeters of the new polygons according to the vertex data of the new polygons; calculate the equivalent lengths and equivalent widths of the new polygons according to the areas and perimeters of the new polygons.

[0100] S105: Calculate the target layer equivalent line width of the target layer of the chip layout according to the equivalent widths of the new polygons, the areas of the new polygons, and the total area of the new polygons; calculate the target layer pattern density of the target layer of the chip layout according to the total area of the new polygons and the total area of the target layer of the chip layout.

[0101] In the embodiments of the present application, the areas and perimeters of each new polygon can be calculated based on the vertex data of each new polygon; based on the areas and perimeters of each new polygon, the equivalent lengths and equivalent widths of each new polygon can be calculated.

[0102] Specifically, when calculating the areas and perimeters of each new polygon, the number of new polygons needs to be determined. To prevent a new polygon from being calculated multiple times, the starting point for traversing each new polygon can be set. The starting point for traversing the new polygon can be set as the lower right vertex, lower left vertex, upper left vertex, upper right vertex, etc. of the new polygon.

[0103] For example, see Figure 4 As shown, it is a schematic diagram of using the upper left vertex of the new polygon as the traversal starting point provided by the embodiments of the present application. To use the upper left vertex to index the new polygon, a judgment is added during convolution. If the current point is a vertex and is the upper left vertex, then this value is set to x, where x≠0,1,2, to distinguish it from other points.

[0104] In the embodiments of the present application, the layout feature extraction for chemical mechanical polishing is based on grids. Therefore, n threads are allocated to each grid, and n depends on the computing power of the GPU.

[0105] See Figure 5 As shown, it is a schematic diagram of thread allocation provided by the embodiments of the present application. In Figure 5 n = 10 is taken as an example. Different colors in the figure represent different grids. Each grid is divided into 10 equal-sized parts, and each thread is responsible for traversing a part of it.

[0106] The traversal process is a process of finding the upper left vertex of the new polygon. The purpose of this process is to find all the new polygons in the memory map. The specific implementation method is to judge whether the current value is x set in the previous step. If it is x, it means that the current point is the upper left vertex of the new polygon.

[0107] When the upper left vertex is traversed, the thread calls the Walk function. Starting from this point, it walks along the edge of the new polygon to find all the vertices of the new polygon, and dynamically applies for space to store it in the heap of the GPU for subsequent calculation use.

[0108] In the actual application process, there is a situation where a new polygon has multiple upper left vertices. As shown in Figure 4 To prevent this new polygon from being calculated multiple times during traversal, a judgment is added in the Walk function. During the process of walking along the edge of the new polygon, if the current vertex is on the left side of the starting point, the walking process stops, the calculation result is not added to the final result, and the applied space is released to prevent memory leakage.

[0109] For example, seeFigure 4 As shown, both start0 and start1 are the upper left vertices. If start0 is used as the starting point and start1 is on the left side of the starting point after reaching it, in order to avoid double - counting this new polygon, the walking process stops at this time.

[0110] In a possible implementation, the equivalent lengths and equivalent widths of each new polygon are calculated according to the areas and perimeters of each new polygon in the embodiments of the present application, and are specifically obtained by solving the following equations:

[0111]

[0112]

[0113] Among them, the value of x1 is the equivalent length, the value of x2 is the equivalent width, x1 > x2, C i The value of is the perimeter of each new polygon, and S i The value of is the area of each new polygon. This equation essentially equivalent a new polygon to a rectangle.

[0114] Then, the equivalent line width of the target layer of the chip layout can be calculated according to the equivalent widths of each new polygon, the areas of each new polygon, and the total area of the new polygons; the target layer pattern density of the target layer of the chip layout can be calculated according to the total area of the new polygons and the total area of the target layer of the chip layout.

[0115] Specifically, for example, there are two new polygons, the equivalent widths are 5 and 2 respectively, the areas are 10 and 8 respectively, and the total area is 18. Then the equivalent line width of the target layer of the chip layout is: (5×10 + 2×8)÷18≈1.72. If the total area of the target layer of the chip layout is 30, then the target layer pattern density of the target layer of the chip layout is 0.6.

[0116] S106: Input the equivalent line width of the target layer and the target layer pattern density into a pre - trained multi - layer perceptron model to obtain the predicted defects of the target layer of the chip layout.

[0117] In the embodiments of the present application, the pre - trained multi - layer perceptron model is trained by the measurement data of the test chips.

[0118] The test chip is designed to contain arrays with different line widths and densities. After the chip is fabricated, the amount of metal dishing and dielectric erosion of each array can be measured using AFM (Atomic Force Microscope) and SEM (scanning electron microscope). Dishing and erosion are often used to measure the surface smoothness of the chip after the CMP process. After measuring all the arrays, the data set shown in Table 1 below can be obtained. This data set is used as the training set to train the initial multi-layer perceptron model to obtain the pre-trained multi-layer perceptron model:

[0119] Line width Density Dishing Erosion 0.05 10.00％ -54.23 -49.91 0.05 20.00％ -78.05 -12.97 ... ... ... ... 5.00 90.00％ -99.55 -24.24

[0120] Table 1

[0121] The process of model establishment is the training process of the multi-layer perceptron. The input nodes of the multi-layer perceptron are two, namely the equivalent line width of the layout target layer and the pattern density of the target layer. Regarding the output nodes, a multi-layer perceptron model can be trained to have two output nodes that simultaneously output dishing and erosion. This multi-layer perceptron model is relatively complex and has a slow output speed, but it outputs the predicted defects simultaneously at one time, which is convenient to use.

[0122] The test layout used for calibrating the multi-layer perceptron model contains limited data. Generally, there are about one hundred arrays in a test chip. Experience shows that due to the limitation of the data volume, the number of layers of the multi-layer perceptron can be set within five, and the number of nodes in each layer can be within 20. In the actual application process, it needs to be adjusted at any time according to the training error and generalization error of the test data.

[0123] In a possible implementation manner, the pre-trained multi-layer perceptron model provided by the embodiments of the present application may include a first multi-layer perceptron model and a second multi-layer perceptron model. Inputting the equivalent line width of the target layer and the pattern density of the target layer into the pre-trained multi-layer perceptron model to obtain the predicted defects of the chip layout target layer may specifically include:

[0124] Inputting the equivalent line width of the target layer and the pattern density of the target layer into the first multi-layer perceptron model to obtain the predicted metal dishing defects of the chip layout target layer; inputting the equivalent line width of the target layer and the pattern density of the target layer into the second multi-layer perceptron model to obtain the predicted dielectric erosion defects of the chip layout target layer; the predicted defects include predicted metal dishing defects and predicted dielectric erosion defects.

[0125] Specifically, the embodiments of the present application can also train two multi-layer perceptrons, which are respectively used to calculate dishing and erosion. The two multi-layer perceptron models are relatively simple and have a fast output speed, but they can only output one predicted defect at a time, which is not convenient to use.

[0126] In a possible implementation manner, the embodiments of the present application provide a method for rendering each initial polygon according to the vertex data of each initial polygon by using a graphics processor, which may specifically include:

[0127] Utilize the bandwidth of the interconnection between the graphics processor and the central processing unit to obtain the vertex data of each initial polygon from the central processing unit and store it in the global memory of the graphics processor; according to the stored vertex data of each initial polygon, allocate the threads of the graphics processor to render the regions enclosed by each initial polygon respectively.

[0128] Specifically, since the threads in the GPU (device side) cannot directly read the data in the memory on the CPU side (host side), it is necessary to allocate space in the global memory of the GPU to store the polygon data, which is denoted by Mem_PolygonData.

[0129] Apply for a space in the global memory of the GPU as a "canvas", denoted by Mem_Canvas, and set this area to 0. The size of this space can be determined according to the accuracy requirements and the layout size, while considering the GPU video memory limit.

[0130] For example: if the processing accuracy is limited to 1 nm and the initial polygons in the layout area of 20 μm × 30 μm are processed each time, the size of the space that needs to be applied for is:

[0131] 20 × 1000 × 30 × 1000 × 1 Byte = 600 Mbytes;

[0132] The last term 1 Byte in the above formula represents using 1 Byte to store whether a pixel is rendered.

[0133] Then, use the ultra-high bandwidth of the interconnection between the GPU and the motherboard to transfer the polygon data on the CPU side to the global memory on the GPU side for storage. A large number of threads (tens of thousands and above) can be started according to the stored vertex data of each initial polygon, and each thread is sequentially assigned an initial polygon. And set all the areas enclosed by the polygon coordinates to 1 in Mem_Canvas. Usually, there are hundreds of thousands of polygons in the layout, so there is a situation where one thread processes multiple polygons. Figure 1 There are hundreds of thousands of polygons in the layout layer, so there is a situation where one thread processes multiple polygons.

[0134] Such as Figure 5As shown, it is a schematic diagram corresponding to the threads and the initial polygons provided by the embodiment of the present application. There can be multiple initial polygons, and there can also be multiple threads: Thread_0, Thread_1, Thread_2, Thread_3... Thread_n. In Figure 5 For example, Thread_0 corresponds to two polygons at the same time and can perform rendering processing simultaneously to reasonably allocate resources and improve efficiency.

[0135] The embodiment of the present application provides a method for predicting defects after chip grinding. The method includes: obtaining vertex data of each initial polygon in the target layer of the chip layout; using a graphics processing unit to render each initial polygon according to the vertex data of each initial polygon; using Roberts filtering to re-divide the boundaries and extract vertices of the rendered initial polygons to obtain vertex data of each new polygon; calculating the areas and perimeters of each new polygon according to the vertex data of each new polygon; calculating the equivalent lengths and equivalent widths of each new polygon according to the areas and perimeters of each new polygon; calculating the equivalent line width of the target layer of the chip layout according to the equivalent widths of each new polygon, the areas of each new polygon, and the total area of the new polygons; calculating the target layer graphic density of the chip layout according to the total area of the new polygons and the total area of the target layer of the chip layout; inputting the equivalent line width of the target layer and the target layer graphic density into a pre-trained multi-layer perceptron model to obtain the predicted defects of the target layer of the chip layout. The present application renders new polygons through a graphics processing unit, avoiding the extremely computationally intensive polygon contact determination and intersection and union operations in the traditional method. Through the pre-trained multi-layer perceptron model, complex interactions and non-linear effects during the grinding process can be captured, thereby realizing accurate and rapid prediction of defects after chip grinding.

[0136] The embodiment of the present application regards the video memory of the GPU as a "canvas" and uses the ultra-high concurrency of the GPU to draw all polygons in the video memory of the GPU, avoiding the time overhead caused by polygon contact determination and "union" operations. By restricting the size of the "canvas" and the way of drawing dividing lines, the process of grid division and polygon "intersection and union" calculation is completed while drawing. On this basis, the boundaries of all polygons in the grid can be calculated through convolution and walking algorithms, and the equivalent line width and density of all polygons in the grid can be quickly extracted and calculated.

[0137] Using the method provided by the embodiments of the present application, the speed of layout feature extraction can be greatly improved. During the process of counting and processing the layout, traditional feature extraction techniques need to perform contact determination on a large number of polygons and perform union operations on the mutually contacting polygons. Using the method provided by the embodiments of the present application can avoid the extremely computationally intensive polygon contact determination and union operations. At the same time, the high concurrency characteristics and automatic scheduling technology of the GPU are suitable for the processing method based on graphics and pixels, greatly improving the efficiency of layout feature parameter extraction.

[0138] In addition, past research related to layout inspection has focused on the connection between the layout image and hotspots, while ignoring the time required for the conversion from layout data to layout image, restricting the practical application of related research. Using the method provided by the embodiments of the present application, the layout data can be quickly converted into the required image, and the converted graphics are stored in the GPU video memory in the form of a matrix. If the subsequent processing process is still carried out in the GPU, the data transfer between the GPU video memory and the host memory can be avoided.

[0139] The CMP modeling and simulation process based on the multi-layer perceptron can be modeled using experimental data without a deep physical understanding. The MLP model can learn non-linear relationships, so it can capture the complex interactions and non-linear effects during the CMP process, making it adaptable to different CMP process parameters and materials. And the MLP (multi-layer perceptron) model has a relatively fast training speed with the support of GPU computing power, and can also quickly generate results during prediction, so it can be used for rapid layout optimization and chip topography control.

[0140] Exemplary device

[0141] See Figure 6 As shown, it is a schematic diagram of a chip grinding defect prediction device provided by the embodiments of the present application, including:

[0142] An acquisition unit 201, configured to acquire vertex data of each initial polygon in the target layer of the chip layout;

[0143] A rendering unit 202, configured to render each of the initial polygons using a graphics processor according to the vertex data of each of the initial polygons;

[0144] A partitioning unit 203, configured to re-partition the boundaries and extract vertices of the rendered initial polygons using Roberts filtering to obtain vertex data of each new polygon;

[0145] The first calculation unit 204 is configured to calculate the areas and perimeters of the new polygons based on the vertex data of the new polygons; calculate the equivalent lengths and equivalent widths of the new polygons based on the areas and perimeters of the new polygons.

[0146] The second calculation unit 205 is configured to calculate the equivalent line width of the target layer of the chip layout based on the equivalent widths of the new polygons, the areas of the new polygons, and the total area of the new polygons; calculate the target layer pattern density of the target layer of the chip layout based on the total area of the new polygons and the total area of the target layer of the chip layout.

[0147] The prediction unit 206 is configured to input the equivalent line width of the target layer and the target layer pattern density into a pre-trained multi-layer perceptron model to obtain the predicted defects of the target layer of the chip layout.

[0148] In a possible implementation manner, the rendering unit is specifically configured to:

[0149] Utilize the bandwidth of the interconnection between the graphics processor and the central processing unit to obtain the vertex data of the initial polygons from the central processing unit and store them in the global memory of the graphics processor.

[0150] According to the stored vertex data of the initial polygons, allocate threads of the graphics processor to respectively render the areas enclosed by the initial polygons.

[0151] In a possible implementation manner, the pre-trained multi-layer perceptron model includes a first multi-layer perceptron model and a second multi-layer perceptron model. The prediction unit is specifically configured to:

[0152] Input the equivalent line width of the target layer and the target layer pattern density into the first multi-layer perceptron model to obtain the predicted metal dishing defects of the target layer of the chip layout.

[0153] Input the equivalent line width of the target layer and the target layer pattern density into the second multi-layer perceptron model to obtain the predicted dielectric erosion defects of the target layer of the chip layout; the predicted defects include the predicted metal dishing defects and the predicted dielectric erosion defects.

[0154] In a possible implementation manner, the first calculation unit is specifically configured to solve for the equivalent lengths and equivalent widths of the new polygons through the following equations:

[0155]

[0156]

[0157] Among them, the value of x1 is the respective equivalent lengths, the value of x2 is the respective equivalent widths, x1 > x2, C i 's value is the respective perimeters of the respective new polygons, S i 's value is the respective areas of the respective new polygons.

[0158] The embodiment of the present application provides a device for predicting defects after chip grinding. The method applied to this device includes: obtaining vertex data of each initial polygon in the target layer of the chip layout; using a graphics processing unit to render each initial polygon according to the vertex data of each initial polygon; using Roberts filtering to re-divide the boundaries and extract vertices of the rendered initial polygons to obtain vertex data of each new polygon; calculating the respective areas and perimeters of each new polygon according to the vertex data of each new polygon; calculating the respective equivalent lengths and equivalent widths of each new polygon according to the respective areas and perimeters of each new polygon; calculating the target layer equivalent line width of the target layer of the chip layout according to the respective equivalent widths of each new polygon, the respective areas of each new polygon, and the total area of the new polygons; calculating the target layer graphic density of the target layer of the chip layout according to the total area of the new polygons and the total area of the target layer of the chip layout; inputting the target layer equivalent line width and the target layer graphic density into a pre-trained multi-layer perceptron model to obtain the predicted defects of the target layer of the chip layout. The present application renders new polygons through a graphics processing unit, avoiding the traditional extremely computationally intensive polygon contact determination and intersection and union operations. Through the pre-trained multi-layer perceptron model, complex interactions and non-linear effects during the grinding process can be captured, thereby realizing accurate and rapid prediction of defects after chip grinding.

[0159] Based on the above embodiments, the embodiment of the present application provides a system for predicting defects after chip grinding, including:

[0160] A memory for storing a computer program;

[0161] A processor for implementing the steps of the method for predicting defects after chip grinding as described above when executing the computer program.

[0162] Based on the above embodiments, the embodiment of the present application further provides a computer-readable medium, on which a computer program is stored, and when the computer program is processed and executed, it implements the steps of the method for predicting defects after chip grinding as described above.

[0163] It should be noted that the computer-readable medium described above in the present disclosure may be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. A computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium that contains or stores a program, and this program can be used by or in combination with an instruction execution system, apparatus, or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, and this computer-readable signal medium can send, propagate, or transmit a program for use by or in combination with an instruction execution system, apparatus, or device. The program code contained on a computer-readable medium can be transmitted by any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0164] The above computer-readable medium may be included in the above system; it may also exist separately without being assembled into the system.

[0165] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart may be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product that includes a computer program carried on a non-transitory computer-readable medium, and this computer program contains program code for executing the method shown in the flowchart.

[0166] Each embodiment in this specification is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the apparatus embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can refer to the description of the method embodiment.

[0167] The above are only the preferred embodiments of the present application. Although the present application has been disclosed above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make many possible changes and modifications to the technical solution of the present application, or modify it into equivalent embodiments with equivalent changes, without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of protection of the technical solution of the present application.

Claims

1. A method for predicting defects after chip grinding, characterized in that Including: Obtain the vertex data of each initial polygon in the target layer of the chip layout; Use a graphics processing unit to render each of the initial polygons according to the vertex data of each of the initial polygons; Use Roberts filtering to re-divide the boundaries and extract vertices of the rendered initial polygons to obtain the vertex data of each new polygon; Calculate the areas and perimeters of each of the new polygons according to the vertex data of each of the new polygons; Calculate the equivalent lengths and equivalent widths of each of the new polygons according to the areas and perimeters of each of the new polygons; Calculate the equivalent line width of the target layer of the chip layout according to the equivalent widths of each of the new polygons, the areas of each of the new polygons, and the total area of the new polygons; Calculate the target layer graphic density of the chip layout target layer according to the total area of the new polygons and the total area of the chip layout target layer; Input the equivalent line width of the target layer and the target layer graphic density into a pre-trained multi-layer perceptron model to obtain the predicted defects of the target layer of the chip layout.

2. The method according to claim 1, wherein The using a graphics processing unit to render each of the initial polygons according to the vertex data of each of the initial polygons includes: Using the bandwidth of the interconnection between the graphics processing unit and the central processing unit to obtain the vertex data of each of the initial polygons from the central processing unit and store it in the global memory of the graphics processing unit; According to the stored vertex data of each of the initial polygons, allocate threads of the graphics processing unit to render the regions enclosed by each of the initial polygons separately.

3. The method according to claim 1, characterized in that The pre-trained multi-layer perceptron model includes a first multi-layer perceptron model and a second multi-layer perceptron model. The inputting the equivalent line width of the target layer and the target layer graphic density into the pre-trained multi-layer perceptron model to obtain the predicted defects of the target layer of the chip layout includes: Input the equivalent line width of the target layer and the target layer graphic density into the first multi-layer perceptron model to obtain the predicted metal dishing defects of the target layer of the chip layout; Input the equivalent line width of the target layer and the target layer graphic density into the second multi-layer perceptron model to obtain the predicted dielectric erosion defects of the target layer of the chip layout; the predicted defects include the predicted metal dishing defects and the predicted dielectric erosion defects.

4. The method according to claim 1, characterized in that, The calculating the equivalent lengths and equivalent widths of each of the new polygons according to the areas and perimeters of each of the new polygons is specifically solved by the following equation: Among them, the value of x1 is the respective equivalent length, the value of x2 is the respective equivalent width, x1 > x2, C i The value of is the respective perimeter of each of the new polygons, S i The value of is the respective area of each of the new polygons.

5. A defect prediction device after chip grinding, characterized in that, Including: An acquisition unit for obtaining the vertex data of each initial polygon in the target layer of the chip layout; A rendering unit for using a graphics processing unit to render each of the initial polygons according to the vertex data of each of the initial polygons; A dividing unit for using Roberts filtering to re-divide the boundaries and extract vertices of the rendered initial polygons to obtain the vertex data of each new polygon; A first calculation unit for calculating the areas and perimeters of each of the new polygons according to the vertex data of each of the new polygons; According to the areas and perimeters of the new polygons, calculate the equivalent lengths and equivalent widths of the new polygons; A second calculation unit, configured to calculate a target layer equivalent line width of the target layer of the chip layout according to the equivalent widths of the new polygons, the areas of the new polygons, and the total area of the new polygons; Calculate a target layer pattern density of the target layer of the chip layout according to the total area of the new polygons and the total area of the target layer of the chip layout; A prediction unit, configured to input the target layer equivalent line width and the target layer pattern density into a pre-trained multi-layer perceptron model to obtain a predicted defect of the target layer of the chip layout; 6. The device according to claim 5, characterized in that, The rendering unit is specifically configured to: Utilize the bandwidth of the interconnection between the graphics processor and the central processing unit to obtain vertex data of the initial polygons from the central processing unit and store the vertex data in the global memory of the graphics processor; According to the stored vertex data of the initial polygons, allocate threads of the graphics processor to separately render the areas enclosed by the initial polygons; 7. The device according to claim 5, characterized in that, The pre-trained multi-layer perceptron model includes a first multi-layer perceptron model and a second multi-layer perceptron model, and the prediction unit is specifically configured to: Input the target layer equivalent line width and the target layer pattern density into the first multi-layer perceptron model to obtain a predicted metal dishing defect of the target layer of the chip layout; Input the target layer equivalent line width and the target layer pattern density into the second multi-layer perceptron model to obtain a predicted dielectric erosion defect of the target layer of the chip layout; the predicted defect includes the predicted metal dishing defect and the predicted dielectric erosion defect.

8. The device according to claim 5, characterized in that The first calculation unit is specifically configured to solve for the equivalent lengths and equivalent widths of the new polygons through the following equations: Among them, the value of x1 is the respective equivalent lengths, the value of x2 is the respective equivalent widths, x1 > x2, C i The value of is the respective perimeters of the respective new polygons, S i The value of is the respective areas of the respective new polygons.

9. A defect prediction system after chip grinding, characterized in that, Comprising: A memory for storing a computer program; A processor, configured to implement the steps of the method for predicting defects after chip grinding according to any one of claims 1-4 when executing the computer program; 10. A computer-readable medium, characterized in that, A computer program is stored on the computer-readable medium, and when the computer program is processed and executed, the steps of the method for predicting defects after chip grinding according to any one of claims 1-4 are implemented.

Images