Generation method of time sequence library and power grid library based on Python script

Abstract

The invention relates to integrated circuit design, in particular to a Python script-based time sequence library and power grid library generation method, the Python script generates a Verilog file according to a module interface information statistical table, the Verilog file is used as an input file of a static time sequence analysis tool PrimeTime, and meanwhile, a Tcl script required by operation of the static time sequence analysis tool PrimeTime and a library compiler Library Compiler is automatically generated; the Python script calls a static time sequence analysis tool PrimeTime, the Tcl script is executed, and a time sequence library Timing Library is automatically generated; according to the time sequence library Timing Library and the power related information in the module interface information statistical table, the Python script is started according to the time sequence library Timing Library and the power related information in the module interface information statistical table; according to the technical scheme provided by the invention, the defect that the time sequence library and the power grid library are difficult to accurately and efficiently generate can be effectively overcome.

Description

Technical Field

[0001] The present invention relates to integrated circuit design, and particularly to a method for generating a timing library and a power grid library based on Python scripts. Background Art

[0002] In integrated circuit design, a timing library and a power grid library are two key components to ensure the reliable operation of a chip under various working conditions. The timing library provides the timing characteristics (such as propagation delay, setup time, hold time, etc.) of each logic unit of the chip under different working conditions; the power grid library describes the layout, topology and electrical characteristics of the power supply and ground network of the chip, ensuring that the chip obtains a stable power supply and avoiding the impact of power noise and voltage drop on performance.

[0003] With the increase in the scale and complexity of chip design, manually generating these library files becomes increasingly cumbersome and error-prone. Through automated scripts, designers can accurately and efficiently generate a timing library and a power grid library, reducing manual intervention and improving the accuracy and efficiency of design. In addition, the automatically generated library files can be reused throughout the design process, reducing the workload of library file update and maintenance, and effectively improving the reusability and scalability of the design process. Summary of the Invention

[0004] (1) Technical Problems to be Solved

[0005] In view of the above-mentioned disadvantages of the prior art, the present invention provides a method for generating a timing library and a power grid library based on Python scripts, which can effectively overcome the defects of the prior art that it is difficult to accurately and efficiently generate a timing library and a power grid library.

[0006] (2) Technical Solutions

[0007] To achieve the above object, the present invention is realized through the following technical solutions:

[0008] A method for generating a timing library and a power grid library based on Python scripts includes the following steps:

[0009] S1. The Python script generates a Verilog file according to the module interface information statistical table as the input file of the static timing analysis tool PrimeTime, and simultaneously automatically generates the Tcl scripts required for the operation of the static timing analysis tool PrimeTime and the library compiler LibraryCompiler;

[0010] S2. The Python script calls the static timing analysis tool PrimeTime and executes the Tcl script to automatically generate the timing library Timing Library.

[0011] S3. The Python script automatically generates the power grid library Power Grid Library according to the power-related information in the timing library Timing Library and the module interface information statistical table.

[0012] S4. The Python script calls the library compiler Library Compiler to check whether the timing library Timing Library and the power grid library Power Grid Library are correct, and converts the text-form Lib file into a binary-form db file.

[0013] Preferably, before the Python script in S1 generates the Verilog file according to the module interface information statistical table, it includes:

[0014] S01. Configure the system environment, install the software tool python3, and add the corresponding environment variables and path variables to the system configuration file.

[0015] S02. Collect the information of each module, fill the information of each module into different worksheets sheet to obtain the module interface information statistical table corresponding to each module, and place the module interface information statistical table in a location supported by the Python script for reading.

[0016] S03. Configure the parameters of the Python script and run the Python script based on the command line mode.

[0017] Preferably, the information of the module includes the interface list, input / output attributes, whether it is a power pin powerpin, the power pin powerpin associated with the signal, and the power down function powerdown function.

[0018] Preferably, the module interface information statistical table includes Module Name, Interface Name, Direction, pg_type, voltage_value, relatedpower, and powerdown function;

[0019] Module Name, fill in the name of the current module, which is the same as the sheet name sheetname of the worksheet sheet;

[0020] InterfaceName, fill in the interface name of the current module;

[0021] Direction, fill in the input and output attributes of the interface, which can only be one of input, output, and inout;

[0022] pg_type, fill in the power supply information of the interface, which can only be one of primary_power, primary_ground, and signal;

[0023] voltage_value, when the power supply information of the interface is primary_power, specify the voltage value in voltage_value; when the power supply information of the interface is primary_ground, specify the fixed voltage value 0V in voltage_value;

[0024] relatedpower, when the power supply information of the interface is signal, specify the related voltage in relatedpower, and the specified voltage is the interface voltage corresponding to primary_power or primary_ground defined in the current module;

[0025] power down function, when the power supply information of the interface is signal, fill in the power down function powerdown function corresponding to the interface in power downfunction.

[0026] Preferably, the parameters of the Python script include the Corner and transition parameters of the Lib file, and the parameters corresponding to the table columns in the module interface information statistical table.

[0027] Preferably, if there is an error during the running of the Python script, the error will be reported and the running will be terminated, and the error information will be displayed in the log file generated after the Python script runs;

[0028] If the Python script runs smoothly, the output path of the Lib file will be reported in the log file generated after the Python script runs.

[0029] (III) Beneficial effects

[0030] Compared with the prior art, the method for generating a timing library and a power grid library based on Python scripts provided by the present invention edits a module interface information statistical table with better interactivity, and uses Python scripts to automatically batch generate timing libraries and power grid libraries for multiple process corners of multiple modules, reducing the large amount of time required for manually generating Lib files, greatly improving the design efficiency, and at the same time reducing the error rate in the chip design process, and can accurately and efficiently generate timing libraries and power grid libraries for multiple modules. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings according to these drawings without creative efforts.

[0032] Figure 1 is a schematic flowchart of the present invention;

[0033] Figure 2 is a schematic diagram of generating Lib files and db files of the timing library and the power grid library in the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0035] The method for generating a timing library and a power grid library based on Python scripts is as Figure 1 shown. S1. The Python script generates a Verilog file according to the module interface information statistical table as an input file for the static timing analysis tool PrimeTime, and at the same time automatically generates Tcl scripts required for running the static timing analysis tool PrimeTime and the library compiler Library Compiler.

[0036] Specifically, before the Python script in S1 generates a Verilog file according to the module interface information statistical table, it includes:

[0037] S01. Configure the system environment, install the software tool Python 3, and add the corresponding environment variables and path variables to the system configuration file;

[0038] S02. Collect the information of each module, fill the information of each module into different worksheets, obtain the module interface information statistical table corresponding to each module, and place the module interface information statistical table at a position where the Python script can read;

[0039] S03. Configure the parameters of the Python script and run the Python script based on the command line mode.

[0040] 1) The information of the module includes the interface list, input / output attributes, whether it is a power pin (powerpin), the power pin (powerpin) associated with the signal, and the power down function.

[0041] 2) The module interface information statistical table includes Module Name, Interface Name, Direction, pg_type, voltage_value, relatedpower, and powerdown function;

[0042] Module Name: Fill in the name of the current module, which is the same as the sheet name of the worksheet;

[0043] InterfaceName: Fill in the interface name of the current module;

[0044] Direction: Fill in the input / output attribute of the interface, which can only be one of input, output, and inout;

[0045] pg_type: Fill in the power information of the interface, which can only be one of primary_power, primary_ground, and signal;

[0046] voltage_value: When the power information of the interface is primary_power, specify the voltage value in voltage_value; when the power information of the interface is primary_ground, specify the fixed voltage value 0V in voltage_value;

[0047] For related power, when the power supply information of the interface is signal, specify the relevant voltage in related power, and the specified voltage is the interface voltage corresponding to primary_power or primary_ground defined in the current module;

[0048] For the power down function, when the power supply information of the interface is signal, fill in the power down function corresponding to the interface, i.e., powerdown function, in the power down function.

[0049] In the technical solution of this application, the module interface information statistical table is as shown in the following table:

[0050] Table 1 Module Interface Information Statistical Table

[0051]

[0052]

[0053] 3) The parameters of the Python script include the Corner and transition parameters of the Lib file, as well as the parameters corresponding to the information in the columns of the table in the module interface information statistical table.

[0054] S2. The Python script calls the static timing analysis tool PrimeTime and executes the Tcl script to automatically generate the timing library Timing Library.

[0055] S3. The Python script automatically generates the power grid library Power Grid Library according to the timing library Timing Library and the power-related information in the module interface information statistical table.

[0056] S4. The Python script calls the library compiler Library Compiler to check whether the timing library Timing Library and the power grid library Power Grid Library are correct, and converts the Lib file in text form into a db file in binary form.

[0057] In the technical solution of this application, if there are errors during the operation of the Python script, the errors will be reported and the operation will be terminated, and the error information will be displayed in the log file generated after the Python script runs;

[0058] If the Python script runs smoothly, the output path of the Lib file will be reported in the log file generated after the Python script runs.

[0059] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for generating a timing library and a power grid library based on a Python script, characterized in that: The following steps are involved: S1. The Python script generates a Verilog file based on the module interface information statistics table as the input file of the static timing analysis tool PrimeTime, and automatically generates the Tcl script required for the static timing analysis tool PrimeTime and the library compiler LibraryCompiler to run; S2, the Python script calls the static timing analysis tool PrimeTime and executes the Tcl script to automatically generate the timing library Timing Library; S3, Python script automatically generates the power grid library Power GridLibrary based on the power related information in the timing library Timing Library and the module interface information statistics table; S4. The Python script calls the library compiler to check whether the timing library Timing Library and the power grid library Power Grid Library are correct, and converts the text-formatted Lib file into a binary-formatted db file.

2. The method for generating a timing library and a power grid library based on Python script according to claim 1, characterized in that: Before the Python script in S1 generates the Verilog file based on the module interface information statistics table, it includes: S01. Configure the system environment, install the software tool python3, and add corresponding environment variables and path variables in the system configuration file; S02. Collect information of each module, fill in the information of each module into different worksheets, obtain the module interface information statistics table corresponding to each module, and place the module interface information statistics table in a position that supports Python script reading; S03. Configure the parameters of the Python script and run the Python script based on the command line mode.

3. The method for generating a timing library and a power grid library based on Python script according to claim 2, characterized in that: The information of the module includes an interface list, input and output properties, whether it is a power pin powerpin, a power pin powerpin associated with a signal, and a power down function powerdown function.

4. The method for generating a timing library and a power grid library based on Python script according to claim 3, characterized in that: The module interface information statistics table includes Module Name, InterfaceName, Direction, pg_type, voltage_value, relatedpower and powerdown function; Module Name, fill in the name of the current module, which should be consistent with the sheet name of the worksheet sheet; InterfaceName, fill in the interface name of the current module; Direction, fill in the input and output properties of the interface, which can only be one of the three options: input, output, or inout; pg_type, fill in the power information of the interface, which can only be one of the three options: primary_power, primary_ground, and signal; voltage_value: when the power information of the interface is primary_power, specify the voltage value in voltage_value; when the power information of the interface is primary_ground, specify a fixed voltage value of 0V in voltage_value; relatedpower, when the power information of the interface is signal, the related voltage is specified in relatedpower, and the specified voltage is the interface voltage corresponding to primary_power or primary_ground defined in the current module; power down function: when the power information of the interface is signal, fill in the power down function corresponding to the interface in power down function.

5. The method for generating a timing library and a power grid library based on Python script according to claim 2, characterized in that: The parameters of the Python script include Corner and transition parameters of the Lib file, and parameters of corresponding information in the table column of the module interface information statistics table.

6. The method for generating a timing library and a power grid library based on Python script according to claim 1, characterized in that: If there is an error during the running of the Python script, the error will be reported and the running will be terminated, and the error information will be displayed in the log file generated after the Python script is run; If the Python script runs smoothly, the output path of the Lib file will be reported in the log file generated after the Python script runs.

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