Bit line sense amplifier and memory device including same

Abstract

The invention discloses a BLSA and a memory device. The BLSA reads data of the memory cell and includes an amplification circuit that amplifies a difference between a first voltage level of the second node and a second voltage level of the first node. The amplifier circuit includes: a first PMOS transistor connected between a second node and a third node and operating in response to a second voltage level; a second PMOS transistor connected between the first node and a third node and operating in response to a first voltage level; a first NMOS transistor connected between the second node and a fourth node connected to a first bit line of the first memory cell, and operating in response to a first voltage level; and a second NMOS transistor connected between the second node and a fifth node connected to a second bit line of the second memory cell, and operating in response to a second voltage level.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0188526, filed with the Korean Intellectual Property Office on December 21, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] Embodiments of the present disclosure described herein relate to a semiconductor memory device, and more particularly, to a bit - line sense amplifier and a memory device including the bit - line sense amplifier. Background art

[0004] Various electronic devices or semiconductor devices require various memory devices to operate. The main memory devices used include dynamic random access memory (DRAM) or static RAM

[0005] (SRAM). Memory devices are used in various fields, and as semiconductor devices become faster, memory devices are being developed to provide data in accordance with the increase in speed. Summary of the invention

[0006] Embodiments of the present disclosure provide a bit - line sense amplifier for determining data of a memory cell by comparing magnitudes of currents of bit - lines and amplifying a comparison result, and a memory device including the bit - line sense amplifier.

[0007] According to an embodiment, a bit - line sense amplifier for reading data of a memory cell includes: a balancing circuit connected to a first node and a second node and providing a balancing voltage to the first node and the second node; and an amplifying circuit that amplifies a difference between a first voltage level of the second node and a second voltage level of the first node. The amplifying circuit includes: a first p - type metal - oxide - semiconductor (PMOS) transistor connected between the second node and a third node and operating in response to the second voltage level; a second PMOS transistor connected between the first node and the third node and operating in response to the first voltage level; a first n - type metal - oxide - semiconductor (NMOS) transistor connected between the second node and a fourth node connected to a first bit - line of a first memory cell and operating in response to the first voltage level; and a second NMOS transistor connected between the second node and a fifth node connected to a second bit - line of a second memory cell and operating in response to the second voltage level.

[0008] According to an embodiment, a bit line sense amplifier for reading data of a memory cell includes: an equalization circuit connected to a first node and a second node and providing an equalization voltage to the first node and the second node; a first amplification circuit amplifying a difference between a first voltage level of the second node and a second voltage level of the first node; and a second amplification circuit disconnecting the bit line sense amplifier from a first bit line connected to a first memory cell and a second bit line connected to a second memory cell. The first amplification circuit includes: a first NMOS transistor connected between the first node and a third node and operating in response to the first voltage level;

[0009] and a second NMOS transistor connected between the second node and a fourth node and operating in response to the second voltage level. The second amplification circuit includes: a third NMOS transistor connected between a fifth node connected to the third node and the first bit line and operating in response to a first control signal; and a fourth NMOS transistor connected between a sixth node connected to the fourth node and the second bit line and operating in response to the first control signal.

[0010] According to an embodiment, a memory device configured to store data includes: a memory cell array storing data and including a first memory cell, a second memory cell, and a bit line sense amplifier; and an input / output circuit inputting data to the memory cell array or receiving data from the memory cell array. The bit line sense amplifier includes: an equalization circuit connected to a first node and a second node and providing an equalization voltage to the first node and the second node; and an amplification circuit amplifying a difference between a first voltage level of the second node and a second voltage level of the first node. The amplification circuit includes: a first NMOS transistor connected between the first node and a third node connected to a first bit line of the first memory cell and operating in response to the first voltage level; and a second NMOS transistor connected between the second node and a fourth node connected to a second bit line of the second memory cell and operating in response to the second voltage level. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects and features of the present disclosure will become apparent by referring to the embodiments of the present disclosure described in detail with reference to the drawings.

[0012] Figure 1 is a block diagram showing a memory device according to an embodiment of the present disclosure.

[0013] Figure 2 is a block diagram showing a Figure 1 bit line sense amplifier and a memory cell according to an embodiment of the present disclosure.

[0014] Figure 3 is a detailed illustration of aFigure 2 Circuit diagram of a bit line sense amplifier.

[0015] Figure 4A Is a detailed illustration of an Figure 3 Circuit diagram of the second read / write circuit according to an embodiment of the present disclosure.

[0016] Figure 4B Is a detailed illustration of an Figure 3 Circuit diagram of the second read / write circuit according to an embodiment of the present disclosure.

[0017] Figure 5A Is a detailed illustration of an Figure 3 Circuit diagram of the equalization circuit according to an embodiment of the present disclosure.

[0018] Figure 5B Is a detailed illustration of an Figure 3 Circuit diagram of the equalization circuit according to an embodiment of the present disclosure.

[0019] Figure 6 Is a timing diagram according to an embodiment of the present disclosure, which shows how signals and voltage levels change over time during the Figure 2 Read operation of the bit line sense amplifier in FIGS. 4 to 5.

[0020] Figure 7 Is a diagram showing an Figure 3 Flowchart of the data read operation sequence of the bit line sense amplifier according to an embodiment of the present disclosure.

[0021] Figure 8 Is a detailed illustration of an Figure 2 Circuit diagram of the bit line sense amplifier according to an embodiment of the present disclosure.

[0022] Figure 9 Is a diagram showing an Figure 2 Circuit diagram of the bit line sense amplifier according to an embodiment of the present disclosure.

[0023] Figure 10 Is a timing diagram according to an embodiment of the present disclosure, which shows how signals and voltages change over time during the Figure 9 Read operation of the bit line sense amplifier in FIG.

[0024] Figure 11 Is a detailed illustration of an Figure 2 Circuit diagram of the bit line sense amplifier according to an embodiment of the present disclosure.

[0025] Figure 12 Is a block diagram of an electronic system according to an embodiment of the present disclosure. Detailed Description

[0026] Hereinafter, embodiments of the present disclosure will be described in detail and clearly so that those of ordinary skill in the art can easily implement the present disclosure. However, the present invention can be implemented in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. These exemplary embodiments are merely examples, and many implementations and variations are possible without the details provided herein. It should also be emphasized that the present disclosure provides details of alternative examples, but such an enumeration of alternative examples is not exhaustive. In addition, any consistency in the details between various examples should not be construed as requiring such details, and it is impractical to list every possible variation for each feature described herein. The language of the claims should be referred to when determining the requirements of the present invention.

[0027] Ordinal numbers such as "first", "second", "third", etc. may simply be used as labels for certain elements, steps, etc. to distinguish these elements, steps, etc. from each other. Terms not described with "first", "second", etc. in the specification may still be referred to as "first" or "second" in the claims. Additionally, a term referred to with a specific ordinal number (e.g., "first" in a specific claim) may be described elsewhere with a different ordinal number (e.g., "second" in the specification or another claim).

[0028] It will be understood that when an element is referred to as being "connected" to another element, the connection referred to is an electrical connection. An electrical connection is an electrical connection through which an electrical signal can be transmitted from one component to another (although the strength of such an electrical signal may attenuate during transmission and may be selectively transmitted). In addition, for example, components that are "directly connected" share a common electrical node through an electrical connection made by one or more conductors (such as, for example, wiring, pads, internal wires, vias, etc.). Thus, components that are directly electrically connected do not include components that are electrically connected through active elements (such as transistors or diodes).

[0029] Figure 1 is a block diagram showing a memory device according to an embodiment of the present disclosure. With the development of various devices such as magnetic random access memory (MRAM), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistor (FeFET), departing from the structure of existing memory devices, it is necessary to sense the current flowing through a bit line connected to a memory cell. Therefore, unlike an amplifier that senses a voltage and amplifies the difference between the sensed voltages, a bit line sense amplifier senses a current and amplifies the difference between the sensed currents, and the sensed current is used to read these non-conventional memory devices.

[0030] Refer to Figure 1, the memory device 1000 may include a memory cell array 1100, a command / address (CA) buffer 1200, an address decoder 1300, a command decoder 1400, and an input / output (I / O) circuit 1500. The memory cell array 1100 may include bit line sense amplifiers 100. A detailed description of the memory device 1000 according to an embodiment of the present disclosure will be made with reference to Figure 1 A detailed description of the memory device 1000 according to an embodiment of the present disclosure will be made.

[0031] The memory cell array 1100 may include a plurality of memory cells. The plurality of memory cells may be connected to word lines and bit lines. In an embodiment, each of the plurality of memory cells may be a ferroelectric field effect transistor (FeFET) cell, but the present disclosure is not limited thereto. For example, each of the plurality of memory cells may be implemented with one of various types of memory cells such as phase RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and thyristor RAM (TRAM).

[0032] The memory cell array 1100 may be connected to a column decoder (Y-DEC 1600) through a plurality of bit lines, and may be connected to a row decoder (X-DEC 1700) through a plurality of word lines. The Y-DEC 1600 may control the plurality of bit lines under the control of the address decoder 1300. The X-DEC 1700 may control the plurality of word lines under the control of the address decoder 1300.

[0033] The bit line sense amplifiers 100 may be included in the memory cell array 1100. The bit line sense amplifiers 100 may read data from respective memory cells, or may write data into respective memory cells. The bit line sense amplifiers 100 may be connected to the bit lines of the memory cells. A detailed description of the bit line sense amplifiers 100 according to an embodiment of the present disclosure will be made with reference to Figures 2 to 11 A detailed description of the bit line sense amplifiers 100 according to an embodiment of the present disclosure will be made.

[0034] The command / address (CA) buffer 1200 may be configured to receive a command / address from an external device (e.g., a memory controller or a register clock driver RCD) through a command / address line CA, and temporarily store or buffer the signals input thereto.

[0035] The address decoder 1300 may be configured to receive an address signal ADDR from the command / address (CA) buffer 1200, and decode the received address signal ADDR. The address decoder 1300 may be configured to control the Y-DEC 1600 and the X-DEC 1700 based on the decoding result.

[0036] The command decoder 1400 may receive a command signal CMD from the command / address (CA) buffer 1200 and may decode the received command signal CMD. The command decoder 1400 may control components of the memory device 1000 based on the decoding result. For example, when the command signal CMD received from the command / address (CA) buffer 1200 corresponds to a write command, the command decoder 1400 may control the operation of the input / output circuit 1500 such that data received through the data lines DQ is written into the memory cell array 1100. Alternatively, when the command signal CMD received from the command / address (CA) buffer 1200 is a read command, the command decoder 1400 may control the operation of the input / output circuit 1500 such that data stored in the memory cell array 1100 is read out.

[0037] Through the data lines DQ / DQS, the input / output circuit 1500 may be configured to receive data from an external device (e.g., a memory controller) or transmit data to an external device. Under the control of the command decoder 1400, the input / output circuit 1500 may read data from the memory cell array 1100 or write data into the memory cell array 1100.

[0038] Figure 2 is a block diagram of a bit line sense amplifier 100 according to an embodiment of the present disclosure. Refer to Figure 2 , the bit line sense amplifier 100, the first memory cell MC1, and the second memory cell MC2 are shown. The first memory cell MC1 may be connected to the first word line WL1 and the first bit line BL, and the second memory cell MC2 may be connected to the second word line WL2 and the second bit line BLB.

[0039] The bit line sense amplifier 100 may be connected to two bit lines. For example, the bit line sense amplifier 100 may be connected to the first bit line BL connected to the first memory cell MC1 and the second bit line BLB connected to the second memory cell MC2. In an embodiment, the bit line sense amplifier 100 may sense and amplify the voltage levels or current levels of the first bit line BL and the second bit line BLB. For example, the bit line sense amplifier 100 may sense and amplify the levels of the current flowing into each of the first bit line BL and the second bit line BLB.

[0040] Hereinafter, the first current IB1 may refer to the current flowing into the first memory cell MC1 (or the current flowing through the first bit line BL) in response to the condition that the first word line WL1 is activated (e.g., the conduction voltage of the memory cell is applied to the first word line WL1). Similarly, the second current IB2 may refer to the current flowing into the second memory cell MC2 (or the current flowing through the second bit line BLB) in response to the condition that the second word line WL2 is activated (e.g., the conduction voltage of the memory cell is applied to the second word line WL2).

[0041] The bit line sense amplifier 100 can compare voltage levels or current levels and can amplify the difference between the voltage levels or current levels. In an embodiment, the bit line sense amplifier 100 can amplify the difference between the current levels of a first bit line BL and a second bit line BLB. For example, the bit line sense amplifier 100 can amplify the difference between a first current IB1 flowing to the first bit line BL and a second current IB2 flowing to the second bit line BLB. Figure 2 An example in which two bit lines are connected to the bit line sense amplifier 100 is shown, but the present disclosure is not limited thereto. For example, it should be understood that embodiments in which multiple pairs of bit lines are additionally connected to each of multiple memory cells also fall within the scope and spirit of the present invention. The bit line sense amplifier 100 according to an embodiment of the present disclosure will be described with reference to the following drawings.

[0042] Figure 3 is a detailed illustration of Figure 2 the bit line sense amplifier 100 according to an embodiment of the present disclosure. Referring to Figure 3 , the bit line sense amplifier 100 may include a first read / write circuit 110A, a second read / write circuit 110B, an equalization circuit 120, and an amplification circuit 130. Figure 3 The bit line sense amplifier 100 of Figure 2 can be connected to Figure 2 the first memory cell MC1 of Figure 3 through the first bit line BL, and can be connected to

[0043] the second memory cell MC2 of Figure 1 through the second bit line BLB. The bit line sense amplifier 100 according to an embodiment of the present disclosure will be described in detail with reference to

[0044] The first read / write circuit 110A or the second read / write circuit 110B can transfer the data stored in the memory cells MC1 and MC2 to Figure 1 the input / output circuit 1500, or can transfer the data to be written into the memory cells MC1 and MC2 to the memory cells MC1 and MC2. In an embodiment, the first read / write circuit 110A or the second read / write circuit 110B can transfer the data to be written into the memory cells MC1 and MC2 in the form of a voltage level. In an embodiment, the first read / write circuit 110A or the second read / write circuit 110B can transfer the data of the memory cells MC1 and MC2 to the input / output circuit 1500 in the form of a voltage level.

[0044] Hereinafter, for ease of description, the first write data WD1 may be data to be written into the first memory cell MC1, and the first read data RD1 may be data read from the first memory cell MC1. Similarly, the second write data WD2 may be data to be written into the second memory cell MC2, and the second read data RD2 may be data read from the second memory cell MC2.

[0045] The first read / write circuit 110A may be connected to opposite ends of the second NMOS transistor NM2 (e.g., the source and drain of the transistor, which may be collectively referred to as the opposite ends of the transistor). In the following description, the phrase "a transistor connected between two elements" means that a first one of the two elements is connected to one of the source / drain of the transistor, and a second one of the two elements is connected to the other of the source / drain of the transistor. For example, the first end and the second end (which may be collectively referred to as opposite ends) of the first read / write circuit 110A may be connected to the third node N13 and the fifth node N15, respectively. In an embodiment, the first read data RD1 from the first memory cell MC1 may be provided to the first read / write circuit 110A. For example, the first read data RD1 from the first memory cell MC1 may be provided to the first read / write circuit 110A based on the first data voltage level VD1 of the third node N13. In an embodiment, the first read / write circuit 110A may provide the second write data WD2 to the second memory cell MC2. For example, the first read / write circuit 110A may provide the second write data WD2 to the second memory cell MC2 based on the second bit line voltage level VB2 of the fifth node N15.

[0046] The second read / write circuit 110B may be connected to opposite ends of the first NMOS transistor NM1. For example, the opposite ends of the second read / write circuit 110B may be connected to the second node N12 and the fourth node N14, respectively. In an embodiment, the second read data RD2 from the second memory cell MC2 may be provided to the second read / write circuit 110B. For example, the second read data RD2 from the second memory cell MC2 may be provided to the second read / write circuit 110B based on the second data voltage level VD2 of the second node N12. In an embodiment, the second read / write circuit 110B may provide the first write data WD1 to the first memory cell MC1. For example, the second read / write circuit 110B may provide the first write data WD1 to the first memory cell MC1 based on the first bit line voltage level VB1 of the fourth node N14.

[0047] Reference will be made to Figure 4A and Figure 4BDescribe examples of read / write circuits such as the first read / write circuit 110A and / or the second read / write circuit 110B. Hereinafter, based on Figure 1 of the memory device 1000 read Figure 2 of the first memory cell MC1 or an embodiment of writing data to the first memory cell MC1 is described. This is provided as an example, and the present disclosure is not limited thereto. A description is given based on the case where the first read / write circuit 110A or the second read / write circuit 110B senses data based on the voltage levels of the second node N12 or the third node N13, but the present disclosure is not limited thereto. For example, it should be understood that embodiments in which data is exchanged based on the level of the current flowing to the second node N12 or the third node N13 also fall within the scope and spirit of the present invention.

[0048] The equalization circuit 120 can equalize the voltages of the second node N12 and the third node N13 of the amplifier circuit 130. The bit line sense amplifier 100 can perform a data read operation based on the operation of the equalization circuit 120. Reference will be made to Figure 5A and Figure 5B to describe the structure of the equalization circuit 120 in detail.

[0049] The amplifier circuit 130 can sense and amplify the current level of the bit line. Referring to Figure 3 , the amplifier circuit 130 can include a zero n-type metal oxide semiconductor field effect transistor (NMOS transistor) NM0, a first NMOS transistor NM1, a second NMOS transistor NM2, a first p-type metal oxide semiconductor field effect transistor (PMOS transistor) PM1, and a second PMOS transistor PM2.

[0050] In an embodiment, the amplifier circuit 130 can sense a first current IB1 and a second current IB2. For example, the amplifier circuit 130 can sense the first current IB1 passing through the fourth node N14, and can sense the second current IB2 passing through the third node N13. In an embodiment, the amplifier circuit 130 can amplify the difference between the first current IB1 and the second current IB2, and the bit line sense amplifier 100 can sense the data stored in the memory cells MC1 and MC2 based on the amplification of the amplifier circuit 130.

[0051] Referring to Figure 3, the zero-th NMOS transistor NM0 can be connected between the power node NP and the first node N11, and can operate in response to a control signal CS (for example, the control signal CS can be sent to the gate of the zero-th NMOS transistor NM0). In the following description, when current passes through a transistor between the source and the drain, the transistor can be said to be "operating". An NMOS transistor can operate in response to a positive voltage difference between the source / drain and the gate exceeding a threshold, while a PMOS transistor can operate in response to a negative voltage difference between the gate and the source / drain exceeding a threshold. When a signal is applied to a transistor, the voltage of the signal can be applied to the gate of the transistor to operate the transistor. The control signal CS will be described in detail with reference to Figure 6 In an embodiment, the voltage applied to the power node NP can be an internal voltage VINT such as provided by a power supply to a memory cell. When the zero-th NMOS transistor NM0 is turned on (for example, the control signal activates the zero-th NMOS transistor NM0), the zero-th NMOS transistor NM0 can supply power to the first node N11 (for example, form a circuit path between the power node NP and the first node N11), and thus, can perform the amplification operation of the amplifier circuit 130.

[0052] The first PMOS transistor PM1 can be connected between the first node N11 and the third node N13, and the gate node of the first PMOS transistor PM1 can be connected to the second node N12. The first PMOS transistor PM1 can operate in response to the second data voltage level VD2. Similarly, the second PMOS transistor PM2 can be connected between the first node N11 and the second node N12, and the gate node of the second PMOS transistor PM2 can be connected to the third node N13. The second PMOS transistor PM2 can operate in response to the first data voltage level VD1.

[0053] The first NMOS transistor NM1 can be connected between the second node N12 and the fourth node N14, and the gate node of the first NMOS transistor NM1 can be connected to the third node N13. That is, the first NMOS transistor NM1 can operate in response to the first data voltage level VD1. The second NMOS transistor NM2 can be connected between the third node N13 and the fifth node N15, and the gate node of the second NMOS transistor NM2 can be connected to the second node N12. That is, the second NMOS transistor NM2 can operate in response to the second data voltage level VD2. In an embodiment, the first NMOS transistor NM1 or the second NMOS transistor NM2 can clamp the first data voltage level VD1 or the second data voltage level VD2 before being supplied with power via the zero-th NMOS transistor NM0. The operation of the amplifier circuit 130 will be described in detail with reference to Figure 6 together.

[0054] The description is based on the case where the bit line sense amplifier is connected to two memory cells MC1 and MC2, with reference to Figure 3 the structure of the bit line sense amplifier described herein and the bit line sense amplifier to be described later. However, the present disclosure is not limited thereto. It should be understood that embodiments in which multiple memory cells are connected to a first bit line BL and a second bit line BLB also fall within the scope and spirit of the present invention. In addition, the description is given based on the case where the bit line sense amplifier 100 senses a pair of bit lines BL and BLB disposed on its opposite sides. However, it should be understood that embodiments in which multiple bit line sense amplifiers having the same structure as the bit line sense amplifier 100 (refer to Figure 3 ) are provided for each of the multiple bit lines also fall within the scope and spirit of the present invention. Figure 2

[0055] Figure 4A and Figure 4B are circuit diagrams showing in detail the second read / write circuit 110B according to an embodiment of the present disclosure. Figure 3 Figure 4A and Figure 4B may be collectively referred to as "FIG. 4". The circuit according to an embodiment of the present disclosure for writing data into Figure 2 the memory cells MC1 and MC2 or reading data from the memory cells MC1 and MC2 will be described in detail with reference to FIG. 4. FIG. 4 shows the second read / write circuit 110B, and the description is based on the second read / write circuit 110B. However, it should be understood that the first read / write circuit 110A is also implemented with the same structure as the second read / write circuit 110B (for example, the first read / write circuit 110A and the second read / write circuit 110B may have the same structure).

[0056] In an embodiment, the input / output circuit IO may correspond to Figure 1 the input / output circuit 1500. In another embodiment, the input / output circuit IO may be located between Figure 1 the input / output circuit 1500 and the bit line sense amplifier 100 to transfer the read data to Figure 1 the input / output circuit 1500 or transfer the write data provided by Figure 1 the input / output circuit 1500 to each node (e.g., the fourth node N14 or the fifth node N15).

[0057] Refer to Figure 3 and Figure 4A, in some embodiments, the second read / write circuit 110B may include a first NMOS transistor NM11 and a second NMOS transistor NM12. The first NMOS transistor NM11 may be connected between the second node N12 and the input / output circuit IO, and may operate in response to a read enable signal RE. The second NMOS transistor NM12 may be connected between the second node N12 and the fourth node N14, and may operate in response to a write enable signal WE.

[0058] The first NMOS transistor NM11 may provide second read data RD2 from the second node N12 to the input / output circuit IO in response to the read enable signal RE. The second NMOS transistor NM12 may provide first write data WD1 to the fourth node N14 in response to the write enable signal WE. In this case, the first NMOS transistor NM11 may be turned on, connecting the second node N12 to the input / output circuit IO.

[0059] Similar to the second read / write circuit 110B, the first read / write circuit 110A may include a first NMOS transistor and a second NMOS transistor. The first NMOS transistor of the first read / write circuit 110A may operate in response to the read enable signal RE and may be connected between the input / output circuit and the third node N13. The second NMOS transistor of the first read / write circuit 110A may be connected between the third node N13 and the fifth node N15, and may operate in response to the write enable signal WE.

[0060] Referring to Figure 3 and Figure 4B , similar to the embodiments described with reference to Figure 4A , in some embodiments, the second read / write circuit 110B may include a first NMOS transistor NM11 and a second NMOS transistor NM12. The first NMOS transistor NM11 may be connected between the second node N12 and the input / output circuit IO, and may operate in response to a read enable signal RE. The second NMOS transistor NM12 may be connected between the fourth node N14 and the input / output circuit IO, and may operate in response to a write enable signal WE. The input / output circuit IO may correspond to Figure 1 the input / output circuit 1500, or may be an input / output circuit between the input / output circuit 1500 of Figure 1 and the bit line sense amplifier 100.

[0061] The first NMOS transistor NM11 can provide second read data RD2 from the second node N12 to the input / output circuit IO in response to a read enable signal RE. The second NMOS transistor NM12 can provide first write data WD1 from the input / output circuit IO to the fourth node N14 in response to a write enable signal WE.

[0062] Similar to the second read / write circuit 110B, the first read / write circuit 110A can include a first NMOS transistor and a second NMOS transistor. The first NMOS transistor of the first read / write circuit 110A can operate in response to a read enable signal RE and can be connected between the input / output circuit and the third node N13. The second NMOS transistor of the first read / write circuit 110A can be connected between the fifth node N15 and the input / output circuit and can operate in response to a write enable signal WE.

[0063] Figure 5A and Figure 5B are circuit diagrams showing an Figure 3 equalization circuit 120 according to an embodiment of the present disclosure. Figure 5A and Figure 5B can be collectively referred to as "Figure 5". Referring to Figure 5, the equalization circuit 120 can include a first NMOS transistor NM21 and a second NMOS transistor NM22. The equalization circuit 120 according to an embodiment of the present disclosure will be described in detail with reference to Figure 5.

[0064] Referring together to Figure 3 and Figure 5A , the first NMOS transistor NM21 can be connected between the equalization node NE and the second node N12 and can operate in response to an equalization signal PEQ. The second NMOS transistor NM22 can be connected between the equalization node NE and the third node N13 and can operate in response to an equalization signal PEQ.

[0065] In an embodiment, the voltage of the equalization node NE can be an equalization voltage VEQ. The second data voltage level VD2 of the second node N12 and the first data voltage level VD1 of the third node N13 can be equalized based on Figure 5A the operation of the equalization circuit 120. For example, the first data voltage level VD1 and the second data voltage level VD2 can be equalized with the equalization voltage VEQ based on the operation of the equalization circuit 120.

[0066] Referring to Figure 3 and Figure 5B, a first NMOS transistor NM21 can be connected between an equalization node NE and a second node N12, and can operate in response to an equalization signal PEQ. A second NMOS transistor NM22 can be connected between the second node N12 and a third node N13, and can operate in response to the equalization signal PEQ.

[0067] In an embodiment, the voltage of the equalization node NE can be an equalization voltage VEQ. The second data voltage level VD2 of the second node N12 and the first data voltage level VD1 of the third node N13 can be equalized based on Figure 5B the operation of the equalization circuit 120 and the equalization voltage VEQ. Figure 5B It is described based on an embodiment where the first NMOS transistor NM21 is connected to the second node N12, but the present disclosure is not limited thereto. For example, it should be understood that the first NMOS transistor NM21 being connected between the third node N13 and the equalization node NE also falls within the scope and spirit of the present invention.

[0068] Hereinafter, for the sake of convenience of description, the read operation or write operation will be described based on Figure 2 a first memory cell MC1. A second memory cell MC2 can be a reference cell, and a reference cell can refer to a cell used to determine the data stored in a memory cell. In an embodiment, the current flowing through the second memory cell MC2 turned on by a word line can be a reference current for determining data 1 or data 0 (for example, the low or high bit in a memory cell). "LOW (low)" can indicate the value (e.g., voltage level) of a signal for turning off a transistor or memory cell operating in response to a signal, and "HIGH (high)" can indicate the value (e.g., voltage level) of a signal for turning on a transistor or memory cell operating in response to a signal. In an embodiment, the magnitude of the current flowing into (or through) a memory cell when data 1 is stored in the memory cell can be greater than the magnitude of the current flowing into (or through) the memory cell when data 0 is stored in the memory cell. Hereinafter, a description will be given based on an embodiment where the magnitude of the current flowing into (or through) a memory cell when data 1 is stored in the memory cell is greater than the magnitude of the current flowing into (or through) the memory cell when data 0 is stored in the memory cell, but the present disclosure is not limited thereto.

[0069] Figure 6 is a timing diagram according to an embodiment of the present disclosure, which shows various voltages and signals that change during the operation of the bit line sense amplifier described with respect to Figure 2 to FIG. 5. The operation of the bit line sense amplifier 100 according to an embodiment of the present disclosure will be described in detail with reference to Figures 2 to 6 The operation of the bit line sense amplifier 100 according to an embodiment of the present disclosure will be described based on the case where data 1 is stored in the first memory cell MC1. Figure 6, but the present disclosure is not limited thereto. For example, it should be understood that embodiments in which data 0 is stored in the first memory cell MC1 or embodiments in which the first memory cell MC1 is a reference cell and a read operation or a write operation is performed on the second memory cell MC2 also fall within the scope and spirit of the present invention. In Figure 6 Since the data read operation of the first memory cell MC1 is performed by the bit line sense amplifier 100, the write enable signal WE can remain LOW during the entire operation. In an embodiment, the read enable signal RE can have HIGH during the entire operation or during the sensing period.

[0070] Referring to Figure 3 and Figure 6 , the period from t10 to t11 as the starting time point can be a precharge period. Before the first time point t11, based on the precharge operation of the bit line sense amplifier 100, the first data voltage level VD1 and the second data voltage level VD2 can reach the equilibrium voltage VEQ. The operation of the bit line sense amplifier 100 during the precharge period will be described in detail in the period from the fourth time point t14 to the fifth time point t15. In Figure 6 , signals before the waveform patterns of the respective signals are provided as examples, but the present disclosure is not limited thereto. For example, it should be understood that the signals are shown to illustrate the states or voltage levels of the respective signals when reaching the first time point t11.

[0071] The period from t11 to t12 can be a bit line sampling period. Referring together to Figure 2 , during the bit line sampling period, the word lines WL1 and WL2 can be HIGH. When the word lines WL1 and WL2 are HIGH, current (i.e., the first current IB1 and the second current IB2) can start to flow in the memory cells MC1 and MC2.

[0072] The bit line sense amplifier 100 can sense the first current IB1 and the second current IB2 passing through the two bit lines BL and BLB and the NMOS transistors NM1 and NM2. The first data voltage level VD1 can decrease in response to the first current IB1, and the second data voltage level VD2 can decrease in response to the second current IB2 (i.e., current flows in a state where a separate external power supply is not applied to the NMOS transistors, so charge is depleted when the current flows from it).

[0073] Since data 1 is present in the first memory cell MC1, the magnitude of the first current IB1 may be greater than the magnitude of the second current IB2. Therefore, the rate at which the second data voltage level VD2 is decreased by the first current IB1 may be faster than the rate at which the first data voltage level VD1 is decreased by the second current IB2. During the bit line sampling period, the equalization signal PEQ may be LOW, and the control signal CS may also be LOW.

[0074] In an embodiment, at the second time point t12 which is the end point of the bit line sampling period, the second NMOS transistor NM2 may be turned off. Since the word line is activated and the first current IB1 flows through the first NMOS transistor NM1, the second data voltage level VD2 may be decreased. When the voltage between the fifth node N15 and the second node N12 is less than the threshold of the second NMOS transistor NM2, the second NMOS transistor NM2 may be turned off. Therefore, at the second time point t12, the second NMOS transistor NM2 is turned off, and the first data voltage level VD1 may be clamped (e.g., maintained at a nearly constant value).

[0075] The period from t12 to t13 may be a clamping period. The first data voltage level VD1 may maintain the voltage level at the second time point t12 during the entire clamping period. The second data voltage level VD2 may continuously decrease during the entire clamping period. Since the first data voltage level VD1 is clamped, the first NMOS transistor NM1 remains in the conducting state, and therefore, the first current IB1 flows through the first NMOS transistor NM1.

[0076] As the first data voltage level VD1 is clamped and the second data voltage level VD2 continues to decrease, the voltage difference dVD between the voltage level of the first data voltage level VD1 and the voltage level of the second data voltage level VD2 may gradually increase. During the clamping period, the word lines WL1 and WL2 may remain HIGH, and the equalization signal PEQ and the control signal CS may remain LOW as in the bit line sampling period.

[0077] The period from t13 to t14 may be a sensing period. At the third time point t13, the amplifier circuit 130 may start the amplification operation. The equalization signal PEQ may remain LOW, the control signal CS may transition to HIGH, and the word lines WL1 and WL2 may be set to LOW.

[0078] In an embodiment, the zero-th NMOS transistor NM0 may be turned on at the third time point t13. For example, the zero-th NMOS transistor NM0 may be turned on in response to the control signal CS transitioning to HIGH at the third time point t13. When the zero-th NMOS transistor NM0 is turned on, the zero-th NMOS transistor NM0 may supply power to the amplifier circuit 130. For example, when the zero-th NMOS transistor NM0 is turned on, a power supply voltage level may be provided to the first node N11, and in response thereto, power may be provided to the amplifier circuit 130.

[0079] When power is supplied to the amplifier circuit 130, the amplifier circuit 130 may start amplifying the voltage difference dVD between the voltage level of the first data voltage level VD1 and the voltage level of the second data voltage level VD2. Specifically, the first PMOS transistor PM1 and the second PMOS transistor PM2 may be turned on in response to the internal voltage VINT being applied to the first node N11 (for example, the voltage difference between the gate of the first PMOS transistor PM1 (which is VD2) and VINT may be negative, and the voltage difference between the gate of the second PMOS transistor PM2 (which is VD1) and VINT may be negative, that is, VD2 < VINT and VD1 < VINT). When the first PMOS transistor PM1 and the second PMOS transistor PM2 are turned on, the amplifier circuit 130 may amplify the voltage difference dVD between the voltage level of the first data voltage level VD1 and the voltage level of the second data voltage level VD2. During the sensing period, the first data voltage level VD1 may become higher than the data voltage level at the third time point t13 and then may be uniformly maintained; the second data voltage level VD2 may become lower than the data voltage level at the third time point t13 and then may be uniformly maintained.

[0080] During the sensing period, the bit line sense amplifier 100 may determine the data stored in the memory cells MC1 and MC2. In an embodiment, the bit line sense amplifier 100 may determine the data of the first memory cell MC1 based on the relationship between the determination voltage level DV and the first data voltage level VD1 corresponding to the first memory cell MC1. For example, when the first data voltage level VD1 is greater than the determination voltage level DV, the bit line sense amplifier 100 may determine that data 1 is stored in the first memory cell MC1. In another example, different from Figure 6 the example shown in, when data 0 is stored in the first memory cell MC1, the bit line sense amplifier 100 may determine that data 0 is stored in the first memory cell MC1 based on the condition that the first data voltage level VD1 is less than the determination voltage level DV.

[0081] The period from t14 to t15 can be a pre-charge period. At the fourth time point t14, the equalization signal PEQ can change from LOW to HIGH, and the control signal CS can change from HIGH to LOW. In an embodiment, during the pre-charge period, the difference between the threshold voltage of the first NMOS transistor NM1 and the threshold voltage of the second NMOS transistor NM2 can be applied to the bit line voltage levels VB1 and VB2.

[0082] For example, the voltages of the second node N12 and the third node N13 can change to the equalization voltage VEQ in response to the equalization signal PEQ, and the voltage levels of the gate nodes and the drain nodes of each of the first NMOS transistor NM1 and the second NMOS transistor NM2 are equalized. The first NMOS transistor NM1 and the second NMOS transistor NM2 effectively form diode connections. The source node of each of the first NMOS transistor NM1 and the second NMOS transistor NM2 that effectively form diode connections can have a voltage level that is at least as small as the threshold voltage compared to the voltage level of the gate node. For example, the first bit line voltage level VB1 and the second bit line voltage level VB2 are the same as the voltage levels obtained by subtracting the threshold voltage of the first NMOS transistor NM1 and the threshold voltage of the second NMOS transistor NM2 from the first data voltage level VD1 and the second data voltage level VD2, respectively. In the above manner, the offset information (e.g., the threshold voltage information of each of the first NMOS transistor NM1 and the second NMOS transistor NM2) of each of the first NMOS transistor NM1 and the second NMOS transistor NM2 can be applied to the bit line voltage levels VB1 and VB2.

[0083] According to the operation described with reference to Figures 2 to 6 the operation described, the bit line sense amplifier 100 can perform operations on the remaining memory cells except the first memory cell MC1 at the first time point t11 to the fifth time point t15, and can transfer the data stored in the relevant memory cells to the input / output circuit 1500 or IO. Similarly, even when the data 0 is stored in the first memory cell MC1, the data can be transferred to the input / output circuit 1500 or IO to be read using the same method as described above. However, in the case of performing a read operation on the first memory cell MC1 in which the data 0 is stored, Figure 6 the waveforms of the first data voltage level VD1 and the second data voltage level VD2 can be changed with respect to each other. That is, during the clamping period, the second data voltage level VD2 can be clamped to the equalization voltage VEQ, and the first data voltage level VD1 can be reduced; after the amplification operation in the sensing period, the bit line sense amplifier 100 can determine that the data 0 is stored in the first memory cell MC1 based on the condition that the first data voltage level VD1 is less than the determination voltage level DV.

[0084] Based on the above operations, the bit line sense amplifier 100 can transfer data stored in the memory cell to the input / output circuit 1500 or the IO. The bit line sense amplifier 100 according to an embodiment of the present disclosure can directly sense the current flowing through the first bit line BL and the second bit line BLB in a state where the first bit line BL and the second bit line BLB are not directly connected to the gate nodes of the transistors included in the bit line sense amplifier 100 (i.e., in a state where the first bit line BL and the second bit line BLB are connected to the source nodes of the first NMOS transistor NM1 and the second NMOS transistor NM2). The bit line sense amplifier 100 can convert the difference between the sensed currents into a voltage level (e.g., the first data voltage level VD1 or the second data voltage level VD2) based on the difference between the sensed currents, such that the data is transferred to the input / output circuit 1500 or the IO. The bit line sense amplifier 100 can read data more quickly by removing the offsets of the first NMOS transistor NM1 and the second NMOS transistor NM2 during a precharge period. Figure 6 shown in and with reference to Figure 6 The time points t10 to t15 described indicate a time sequence, but should not be construed as Figure 6 The time intervals between the time points t10 to t15 shown in indicate the relative time lengths for performing actual operations.

[0085] With reference to Figures 2 to 6 The bit line sense amplifier 100 described can write data to the first memory cell MC1 through the second read / write circuit 110B. In this case, since the equalization operation and the sensing operation are not required, both the equalization signal PEQ and the control signal CS can be LOW. The write enable signal WE of the second read / write circuit 110B in the bit line sense amplifier 100 can be set to HIGH to provide the data (e.g., data 1 or data 0) to be written to the first memory cell MC1.

[0086] Figure 7 is a flowchart showing the read operation sequence of the bit line sense amplifier 100 according to an embodiment of the present disclosure. The read operation sequence of the bit line sense amplifier 100 according to an embodiment of the present disclosure will be described with reference to Figure 3 Figures 2 to 7 The read operation sequence of the bit line sense amplifier 100 according to an embodiment of the present disclosure will be described.

[0087] With reference to Figures 2 to 7 , in operation S110, the bit line sense amplifier 100 can perform a precharge and offset cancellation operation. For example, when the equalization voltage VEQ is provided to the second node N12 and the third node N13 via the equalization circuit 120 of FIG. 4, the precharge operation can be performed.

[0088] The first NMOS transistor NM1 and the second NMOS transistor NM2 may have an effective diode-connected structure depending on the pre-charge operation. The first bit line voltage level VB1 may have a voltage level obtained by subtracting the threshold voltage of the first NMOS transistor NM1 from the equalization voltage VEQ, and similarly, the second bit line voltage level VB2 may have a voltage level obtained by subtracting the threshold voltage of the second NMOS transistor NM2 from the equalization voltage VEQ. An offset cancellation operation may be performed based on the formation of the first bit line voltage level VB1 and the second bit line voltage level VB2 (e.g., the difference between the threshold voltage of the first NMOS transistor NM1 and the threshold voltage of the second NMOS transistor NM2 may be removed).

[0089] In operation S120, the bit line sense amplifier 100 may sense the current flowing into each of the first NMOS transistor NM1 and the second NMOS transistor NM2. In this case, the conduction voltage may be applied to the word lines WL1 and WL2 connected to the memory cells MC1 and MC2. In an embodiment, the bit line sense amplifier 100 may sense the first current IB1 and the second current IB2 through the source terminals of the transistors included in the amplifier circuit 130. The bit line sense amplifier 100 may sense the first current IB1 flowing to the first bit line BL through the source terminal of the first NMOS transistor NM1 (i.e., through the fourth node N14), and may sense the second current IB2 flowing to the second bit line BLB through the source terminal of the second NMOS transistor NM2 (i.e., through the fifth node N15).

[0090] In operation S130, the bit line sense amplifier 100 may clamp the first data voltage level VD1. For example, when data 1 is stored in the first memory cell MC1, since the first current IB1 flows to the first NMOS transistor NM1, the second data voltage level VD2 may decrease (e.g., since the first current IB1 is greater than the second current IB2, it may decrease at a rate higher than the first data voltage level VD1). The second NMOS transistor NM2 may turn off in response to the decrease in the second data voltage level VD2. When the second NMOS transistor NM2 is turned off, the first data voltage level VD1 may be clamped without a voltage change.

[0091] Again, for example, when data 0 is stored in the first memory cell MC1, since the second current IB2 flows to the second NMOS transistor NM2, the first data voltage level VD1 may decrease (e.g., since the second current IB2 is greater than the first current IB1, it may decrease at a rate higher than the second data voltage level VD2), and the first NMOS transistor NM1 may turn off in response thereto. When the first NMOS transistor NM1 is turned off, the second data voltage level VD2 may be clamped.

[0092] In operation S140, the bit line sense amplifier 100 may amplify the difference between the first data voltage level VD1 and the second data voltage level VD2. The bit line sense amplifier 100 may perform the amplification operation through the amplification circuit 130. For example, when a power supply voltage is supplied to the first node N11, the bit line sense amplifier 100 may supply power to the amplification circuit 130 and may amplify the difference between the first data voltage level VD1 and the second data voltage level VD2.

[0093] In operation S150, the bit line sense amplifier 100 may determine the data of the memory cell based on the thus amplified first data voltage level VD1. For example, referring together Figure 6 , when data 1 is stored in the first memory cell MC1, the bit line sense amplifier 100 may determine that data 1 is stored in the first memory cell MC1 based on the condition that the first data voltage level VD1 is greater than the determination voltage level DV. Again, for example, when data 0 is stored in the first memory cell MC1, the bit line sense amplifier 100 may determine that data 0 is stored in the first memory cell MC1 based on the condition that the first data voltage level VD1 is less than the determination voltage level DV.

[0094] The bit line sense amplifier 100 may read the data stored in the first memory cell MC1 based on the above operations. The case where the second memory cell MC2 is a reference cell and data is read from the first memory cell MC1 is shown and described Figure 7 , but the present disclosure is not limited thereto. For example, it should be understood that an embodiment in which the first memory cell MC1 is a reference cell and data is read from the second memory cell MC2 also belongs to the scope and spirit of the present invention.

[0095] Figure 8 is a circuit diagram of a bit line sense amplifier according to an embodiment of the present disclosure. Referring to Figure 2 , the bit line sense amplifier 200 may include a first read / write circuit 210A, a second read / write circuit 210B, an equalization circuit 220, and an amplification circuit 230. The bit line sense amplifier 200 according to an embodiment of the present disclosure will be described with reference to Figure 8 , Figure 2 and Figure 8 .

[0096] The first read / write circuit 210A or the second read / write circuit 210B may correspond to Figure 3the first read / write circuit 110A or the second read / write circuit 110B. For example, the first read / write circuit 210A may be provided with the first read data RD1 or may provide the second write data WD2, and the second read / write circuit 210B may be provided with the second read data RD2 or may provide the first write data WD1. The structure of the first read / write circuit 210A or the second read / write circuit 210B may be the same as that of FIG. 4, and the operation of the first read / write circuit 210A or the second read / write circuit 210B may be the same as or similar to the operation of the first read / write circuit 110A or the second read / write circuit 110B described with reference to Figures 1 to 7 The operation of the first read / write circuit 110A or the second read / write circuit 110B is the same or similar.

[0097] The equalization circuit 220 may equalize the voltages of the second node N22 and the third node N23. Referring to Figure 8 , the equalization circuit 220 may include a first transistor 221 and a second transistor 222. The first transistor 221 may operate in response to an equalization signal PEQ and may be connected between an equalization node NE and the first node N21. The second transistor 222 may operate in response to the equalization signal PEQ and may be connected between the second node N22 and the third node N23.

[0098] The first transistor 221 may provide a specific voltage level to the first node N21 in response to the equalization signal PEQ. In an embodiment, the voltage of the equalization node NE may be an equalization voltage VEQ. For example, the first transistor 221 may be turned on in response to the equalization signal PEQ, and the equalization voltage VEQ may be provided to the first transistor 221.

[0099] In this case, as the difference between the second data voltage level VD2 and the voltage level of the first node N21 increases, the first PMOS transistor PM1 may be turned on. When the first PMOS transistor PM1 is turned on, the first data voltage level VD1 may become the voltage level of the first node N21. For example, the first PMOS transistor PM1 may be turned on, and thus, the first data voltage level VD1 may become the equalization voltage VEQ.

[0100] The second transistor 222 may be turned on in response to the equalization signal PEQ so that the voltage levels of the second node N22 and the third node N23 are equalized. For example, the second transistor 222 may be turned on in response to the equalization signal PEQ so that the second data voltage level VD2 of the second node N22 becomes the equalization voltage VEQ. After the precharge operation, based on the above structure and operation, the equalization circuit 220 may equalize the first data voltage level VD1 and the second data voltage level VD2 with the equalization voltage VEQ.

[0101] The amplifier circuit 230 may amplify the difference between a first data voltage level VD1 and a second data voltage level VD2 generated based on current sensing of bit lines BL and BLB. The amplifier circuit 230 may correspond to Figure 3 the amplifier circuit 130. The operation of the amplifier circuit 230 may be similar to that of the amplifier circuit 130 described with reference to Figures 3 to 7 . That is, the amplifier circuit 230 may transmit data of the first memory cell MC1 or the second memory cell MC2 to the first read / write circuit 210A or the second read / write circuit 210B, or may receive data to be written to the first memory cell MC1 or the second memory cell MC2 from the first read / write circuit 210A or the second read / write circuit 210B and provide it to the amplifier circuit 230.

[0102] In an embodiment, the amplifier circuit 230 may include a plurality of transistors. For example, the amplifier circuit 230 may include three NMOS transistors NM0, NM1, and NM2 and two PMOS transistors PM1 and PM2. The NMOS transistors NM0, NM1, and NM2 and the PMOS transistors PM1 and PM2 of the amplifier circuit 230 may respectively correspond to Figure 3 the NMOS transistors NM0, NM1, and NM2 and the PMOS transistors PM1 and PM2, and may have the same connection structure as the Figure 3 NMOS transistors NM0, NM1, and NM2 and the PMOS transistors PM1 and PM2. For example, the first PMOS transistor PM1 may include a gate node connected to the second node N22 and may be connected between the first node N21 and the third node N23. Again, for example, the first NMOS transistor NM1 may include a gate node connected to the third node N23 and may be connected between the second node N22 and the fourth node N24.

[0103] Figure 8 The bit line sense amplifier 200 of Figure 6 and Figure 7 may sense the data of the memory cells MC1 and MC2 in the same manner as described. For example, during a precharge period, the bit line sense amplifier 200 may equalize the first data voltage level VD1 and the second data voltage level VD2 with an equalization voltage VEQ in response to the equalization signal PEQ transitioning to HIGH; the bit line sense amplifier 200 may determine the data stored in the first memory cell MC1 or the second memory cell MC2 by sequentially performing the Figure 6 sampling period, clamping period, and sensing period operations.

[0104] Figure 9 is a circuit diagram showing a Figure 2 bit line sense amplifier according to an embodiment of the present disclosure. Refer toFigure 9 , the bit line sense amplifier 300 may include a first read / write circuit 310A, a second read / write circuit 310B, an equalization circuit 320, a first amplifier circuit 330, and a second amplifier circuit 340. Reference will be made to Figure 2 and Figure 9 for a detailed description of the bit line sense amplifier 300 according to an embodiment of the present disclosure.

[0105] The first read / write circuit 310A or the second read / write circuit 310B may correspond to Figure 3 the first read / write circuit 110A or the second read / write circuit 110B. For example, the first read / write circuit 310A may be provided with first read data RD1 or may provide second write data WD2, and the second read / write circuit 310B may be provided with second read data RD2 or may provide first write data WD1. The structure of the first read / write circuit 310A or the second read / write circuit 310B may be the same as that of FIG. 4, and the operation of the first read / write circuit 310A or the second read / write circuit 310B may be the same as or similar to the operation of the first read / write circuit 110A / 210A or the second read / write circuit 110B / 210B described with reference to Figure 3 , FIG. 4, and Figures 6 to 8 described.

[0106] The equalization circuit 320 may equalize the voltage of the second node N32 and the voltage of the third node N33. The equalization circuit 320 may correspond to Figure 3 the equalization circuit 120, and may include the structure of the equalization circuit 120 of FIG. 5. The operation of the equalization circuit 320 may be the same as or similar to the operation of the equalization circuit 120 / 220 described with reference to Figure 3 , FIGS. 5 to Figure 8 described.

[0107] The first amplifier circuit 330 may amplify the difference between a first data voltage level VD1 and a second data voltage level VD2 generated based on the current of the bit line BL and the current of the BLB. The first amplifier circuit 330 may correspond to Figure 3 the amplifier circuit 130 or Figure 8 the amplifier circuit 230. The operation of the first amplifier circuit 330 may be the same as or similar to the operation of the amplifier circuit 130 / 230 described with reference to Figures 3 to 8 described. That is, the first amplifier circuit 330 may transfer the data of the first memory cell MC1 or the second memory cell MC2 to the first read / write circuit 310A or the second read / write circuit 310B, or may provide the data to be written to the first memory cell MC1 or the second memory cell MC2 from the first read / write circuit 310A or the second read / write circuit 310B to the first amplifier circuit 330.

[0108] In an embodiment, the first amplifier circuit 330 may include a plurality of transistors. For example, the first amplifier circuit 330 may include three NMOS transistors NM0, NM1, and NM2 and two PMOS transistors PM1 and PM2. The NMOS transistors NM0, NM1, and NM2 and the PMOS transistors PM1 and PM2 of the first amplifier circuit 330 may respectively correspond to Figure 3 the NMOS transistors NM0, NM1, and NM2 and the PMOS transistors PM1 and PM2 of Figure 3 , and may have the same connection structure as the NMOS transistors NM0, NM1, and NM2 and the PMOS transistors PM1 and PM2 of

[0109] The second amplifier circuit 340 may be connected to the first amplifier circuit 330 and may be implemented to connect the first bit line BL and the second bit line BLB to the first amplifier circuit 330. In an embodiment, based on the connection to the source extreme of the transistors included in the first amplifier circuit 330, the second amplifier circuit 340 may be connected to the first amplifier circuit 330. For example, the seventh node N37 of the second amplifier circuit 340 may be connected to the fourth node N34 which is the source extreme of the first NMOS transistor NM1 included in the first amplifier circuit 330. Similarly, the eighth node N38 of the second amplifier circuit 340 may be connected to the fifth node N35 which is the source extreme of the second NMOS transistor NM2 included in the first amplifier circuit 330. The second amplifier circuit 340 may be connected to the first amplifier circuit 330 based on the connection between the nodes. Based on the connection to the first amplifier circuit 330, the second amplifier circuit 340 may connect the first amplifier circuit 330 to the first bit line BL and the second bit line BLB, or may connect the first amplifier circuit 330 to the memory cells MC1 and MC2 through the bit lines BL and BLB.

[0110] The second amplifier circuit 340 may accelerate the amplification of the difference between the first data voltage level VD1 and the second data voltage level VD2 of the first amplifier circuit 330. In an embodiment, the second amplifier circuit 340 may disconnect the bit line sense amplifier 300 from the bit lines BL and BLB. Refer to Figure 9, the second amplifier circuit 340 may include a third NMOS transistor NM3 to a seventh NMOS transistor NM7. The operation of the second amplifier circuit 340 will be described in detail together with the third NMOS transistor NM3 to the seventh NMOS transistor NM7.

[0111] The third NMOS transistor NM3 may connect the second amplifier circuit 340 and the ground node. The third NMOS transistor NM3 may be connected between the ground node and the sixth node N36; similar to the zero-th NMOS transistor NM0, the third NMOS transistor NM3 may operate in response to the second control signal CS2. When the third NMOS transistor NM3 is turned on, the second amplifier circuit 340 may start to accelerate the amplification of the difference between the first data voltage level VD1 and the second data voltage level VD2 of the first amplifier circuit 330.

[0112] The fourth NMOS transistor NM4 may be connected between the sixth node N36 and the seventh node N37 connected to the fourth node N34, and may operate in response to the second control signal CS2. The fifth NMOS transistor NM5 may be connected between the sixth node N36 and the eighth node N38 connected to the fifth node N35, and may operate in response to the second control signal CS2. The fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 may accelerate the amplification of the difference between the first data voltage level VD1 and the second data voltage level VD2 of the first amplifier circuit 330.

[0113] The sixth NMOS transistor NM6 may be connected between the seventh node N37 and the first bit line BL, and may operate in response to the first control signal CS1. The first control signal CS1 and the second control signal CS2 may be complementary to each other. For example, when the second control signal CS2 is HIGH, the first control signal CS1 may be LOW; when the second control signal CS2 is LOW, the first control signal CS1 may be HIGH. The second control signal CS2 may correspond to Figure 3 and Figures 6 to 8 the control signal CS.

[0114] The seventh NMOS transistor NM7 may be connected between the eighth node N38 and the second bit line BLB, and may operate in response to the first control signal CS1. The sixth NMOS transistor NM6 and the seventh NMOS transistor NM7 may disconnect the bit line sense amplifier 300 from the bit lines BL and BLB. Therefore, the bit line sense amplifier 300 may accelerate the amplification of the difference between the first data voltage level VD1 and the second data voltage level VD2. The operation of the second amplifier circuit 340 will be described in detail with reference to Figure 10 in detail.

[0115] Figure 10 is a timing diagram according to an embodiment of the present disclosure, which shows that inFigure 9 how signals and voltages change over time during the read operation of the bit line sense amplifier 300. Reference will be made to Figure 2 FIG. 4, FIG. 5, Figure 9 and Figure 10 to describe an example of the read operation of the bit line sense amplifier 300 according to an embodiment of the present disclosure. The description will be based on the case where data 1 is stored in the first memory cell MC1, Figure 10 but the present disclosure is not limited thereto. In Figure 10 , since the bit line sense amplifier 300 performs a read operation, the write enable signal WE may be LOW throughout the operation.

[0116] The period from t20 to t21 may be a precharge period. During the precharge period, since the bit line sense amplifier 300 performs the same operation as described with reference to Figure 6 , the first data voltage level VD1 and the second data voltage level VD2 may reach the equalization voltage VEQ. The operation during the precharge period will be described in detail by the period from t24 to t25. In Figure 10 , the signals before the waveform pattern are the respective signals or voltage levels for displaying the first time point t21, and the present disclosure is not limited to Figure 10 the signals before the waveform pattern shown.

[0117] During the precharge period, since the first control signal CS1 of the bit line sense amplifier 300 remains HIGH, the bit line sense amplifier 300 may be connected to the first bit line BL and the second bit line BLB. The second control signal CS2 may remain LOW, which is opposite to the state of the first control signal CS1.

[0118] The period from t21 to t22 may be a bit line sampling period. During the bit line sampling period, the word lines WL1 and WL2 may be HIGH. When the word lines WL1 and WL2 are HIGH, the first current IB1 and the second current IB2 may flow in the memory cells MC1 and MC2. Similar to Figure 6 the bit line sampling period of the bit line sense amplifier 100, the first data voltage level VD1 may decrease in response to the first current IB1, and the second data voltage level VD2 may decrease in response to the second current IB2.

[0119] During the bit line sampling period, the equalization signal PEQ may transition to LOW (e.g., at the second time point t22). The second control signal CS2 may remain LOW, and the first control signal CS1 may remain HIGH. Since the first control signal CS1 remains HIGH, the bit line sense amplifier 300 may remain connected to the bit lines BL and BLB.

[0120] In an embodiment, at a second time point t22 that is the end of a bit line sampling period, the first data voltage level VD1 may be clamped in response to the second NMOS transistor NM2 being turned off due to a voltage drop at VD2 connected to the gate of the second NMOS transistor NM2. That is, as referred to Figure 6 as described, since the first current IB1 is greater than the second current IB2, the second data voltage level VD2 decreases faster than the first data voltage level VD1.

[0121] The period from t22 to t23 may be a clamping period. The bit line sense amplifier 300 may operate similarly to Figure 6 the bit line sense amplifier 100. Similar to the bit line sampling period, the equalization signal PEQ and the second control signal CS2 may be kept LOW, and the first control signal CS1 and the word lines WL1 and WL2 may be kept HIGH.

[0122] The period from t23 to t24 may be a sensing period. The bit line sense amplifier 300 may operate similarly to Figure 6 the bit line sense amplifier 100. In an embodiment, during the sensing period, the bit line sense amplifier 300 may be disconnected from the bit lines BL and BLB. For example, at a third time point t23, the first control signal CS1 of the bit line sense amplifier 300 may transition to LOW. When the sixth NMOS transistor NM6 and the seventh NMOS transistor NM7 are turned off in response to the first control signal CS1, the bit line sense amplifier 300 may be disconnected from the bit lines BL and BLB.

[0123] The second control signal CS2 may transition to HIGH; in this case, when power is supplied to the first node N11, similar to Figure 6 the operation during the sensing period of the amplifier circuit 130, the first amplifier circuit 330 may start amplifying the voltage difference dVD between the first data voltage level VD1 and the second data voltage level VD2. The third NMOS transistor NM3 may be turned on in response to the second control signal CS2, and thus, the ground voltage may be supplied to the sixth node N36. Similarly, the zero-th NMOS transistor NM0 may be turned on in response to the second control signal CS2, and thus, the power supply voltage may be supplied to the first node N31. The fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 may be turned on in response to the second control signal CS2, and the second amplifier circuit 340 may also accelerate the amplification operation of the voltage difference dVD between the voltage levels of the first data voltage level VD1 and the second data voltage level VD2.

[0124] During the sensing period, the word lines WL1 and WL2 may be kept LOW, and the equalization signal PEQ may be kept in the LOW state. Similar to Figure 6, the bit line sense amplifier 300 can determine the data stored in the first memory cell MC1 based on whether the thus amplified first data voltage level VD1 is greater than or less than the determination voltage level DV.

[0125] The period from t24 to t25 can be a precharge period. The bit line sense amplifier 300 can operate similarly to Figure 6 the precharge period of the bit line sense amplifier 100. In an embodiment, during the precharge period, the bit line sense amplifier 300 can be connected to the bit lines BL and BLB again. For example, the first control signal CS1 can transition to HIGH at the fourth time point t24, causing the sixth NMOS transistor NM6 and the seventh NMOS transistor NM7 to conduct; in this case, the bit line sense amplifier 300 can be connected to the bit lines BL and BLB. Similar to Figure 6 the bit line sense amplifier 100, the bit line sense amplifier 300 can perform an offset cancellation operation during the precharge period.

[0126] Referring to Figure 9 and Figure 10 the described bit line sense amplifier 300 can perform a data read operation of any memory cell based on the operations at the first time point t21 to the fifth time point t25. Similar to Figure 6 the bit line sense amplifier 100, the bit line sense amplifier 300 can perform a data write operation of the memory cell. Different from Figure 3 the bit line sense amplifier 100, referring to Figure 9 and Figure 10 the described bit line sense amplifier 300 can be disconnected from the first bit line BL and the second bit line BLB, and thus can further accelerate the amplification of the voltage difference between the first data voltage level VD1 and the second data voltage level VD2. In addition, when the second amplifier circuit 340 supplies current to the fourth node N34 and the fifth node N35 through the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5, the amplification of the first amplifier circuit 330 can be further accelerated. Referring to Figure 10 the time points t20 to t25 described are used to illustrate the sequence of operations, and it does not mean that the time intervals between the time points t20 to t25 indicate the relative magnitudes of the time intervals during which the operations are performed.

[0127] Figure 11 is a detailed circuit diagram of the bit line sense amplifier according to an embodiment of the present disclosure. Referring to Figure 2 the bit line sense amplifier 400 can include a first read / write circuit 410A, a second read / write circuit 410B, an equalization circuit 420, a first amplifier circuit 430, and a second amplifier circuit 440. Referring to Figure 11 and Figure 2 andFigure 11 Describe in detail the bit line sense amplifier 400 according to an embodiment of the present disclosure.

[0128] The first read / write circuit 410A or the second read / write circuit 410B may correspond to Figure 3 the first read / write circuit 110A or the second read / write circuit 110B. For example, the first read / write circuit 410A may be provided with the first read data RD1 or may provide the second write data WD2, and the second read / write circuit 410B may be provided with the second read data RD2 or may provide the first write data WD1. The structure of the first read / write circuit 410A or the second read / write circuit 410B may be the same as that in FIG. 4, and the operation of the first read / write circuit 410A or the second read / write circuit 410B may be the same as or similar to that of the first read / write circuit 110A / 210A / 310A or the second read / write circuit 110B / 210B / 310B described with reference to Figure 3 FIG. 4 and Figures 6 to 10 FIG. 4 and

[0129] The equalization circuit 420 may equalize the voltages of the second node N42 and the third node N43, and may correspond to Figure 8 the equalization circuit 220. Referring to Figure 11 FIG. 4, the equalization circuit 420 may include a first transistor 421 and a second transistor 422. The first transistor 421 may operate in response to an equalization signal PEQ and may be connected between the equalization node NE and the first node N41. The second transistor 422 may operate in response to the equalization signal PEQ and may be connected between the second node N42 and the third node N43. The equalization circuit 420 may operate in the same or similar manner as the equalization circuit 220, and may equalize the voltage levels of the second node N42 and the third node N43 with the equalization voltage VEQ. Figure 8 FIG. 4, the equalization circuit 420 may include a first transistor 421 and a second transistor 422. The first transistor 421 may operate in response to an equalization signal PEQ and may be connected between the equalization node NE and the first node N41. The second transistor 422 may operate in response to the equalization signal PEQ and may be connected between the second node N42 and the third node N43. The equalization circuit 420 may operate in the same or similar manner as the equalization circuit 220, and may equalize the voltage levels of the second node N42 and the third node N43 with the equalization voltage VEQ.

[0130] The first amplifier circuit 430 may amplify the difference between the first data voltage level VD1 and the second data voltage level VD2 generated based on the currents of the bit line BL and BLB. The first amplifier circuit 430 may correspond to Figure 3 or Figure 8 the amplifier circuit 130 or 230 or Figure 9 the first amplifier circuit 330. The operation of the first amplifier circuit 430 may be the same as that of the amplifier circuit 130 or 230 described with reference to Figure 3 FIG. 4 and Figures 6 to 8 FIG. 4 or the operation of the amplifier circuit 130 or 230 described with reference to Figure 9 FIG. 4 and Figure 10The operation of the described first amplifier circuit 330 is the same or similar. The first amplifier circuit 430 can transfer data of the first memory cell MC1 or the second memory cell MC2 to the first read / write circuit 410A or the second read / write circuit 410B, or can provide data to be written to the first memory cell MC1 or the second memory cell MC2 from the first read / write circuit 410A or the second read / write circuit 410B to the first amplifier circuit 430.

[0131] In an embodiment, the first amplifier circuit 430 may include a plurality of transistors. For example, the first amplifier circuit 430 may include three NMOS transistors NM0, NM1, and NM2 and two PMOS transistors PM1 and PM2. The NMOS transistors NM0, NM1, and NM2 and the PMOS transistors PM1 and PM2 of the first amplifier circuit 430 may respectively correspond to Figure 3 or Figure 8 the NMOS transistors NM0, NM1, and NM2 and the PMOS transistors PM1 and PM2 of Figure 3 or Figure 8 and may have the same connection structure as the NMOS transistors NM0, NM1, and NM2 and the PMOS transistors PM1 and PM2 of

[0132] The second amplifier circuit 440 may be connected to the first amplifier circuit 430 and may be implemented to connect the first bit line BL and the second bit line BLB to the first amplifier circuit 430. The second amplifier circuit 440 may correspond to Figure 9 the second amplifier circuit 340 of Figure 9 For example, similar to the second amplifier circuit 340 of

[0133] Similar to Figure 9 the second amplifier circuit 340 ofFigure 9 The second amplifier circuit 440 is similar to the second amplifier circuit 340. The second amplifier circuit 440 can connect the bit line sense amplifier 400 to the bit lines BL and BLB or disconnect it from the bit lines BL and BLB. The operation of the second amplifier circuit 440 can be the same as or similar to the operation of the second amplifier circuit 340 described with reference to Figure 9 and Figure 10 The operation of the second amplifier circuit 340 described.

[0134] In an embodiment, the second amplifier circuit 440 can include a plurality of transistors. For example, the second amplifier circuit 440 can include five NMOS transistors NM3 to NM7. The NMOS transistors NM3 to NM7 of the second amplifier circuit 440 can respectively correspond to Figure 9 the NMOS transistors NM3 to NM7 of Figure 9 and can have the same connection structure as the NMOS transistors NM3 to NM7 of

[0135] Figure 11 For example, the third NMOS transistor NM3 can operate in response to the second control signal CS2 and can be connected between the ground node and the eighth node N48, and the seventh NMOS transistor NM7 can operate in response to the first control signal CS1 and can be connected between the second bit line BLB and the seventh node N47. Figure 9 The bit line sense amplifier 400 of Figure 7 can operate in a method similar to the bit line sense amplifier 300 of Figure 9 and Figure 10 For example, the bit line sense amplifier 400 can read the data of the memory cells MC1 and MC2 by sensing the currents of the first bit line BL and the second bit line BLB and amplifying the difference between the first data voltage level VD1 and the second data voltage level VD2 in the method described with reference to Figure 9 The bit line sense amplifier 400 can write data into the memory cells MC1 and MC2 in a method similar to the method of the bit line sense amplifier 300 of

[0136] Figures 3 to 11 The NMOS transistors and PMOS transistors shown in Figures 3 to 11 and described with reference to Figure 6 and Figure 10 are provided as examples, and the present disclosure is not limited thereto. It should be understood that within the operating range of the bit line sense amplifier 100 / 200 / 300 / 400, the NMOS transistors and PMOS transistors can be replaced with other types of transistors, and it should be understood that the signals described with reference to

[0137] Figure 12It is a block diagram showing the configuration of an electronic system according to an embodiment. The electronic system 2000 may include a main processor 2100, a main memory 2200, a storage device 2300, a communication block 2400, and a user interface 2500. For example, the electronic system 2000 may be one of electronic devices such as a desktop computer, a laptop computer, a tablet computer, a smart phone, a wearable device, a video game console, a workstation, and a server.

[0138] The main processor 2100 may control all operations of the electronic system 2000. The main processor 2100 may perform various types of arithmetic operations and / or logical operations. To this end, the main processor 2100 may include dedicated circuits (e.g., a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC)). For example, the main processor 2100 may include one or more processor cores and may be implemented with a general-purpose processor, a dedicated processor, or an application processor.

[0139] The main memory 2200 may store data used in the operation of the electronic system 2000. For example, the main memory 2200 may temporarily store data that has been processed or will be processed by the main processor 2100. For example, the main memory 2200 may include volatile memory (such as dynamic DRAM (DRAM) or synchronous DRAM (SDRAM)) and / or non-volatile memory (such as phase change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (ReRAM), or ferroelectric RAM (FRAM)). In an embodiment, the main memory 2200 may be the memory device 1000 described with reference to Figures 1 to 11 or may include the memory device 1000.

[0140] The storage device 2300 may include a memory device and a controller. The memory device of the storage device 2300 may store data regardless of whether power is supplied. For example, the storage device 2300 may include non-volatile memory such as flash memory, PRAM, MRAM, ReRAM, or FRAM. For example, the storage device 2300 may include a storage medium such as a solid state drive (SSD), an embedded multimedia card (eMMC), or a universal flash storage (UFS). The controller may control the memory device so that the memory device stores or outputs data.

[0141] The communication block 2400 can communicate with external devices / systems of the electronic system 2000. For example, the communication block 2400 can support at least one of various wireless communication protocols (such as Long Term Evolution (LTE), Worldwide Interoperability for Microwave Access (WiMax), Global System for Mobile Communications (GSM), Code Division Multiple Access (CDMA), Bluetooth, Near Field Communication (NFC), and Wireless Fidelity (Wi-Fi), Radio Frequency Identification (RFID)) and / or at least one of various wired communication protocols (such as Transmission Control Protocol / Internet Protocol (TCP / IP), Universal Serial Bus (USB), and FireWire).

[0142] The user interface 2500 can perform communication arbitration between the user and the electronic system 2000. For example, the user interface 2500 can include input interfaces such as a keyboard, a mouse, a keypad, buttons, a touch panel, a touch screen, a touchpad, a trackball, a camera, a microphone, a gyroscope sensor, and a vibration sensor. For example, the user interface 2500 can include output interfaces such as a liquid crystal display (LCD) device, a light emitting diode (LED) display device, an organic LED (OLED) display device, an active matrix OLED (AMOLED) display device, a speaker, and a motor.

[0143] The bus 2600 can provide a communication path between components of the electronic system 2000. The components of the electronic system 2000 can exchange data with each other based on the bus format of the bus 2600. For example, the bus format can include at least one or more of various interface protocols such as USB, Small Computer System Interface (SCSI), Peripheral Component Interconnect Express (PCIe), Mobile PCIe (M-PCIe), Advanced Technology Attachment (ATA), Parallel ATA (PATA), Serial ATA (SATA), Serial Attached SCSI (SAS), Integrated Drive Electronics (IDE), Enhanced IDE (EIDE), Non-Volatile Memory Express (NVMe), and Universal Flash Storage (UFS).

[0144] According to an embodiment of the present disclosure, a bit line sense amplifier and a memory device including the bit line sense amplifier are provided. The bit line sense amplifier determines data of a memory cell by sensing a magnitude of a current of a bit line, comparing the sensed magnitude, and amplifying a comparison result.

[0145] Although the present disclosure has been described with reference to embodiments of the present disclosure, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made to the present disclosure without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A bit line sense amplifier for reading data of a memory cell, the bit line sense amplifier comprising: an equalizing circuit connected to a first node and a second node and configured to provide an equalizing voltage to the first node and the second node; as well as an amplifier circuit configured to amplify a difference between a first voltage level of the second node and a second voltage level of the first node, Wherein, the amplifying circuit comprises: a first p-type metal oxide semiconductor transistor connected between the second node and a third node and configured to operate in response to the second voltage level; a second p-type metal oxide semiconductor transistor connected between the first node and the third node and configured to operate in response to the first voltage level; a first n-type metal oxide semiconductor transistor connected between the first node and a fourth node connected to a first bit line of the first memory cell and configured to operate in response to the first voltage level; and A second n-type metal oxide semiconductor transistor is connected between the second node and a fifth node connected to a second bit line of a second memory cell and is configured to operate in response to the second voltage level.

2. The bit line sense amplifier of claim 1 , further comprising: a first read / write circuit connected to the second node and the fifth node; a second read / write circuit connected to the first node and the fourth node, wherein the first read / write circuit is provided with first read data of the first memory cell through the second node, and is provided with second write data to be written into the second memory cell through the fifth node, and The second read / write circuit is provided with second read data of the second memory cell through the first node, and is provided with first write data to be written into the first memory cell through the fourth node.

3. The bit line sense amplifier of claim 1 , wherein: The equalization circuit comprises: a first transistor connected between the first node and an equalization node to which the equalization voltage is applied and configured to operate in response to an equalization signal; and A second transistor is connected between the equalization node and the second node and is configured to operate in response to the equalization signal.

4. The bit line sense amplifier of claim 1 , wherein: The equalization circuit comprises: a first transistor connected between the first node and an equalization node to which the equalization voltage is applied and configured to operate in response to an equalization signal; and A second transistor is connected between the first node and the second node and is configured to operate in response to the equalization signal.

5. The bit line sense amplifier of claim 2, wherein: The first read / write circuit comprises: an input / output circuit configured to receive the first read data and provide the second write data; a first transistor connected between the second node and the input / output circuit and configured to operate in response to a read enable signal; and A second transistor is connected between the second node and the fifth node and is configured to operate in response to a write enable signal.

6. The bit line sense amplifier of claim 2, wherein: The first read / write circuit comprises: an input / output circuit configured to receive the first read data and provide the second write data; a first transistor connected between the second node and the input / output circuit and configured to operate in response to a read enable signal; and A second transistor is connected between the fifth node and the input / output circuit and is configured to operate in response to a write enable signal.

7. The bit line sense amplifier of claim 2, wherein: The equalization circuit performs a precharge operation of providing the equalization voltage to the first node and the second node, wherein the voltage level of the fourth node has a value obtained by subtracting a threshold voltage level of the first n-type metal oxide semiconductor transistor from the equalization voltage in response to the precharge operation, and The voltage level of the fifth node has a value obtained by subtracting a threshold voltage level of the second n-type metal oxide semiconductor transistor from the equalization voltage in response to the precharge operation.

8. The bit line sense amplifier of claim 7, wherein: The third node is connected to a power n-type metal oxide semiconductor transistor, and The power n-type metal oxide semiconductor transistor is connected to the third node and a power node to which a power supply voltage is applied, and is configured to operate in response to a control signal.

9. The bit line sense amplifier of claim 8, wherein: The second memory cell is a reference cell storing reference data, and wherein, in response to the word line of the first memory cell and the word line of the second memory cell being activated, A first current corresponding to first data of the first memory cell flows through the first node and the fourth node, and A second current corresponding to the reference data of the second memory cell flows through the second node and the fifth node, and When data 1 is stored in the first memory cell, the first current is greater than the second current.

10. The bit line sense amplifier of claim 9, wherein: the second voltage level decreases in response to the first current, wherein the first voltage level decreases in response to the second current, and When data 1 is stored in the first memory cell, in response to the second voltage level decreasing faster than the first voltage level, the second n-type metal oxide semiconductor transistor is turned off, and the second voltage level is clamped.

11. The bit line sense amplifier of claim 10, wherein: The power n-type metal oxide semiconductor transistor is turned on by the control signal, and When the power supply voltage is supplied to the third node, the amplifier circuit starts to amplify the difference between the first voltage level and the second voltage level.

12. The bit line sense amplifier of claim 11, wherein: When data 1 is stored in the first memory cell, the amplifying circuit amplifies the first voltage level to reach the equilibrium voltage.

13. A bit line sense amplifier for reading data of a memory cell, the bit line sense amplifier comprising: an equalizing circuit connected to a first node and a second node and configured to provide an equalizing voltage to the first node and the second node; a first amplifying circuit configured to amplify a difference between a first voltage level of the second node and a second voltage level of the first node; as well as a second amplification circuit configured to disconnect the bit line sense amplifier from a first bit line connected to the first memory cell and a second bit line connected to the second memory cell, Wherein, the first amplifying circuit comprises: a first n-type metal oxide semiconductor transistor connected between the first node and a third node and configured to operate in response to the first voltage level; and a second n-type metal oxide semiconductor transistor connected between the second node and a fourth node and configured to operate in response to the second voltage level, and Wherein, the second amplifying circuit comprises: a third n-type metal oxide semiconductor transistor connected between a fifth node connected to the third node and the first bit line and configured to operate in response to a first control signal; and A fourth n-type metal oxide semiconductor transistor is connected between a sixth node connected to the fourth node and the second bit line and is configured to operate in response to the first control signal.

14. The bit line sense amplifier of claim 13, wherein: The first amplifying circuit further includes: a fifth n-type metal oxide semiconductor transistor connected between the power node to which the power supply voltage is applied and the seventh node and configured to operate in response to the second control signal; a first p-type metal oxide semiconductor transistor connected between the second node and the seventh node and configured to operate in response to the second voltage level; and A second p-type metal oxide semiconductor transistor is connected between the first node and the seventh node and is configured to operate in response to the first voltage level.

15. The bit line sense amplifier of claim 14, wherein: The second amplifying circuit further includes: a sixth n-type metal oxide semiconductor transistor connected between the ground node and the eighth node and configured to operate in response to the second control signal; a seventh n-type metal oxide semiconductor transistor connected between the fifth node and the eighth node and configured to operate in response to the second control signal; and an eighth n-type metal oxide semiconductor transistor connected between the sixth node and the eighth node and configured to operate in response to the second control signal, and The first control signal and the second control signal are complementary signals.

16. The bit line sense amplifier of claim 15, further comprising: a first read / write circuit connected to the second node and the fourth node; as well as a second read / write circuit connected to the first node and the third node, wherein the first read / write circuit is provided with first read data of the first memory cell through the second node and is provided with second write data to be written into the second memory cell through the fourth node, and The second read / write circuit is provided with second read data of the second memory cell through the first node, and is provided with first write data to be written into the first memory cell through the third node.

17. The bit line sense amplifier of claim 15, wherein: The equalization circuit comprises: a first transistor connected between the first node and an equalization node to which the equalization voltage is applied and configured to operate in response to an equalization signal; and A second transistor is connected between the equalization node and the second node and is configured to operate in response to the equalization signal.

18. The bit line sense amplifier of claim 15, wherein: The equalization circuit comprises: a first transistor connected between the first node and an equalization node to which the equalization voltage is applied and configured to operate in response to an equalization signal; and A second transistor is connected between the first node and the second node and is configured to operate in response to the equalization signal.

19. The bit line sense amplifier of claim 15, wherein: The first amplifying circuit amplifies a difference between the first voltage level and the second voltage level in response to the second control signal, and In response to the first control signal, the second amplifying circuit disconnects the first bit line from the fifth node and disconnects the second bit line from the sixth node.

20. A memory device configured to store data, the memory device comprising: a memory cell array configured to store the data and comprising a first memory cell, a second memory cell, and a bit line sense amplifier; as well as an input / output circuit configured to input the data to the memory cell array or receive the data from the memory cell array, Wherein, the bit line sense amplifier comprises: an equalizing circuit connected to a first node and a second node and configured to provide an equalizing voltage to the first node and the second node; and an amplifier circuit configured to amplify a difference between a first voltage level of the second node and a second voltage level of the first node, and Wherein, the amplifying circuit comprises: a first n-type metal oxide semiconductor transistor connected between the first node and a third node connected to a first bit line of the first memory cell and configured to operate in response to the first voltage level; and A second n-type metal oxide semiconductor transistor is connected between the second node and a fourth node connected to a second bit line of the second memory cell and is configured to operate in response to the second voltage level.

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