SRAM device

Abstract

In one aspect, there is provided an SRAM device comprising: a plurality of bit cells, each bit cell comprising a first half cell and a second half cell, each half cell comprising first and second CFET devices, each CFET device comprising a bottom device and a top device stacked on top of the bottom device, wherein the first CFET device includes a common gate shared by the bottom device and the top device and is configured as an inverter cross-coupled to the other half cell, and wherein the bottom device of the second CFET device is configured as a first pass gate of the first port of the half cell and includes a bottom gate coupled to the first word line, and the top device is configured as a second pass gate of the second port of the half cell. And wherein a top device of the second CFET device is configured as a second pass gate of a second port of the half-cell and includes a top gate spaced apart from the bottom gate and coupled to a second word line.

Description

Technical Field

[0001] The present invention generally relates to static random access memory (SRAM) devices. Background Art

[0002] The demand for higher performance dual-port SRAMs is increasing, especially in advanced system-on-chip (SoC) applications such as CPUs, GPUs, etc. Parallel processing is key in these applications, where embedded memories of the multi-port type are beneficial as they improve system performance by enabling two processors, threads, or processes to read / write to the memory simultaneously. The 8-transistor (8T) dual-port SRAM bit cell can provide high-performance 2-read / write port (2RW) operation, but introduces significant area overhead, typically 1.5 times larger than the 6T single-port SRAM bit cell in current technology nodes. Due to its smaller footprint, the 6T single-port bit cell is the typical choice for current high-density applications.

[0003] Complementary field-effect transistor (CFET) devices are transistor devices having a complementary pair of FETs stacked on top of each other (e.g., an NMOS device stacked on top of a PMOS device, or vice versa). Compared to the traditional side-by-side arrangement of pFETs and nFETs, CFETs allow for a reduced footprint. The two device and contact levels provided by CFETs (e.g., "2-level middle-of-line / MOL") further allow for a reduction in the use of wiring layers (e.g., in the back-end-of-line / BEOL). Thus, CFETs contribute to the realization of area-efficient circuit systems.

[0004] Figure 1Shows the area occupancy ratio of dual-port to single-port SRAM bit cells for various technology nodes and device types. Due to the additional two transistors in the 8T bit cell, the inability to stack devices in non-CFET nodes results in a typical area occupancy ratio of 1.51. In CFET technology, due to the vertical stacking of two transistors (e.g., NMOS on PMOS), the area occupancy ratio of dual-port (8T) to single-port (6T) bit cells can theoretically be 1. This is because the additional two transistors in the 8T bit cell can be stacked on the pass-gate of the 6T bit cell without additional area on the 6T CFET bit cell. Achieving this theoretical ratio would make the 8T bit cell the main choice for designing on-chip memories in modern SoCs as it provides more functionality within the same physical area occupancy compared to the 6T single-port bit cell. Although 6T SRAM bit cell designs based on stacking complementary transistor pairs have been proposed, to the inventors' knowledge, there is currently no known 8T dual-port SRAM circuit design that is both compatible with the CFET device architecture and capable of achieving a small area occupancy close to the theoretical dual-port to single-port bit cell area occupancy ratio of 1. SUMMARY OF THE INVENTION

[0005] Accordingly, an object of the present invention is to provide a CFET-based 8T SRAM bit cell suitable for dual-port implementation, thereby enabling an area occupancy ratio of dual-port to single-port bit cells close to 1.

[0006] Accordingly, in one aspect of the present invention, there is provided an SRAM device, comprising:

[0007] a plurality of bit cells, each bit cell including a first half-cell and a second half-cell, each half-cell including first and second CFET devices, each CFET device including a bottom device and a top device stacked on top of the bottom device,

[0008] wherein the first CFET device includes a common gate shared by the bottom device and the top device and is configured as an inverter cross-coupled to an inverter of the other half-cell,

[0009] wherein the bottom device of the second CFET device is configured as a first transfer gate of a first port of the half-cell and includes a bottom gate coupled to a first word line, and

[0010] wherein the top device of the second CFET device is configured as a second transfer gate of a second port of the half-cell and includes a top gate separated from the bottom gate and coupled to a second word line.

[0011] Accordingly, the present invention is based on the recognition that an 8T bit cell design compatible with a CFET device architecture can be implemented based on a bit cell including an equal number of NMOS and PMOS devices. Thus, the first and second transfer gates (interchangeably referred to as a transfer gate pair) of each half cell are implemented by CFET devices, which means that the first and second transfer gates are complementary devices stacked on top of each other. The bottom and top devices of the second CFET device (i.e., the first and second transfer gates) can be a PMOS device and an NMOS device, respectively, or vice versa. Since the bottom and top gates of the second CFET device are separate, the first transfer gate (bottom device) and the second transfer gate (top device) can be individually controlled by the first and second word lines, respectively. Thus, the bit cell design of the SRAM device according to this aspect is an enabler for high-density, dual-port, CFET-based SRAM.

[0012] Each CFET device may include first and second S / D regions. The common gate of the first CFET device of the first half cell and the bottom and top gates of the second CFET device of the second half cell may be arranged along a first gate rail, and the common gate of the first CFET device of the second half cell and the bottom and top gates of the second CFET device of the first half cell may be arranged along a second gate rail, the first and second gate rails being parallel to the cell height dimension of the bit cell.

[0013] In addition, each CFET device may include first and second S / D regions, wherein the S / D regions of the CFET devices of the first half cell may be arranged along a first active rail, and the S / D regions of the CFET devices of the second half cell may be arranged along a second active rail, the first and second active rails being parallel to the cell width dimension of the bit cell and transverse to the cell height dimension.

[0014] Thus, two inverters (first CFET devices) can be accommodated along only two parallel gate rails, with a layout such that the inverters are located in the first pair of diagonally opposite quadrants of the bit cell, and the two transfer gates are located in the second pair of diagonally opposite quadrants of the bit cell. This bit cell layout facilitates the interconnection wiring within the bit cell, particularly the cross-coupling between the inverter pairs, since the two cross-couplings between the inverters can be wired within the bit cell without crossing or blocking each other.

[0015] In some embodiments, the first half cell includes a first common S / D contact arranged between and shared by the first and second CFET devices of the first half cell, and the second half cell includes a second common S / D contact arranged between and shared by the first and second CFET devices of the second half cell,

[0016] wherein the common S / D contacts of the first and second half-units each include contact extensions protruding towards the common S / D contacts of the other half-unit,

[0017] wherein the common gates of the first CFET devices of the first and second half-units respectively define first and second common gates, and wherein the first and second common gates each include gate extensions protruding towards the second CFET devices of the other half-unit (i.e., towards its bottom and top gates, and along the cell height dimension),

[0018] wherein the bit cell includes:

[0019] a first local cross-coupled interconnect that extends between and interconnects corresponding tip portions of the gate extension of the first common gate and the contact extension of the second common S / D contact, and

[0020] a second local cross-coupled interconnect that extends between and interconnects corresponding tip portions of the gate extension of the second common gate and the contact extension of the first common S / D contact.

[0021] This further facilitates area-efficient interconnect routing within the bit cell, as the separation between internal storage nodes (along the cell height dimension) defined by an inverter of one half-unit and the common gate of the other half-unit can be at least partially bridged by extending the local S / D contacts and the common gates.

[0022] In some embodiments, the end portion of the gate extension of the first common gate is separated from the end portions of the bottom and top gates of the second CFET device of the second half-unit by a first gate cut region, and wherein the end portion of the gate extension of the second common gate is separated from the end portions of the bottom and top gates of the second CFET device of the first half-unit by a second gate cut region.

[0023] As is known in the art, circuits typically include gate cut regions that are defined to ensure sufficient end-to-end spacing between gates along the same gate track. Thus, by separating the end portions of the gate extensions and the end portions of the bottom / top gates along the same gate track by at least one gate cut region, the bit cell layout can provide sufficient process margin for gate fabrication. For example, the end portions can be separated only by the gate cut region. This can help achieve a low cell height for the bit cell.

[0024] In some embodiments, the first and second local cross-coupled interconnections are respectively configured as a first metal strip and a second metal strip, and the first metal strip and the second metal strip extend along the cell width dimension to bridge the distance between corresponding end portions. Accordingly, the gate extensions and the contact extensions can be interconnected by the laterally extending intra-cell metal strips.

[0025] The first and second metal strips can be particularly arranged on top of the corresponding end portions.

[0026] In some embodiments, the bottom device is arranged in the bottom device level of the bit cell, while the top device is arranged in the top device level of the bit cell,

[0027] wherein the gate extension of the first common gate and the contact extension of the second common S / D contact are arranged in the bottom device level and not in the top device level, and

[0028] wherein the gate extension of the second common gate and the contact extension of the first common S / D contact are arranged in the top device level and not in the bottom device level.

[0029] Accordingly, the two cross-couplings (first common gate to second common S / D contact and second common gate to first common S / D contact) between the inverters can thus be split between the bottom and device levels. Accordingly, the first and second metal strips can be offset along the vertical dimension (i.e., the stacking direction of the devices), such that the spacing requirement along the cell height dimension between the metal strips (and thus a larger cell height dimension is required) can be alleviated.

[0030] In other words, the gate extension of the first common gate can extend from the bottom gate portion of the first common gate to protrude relative to the top gate portion of the first common gate. Correspondingly, the contact extension of the second common S / D contact can extend from the bottom contact portion of the second common S / D contact to protrude relative to the top contact portion of the second common S / D contact. On the other hand, the gate extension of the second common gate can extend from the top gate portion of the second common gate to protrude relative to the bottom gate portion of the second common gate. Correspondingly, the contact extension of the first common S / D contact can extend from the top contact portion of the first common S / D contact to protrude relative to the bottom contact portion of the first common S / D contact.

[0031] The first metal strip can be included in a local interconnect layer between the bottom and top device levels.

[0032] The second metal strip can be included in a local interconnect layer arranged on top of the top device level.

[0033] The contact extension can protrude at least to the midline of the bit cell. Thus, the common gate of either half cell only needs to extend to the shorter portion of the distance of the second CFET device of the other half cell to facilitate cross-coupling, which allows increasing the margins of the bottom and top gates of the second CFET device.

[0034] In some embodiments, each bottom device is a nanosheet FET device (e.g., including a channel structure formed by multiple nanosheets), and each top device is a finFET device, including a channel structure (e.g., a fin-shaped channel structure) having a width dimension (i.e., along the cell height dimension) smaller than the width dimension of the channel structure of each nanosheet FET device. The narrower channel structure of the finFET enables further reduction of the cell height.

[0035] In some embodiments, the bottom devices are arranged in the bottom device level of the bit cell, and the top devices are arranged in the top device level of the bit cell,

[0036] wherein the gate extensions of the first and second common gates and the contact extensions of the first and second common S / D contacts are arranged at least in the top device level.

[0037] Thus, the two cross-couplings between the inverters (the first common gate to the second common S / D contact and the second common gate to the first common S / D contact) can thus be provided by metal strips in a common local interconnect layer arranged on the top device level. This can reduce the complexity of the interconnect wiring within the bit cell.

[0038] In some embodiments, the first and second transmission gates of the first half cell are respectively coupled to the first and second bit lines,

[0039] the first and second transmission gates of the second half cell are respectively coupled to the first and second complementary bit lines, and

[0040] the inverters of the first and second half cells are coupled to a first power rail and a second power rail, one providing a pull-up voltage and the other providing a pull-down voltage.

[0041] In embodiments where two inverters (first CFET devices) are accommodated only along two parallel gate tracks, as described above, the inverters of the first half-cell can be coupled to a first instance of a first power rail, while the inverters of the second half-cell can be coupled to a second instance of the first power rail. The first and second instances of the first power rail can be configured as respective buried power rails extending along the bottom and top edges of the corresponding bit cell. The inverters of the first and second half-cells can be coupled to the same (single) instance of a second power rail, where this instance of the second power rail can be configured as a buried power rail (BPR) extending along the midline of the corresponding bit cell. By configuring the power rails as BPRs, routing resources can be freed up for routing bit lines and word lines in the interconnect levels above the respective bit cells.

[0042] In embodiments where the top device is a finFET device, the instance of the second power rail can be configured as a metal line in a routing track of an interconnect level disposed above the bit cell, where a first bit line and a first complementary bit line can be configured as buried signal lines disposed between the first and second instances of the first power rail. By burying two bit lines and shifting the second power rail to the interconnect structure, the number of tracks that need to be routed above the bit cell can be reduced by one. This can further facilitate scaling, as the routing tracks may not limit the reduction in cell height achieved by configuring the top device as a finFET device.

[0043] The routing track can be an intermediate track in a set of routing tracks of the interconnect level and associated with the bit cell, the set of routing tracks extending along the cell width dimension and further including: a first edge track and a second edge track respectively overlapping the top and bottom edges of the bit cell, a first eccentric track and a second eccentric track disposed on opposite sides of the intermediate track, a third eccentric track disposed between the first eccentric track and the first edge track, and a fourth eccentric track disposed between the second eccentric track and the second edge track.

[0044] First and second instances of a first word line (WL-A) can be respectively disposed in the first and second edge tracks.

[0045] First and second instances of a second word line (WL-B) can be respectively disposed in the third and fourth eccentric tracks.

[0046] A second bit line and a second complementary bit line can be respectively disposed in the first and second eccentric tracks. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] This and other aspects of the invention will now be described in more detail with reference to the drawings showing embodiments of the invention.

[0048] Figure 1 is a diagram showing the occupied area ratio of a dual-port (8T) to a single-port (6T) bit cell for different device nodes and types.

[0049] Figure 2 is a circuit diagram of a conventional 8T SRAM bit cell with 6 NMOS and 2 PMOS devices.

[0050] Figure 3 is a circuit diagram of an SRAM device including a CFET-based 8T SRAM bit cell having four NMOS and four PMOS devices according to an implementation.

[0051] Figure 4 is a schematic perspective view of a CFET device.

[0052] Figure 5a -f show cross sections of various implementations of CFET devices.

[0053] Figure 6a -c shows a SRAM device including a bit cell according to an implementation.

[0054] Figure 7a -c shows a SRAM device including a bit cell according to yet another implementation.

[0055] Figure 8a -c shows a SRAM device including a bit cell according to yet another implementation. DETAILED DESCRIPTION

[0056] The implementation and examples of SRAM devices and bit cells will be described below with reference to the accompanying drawings. The accompanying drawings are schematic diagrams only, and the relative sizes of certain structures and layers may be exaggerated and not drawn to scale. On the contrary, the sizes can be adjusted to make the illustration clear and easy to understand. When present in the figure, the indicated axes X, Y and Z respectively refer to the first horizontal or lateral, second horizontal or lateral and vertical directions. As used herein, the terms "horizontal" and "lateral" refer to the direction parallel to the (main surface) of the supporting substrate of the memory structure. The term "vertical" refers to the direction parallel to the normal direction of the substrate (main surface), that is, transverse to the substrate. The first horizontal direction X can specifically correspond to the channel direction, or equivalently to the channel or gate length of the CFET device. In the embodiments of the bit cell listed below, the X direction can also correspond to the width dimension of the bit cell (meaning that the channel direction of the CFET device of the bit cell is consistent with the width dimension of the bit cell). The second horizontal direction Y can then correspond to the cell height dimension of the bit cell.

[0057] Figure 2It is a circuit diagram of a conventional dual 8T SRAM bit cell that can be implemented using conventional non-CFET devices, six N-type metal-oxide-semiconductor field-effect transistor (MOSFET) devices (NMOS) and two P-type MOSFET devices (PMOS). The bit cell includes two cross-coupled inverter pairs, each including PMOS pull-up (PU) devices PU1, PU2 and NMOS pull-down (PD) devices PD1, PD2. The bit cell also includes two NMOS access transistors or transmission gate devices (PG) for each port (port A: PG1-A, PG2-A and port B: PG1-B, PG2-B). Since the PG devices of each port are independently connected to their respective word lines (WL-A, WL-B) and bit lines (BL-A, BLB-A, BL-B, BLB-B), the storage nodes Q, QB formed by the cross-coupled inverters can be accessed simultaneously through these two ports.

[0058] In a conventional non-CFET device 8T SRAM bit cell as shown in Figure 2 switching the access NMOS transistors to PMOS (one NMOS access transistor at port A and one PMOS access transistor at port B, and vice versa) is not beneficial for the bit cell footprint. Also, as recognized by the inventors, for CFET devices, the conventional approach (i.e., six NMOS + two PMOS devices or six PMOS + two NMOS devices) will not be effective as it results in a larger CFET 8T bit cell footprint.

[0059] Therefore, according to the present disclosure, a CFET-based 8T bit cell is provided that has an equal number of NMOS and PMOS devices (four NMOS and four PMOS devices), and its circuit layout is as shown in Figure 3 As shown in Figure 3 the access transistors for ports A and B are PMOS (PG1-A and PG2-A) and NMOS (PG1-B and PG2-B) devices respectively. This allows the proposed bit cell to more efficiently utilize the CFET device architecture, thereby achieving a small CFET 8T bit cell layout. This can be more fully understood by considering the following.

[0060] As used herein, the term "CFET" device refers to a device that includes a bottom FET device of a first conduction type and a top FET device of a second conduction type opposite to the first conduction type stacked on top of the bottom FET device (e.g., an NMOS top device stacked on top of a PMOS bottom device, or vice versa). For simplicity, the bottom FET device and the top FET device can be interchangeably referred to as the bottom device and the top device respectively.

[0061] A CFET device can be provided in a split-gate configuration, where the bottom device and the top device have separate (i.e., unconnected) gates. In other words, a CFET device with a split-gate configuration includes a bottom gate for the bottom device and a top gate for the top device that is separate from the bottom gate. A CFET device can also be provided in a common-gate configuration, where the bottom and top devices share a common gate. In other words, a CFET device with a common-gate configuration includes a common gate shared by the bottom and top devices. Thus, the common gate can include a bottom gate portion for the bottom device and a top gate portion for the top device that is coupled to the bottom gate portion.

[0062] Figure 4 FIG. 4 is a schematic perspective view of a CFET device 100, which includes a bottom device 110 and a top device 120 stacked on top of the bottom device 110. The bottom device 110 defines the bottom tier or level of the CFET device 100, while the top device 120 defines the top tier or level of the CFET device 100. The bottom device 110 can be a PMOS device, while the top device 120 can be an NMOS device, or vice versa.

[0063] The CFET device 100 is disposed on a substrate schematically represented by reference numeral 101. The substrate 101 can be of a conventional type suitable for CMOS devices, and by way of non-limiting examples only, such as a bulk substrate of a semiconductor such as Si or SiGe, or a silicon-on-insulator (SOI) substrate.

[0064] The bottom device 110 includes a first source / drain (S / D) region 111, a second S / D region 112, a channel structure 113 extending between the first S / D region 111 and the second S / D region 112, and a gate 114 surrounding the channel structure 113. The top device 120 includes a first S / D region 121, a second S / D region 122, a channel structure 123 extending between the first S / D region 121 and the second S / D region 122, and a gate 124 surrounding the channel structure 114. The labels “bottom” and “top” may be used hereinafter to refer to the elements of the bottom device 110 and the top device 120 or elements associated therewith, such as the first S / D regions 111 / 121, the second S / D regions 112 / 122, the channel structures 113 / 123, the gates 114 / 124, etc.

[0065] The top device 120 is stacked on top of the bottom device 110 such that the first top S / D region 121 overlaps the first bottom S / D region 111, the second top S / D region 122 overlaps the second bottom S / D region 112, and the top channel structure 123 overlaps the bottom channel structure 113. “Overlap” herein refers to the overlap seen along the vertical direction Z. Thus, as Figure 4As shown, the first S / D regions 111 / 121, the second S / D regions 112 / 122, and the channel structures 113 / 123 intersect a common (geometric) vertical plane P1 (parallel to the XZ plane).

[0066] As shown, the corresponding S / D contacts 115, 116, 125, and 126 can be respectively disposed on each of the first bottom S / D region 111, the second bottom S / D 112, the first top S / D region 121, and the second top S / D region 122. Similar to the first S / D regions 111 / 121 and the second S / D regions 112 / 122, the first top S / D contact 125 can overlap with the first bottom S / D contact 115, and the second top S / D contact 125 can overlap with the second bottom S / D contact 115.

[0067] In Figure 4 , the channel structures 113, 123 are only schematically shown, but generally can include a plurality (i.e., one or more) of channel nanosheets. Thus, the CFET device 100 can include a bottom nanosheet FET (NSHFET) 110 and a top NSHFET 120. In another CFET design, the channel structure 113 of the bottom device 110 can include a plurality of channel nanosheets, and the channel structure 123 of the top device 120 can include a semiconductor fin (i.e., a fin-shaped channel structure). Thus, the CFET device 100 can include a bottom nanosheet FET (NSHFET) 110 and a top FinFET 120.

[0068] The bottom gate 114 can partially (e.g., on three sides) or completely surround the bottom channel structure 113 to define a gate-all-around (GAA) for one or more channel nanosheets of the bottom channel structure 113. The top gate 124 can partially (e.g., on three sides) or completely surround the top channel structure 123 to define a gate-all-around (GAA) for one or more channel nanosheets of the top channel structure 123.

[0069] The channel structures 113, 123 include a semiconductor material, such as a Group-IV semiconductor, e.g., Si, Ge, or SiGe. However, other materials are also possible, e.g., Group-III-V semiconductors (e.g., InP, InAs, GaAs, GaN).

[0070] The S / D regions 111, 112, 121, 122 can include or be formed of an epitaxial S / D body. The epitaxial S / D body can include a doped semiconductor material (e.g., Si, Ge, SiGe), e.g., grown epitaxially on the channel structures 113, 123. The S / D regions 111, 112, 121, 122 can optionally be formed of a doped portion of the channel structures 113, 123.

[0071] The S / D contacts 115, 116, 125, 126 may include one or more contact metals such as W, Al, Ru, Mo, or Co, and optionally conventional barrier metals such as Ta, TiN, or TaN.

[0072] The gates 114, 124 may include one or more gate metal layers such as one or more work function metal (WFM) layers and / or gate fill layers. Example WFMs include conventional n-type and p-type effective WFM metals such as TiN, TaN, TiAl, TiAlC, or WCN or combinations thereof. Example fill materials include W and Al. A gate dielectric layer (not shown) is disposed between the gates 114, 124 and the corresponding channel structures 113, 123. Example gate dielectrics include conventional gate dielectrics such as high-k dielectrics such as HfO2, LaO, AlO, and ZrO.

[0073] As Figure 4 shown, the CFET device 100 has a split gate configuration and separate (i.e., disconnected) first S / D contacts 115, 125 and separate second S / D contacts 116, 126. However, there are many other configurations for the CFET device, which will now be discussed with reference to Figure 5a -f. Figure 5a , 5c , 5e each show a cross-section of a corresponding configuration of the CFET device taken through the channel structures 113, 123 and along the gates 114, 124 (i.e., along the Figure 4 plane P2 shown in). At the same time, Figure 5b , 5d , 5f each show a cross-section of a corresponding configuration of the CFET device taken through the sources 111, 121 and the contacts 115, 125 (i.e., along the Figure 4 plane P3 shown in). Although Figure 5b , 5d , 5f show cross-sections at one side of the first S / D region of the CFET device, the configurations shown in these figures can be applied to the second opposite S / D region of the CFET device in a corresponding manner.

[0074] Figure 5a shows a CFET device 100a having a split gate configuration, which has a separate bottom gate 114 and a top gate 124. As shown, the bottom gate 114 includes a side gate portion or gate extension that protrudes beyond the top gate 124 to define a landing portion for the gate via GV. The gate extension extends laterally with respect to the channel structures 113, 123, i.e., along the Y direction. The size or extent of the gate extension may vary depending on the available space adjacent to the CFET device 100a in a given circuit implementation. However, the minimum extension of the gate extension is determined byFigure 5a The critical dimension (CD) shown in Figure 5a corresponds to the minimum spacing between the GV and the top gate 124. As shown, the top gate 124 can be contacted through a separate GV.

[0075] Figure 5b The CFET device 100b is shown, which includes separate first S / D contacts 115, 125, where the bottom contact 115 includes a side contact portion or contact extension that protrudes outside the top contact 125 to define a landing portion for the contact via CV. The gate extension extends laterally with respect to the channel structures 113, 123, i.e., along the Y direction. The size or extent of the contact extension can vary depending on the available space adjacent to the CFET device 100b. However, the minimum extension of the contact extension is determined by Figure 5b the critical dimension (CD) shown in Figure 5b , which corresponds to the minimum spacing between the GV and the top contact 125. As shown, the top contact 125 can be contacted through a separate GV.

[0076] Figure 5b Another contact scheme for the bottom contact 115 is also shown, where the bottom contact 115 is contacted from the backside of the substrate or device through a BPR via (VBPR) (also known as a power via (PV)). The VBPR can in turn be connected to a backside or buried power rail (BPR). The term BPR is used herein in an inclusive sense to refer to a power rail, whether it is formed in a trench embedded in the substrate in a front-end process or as part of a backside power distribution network (PDN) formed on the backside of the substrate in a back-end process.

[0077] Figure 5c The CFET device 100c with a common gate configuration is shown, and thus includes a common gate 104 shared by the bottom device 110 and the top device 120. The common gate 104 includes a bottom gate portion 114 and a top gate portion 124 coupled to the bottom gate portion 114 through a gate merge via GM. The gate merge via is disposed between the bottom gate portion 114 and the top gate portion 124 and extends therebetween (i.e., vertically along the Z direction) to interconnect the gate portions 114 and 124. As shown, the common gate can be contacted through a GV landing on the top gate portion 124.

[0078] Figure 5dIllustrated is a CFET device 100d, which includes a common S / D contact 105 shared by a bottom device 110 and a top device 120, more specifically, shared by a first bottom S / D region 111 and a first top S / D region 121. The common S / D contact 105 includes a bottom contact portion 115 and a top contact portion 125 coupled to the bottom contact portion 115 through a contact merge via M0AM (where M0A represents a local interconnect level of the CFET device 100d). The contact merge via is disposed between the bottom contact portion 115 and the top contact portion 125 and extends therebetween (i.e., vertically extends in the Z direction) to interconnect the contact portions 115 and 125. The bottom contact portion 115 is disposed on (e.g., surrounds) the bottom source 111, and the top contact portion 125 is disposed on (e.g., surrounds) the top source 121. As shown, the common gate 105 can be contacted through a CV landing on the top contact portion 125. Although Figure 5d not shown in Figure 5b , the common contact can also be contacted from the back, e.g., in a manner similar to

[0079] Figure 5e Illustrated is a CFET device 100e, which includes a common gate 104’, which includes a bottom gate portion 114’ and a top gate portion 124’. The bottom gate portion 114’ and the top gate portion 124’ form part of a continuous common gate 104’ (e.g., as an integrally formed gate body). Thus, Figure 5e Illustrated is another example of a CFET device 100e, which includes a common gate shared by a bottom device 110 and a top device 120. As Figure 5e shown, the bottom gate portion 114’ corresponds to the portion of the common gate 104’ surrounding the channel structure of the bottom device 110, while the top gate portion 124’ corresponds to the portion of the common gate 104’ surrounding the channel structure of the top device 120. As shown, the common gate can be contacted through a GV landing on the top gate 124. Although Figure 5e shown with the same fill pattern for the bottom gate 114 and the top gate 124, bottom gate portions 114 and top gate portions 124 of different compositions can also be formed using appropriate process techniques (e.g., “split RMG” CFET process).

[0080] Figure 5f Illustrated is a CFET device 100f, which includes a common S / D contact 105’, including a bottom contact portion 115’ and a top contact portion 125’. The bottom contact 115 and the top contact 125 form part of a continuous common contact 105’ (e.g., as an integrally formed contact body). Thus, Figure 5fAnother example of a CFET device 100f is shown, which includes a common S / D contact 105' shared by a bottom device 110 and a top device 120. As Figure 5f shown, the bottom contact portion 115' corresponds to the portion of the common contact 105' disposed on (e.g., surrounding) the bottom source 111, while the top contact portion 125' corresponds to the portion of the common contact 105' disposed on (e.g., surrounding) the top source 121. As shown, the common S / D contact 105' can be contacted by a CV landing on the top contact portion 125. Although Figure 5f the same fill pattern for the bottom contact portion 115' and the top gate 125' is shown, different compositions of the bottom contact portion 115' and the top contact portion 125' can also be formed using appropriate process techniques.

[0081] For example, Figure 5a the split gate configuration shown can be obtained using a "sequential CFET process". As is known in the art, in a sequential CFET process, the bottom and top devices are formed sequentially, resulting in separation of the bottom gate and the top gate.

[0082] Figure 5c The common gate configuration of can be achieved by supplementing the standard sequential CFET process with additional process steps to form a gate merge via GM to interconnect the bottom and top gate portions. For example, Figure 5e the common gate configuration shown can be obtained using a "monolithic CFET process". As is known in the art, in a monolithic CFET process, the bottom and top devices are processed in parallel, top-down. Although the standard monolithic CFET process results in a common gate configuration, additional process steps can be supplemented to achieve a split gate configuration for selected CFET devices (e.g., bottom gate grooving, bottom gate capping, and then forming the top gate).

[0083] Conventional CFET device processing techniques can be used to form common or separate source or drain contacts. For example, separate (first or second) S / D contacts can be formed by depositing contact metal on the (first or second) S / D region, etching the contact metal back to a level below the (first or second) top S / D region, capping the remaining contact metal of the (first or second) bottom S / D region with an insulating layer, and subsequently depositing contact metal on the (first or second) top S / D.

[0084] Now reference will be made to Figure 6a-c, 7a-c and 8a-c describe various example implementations of SRAM devices with CFET-based 8T dual-port bit cells. The common feature is that the bit cell includes a first half cell H1 and a second half cell H2, each half cell including first and second CFET devices, wherein the first CFET device includes a common gate shared by its bottom device and top device and is configured as an inverter (corresponding to the inverter of the other half cell) cross-coupled to the inverter of the other half cell. Figure 3 In addition, the bottom device of the second CFET device of each half cell is configured as the corresponding half cell (corresponding to Figure 3 The first transmission gate of the first port of BL-A and BLB-A in FIG. Figure 3 PG1-A and PG2-A in FIG3 ), and includes a bottom gate coupled to a first word line (corresponding to WL-A in FIG3 ). In addition, the top device of the second CFET device of each half cell is configured as a corresponding half cell (corresponding to Figure 3 The second transmission gate of the second port of BL-B and BLB-B in FIG. Figure 3 3 ), and includes a top gate separated from a bottom gate and coupled to a second word line (corresponding to WL-B in FIG. 3 ). Each bit cell design will be described in more detail below.

[0085] exist Figure 6a In FIG. 1 , the first and second CFET devices of the first half cell H1 and the second half cell H2 have reference numerals 21 and 22, and 23 and 24, respectively. Figure 7a In FIG. 1 , the first and second CFET devices of the first half cell H1 and the second half cell H2 have reference numerals 31 and 32, and 33 and 34, respectively. Figure 8a In FIG. 1 , the first and second CFET devices of the first half cell H1 and the second half cell H2 have reference numerals 41 and 42, and 43 and 44, respectively.

[0086] In addition, the reference numerals and labels in the drawings have the following common meanings:

[0087] Reference numeral E denotes the edge of the bit cell. Reference numerals H1 and H2 denote the first and second half cells of the bit cell. Direction X represents the cell width dimension and equivalently represents the channel direction of the CFET of the bit cell, while direction Y represents the cell height dimension. Lines A1 and A2 denote the first and second active rails of the bit cell extending parallel in the cell width dimension X. Lines G1 and G2 denote the first and second gate rails of the bit cell extending parallel in the cell height dimension Y. Lines S1 - S3 denote the respective S / D contact rails extending parallel in the cell height dimension Y, where the first and third S / D contact rails S1, S3 extend along the opposite edges of the bit cell, while the second S / D contact rail S3 extends midway between G1 and G2. The crossed - out rectangular region denotes the gate cut region (GC).

[0088] The fill patterns used in the figures have the following meanings:

[0089] “M0AB” is the local interconnect level of the bottom level. Thus, the fill pattern associated with “M0AB” features contacts at the bottom level (e.g., bottom S / D contacts). M0AT is the local interconnect level of the top level. Thus, the fill pattern associated with M0AT features contacts at the top level (e.g., top S / D contacts). M0AB and M0AT are each included in the local interconnect level “M0A” of the bit cell.

[0090] The fill pattern associated with “GV” is used to indicate the gate vias extending between the bottom gate / bottom gate part (“GB”) and the upper interconnect level or the top gate / top gate part (“GT”), as Figure 5a shown. The upper interconnect level can be the first interconnect level above the local interconnect level M0A (sometimes denoted as “M0” or “MINT” depending on the context).

[0091] The fill pattern associated with “CV” represents the contact vias extending between M0AB or M0AT and the upper interconnect level, as Figure 5b shown. Similar to the gate via GV, the upper interconnect level can be the first interconnect level above the local interconnect level M0A (e.g., M0).

[0092] The fill pattern associated with “M0AM” is the local interconnect merge layer or via that interconnects the contacts in M0AB with the contacts in M0AT, as Figure 5d shown.

[0093] The fill pattern associated with “GM” represents the gate merge layer or via that interconnects the bottom gate or bottom gate part (GB) with the top gate or top gate part (GT), as Figure 5c shown.

[0094] The fill pattern associated with "B-NS" represents nanosheets or stacks of nanosheets in the bottom level B. The fill pattern associated with "T-NS" represents nanosheets or stacks of nanosheets in the top level T. The fill pattern associated with "T-Fin" represents fins or fin-shaped channel structures in the top level T.

[0095] The fill pattern associated with "XC" represents a cross-coupled merge layer or metal strip formed on top of M0AT and included in the local interconnect layer M0A. It can also be referred to as a gate spacer merge layer because it can be arranged to extend over the gate spacer to merge or interconnect the gate with the S / D contacts in M0AT.

[0096] The fill pattern associated with "VBPR" represents a via to the BPR. In the case where VBPR is shown above a contact in M0AT, it will be understood that another via extends from M0AT through the local interconnect layer M0AB and lands on VBPR.

[0097] Figure 6a 、 7a The rectangular box to the left of the bit cell in 8a represents an instance of BPR extending parallel in the Y direction below the bit cell.

[0098] The rectangular box to the right of the bit cell represents a wiring track in the first interconnect layer above the local interconnect layer M0A (e.g., M0) extending parallel in the Y direction within the footprint of the bit cell. As is known to those skilled in the art, the metal lines (e.g., word lines or bit lines) in any given wiring track arranged in the first interconnect level (or the second interconnect level) do not need to extend along the full width dimension (or full height dimension) of the bit cell, but should at least extend to define an overlap with any contact via CV, gate via GV arranged along the wiring track, so as to achieve coupling between the metal line and the underlying contact or gate.

[0099] The rectangular box below the bit cell represents a wiring track in the second interconnect layer above the first interconnect level (e.g., M1). The metal lines in any given wiring track arranged in the second interconnect layer can be coupled (e.g., through vias in M1) to the metal lines in the correspondingly marked wiring track in the first interconnect layer.

[0100] Figure 6a -c shows an SRAM device 2 according to a first design, which includes a CFET-based dual-port 8T bit cell.

[0101] As shown in the figure, the S / D regions, S / D contacts, and gates of the first CFET device 21 and the second CFET device 22 in the first half unit H1 are arranged along the first active rail A1. Correspondingly, the S / D regions, S / D contacts, and gates of the first CFET device 23 and the second CFET device 24 in the second half unit H2 are arranged along the second active rail A2. In addition, the common gate of the first CFET device 21 in the first half unit H1 and the separate bottom and top gates of the second CFET device 24 in the second half unit H2 are arranged along the first gate rail G1, while the common gate of the first CFET device 23 in the second half unit H2 and the separate bottom and top gates of the second CFET device 22 in the first half unit H1 are arranged along the second gate rail G2.

[0102] Each bottom device 21B, 22B, 23B, 24B and each top device 21T, 22T, 23T, 24T of the CFET devices 21, 22, 23, 24 include a first S / D region and a second S / D region. The first S / D regions of the CFET devices 21 and 24 are arranged along the first S / D contact rail S1. The first S / D regions of the CFET devices 22 and 23 are arranged along the third S / D contact rail S3. The second S / D regions of the CFET devices 21, 22, 23, 24 are arranged along the second S / D contact rail S2.

[0103] The first half unit H1 includes a first common S / D contact, which is arranged between the first CFET 21 and the second CFET 22 in the first half unit H1 and is shared by their respective second S / D regions. The second half unit H2 includes a second common S / D contact, which is arranged between the first CFET 23 and the second CFET 24 in the second half unit H2 and is shared by their respective second S / D regions. The first and second common S / D contacts are arranged along the second S / D contact rail S2.

[0104] The first S / D region of each CFET device 21, 22, 23, 24 is respectively coupled to a corresponding S / D contact separated between the bottom stage 20B and the top stage 20T. Therefore, the first S / D regions of the bottom and top devices of the CFET devices 21, 22, 23, 24 are separately contacted. The S / D contacts coupled to the first S / D region of the first CFET device 21 in the first half unit H1 and the first S / D region of the second CFET device 24 in the second half unit H2 are arranged along the first S / D contact rail S1. The S / D contacts coupled to the first S / D region of the second CFET device 22 in the first half unit H1 and the first S / D region of the first CFET device 23 in the second half unit H2 are arranged along the third S / D contact rail S3.

[0105] According to the illustrated example, the bottom level 20B and the top level 20T each include four PMOS devices (PU-1, PU-2, PG1-A, and PG2-A) and four NMOS devices (PD-1, PD-2, PG1-B, and PG2-B).

[0106] By using the M0A merge layer M0AM to merge the drains of PU-1 (PU-2) and PD-1 (PD-2) of the first CFET devices 21 (and 23) and using the gate merge layer GM to merge their top and bottom gates, two inverters are created.

[0107] The gate spacer merge layer XC on the top level 20T is used to implement inverter cross-coupling. More specifically, as shown, each of the first and second common S / D contacts includes a respective contact extension that protrudes along the cell height dimension X towards the other common S / D contact. Additionally, the common gates of the first CFET devices 21, 23 each include a gate extension that protrudes towards the (separate) gates of the second CFET devices 22, 24 of the opposite half-cells H1, H2.

[0108] The gate extension of the common gate of the first CFET device 21 of the first half-cell H1 protrudes such that its end portion is separated from the end portions of the bottom and top gates of the second CFET device 24 of the second half-cell H2 by the first gate cut region GC. Correspondingly, the gate extension of the common gate of the first CFET device 23 of the second half-cell H2 can protrude such that its end portion is separated from the end portions of the bottom and top gates of the second CFET device 22 of the first half-cell H1 by the second gate cut region GC.

[0109] The first metal strip XC extends in the Y direction to bridge the distance between the respective end portions of the gate extensions of the common gate of the first CFET device 21 of the first half-cell H1 and the respective end portions of the contact extensions of the second common S / D contact of the second half-cell H2, thereby interconnecting them. Correspondingly, the second metal strip XC extends in the Y direction to bridge the distance between the respective end portions of the gate extensions of the common gate of the first CFET device 23 of the second half-cell H2 and the respective end portions of the contact extensions of the first common S / D contact of the first half-cell H1, thereby interconnecting them.

[0110] The PMOS transmission gates of port A (PG1-A and PG2-A) are arranged in the bottom level 20B below the NMOS transmission gates of port B (PG1-B and PG2-B). When the top and bottom gates of the respective second CFETs 22 and 24 are separate, the transmission gates of port A and port B can be independently controlled.

[0111] Layout of the bottom level 20B and Figure 6b cross-sectional view (taken along Figure 6a A-A of) shows the split-gate configuration of the stacked transfer gates PG1-A, PG1-B, the minimum gate extension GE, and the 1CD (critical dimension) spacing requirement from the top gate TG to the gate via GV to the bottom gate BG to connect to WL-A.

[0112] The SRAM device 2 includes two instances of the pull-up power rail (“first power rail”) VDD as shown, which are configured as BPRs extending in the cell width dimension X along opposite edges of the bit cell 20. The pull-up devices PU-1 and PU-2 are coupled to the respective instances of the pull-up power rail VDD through corresponding VBPRs.

[0113] The SRAM device 2 also includes an instance of the pull-down power rail (“second power rail”) VSS, which is also configured as a BPR and extends along the midline C of the bit cell 20 in the cell width dimension X. The pull-down devices PD-1 and PD-2 are coupled to the instance of the pull-down power rail VSS through corresponding VBPRs.

[0114] The bit cell interconnections are otherwise as follows:

[0115] The bit cell 20 is associated with eight wiring rails, each wiring rail including a respective instance of the first or second word line WL-A, WL-B, the first or second bit line BL-A, BL-B, or the first or second complementary bit line BLB-A, BLB-B. As shown, the first and second instances of the first word line WL-A can be arranged in the respective edge rails, overlapping the top and bottom edges of the bit cell 20. This allows the instances of the first word line WL-A to be shared by adjacent bit cells.

[0116] The separate bottom and top S / D contacts (in M0AB and M0AT respectively) of the first and second transfer gates PG1-A, PG1-B of the first half cell H1 are coupled to the first and second bit lines BL-A, BL-B (arranged in M0) through respective contact vias CV. The contact vias are arranged at opposite lateral sides of the first active rail A1 as shown.

[0117] The separate bottom gates GB and top gates GT of the first and second transfer gates PG1-A, PG1-B of the first half cell H1 are coupled to the first instance of the first word line WL-A and the first instance of the second word line WL-B (arranged in M0) through respective gate vias GV. The gate vias are arranged at opposite lateral sides of the first active rail A1 as shown.

[0118] The separate bottom and top S / D contacts (in M0AB and M0AT, respectively) of the first and second transfer gates PG2-A and PG2-B of the second half cell H2 are coupled to the first and second complementary bitlines BLB-A and BLB-B (arranged in M0) through respective contact vias CV. The contact vias are arranged at opposite lateral sides of the second active rail A2 as shown.

[0119] The separate bottom gates GB and top gates GT of the first and second transfer gates PG2-A and PG2-B of the second half cell H2 are coupled to a second instance of the first wordline WL-A and a second instance of the second wordline WL-B (arranged in M0) through respective gate vias GV. The gate vias are arranged at opposite lateral sides of the second active rail A2 as shown.

[0120] From Figure 6a -c, it can be understood that the bit cell height along the bit cell height dimension X is determined by the minimum gate cut (GC), minimum gate extension (GE), nanosheet width (NSHW), minimum gate internal spacer merge width (GI), minimum space between gate spacer merge layers (GIP), and the CD requirement from the gate via to the bottom gate. As an illustrative example, for an existing technology node, the total cell height becomes 136 nm:

[0121] Cell height = 2*GC + 4*GE + 2*NSHW + 2*GI + GIP + 3*CD = 2*12 + 4*9 + 2*11 + 2*9 + 9 + 3*9 = 136 nm (Equation 1)

[0122] It can be understood that the parameter values in Equation 1 should only be regarded as representative examples. However, the form of Equation 1 is of course also applicable to other values of various parameters.

[0123] As Figure 6a -c shows, most of the signal routing and integration are enabled in the top level 20T, so that the bottom level 20B is basically unoccupied. However, as shown in the above cell height equation, the formation of cross-coupling requires two gate spacer merge layer widths GI and a spacing GIP. This limits the ability to shrink the bit cell height. By forming part of the cross-coupling in the bottom level (which is basically empty) instead of only in the top level, this limitation can be avoided. Thus, as Figure 7a shown by the SRAM device 3 and the bit cell 30 in -c, the cross-coupling formation is split into partial integration in the bottom level 30B and the top level 30T. However, compared with the layout in Figure 6a -c, this layout design requires a bottom cross-coupling merge layer (bottom metal strip) "XCB" and a top cross-coupling merge layer (top metal strip) "XCT".

[0124] More specifically, the gate extension of the common gate (the first common gate) of the first CFET device 31 of the first half unit H1 and the contact extension of the second common S / D contact of the second half unit H2 are arranged in the bottom device level 30B, rather than in the top device level 30T. At the same time, the gate extension of the common gate (the second common gate) of the first CFET device 33 of the second half unit H2 and the contact extension of the first common S / D contact are arranged in the top device level 30T, rather than in the bottom device level 30B.

[0125] Therefore, the gate extension of the first common gate is included in the bottom gate portion GB and protrudes relative to the top gate portion GT in the first common gate. Correspondingly, the contact extension of the second common S / D contact is included in the bottom contact portion of the second common S / D contact and protrudes relative to the top contact portion (in M0AT) of the second common S / D contact. On the other hand, the gate extension of the second common gate is included in the top gate portion GT of the second common gate and protrudes relative to the bottom gate portion GB of the second common gate. Correspondingly, the contact extension of the first common S / D contact is included in the top contact portion (in M0AT) of the first common S / D contact and protrudes relative to the bottom contact portion (in M0AB) of the first common S / D contact.

[0126] As shown, the corresponding contact extensions can protrude beyond the midline C of the bit cell 30. The cross-coupling merge layer / first metal strip XC for cross-coupling in the bottom level 30B can be included in the local interconnect layer M0A and is arranged on top of the bottom-level local interconnect layer M0AB.

[0127] The cross-coupling merge layer / first metal strip XC for cross-coupling in the top level 30T can be included in the local interconnect layer M0A and is arranged on top of the top-level local interconnect layer M0AT.

[0128] In addition, to avoid a direct impact on the cell height and facilitate process integration, as Figure 7a shown, the corresponding M0A merge layers M0AM of the first and second common S / D contacts and the gate merge layer GM of the common gates of the first CFET devices 21 and 23 have been shifted towards the cell edge to be arranged outside the region between the first and second active rails A1, A2. These two changes, namely enabling cross-coupling separately in the top and bottom levels and removing M0A MRG between the devices, result in a bit cell height of 114 nm:

[0129] Cell height = GC + 3*GE + 2*NSHW + GI + GIP + 3*CD + M0A_extn

[0130] = 12 + 3*9 + 2*11 + 9 + 12 + 3*9 + 5 = 114 nm (Equation 2)

[0131] It is 22 nm smaller than the layout design of -c. The additional term M0A_extn (denoted as ME in the figure) is the minimum extension of the S / D contacts in M0AB or M0AT. Figure 6a -c's layout design of the CFET NS-on-NS scheme bit cell's ratio of the dual-port 8T to the single-port 6Td is 114 nm / 97 nm (= 1.18). To further scale the CFET dual-port 8T bit cell, the top nanosheet is located

[0132] The above Figure 7a -c's CFET NS-on-NS scheme bit cell design of the dual-port 8T to the single-port 6Td is 114 nm / 97 nm (= 1.18). To further scale the CFET dual-port 8T bit cell, the top nanosheet is located Figure 8a in the bit cell 40 of the SRMAM device 4 of -c, and is replaced by Fin NMOS devices to obtain the first and second Fin-on-NS CFETs 41, 42, 43, 44 in each half cell H1, H2. In other words, the bottom devices of the CFET devices 41, 42, 43, 44 are configured as nanosheet FETs, while the top devices are configured as finFETs. This enables further shrinkage, as described below.

[0133] However, the height of the Fin-on-NS bit cell is not sufficient for all the wiring tracks in the first interconnect level M0. Therefore, the second power rail VSS is shifted to the first interconnect level M0, and the bit lines of port A (BL-A and BLB-A) are configured as buried bit lines, as Figure 8b shown in the cross-sectional view of -c, and are arranged between two instances of the first BPR VDD.

[0134] Therefore, compared with the bit cell 30, the bit cell 40 is only associated with seven wiring tracks of the first interconnect level M0. Similar to the bit cell 30, the first and second instances of the first word line WL-A are arranged along the first and second edge tracks. The second power rail VSS is arranged along the middle track (or center track). The second bit line BL-B and the second complementary bit line BLB-B are respectively arranged in the first and second eccentric tracks, and the first and second eccentric tracks are arranged on the opposite sides of the middle track. The first and second instances of the second word line WL-B are respectively arranged in the third and fourth eccentric tracks, the third eccentric track is arranged between the first edge track and the first eccentric track, and the fourth eccentric track is arranged between the second edge track and the second eccentric track.

[0135] Therefore, inside the bit cells 30, 40 (i.e., between the active tracks A1 - A2), Figure 7a and 8a the layout dimensions are basically the same, and ignoring the nanosheet width NSHW and the fin width FW, it is given by GE + GC + GI + GIP + M0A_extn.

[0136] Towards the edge of bit cell 30, the remaining dimension is calculated as 2*(NSHW + GE + CD + 0.5CD). The additional 0.5CD is introduced by the WL-A routing track in the first interconnect layer M0 of WL, which will be shared with adjacent top and bottom bit cells ( Figure 7a not visible in), which gives the cell height calculated in Equation 2.

[0137] For the Fin-on-NS case of bit cell 40, the cell height is determined only by the layout design requirements of the top level 40T. This is because the gate extension GE required for the top Fin T-Fin starts from the edge of the fin (within the occupied area of the bottom nanosheet B-NS) and extends over the bottom nanosheet B-NS. Therefore, in this layout, the nanosheet width NSHW has no effect on the cell height. Thus, the remaining contribution to the cell height becomes 2*(FW + GE + CD + 0.5*GC), which gives the total cell height:

[0138] Cell height = (GE + GC + GI + GIP + M0A_extn) + 2*(FW + GE + CD + 0.5*GC) = 2*GC + 3*GE + 2*FW + GI + GIP + 2*CD + M0A_extn

[0139] = 2*12 + 3*9 + 2*5 + 9 + 12 + 3*9 + 5 = 105 nm (Equation 3)

[0140] Placing the Fin device on top does not scale the 6T CFET bit cell height. Thus, the bit cell occupied area ratio of dual-port (8T) to single-port (6T) is 1.08, which is very close to the ratio 1 theoretically possible in the CFET device architecture.

[0141] Those skilled in the art will realize that the present invention is in no way limited to the above-described embodiments. On the contrary, within the scope of the appended claims, many modifications and variations are possible. For example, although in the illustrated example, the PMOS device is arranged in the bottom level while the NMOS device is arranged in the top level, the NMOS device can also be arranged in the bottom level and the PMOS device in the top level. This can be done without changing the inverter cross-coupling, but only requires some corresponding permutations of the power rails and routing tracks, such as the configuration of the power rails VDD, VSS, such that there are two instances of the pull-down power rail VSS and one instance of the pull-up power rail VDD. Additionally, although in the illustrated example, the configuration of the CFET device can be obtained using, for example, a sequential CFET process. It is envisioned that a similar bit cell layout can be implemented using a monolithic CFET process, supplemented with an additional process step of forming split gates between the bottom and top transfer gates.

Claims

1. A static random access memory (SRAM) device (1, 2, 3, 4), comprising: A plurality of bit cells (10, 20, 30, 40), each bit cell comprising a first half cell (H1) and a second half cell (H2), each half cell comprising: first and second complementary field effect transistor (CFET) devices (21, 22, 23, 24), each CFET device comprising a bottom device (21B, 22B, 23B, 24B) and a top device (21T, 22T, 23T, 24T) stacked on top of the bottom device (21B, 22B, 23B, 24B), wherein the first CFET device (21, 23) includes a common gate shared by the bottom device (21B, 23B) and the top device (21T, 23T) and is configured as an inverter (PU-1, PD-1; PU-2, PD-2) cross-coupled to the inverter of the other half cell (H2, H1), wherein a bottom device (22B, 24B) of the second CFET device (22, 24) is configured as a first pass gate (PG1-A, PG2-A) for a first port of the half cell (H1, H2) and includes a bottom gate coupled to a first word line (WL-A), and The top device (22T, 24T) of the second CFET device (22, 24) is configured as a second transmission gate (PG1-B, PG2-B) for the second port of the half cell (H1, H2), and includes a top gate separated from the bottom gate and coupled to a second word line (WL-B).

2. The SRAM device according to claim 1, characterized in that: The common gate of the first CFET device (21) of the first half cell (H1) and the bottom gate and the top gate of the second CFET device (24) of the second half cell (H2) are arranged along a first gate rail (G1), and the common gate of the first CFET device (23) of the second half cell (H1) and the bottom gate and the top gate of the second CFET device (22) of the first half cell (H1) are arranged along a second gate rail (G2), the first gate rail (G1) and the second gate rail (G2) being parallel to a cell height dimension (Y) of the bit cell (10, 20), and Wherein, each CFET device (21, 22, 23, 24) includes a first and a second S / D region, wherein the S / D region of the CFET device (21, 22) of the first half cell (H1) is arranged along a first active rail (A1), and the S / D region of the CFET device (23, 24) of the second half cell (H2) is arranged along a second active rail (A2), and the first and second active rails (A1, A2) are parallel to a cell width dimension (X) of the bit cell (10, 20) and transverse to the cell height dimension (Y).

3. The SRAM device according to claim 2, characterized in that: The first half cell (H1) comprises a first common S / D contact, the first common S / D contact being arranged between and shared by the first and second CFET devices (21, 22; 31, 32) of the first half cell (H1), and the second half cell (H2) comprises a second common S / D contact, the second common S / D contact being arranged between and shared by the first and second CFET devices (23, 24; 33, 34) of the second half cell (H2), wherein the common S / D contacts of the first and second half cells each include a contact extension projecting toward the common S / D contact of the other half cell (H1, H2), wherein the common gates of the first CFET devices (21, 23; 31, 33) of the first and second half cells (H1, H2) define a first common gate and a second common gate, respectively, wherein the first common gate and the second common gate each include a gate extension protruding toward the second CFET device (22, 24; 32, 34) of the other half cell (H1, H2), The bit unit (20; 30) comprises: a first local cross-coupling interconnect extending between and interconnecting respective end portions of a gate extension of the first common gate and a contact extension of the second common S / D contact, and A second local cross-coupling interconnect extends between and interconnects respective end portions of a gate extension of the second common gate and a contact extension of the first common S / D contact.

4. The SRAM device according to claim 3, characterized in that: The end portion of the gate extension of the first common gate is separated from the end portions of the bottom gate and the top gate of the second CFET device (24) of the second half unit (H2) by a first gate cutting region (GC), and wherein the end portion of the gate extension of the second common gate is separated from the end portions of the bottom gate and the top gate of the second CFET device (22) of the first half unit (H1) by a second gate cutting region (GC).

5. The SRAM device according to any one of claims 3 to 4, characterized in that: The first local cross-coupling interconnect and the second local cross-coupling interconnect are configured as first and second metal strips, respectively, extending along the cell width dimension (X) to bridge a distance between respective end portions.

6. The SRAM device according to claim 5, characterized in that: The first metal strip and the second metal strip are arranged on top of the respective end portions.

7. The SRAM device according to any one of claims 5 to 6, characterized in that: The bottom device (31B, 32B, 33B, 34B) is arranged in a bottom device level (30B) of the bit cell (30), and the top device (31T, 32T, 33T, 34T) is arranged in a top device level (30T) of the bit cell (30), wherein the gate extension of the first common gate and the contact extension of the second common S / D contact are arranged in the bottom device level (30B) and not in the top device level (30T), and Wherein the gate extension of the second common gate and the contact extension of the first common S / D contact are arranged in the top device level (30T) but not in the bottom device level (30B).

8. The SRAM device according to claim 7, characterized in that: The contact extension portion protrudes at least to the center line (C) of the position unit (30).

9. The SRAM device according to any one of claims 7 to 8, characterized in that: Each bottom device (41B, 42B, 43B, 44B) is a nanosheet FET device, and each top device (41T, 42T, 43T, 44T) is a finFET device including a channel structure having a width dimension less than a width dimension of the channel structure of each nanosheet FET device.

10. The SRAM device according to any one of claims 5 to 6, characterized in that: The bottom device (21B, 22B, 23B, 24B) is arranged in a bottom device level (20B) of the bit cell (20), and the top device (21T, 22T, 23T, 24T) is arranged in a top device level (20T) of the bit cell (20), Wherein gate extensions of the first common gate and the second common gate and contact extensions of the first common S / D contact and the second common S / D contact are arranged at least in the top device level (20T).

11. The SRAM device according to any one of the preceding claims, characterized in that The first and second transmission gates (PG1-A, PG1-B) of the first half cell (H1) are coupled to the first and second bit lines (BL-A, BL-B), respectively. wherein the first and second transmission gates (PG2-A, PG2-B) of the second half cell (H2) are coupled to first and second complementary bit lines (BLB-A, BLB-B), and Wherein the inverters of the first half cell and the second half cell are coupled to a first power rail (VDD) and a second power rail (VSS), one providing a pull-up voltage and the other providing a pull-down voltage.

12. The SRAM device according to claim 11, when referring to claim 2, characterized in that: an inverter of the first half cell (H1) is coupled to a first instance of the first power rail (VDD), and an inverter of the second half cell (H2) is connected to a second instance of the first power rail (VDD), wherein the first instance and the second instance of the first power rail (VDD) are configured as respective buried power rails extending along a bottom edge and a top edge of the respective bit cell (20, 30, 40), and wherein the inverters of the first half cell (H1) and the second half cell (H2) are coupled to a same instance of the second power rail (VSS), wherein the instance of the second power rail (VSS) is configured as a buried power rail extending along a centerline of the corresponding bit cell (20, 30), or as a metal line in a routing track of an interconnect level above the bit cell (40).

13. The SRAM device according to claim 12, when further referred to in claim 9, characterized in that: The instance of the second power rail (VSS) is configured as a metal line in a wiring track of an interconnect level arranged above the bit cell (40), and the first bit line (BL-A) and the first complementary bit line (BLB-A) are configured as buried signal lines arranged between a first instance and a second instance of the first power rail.

14. The SRAM device according to claim 13, characterized in that: The routing track is a middle track of a set of routing tracks of the interconnect level and is associated with the bit cell (40), the set of routing tracks extending along the cell width dimension (X) and further comprising: a first edge track and a second edge track overlapping the top edge and the bottom edge of the bit cell, respectively, a first eccentric track and a second eccentric track arranged on opposite sides of the middle track, a third eccentric track arranged between the first eccentric track and the first edge track, and a fourth eccentric track arranged between the second eccentric track and the second edge track, wherein a first instance and a second instance of the first word line (WL-A) are arranged in the first edge rail and the second edge rail, respectively, a first instance and a second instance of the second word line (WL-B) are arranged in the third eccentric track and the fourth eccentric track, respectively, and The second bit line (BL-B) and the second complementary bit line (BLB-B) are arranged in the first eccentric track and the second eccentric track, respectively.

15. The SRAM device according to any one of the preceding claims, characterized in that The bottom device (21B, 22B, 23B, 24B) of each CFET (21, 22, 23, 24) is a PMOS device, and the top device (21T, 22T, 23T, 24T) of each CFET (21, 22, 23, 24) is an NMOS device, or vice versa.

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