Semiconductor device and operation method of semiconductor device

Abstract

The present disclosure relates to a semiconductor device and an operating method of the semiconductor device, the semiconductor device may include: at least one string connected between a bit line and a source line, and including a plurality of memory cells connected to a plurality of word lines; and a page buffer connected to the bit line and configured to sense data stored in the plurality of memory cells. In a state in which a pass voltage is supplied to an unselected word line among the plurality of word lines, multi-bit data stored in a selected memory cell among the plurality of memory cells may be continuously output by sequentially supplying read voltages having different levels to a selected word line among the plurality of word lines.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0188061, filed on December 21, 2023, which is incorporated herein by reference in its entirety. Technical field

[0003] Embodiments of the present disclosure relate to an integrated circuit technology, and more particularly, to a semiconductor device and an operation method of the semiconductor device. Background art

[0004] Recently, as the sizes of various electronic devices are reduced and have low power consumption and high performance, various electronic devices such as computers and portable communication devices require semiconductor devices capable of storing information. The semiconductor device may be a volatile memory device or a non - volatile memory device. The volatile memory device has a high data processing speed, but the disadvantage is that continuous power supply needs to be provided to the volatile memory device to retain the data stored in the volatile memory device. The non - volatile memory device does not need to be continuously powered to retain the data already stored in the non - volatile memory device, but the disadvantage is that the data processing speed of the non - volatile memory device is low.

[0005] The non - volatile memory device performs a programming operation to store data therein and performs an erase operation to erase the data stored therein. In addition, the non - volatile memory device performs an operation of verifying whether the data is normally programmed or erased and a read operation for outputting the programmed data after the start of the programming operation or the erase operation.

[0006] Therefore, in order to improve the data processing speed of the non - volatile memory device, in addition to research for reducing the time taken for the programming or erase operation, research for reducing the time taken for the verification operation or the read operation is also continuously carried out. Summary of the invention

[0007] In an embodiment of the present disclosure, a semiconductor device may include: at least one memory string connected between a bit line and a source line and including a plurality of memory cells connected to a plurality of word lines; and a page buffer connected to the bit line and configured to sense data stored in the plurality of memory cells. In a state where an unselected word line among the plurality of word lines is provided with a pass voltage, multi - bit data stored in a selected memory cell among the plurality of memory cells may be continuously output by sequentially providing read voltages having different levels to a selected word line among the plurality of word lines.

[0008] In an embodiment of the present disclosure, an operation method of a semiconductor device may include: receiving a read command that instructs to continuously output multi-bit data stored in memory cells of a memory string coupled to a plurality of word lines; providing a pass voltage to unselected word lines among the plurality of word lines until an operation corresponding to the read command is completed; and sequentially providing read voltages having different levels to a selected word line among the plurality of word lines to sequentially determine the multi-bit data.

[0009] In an embodiment of the present disclosure, an operation method of a semiconductor device may include: receiving a read command; checking that the read command is received before a checkpoint; outputting data sensed in a previous read command in response to checking the reception of the read command; and sensing data by sequentially providing read voltages having different levels to a selected word line in response to checking the reception of the read command. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a diagram showing a configuration of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 2 is a diagram showing a configuration of a memory block according to an embodiment of the present disclosure.

[0012] Figure 3 is a diagram showing a configuration of a page buffer according to an embodiment of the present disclosure.

[0013] Figures 4 to 9 is a diagram for describing an operation of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 10 is a diagram showing a configuration of a semiconductor device according to another embodiment of the present disclosure.

[0015] Figure 11 is a diagram for describing an operation of a semiconductor device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] Hereinafter, embodiments according to the technical spirit of the present disclosure will be described with reference to the drawings.

[0017] Embodiments of the present disclosure may provide a semiconductor device and an operation method of the semiconductor device for reducing time taken for a read operation.

[0018] By reducing time taken for reading memory cells storing multiple bits, a data processing speed of the semiconductor device can be increased.

[0019] Figure 1 is a diagram showing a configuration of a semiconductor device 100 according to an embodiment of the present disclosure.

[0020] Reference Figure 1 , the semiconductor device 100 may include a control circuit 110, a page buffer group 120, a voltage generation circuit 130, a line drive circuit 140, and a memory cell array 150.

[0021] The control circuit 110 may program data into the memory cell array 150 by controlling the page buffer group 120, the voltage generation circuit 130, and the line drive circuit 140, or may erase the data that has been programmed into the memory cell array 150. In addition, the control circuit 110 may sense the data stored in the memory cell array 150 or output the sensed data by controlling the page buffer group 120, the voltage generation circuit 130, and the line drive circuit 140.

[0022] For example, the control circuit 110 may generate a page buffer control signal PB_ctrl based on a command signal CMD and an address signal ADD received from the outside (e.g., a host), and may provide the page buffer control signal PB_ctrl to the page buffer group 120.

[0023] The control circuit 110 may generate a voltage control signal V_ctrl based on the command signal CMD, and may provide the voltage control signal V_ctrl to the voltage generation circuit 130.

[0024] The control circuit 110 may generate a drive address signal ADD_d based on the command signal CMD and the address signal ADD, and may provide the drive address signal ADD_d to the line drive circuit 140.

[0025] The page buffer group 120 may include a plurality of page buffers PB1, PB2, ……, PBm. The plurality of page buffers PB1, PB2, ……, PBm may be respectively connected to a plurality of bit lines BL1, BL2, ……, BLm, where m is a natural number. The plurality of page buffers PB1, PB2, ……, PBm may respectively sense the data values stored in the memory cells through the bit lines, and may output the sensed values as data DATA.

[0026] The voltage generation circuit 130 may generate an internal voltage V_int having various voltage levels based on the voltage control signal V_ctrl, and may provide the internal voltage V_int to the line drive circuit 140. For example, the voltage generation circuit 130 may generate an internal voltage V_int having various voltage levels based on the voltage control signal V_ctrl, such as a programming voltage, a read voltage, and a pass voltage, and may provide the generated internal voltage V_int to the line drive circuit 140.

[0027] The line driving circuit 140 may drive the drain selection line DSL, the word line WL, and the source selection line SSL to the voltage level of the internal voltage V_int based on the driving address signal ADD_d. For example, the line driving circuit 140 may drive at least one of the drain selection line DSL, the word line WL, and the source selection line SSL to the voltage level of the internal voltage V_int based on the driving address signal ADD_d. More particularly, for example, the line driving circuit 140 may drive at least one drain selection line DSL and at least one source selection line SSL to the voltage level of the pass voltage after the start of the read operation. In addition, the line driving circuit 140 may drive at least one word line WL to the voltage level of the read voltage and the remaining word lines to the voltage level of the pass voltage after the start of the read operation.

[0028] The memory cell array 150 may include a plurality of memory blocks BK1, BK2, ……, BKn, where n is a natural number. Each of the plurality of memory blocks BK1, BK2, ……, BKn may be selected by the word line WL. The memory strings of the selected memory block may be connected to the plurality of page buffers PB1, PB2, ……, PBm through the bit lines BL1, BL2, ……, BLm. In addition, each of the plurality of memory blocks BK1, BK2, ……, BKn may include a plurality of memory strings, and a plurality of memory cells are connected in series in each memory string. In addition to the plurality of memory cells connected in series, each of the plurality of memory strings may include a first selection transistor (e.g., a drain selection transistor), a second selection transistor (e.g., a source selection transistor), and a dummy cell. The first selection transistor may be configured to be turned on or off through the drain selection line DSL. The second selection transistor may be configured to be turned on or off through the source selection line SSL.

[0029] Figure 2 is a diagram showing the configuration of a memory block according to an embodiment of the present disclosure.

[0030] Figure 2 may show Figure 1 the memory block BK1 among the plurality of memory blocks BK1, BK2, ……, BKn included in the memory cell array 150 of

[0031] Refer to Figure 2, the memory block BK1 may include a plurality of memory strings St_1 to St_m, and the plurality of memory strings St_1 to St_m are respectively connected between a plurality of bit lines BL1 to BLm and a source line SL. Each of the plurality of memory strings St_1 to St_m may include at least one drain select transistor DST, a plurality of memory cells MC1 to MCn, and at least one source select transistor SST. For example, the first memory string St_1 may include a drain select transistor DST, a plurality of memory cells MC1 to MCn, and a source select transistor SST connected in series between the first bit line BL1 and the source line SL. The drain select transistor DST may be configured to be turned on or off through a drain select line DSL. The source select transistor SST may be configured to be turned on or off through a source select line SSL. In addition, the plurality of memory cells MC1 to MCn may be configured to be controlled by a plurality of word lines WL1 to WLn respectively.

[0032] Figure 3 is a diagram showing the configuration of a page buffer according to an embodiment of the present disclosure.

[0033] Figure 3 may show Figure 1 the structure of one page buffer PB among the plurality of page buffers PB1 to PBm included in the page buffer group 120.

[0034] Referring to Figure 3 , the page buffer PB may include a plurality of latches Latch1 to Latch5. In addition, the page buffer PB may further include at least one switch SW. The plurality of latches Latch1 to Latch5 may be configured to be commonly connected to a common node Node_so. The switch SW may be configured to connect or disconnect the bit line BL and the common node Node_so based on a page buffer control signal PB_ctrl.

[0035] When the bit line BL and the common node Node_so are connected, the page buffer PB may sense the current or voltage of the bit line BL by using one of the plurality of latches Latch1 to Latch5 and store the sensed value. The plurality of latches Latch1 to Latch5 may store the value sensed from the bit line BL after the start of a read operation, and may move the stored value to another latch based on the page buffer control signal PB_ctrl.

[0036] Figures 4 to 9 is a diagram for describing the operation of a semiconductor device according to an embodiment of the present disclosure.

[0037] Figure 4is a diagram for describing the programming state of a memory cell and the read operation of the memory cell, where multiple bits of data are stored in each memory cell. In this case, in order to describe the programming state of a memory cell storing multiple bits of data, Figure 4 an example of a memory cell capable of storing 3 bits of data can be shown.

[0038] Referring to Figure 4 , the memory cell can store 3 bits of data. For example, the memory cell can store the most significant bit (MSB), the central significant bit (CSB), and the least significant bit (LSB). According to the data values of each of the MSB, CSB, and LSB, the state of the memory cell can transition to an erased state E, a first programming state P1, a second programming state P2, a third programming state P3, a fourth programming state P4, a fifth programming state P5, a sixth programming state P6, and a seventh programming state P7. The erased state E can correspond to the case where the MSB, CSB, and LSB all have a digital logic value of 1. The first programming state P1 can correspond to the case where the MSB has a digital logic value of 0 and the CSB and LSB have digital logic values of 1. The second programming state P2 can correspond to the case where the MSB and CSB have digital logic values of 0 and the LSB has a digital logic value of 1. The third programming state P3 can correspond to the case where the MSB, CSB, and LSB all have digital logic values of 0. The fourth programming state P4 can correspond to the case where the MSB and LSB have digital logic values of 0 and the CSB has a digital logic value of 1. The fifth programming state P5 can correspond to the case where the MSB and CSB have digital logic values of 1 and the LSB has a digital logic value of 0. The sixth programming state P6 can correspond to the case where the MSB has a digital logic value of 1 and the CSB and LSB have digital logic values of 0. The seventh programming state P7 can correspond to the case where the MSB and LSB have digital logic values of 1 and the CSB has a digital logic value of 0.

[0039] In addition, in the distribution of the threshold voltage Vth of a memory cell having an erased state E and first to seventh programming states P1, P2, P3, P4, P5, P6, and P7, the erased state E can correspond to the distribution of the threshold voltage having the lowest level. In addition, the distribution of the threshold voltage Vth of a memory cell having first to seventh programming states P1, P2, P3, P4, P5, P6, and P7 can have sequentially increasing values. That is, the distribution of the threshold voltage of a memory cell having the first programming state P1 among the first to seventh programming states P1, P2, P3, P4, P5, P6, and P7 can be the lowest. The distribution of the threshold voltage of a memory cell having the seventh programming state P7 among the first to seventh programming states P1, P2, P3, P4, P5, P6, and P7 can be the highest.

[0040] The first read voltage VR1 can be a voltage for determining the erased state E and the first programmed state P1, and can be a voltage having a level corresponding to a level between a maximum value of a distribution of threshold voltages corresponding to the erased state E and a minimum value of a distribution of threshold voltages corresponding to the first programmed state P1.

[0041] The second read voltage VR2 can be a voltage for determining the first programmed state P1 and the second programmed state P2, and can be a voltage having a level corresponding to a level between a maximum value of a distribution of threshold voltages corresponding to the first programmed state P1 and a minimum value of a distribution of threshold voltages corresponding to the second programmed state P2.

[0042] The third read voltage VR3 can be a voltage for determining the second programmed state P2 and the third programmed state P3, and can be a voltage having a level corresponding to a level between a maximum value of a distribution of threshold voltages corresponding to the second programmed state P2 and a minimum value of a distribution of threshold voltages corresponding to the third programmed state P3.

[0043] The fourth read voltage VR4 can be a voltage for determining the third programmed state P3 and the fourth programmed state P4, and can be a voltage having a level corresponding to a level between a maximum value of a distribution of threshold voltages corresponding to the third programmed state P3 and a minimum value of a distribution of threshold voltages corresponding to the fourth programmed state P4.

[0044] The fifth read voltage VR5 can be a voltage for determining the fourth programmed state P4 and the fifth programmed state P5, and can be a voltage having a level corresponding to a level between a maximum value of a distribution of threshold voltages corresponding to the fourth programmed state P4 and a minimum value of a distribution of threshold voltages corresponding to the fifth programmed state P5.

[0045] The sixth read voltage VR6 can be a voltage for determining the fifth programmed state P5 and the sixth programmed state P6, and can be a voltage having a level corresponding to a level between a maximum value of a distribution of threshold voltages corresponding to the fifth programmed state P5 and a minimum value of a distribution of threshold voltages corresponding to the sixth programmed state P6.

[0046] The seventh read voltage VR7 can be a voltage for determining the sixth programmed state P6 and the seventh programmed state P7, and can be a voltage having a level corresponding to a level between a maximum value of a distribution of threshold voltages corresponding to the sixth programmed state P6 and a minimum value of a distribution of threshold voltages corresponding to the seventh programmed state P7.

[0047] Therefore, the voltage with the lowest level among the first to seventh read voltages VR1, VR2, VR3, VR4, VR5, VR6, and VR7 can be the first read voltage VR1. The voltage with the highest level among the first to seventh read voltages VR1, VR2, VR3, VR4, VR5, VR6, and VR7 can be the seventh read voltage VR7. In addition, the first to seventh read voltages VR1, VR2, VR3, VR4, VR5, VR6, and VR7 can be voltages with gradually increasing levels respectively.

[0048] Figure 5 is a diagram for describing an operation of reading data stored in a memory cell storing 3-bit data. This case can be a case where the semiconductor device receives a read command instructing to continuously output data of the LSB, CSB, and MSB stored in the memory cell. In Figure 5 as an example, the first memory string St_1 of Figure 2 is selected.

[0049] Referring to Figure 2 , a voltage higher than the ground voltage can be provided to the first bit line BL1 among the plurality of bit lines BL1 to BLm. The ground voltage can be provided to the remaining bit lines BL2 to BLm. In addition, the drain select transistor DST and the source select transistor SST of the first memory string St_1 can be turned on through the drain select line DSL and the source select line SSL. At least one of the plurality of word lines WL1 to WLn can be selected. A read voltage can be provided to the selected word line, and a pass voltage can be provided to the unselected word line. In this case, as shown in Figure 4 and Figure 5 , the read voltage can include the first to seventh read voltages VR1, VR2, VR3, VR4, VR5, VR6, and VR7.

[0050] Referring to Figure 3 , the bit line BL, that is, the first bit line BL1, and the page buffer PB (PB1 in Figure 1 ) can be electrically connected through the switch SW. That is, the first bit line BL1 and the common node Node_so can be electrically connected.

[0051] Referring to Figure 3 and Figure 5 , the first latch Latch1 can sense the data value stored in the memory cell belonging to the first memory string St_1 and connected to the selected word line s_WL based on the voltage or current of the first bit line BL1. In this case, the first latch Latch1 can act as the latch QS for sensing.

[0052] The second to fourth latches, Latch2, Latch3, and Latch4, can store the data sensed from the first latch, Latch1 (i.e., the latch QS for sensing). In this case, the second to fourth latches, Latch2, Latch3, and Latch4, can respectively act as the roles of the latches QM, Q1, and Q2 for storage.

[0053] The fifth latch, Latch5, can act as the cache latch Qc, which receives the data stored in the latches QM, Q1, and Q2 for storage and outputs the received data to the outside of the page buffer PB.

[0054] The following will refer to Figure 5 More specifically, the operation of continuously sensing and outputting the LSB, CSB, and MSB data stored in the memory cells will be described.

[0055] A pass voltage can be provided to the unselected word line uns_WL.

[0056] The seventh read voltage VR7 and the third read voltage VR3 can be sequentially provided to the selected word line s_WL to determine the LSB. In this case, when the seventh read voltage VR7 and the third read voltage VR3 are sequentially provided to the selected word line s_WL, the sensing latch QS can sense the LSB of the memory cell connected to the selected word line s_WL through the bit line BL1. Thereafter, the LSB sensed by the sensing latch QS can be stored in the storage latch QM.

[0057] When the pass voltage is provided to the unselected word line uns_WL, the LSB can be stored in the storage latch QM, and the sixth read voltage VR6, the fourth read voltage VR4, and the second read voltage VR2 can be sequentially provided to the selected word line s_WL. At this time, the sensing latch QS can sense the CSB of the memory cell that has been connected to the selected word line s_WL through the bit line BL1. Thereafter, the CSB sensed by the sensing latch QS can be stored in the storage latch Q1.

[0058] When the pass voltage is provided to the unselected word line uns_WL, the CSB can be stored in the storage latch Q1, and the fifth read voltage VR5 and the first read voltage VR1 can be sequentially provided to the selected word line s_WL. At this time, the sensing latch QS can sense the MSB of the memory cell that has been connected to the selected word line s_WL through the bit line BL1. Thereafter, the MSB sensed by the sensing latch QS can be stored in the storage latch Q2.

[0059] As described above, when a read command for sequentially outputting multi-bit data stored in a multi-bit memory cell is received, a semiconductor device according to an embodiment of the present disclosure may sequentially provide read voltages having different levels to a selected word line while providing a pass voltage to an unselected word line, may sense multi-bit data of the memory cell, and may store the multi-bit data in a page buffer. Thereafter, the semiconductor device may output the multi-bit data stored in the page buffer to the outside of the page buffer.

[0060] Figure 6 is a diagram for describing an operation of reading data of a memory cell storing 3-bit data. This case may be a case where the semiconductor device sequentially receives read commands for outputting data of the LSB, CSB, and MSB stored in the memory cell.

[0061] The first read command CMD1 may be a command including a command indicating reading the LSB of the currently selected memory cell and a command indicating outputting the sensed MSB of the previous memory cell. The second read command CMD2 may be a command including a command indicating reading the CSB of the currently selected memory cell and a command indicating outputting the sensed LSB of the previous memory cell. The third read command CMD3 may be a command including a command indicating reading the MSB of the currently selected memory cell and a command indicating outputting the sensed CSB of the previous memory cell. Subsequently, a command including a command indicating reading the LSB of the next selected memory cell and a command indicating outputting the sensed MSB of the previous memory cell may be received through the fourth read command CMD4.

[0062] When the first read command CMD1 is received, the seventh read voltage VR7 and the third read voltage VR3 may be sequentially provided to the currently selected word line s_WL. At this time, a pass voltage may be provided to the unselected word line uns_WL. In addition, the sensed MSB of the previous memory cell may be output from the cache latch Qc. The LSB of the currently selected memory cell may be sensed by the latch QS for sensing and may be stored in the latch QM for storage.

[0063] The second read command CMD2 can be received before the first checkpoint. When the second read command CMD2 is received before the first checkpoint, a pass voltage can be continuously supplied to the unselected word line uns_WL. The sixth read voltage VR6, the fourth read voltage VR4, and the second read voltage VR2 can be sequentially supplied to the selected word line s_WL to determine the CSB of the currently selected memory cell. At this time, after the first checkpoint, the LSB stored in the latch QM for storage can be moved to the cache latch Qc and output to the outside of the page buffer PB. In addition, the CSB of the currently selected memory cell can be sensed by the latch QS for sensing and stored in the latch Q1 for storage.

[0064] The third read command CMD3 can be received before the second checkpoint. When the third read command CMD3 is received before the second checkpoint, a pass voltage can be continuously supplied to the unselected word line uns_WL. The fifth read voltage VR5 and the first read voltage VR1 can be sequentially supplied to the selected word line s_WL to determine the MSB of the currently selected memory cell. At this time, after the second checkpoint, the CSB stored in the latch Q1 for storage can be moved to the cache latch Qc and output to the outside of the page buffer PB. In addition, the MSB of the currently selected memory cell can be sensed by the latch QS for sensing and stored in the latch Q2 for storage.

[0065] The fourth read command CMD4 can be received before the third checkpoint. When the fourth read command CMD4 is received before the third checkpoint, the voltage levels of the currently selected word line s_WL and the unselected word line uns_WL can be precharged to a specific voltage level. In addition, at least one of the first read voltage VR1 to the seventh read voltage VR7 can be sequentially supplied to the next selected word line, and a pass voltage can be supplied to the unselected word line. In addition, the MSB of the currently selected memory cell stored in the latch Q2 for storage can be moved to the cache latch Qc and output to the outside of the page buffer PB.

[0066] As described above, in the read operation of the semiconductor device according to an embodiment of the present disclosure, when sequentially outputting a plurality of bits stored in one memory cell by the read commands received before each checkpoint, a pass voltage can be continuously supplied to the unselected word line without precharging the word line, and read voltages for determining each of the plurality of bits can be sequentially supplied to the selected word line. In addition, the latch for sensing can sense data by the read command received before the checkpoint, and the sensed data can be stored in the latch for storage and output. Therefore, a plurality of bits of data stored in the memory cell can be sequentially read.

[0067] Figure 7 is a diagram for describing an operation of reading data of a memory cell storing multi-bit data as shown in Figure 6 . In this case, Figure 6 is a diagram for describing a read operation using a latch QS for sensing, latches QM, Q1, and Q2 for storage, and a cache latch Qc. In contrast, Figure 7 is a diagram for describing a read operation using a latch QS for sensing and a cache latch Qc.

[0068] Referring to Figure 7 , when a first read command CMD1 is received, a seventh read voltage VR7 and a third read voltage VR3 can be sequentially provided to a currently selected word line s_WL. At this time, a pass voltage can be provided to an unselected word line uns_WL. In addition, a sensed MSB of a previous memory cell can be output from the cache latch Qc. An LSB of the currently selected memory cell can be sensed by the latch QS for sensing and stored in the cache latch Qc.

[0069] A second read command CMD2 can be received before a first checkpoint. When the second read command CMD2 is received before the first checkpoint, a pass voltage can be continuously provided to the unselected word line uns_WL. A sixth read voltage VR6, a fourth read voltage VR4, and a second read voltage VR2 can be sequentially provided to the selected word line s_WL to determine a CSB of the currently selected memory cell. At this time, after the first checkpoint, the LSB stored in the cache latch Qc can be output to the outside of a page buffer PB. In addition, the CSB of the currently selected memory cell can be sensed by the latch QS for sensing and stored in the cache latch Qc.

[0070] A third read command CMD3 can be received before a second checkpoint. When the third read command CMD3 is received before the second checkpoint, a pass voltage can be continuously provided to the unselected word line uns_WL. A fifth read voltage VR5 and a first read voltage VR1 can be sequentially provided to the selected word line s_WL to determine an MSB of the currently selected memory cell. At this time, after the second checkpoint, the CSB stored in the cache latch Qc can be output to the outside of the page buffer PB. In addition, the MSB of the currently selected memory cell can be sensed by the latch QS for sensing and stored in the cache latch Qc.

[0071] The fourth read command CMD4 can be received before the third checkpoint. When the fourth read command CMD4 is received before the third checkpoint, the voltage levels of the currently selected word line s_WL and the unselected word lines uns_WL can be precharged to a specific voltage level. In addition, at least one of the first read voltage VR1 to the seventh read voltage VR7 can be sequentially provided to the next selected word line, and a pass voltage can be provided to the unselected word lines. In addition, the MSB of the memory cell stored in the cache latch Qc can be output to the outside of the page buffer PB.

[0072] As described above, in the read operation of the semiconductor device according to an embodiment of the present disclosure, when sequentially outputting a plurality of bits stored in one memory cell by read commands received before each checkpoint, a pass voltage can be continuously provided to the unselected word lines without precharging the word lines, and read voltages for determining each of the plurality of bits can be sequentially provided to the selected word line. In addition, the latch for sensing can sense data by a read command received before the checkpoint, and the sensed data can be stored in the cache latch and output. Therefore, a plurality of bits of data stored in the memory cell can be sequentially read.

[0073] Figure 8 and Figure 9 are diagrams for describing an operation of reading data of a memory cell storing 3-bit data. In this case, the following situation is described: The semiconductor device continuously receives read commands instructing to output the LSB, CSB, and MSB of the data stored in the memory cell, but at least one of the continuously received read commands is received after the checkpoint. Except for the timing of receiving the third read command CMD3, Figure 8 and Figure 9 The description of the read operation in can be the same as the description of the read operation in Figure 6 and Figure 7 . Therefore, in Figure 8 and Figure 9 's description, the timing of receiving the third read command CMD3 is described, and the description of other operations can be replaced with the description of the operations in Figure 6 and Figure 7 .

[0074] For example, as in Figure 8As shown, the third read command CMD3 can be received after the second checkpoint. This can be the case where the third read command CMD3 is received within a set time after the second checkpoint. In this case, each of the unselected word line uns_WL and the selected word line s_WL can maintain the voltage level until the third read command CMD3 is received. In addition, after the third read command CMD3 is received, the fifth read voltage VR5 and the first read voltage VR1 can be sequentially provided to the selected word line s_WL. The CSB sensed by the second read command CMD2 can be moved from the latch Q1 for storage to the cache latch Qc, and can be output to the outside of the page buffer PB.

[0075] As Figure 9 shown, the third read command CMD3 can be received after a time greater than the set time after the second checkpoint. In this case, when the set time after the second checkpoint has passed, all the unselected word lines uns_WL and the selected word line s_WL can be precharged until the third read command CMD3 is received. Thereafter, when the third read command CMD3 is received, a pass voltage can be provided to the unselected word line uns_WL, and the fifth read voltage VR5 and the first read voltage VR1 can be sequentially provided to the selected word line s_WL. In addition, the CSB sensed by the second read command CMD2 can be moved from the latch Q1 for storage to the cache latch Qc, and can be output to the outside of the page buffer PB.

[0076] As described above, if consecutive read commands are received for a memory cell storing multiple bits, when the time between the pieces of timing of the consecutive read commands is greater than the set time, the semiconductor device according to an embodiment of the present disclosure can reduce the power consumption of the semiconductor device by precharging the word lines until the next read command is received.

[0077] Figure 10 is a diagram showing the configuration of a semiconductor device according to another embodiment of the present disclosure.

[0078] Figure 10 It can be a diagram for describing a multi-string structure in which multiple memory strings String0, String1, String2, and String3 are connected to one bit line.

[0079] Referring to Figure 10, multiple memory strings String0, String1, String2, and String3 can be connected between a bit line BL and a source line SL. In this case, the multiple memory strings String0, String1, String2, and String3 can include a first memory string String0, a second memory string String1, a third memory string String2, and a fourth memory string String3.

[0080] For example, the first memory string String0 can include a drain select transistor, multiple memory cells, and a source select transistor connected in series between the bit line BL and the source line SL. In this case, the drain select transistor of the first memory string String0 can be connected to a first drain select line DSL<0>, and the source select transistor of the first memory string String0 can be connected to a first source select line SSL<0>. In addition, the multiple memory cells can be connected to multiple word lines including a select word line Sel.WL and an unselected word line Unsel.WL.

[0081] The second memory string String1 can include a drain select transistor, multiple memory cells, and a source select transistor connected in series between the bit line BL and the source line SL. In this case, the drain select transistor of the second memory string String1 can be connected to a second drain select line DSL<1>. The source select transistor of the second memory string String1 can be connected to the first source select line SSL<0>. In addition, the multiple memory cells can be connected to multiple word lines including a select word line Sel.WL and an unselected word line Unsel.WL.

[0082] The third memory string String2 can include a drain select transistor, multiple memory cells, and a source select transistor connected in series between the bit line BL and the source line SL. In this case, the drain select transistor of the third memory string String2 can be connected to a third drain select line DSL<2>. The source select transistor of the third memory string String2 can be connected to a second source select line SSL<1>. In addition, the multiple memory cells can be connected to multiple word lines including a select word line Sel.WL and an unselected word line Unsel.WL.

[0083] The fourth memory string String3 may include a drain select transistor, a plurality of memory cells, and a source select transistor connected in series between a bit line BL and a source line SL. In this case, the drain select transistor of the fourth memory string String3 may be connected to a fourth drain select line DSL<3>. The source select transistor of the fourth memory string String3 may be connected to a second source select line SSL<1>. In addition, the plurality of memory cells may be connected to a plurality of word lines including a select word line Sel.WL and an unselected word line Unsel.WL.

[0084] The semiconductor device configured as described above according to another embodiment of the present disclosure may select the first memory string String0 by enabling the first drain select line DSL<0> and the first source select line SSL<0>, and may select the second memory string String1 by enabling the second drain select line DSL<1> and the first source select line SSL<0>. In addition, the semiconductor device may select the third memory string String2 by enabling the third drain select line DSL<2> and the second source select line SSL<1>, and may select the fourth memory string Stirng3 by enabling the fourth drain select line DSL<3> and the second source select line SSL<1>.

[0085] Figure 11 is a diagram for describing the operation of a semiconductor device according to another embodiment of the present disclosure.

[0086] Refer to Figure 10 and Figure 11 , the semiconductor device according to another embodiment of the present disclosure may perform a consecutive read operation on a plurality of memory strings (e.g., the first to fourth memory strings String0, String1, String2, String3) connected between one bit line BL and a source line SL.

[0087] With the voltage level of the unselected word line uns_WL among multiple word lines driven to the pass voltage state, in order to select the first memory string String0, the first drain select line DSL<0> and the first source select line SSL<0> can be enabled. In addition, in order to continuously read 3-bit data of the memory cells controlled by the selected word line s_WL among the memory cells included in the first memory string String0, the seventh read voltage VR7, the third read voltage VR3, the sixth read voltage VR6, the fourth read voltage VR4, the second read voltage VR2, the fifth read voltage VR5, and the first read voltage VR1 can be sequentially provided to the selected word line s_WL. In this case, the seventh read voltage VR7 and the third read voltage VR3 can be voltages provided to determine the MSB of the memory cell respectively. The sixth read voltage VR6, the fourth read voltage VR4, and the second read voltage VR2 can be voltages provided to determine the CSB of the memory cell respectively. The fifth read voltage V5 and the first read voltage VR1 can be voltages provided to determine the LSB of the memory cell respectively.

[0088] After completing the continuous read operation of multiple bits (e.g., 3 bits) stored in the memory cells of the first memory string String0, the second memory string String1 can be selected. At this time, the voltage level of the unselected word line uns_WL driven to the pass voltage can be maintained. In order to select the second memory string String1, the second drain select line DSL<1> can be enabled while the first drain select line DSL<0> is disabled and the first source select line SSL<0> is enabled. In addition, in order to continuously read 3-bit data of the memory cells controlled by the selected word line s_WL among the memory cells included in the second memory string String1, the seventh read voltage VR7, the third read voltage VR3, the sixth read voltage VR6, the fourth read voltage VR4, the second read voltage VR2, the fifth read voltage VR5, and the first read voltage VR1 can be sequentially provided to the selected word line s_WL.

[0089] After completing a consecutive read operation on a plurality of bits (e.g., 3 bits) stored in the memory cells of the second storage string String1, the third storage string String2 can be selected. At this time, the voltage level of the unselected word line uns_WL driven to the pass voltage can be maintained. To select the third storage string String2, the second drain select line DSL<1> and the first source select line SSL<0> can be disabled, and the second source select line SSL<1> and the third drain select line DSL<2> can be enabled. In addition, to consecutively read 3-bit data of the memory cells controlled by the select word line s_WL among the memory cells included in the third storage string String2, the seventh read voltage VR7, the third read voltage VR3, the sixth read voltage VR6, the fourth read voltage VR4, the second read voltage VR2, the fifth read voltage VR5, and the first read voltage VR1 can be sequentially provided to the select word line s_WL.

[0090] After completing a consecutive read operation on a plurality of bits (e.g., 3 bits) stored in the memory cells of the third storage string String2, the fourth storage string String3 can be selected. At this time, the voltage level of the unselected word line uns_WL driven to the pass voltage can be maintained. To select the fourth storage string String3, the fourth drain select line DSL<3> can be enabled in a state where the third drain select line DSL<2> is disabled and the second source select line SSL<1> is enabled. In addition, to consecutively read 3-bit data of the memory cells controlled by the select word line s_WL among the memory cells included in the fourth storage string String3, the seventh read voltage VR7, the third read voltage VR3, the sixth read voltage VR6, the fourth read voltage VR4, the second read voltage VR2, the fifth read voltage VR5, and the first read voltage VR1 can be sequentially provided to the select word line s_WL.

[0091] As described above, after the start of the read operation, the semiconductor device according to an embodiment of the present disclosure can continuously output multi-bit data stored in the memory cells by sequentially providing a plurality of read voltages for determining a plurality of bits to the select word line in a state where the pass voltage is provided to the unselected word line. In addition, even in the case of a structure including a plurality of storage strings connected between one bit line and a source line, the semiconductor device can select each storage string in a state where the unselected word line is provided with the pass voltage and sequentially provide a plurality of read voltages for determining a plurality of bits to the select word line whenever the storage string is selected. Therefore, the semiconductor device can continuously output multi-bit data stored in the memory cells for each storage string.

[0092] Although embodiments in accordance with the technical spirit of the present disclosure have been described above with reference to the accompanying drawings, the embodiments are provided only to describe the embodiments in accordance with the concept of the present disclosure, and the present disclosure is not limited to these embodiments. Those of ordinary skill in the art to which the present disclosure pertains may replace, modify, and change the embodiments in various ways without departing from the technical spirit of the present disclosure written in the claims. It can be said that these replacements, modifications, and changes fall within the scope of the present disclosure. In addition, the embodiments may be combined to form additional embodiments.

Claims

1. A semiconductor device comprising: at least one memory string connected between the bit line and the source line and including a plurality of memory cells connected to a plurality of word lines; as well as a page buffer connected to the bit lines and sensing data stored in the plurality of memory cells, In which, when unselected word lines among the multiple word lines are provided with pass voltages, multi-bit data stored in selected memory cells among the multiple memory cells are continuously output by sequentially providing read voltages with different levels to selected word lines among the multiple word lines.

2. The semiconductor device according to claim 1, wherein The multi-bit data includes a most significant bit (MSB), a center significant bit (CSB), and a least significant bit (LSB).

3. The semiconductor device according to claim 2, wherein: The read voltages include first to seventh read voltages having different levels; Each of the seventh read voltage and the third read voltage is used to determine the LSB; Each of the sixth read voltage, the fourth read voltage, and the second read voltage is used to determine the CSB; and Each of the fifth read voltage and the first read voltage is used to determine the MSB.

4. The semiconductor device according to claim 3, wherein: In order to sequentially determine the LSB, CSB and MSB stored in the selected memory cell, in a state where the unselected word line is provided with the pass voltage, the seventh read voltage, the third read voltage, the sixth read voltage, the fourth read voltage, the second read voltage, the fifth read voltage and the first read voltage are sequentially provided to the selected word line.

5. The semiconductor device according to claim 4, wherein: determining the LSB through the bit line after the seventh read voltage and the third read voltage are provided to the selection word line; determining the CSB through the bit line after the sixth read voltage, the fourth read voltage, and the second read voltage are provided to the selection word line; and After the fifth read voltage and the first read voltage are supplied to the selection word line, the MSB is determined by the bit line.

6. The semiconductor device according to claim 5, wherein: The page buffer includes a cache latch, a latch for storing, and a latch for sensing; When the seventh read voltage and the third read voltage are supplied to the selection word line, the latch for sensing senses the LSB; When the sixth read voltage, the fourth read voltage, and the second read voltage are supplied to the selection word line, the latch for sensing senses the CSB; and When the fifth read voltage and the first read voltage are supplied to the selection word line, the latch for sensing senses the MSB.

7. The semiconductor device according to claim 3, wherein: The at least one memory string includes a first memory string and a second memory string sharing the plurality of word lines and the source line; and In a state where the unselected word line is provided with the pass voltage, the LSB, CSB and MSB stored in the selected memory cell of the first memory string are determined in sequence, and the LSB, CSB and MSB stored in the selected memory cell of the second memory string are determined.

8. The semiconductor device according to claim 7, wherein: When the LSB, CSB and MSB stored in the selected memory cell of the first memory string are determined in sequence, the seventh read voltage, the third read voltage, the sixth read voltage, the fourth read voltage, the second read voltage, the fifth read voltage and the first read voltage are sequentially provided to the selected word line; and When the LSB, CSB and MSB stored in the selected memory cell of the second storage string are determined, the seventh read voltage, the third read voltage, the sixth read voltage, the fourth read voltage, the second read voltage, the fifth read voltage and the first read voltage are sequentially provided to the selected word line.

9. A method for operating a semiconductor device, comprising: receiving a read command instructing to continuously output a plurality of bits of data stored in memory cells of a memory string coupled to a plurality of word lines; providing a pass voltage to unselected word lines among the plurality of word lines until an operation corresponding to the read command is completed; as well as Read voltages having different levels are sequentially supplied to selected word lines among the plurality of word lines to sequentially determine the plurality of bits of data.

10. The operating method according to claim 9, wherein: The multi-bit data includes a least significant bit (LSB), a center significant bit (CSB), and a most significant bit (MSB).

11. The operating method according to claim 10, wherein: The read voltages include first to seventh read voltages having different levels; and Each of the seventh read voltage and the third read voltage is used to determine the LSB, each of the sixth read voltage, the fourth read voltage, and the second read voltage is used to determine the CSB, and each of the fifth read voltage and the first read voltage is used to determine the MSB.

12. The operating method according to claim 11, wherein: Providing the read voltages sequentially to the selection word line includes sequentially providing the seventh read voltage, the third read voltage, the sixth read voltage, the fourth read voltage, the second read voltage, the fifth read voltage, and the first read voltage to the selection word line.

13. The operating method according to claim 12, wherein: Providing the read voltage to the selected word lines in sequence comprises: determining the LSB by sequentially providing the seventh read voltage and the third read voltage to the selection word line; determining the CSB by sequentially supplying the sixth read voltage, the fourth read voltage, and the second read voltage to the selection word line; and The MSB is determined by sequentially supplying the fifth read voltage and the first read voltage to the selection word line.

14. A method for operating a semiconductor device, comprising: Receive a read command; detecting that the read command is received before a checkpoint; outputting data sensed in a previous read command in response to detecting receipt of the read command; as well as In response to checking the reception of the read command, data is sensed by sequentially supplying read voltages having different levels to the selected word lines.

15. The operating method according to claim 14, wherein: The output data includes data stored in a cache latch included in the output page buffer.

16. The operating method according to claim 14, wherein: The sensor data includes: In a state where a non-selected word line is supplied with a pass voltage, supplying a read voltage having a different level to the selected word line; and Data of memory cells connected to the selection word line are sensed by using a latch for sensing included in the page buffer.

17. The operating method according to claim 16, wherein: Sensing the data of the memory cell includes moving the data sensed by the latch for sensing to a latch for storing or a cache latch included in the page buffer.

18. The operating method according to claim 14, wherein: When reception of the read command is checked in a state where a set time has passed after the check point: precharging the unselected word lines and the selected word lines; providing a pass voltage to the unselected word lines; and The read voltage is provided to the selected word line.

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