Suppression of auto-doping during epitaxial growth of epitaxial layers in semiconductor devices

Abstract

A semiconductor device is presented that includes one or more substrate layers, one or more epitaxial layers over the one or more substrate layers, and a buffer layer directly between the one or more substrate layers and the one or more epitaxial layers. The substrate layer may be a highly doped arsenic layer. The epitaxial layer may be low doped. The buffer layer may be a high phosphorus doped silicon layer. The buffer layer may be relatively thin, about 1 [mu] m to 5 [mu] m. The invention further relates to a method for producing such a semiconductor device.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing such a semiconductor device. More specifically, the present disclosure relates to forming a low-doped epitaxial layer on a highly doped substrate layer. Background Art

[0002] In the context of semiconductor technology, epitaxial layers play an important role in forming complex semiconductor devices. For example, adding an epitaxial layer on a substrate can change the properties and characteristics of the material. These layers can be designed to have specific doping levels, thicknesses, and crystal structures to customize the electrical, optical, or mechanical properties of the semiconductor for various applications in electronics, optoelectronics, and photonics.

[0003] An epitaxial layer can be grown or deposited on a substrate using a process called epitaxy. Epitaxy involves depositing a crystalline layer on top of a crystalline substrate, where the deposited atoms align with the atoms of the substrate to form a single-crystalline structure.

[0004] An example of a semiconductor device is a diode device. Modern silicon (Si) diode devices for electric vehicles and consumer devices often require high blocking voltages such as 400V, 650V, and above. To obtain a high breakdown voltage, a high thickness of the epitaxial layer may be required, and at the same time, an ultra-low dopant concentration is needed. For example, a 400V diode may include a 6-inch arsenic (As)-doped silicon substrate and an epitaxial layer with a dopant concentration of 0.08E15 1 / cm 3 and a thickness of 45μm. In another example, a 650V diode may include an 8-inch Si:As substrate and an epitaxial layer having a dopant concentration of 0.15E15 1 / cm 3 and a thickness of 60μm.

[0005] FIG. 1 shows a cross-section of a portion 100 of a semiconductor device including two layers. The semiconductor device typically includes other layers and / or structures not shown in FIG. 1. An example of a semiconductor device is the Si diode device described above. The substrate 101 used may have a high concentration of, for example, As dopant ions to reduce the resistivity as low as possible. An ultra-low doped Si epitaxial layer 103 can be deposited on top of the substrate 101. Due to its high vapor pressure, and during heat treatment and epitaxial growth, ions will diffuse outwards from the substrate 101 and redeposit in the epitaxial layer 103, especially at the wafer edge, which disadvantageously results in an increase in the dopant concentration at this position, accompanied by a decrease in the breakdown voltage and an increase in non-uniformity on the wafer. Summary of the Invention

[0006] The following presents an overview of aspects of specific examples disclosed herein. It should be understood that these aspects are presented only to provide a brief overview of these specific embodiments to the reader, and these aspects are not intended to limit the scope of the present disclosure. Indeed, the present disclosure may cover a number of aspects and / or combinations of aspects that may not be elaborated upon.

[0007] The present disclosure aims to overcome the drawbacks identified in the background section. Advantageously, the solution of the present disclosure is capable of suppressing self-doping, and in particular arsenic (As) self-doping, during the epitaxial growth of a silicon (Si) layer on a blank substrate, particularly an As-doped substrate.

[0008] According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device may include one or more substrate layers. The semiconductor device may further include one or more epitaxial layers located above the one or more substrate layers. The semiconductor device may further include one or more buffer layers directly between the one or more substrate layers and the one or more epitaxial layers.

[0009] In one embodiment, the one or more substrate layers may be highly doped, for example, above 1e15 1 / cm 3 or above 6e18 1 / cm 3 . The one or more epitaxial layers may be lightly doped, for example, below 1e15 1 / cm 3 . The one or more buffer layers may be highly doped.

[0010] In one embodiment, the one or more substrate layers may include an As-doped silicon substrate. The one or more epitaxial layers may include a silicon epitaxial layer. The one or more buffer layers may include a P-doped silicon layer.

[0011] In one embodiment, the one or more buffer layers may have a thickness of about 1 μm to 5 μm.

[0012] In one embodiment, the semiconductor device may be a silicon-based device.

[0013] In one embodiment, the semiconductor device may be a silicon-based power device.

[0014] In one embodiment, the semiconductor device may be one of a diode device, an insulated gate bipolar transistor (IGBT), a bipolar transistor, a metal oxide semiconductor field effect transistor (MOSFET), a rectifier, a Schottky diode.

[0015] According to one aspect of the present disclosure, a method of manufacturing a semiconductor device is provided. The semiconductor device may have one or more of the above-described features. The method may include providing a substrate layer. The method may further include forming a buffer layer on top of the substrate layer. The method may further include forming an epitaxial layer on top of the buffer layer.

[0016] In one embodiment, the substrate layer may be highly doped. The buffer layer may be highly doped. The epitaxial layer may be lightly doped.

[0017] In one embodiment, the substrate layer may include an arsenic-doped silicon substrate. The buffer layer may include a phosphorus-doped silicon layer. The epitaxial layer may include a silicon epitaxial layer.

[0018] In one embodiment, the buffer layer may have a thickness of about 1 μm to 5 μm.

[0019] In one embodiment, the formation of the buffer layer may include growing a highly phosphorus-doped silicon layer on the substrate layer at an epitaxial temperature. The formation of the epitaxial layer may include growing a lightly doped epitaxy.

[0020] In one embodiment, the formation of the buffer layer and the formation of the epitaxial layer may be performed in different reactors.

[0021] In one embodiment, the formation of the buffer layer and the formation of the epitaxial layer may be performed in the same reactor. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Embodiments of the present disclosure will now be described, by way of example only, with reference to the schematic drawings, in which corresponding reference symbols indicate corresponding parts, wherein:

[0023] FIG. 1 shows a cross-section of a part of a prior art semiconductor device;

[0024] Figure 2 shows a cross-section of a part of a semiconductor device according to one aspect of the present disclosure;

[0025] Figure 3 is an abstract representation of a semiconductor device according to one aspect of the present disclosure;

[0026] Figure 4 is a graph comparing the profiles of epitaxial layers with and without a phosphorus-doped silicon buffer; and

[0027] Figure 5 shows a block diagram of an exemplary manufacturing process for forming a buffer layer according to one aspect of the present disclosure.

[0028] The drawings are for illustrative purposes only and do not limit the scope of protection defined by the claims. DETAILED DESCRIPTION

[0029] It will be readily understood that the components of the embodiments generally described herein and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Thus, the following more detailed description of the various embodiments shown in the drawings is not intended to limit the scope of the present disclosure, but is merely representative of the various embodiments. While aspects of the embodiments are presented in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0030] The described embodiments are to be considered in all respects as illustrative and not restrictive. Thus, the scope of the present disclosure is indicated by the appended claims rather than by this detailed description. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope.

[0031] References throughout this specification to features, advantages, or similar language do not imply that all of the features and advantages that can be realized with the present disclosure should be in or should be realized in any single embodiment of the present disclosure. Rather, the language referring to the features and advantages is understood to mean that a particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, discussions of the features and advantages throughout this specification, and similar language, may, but do not necessarily, refer to the same embodiment.

[0032] Furthermore, the described features, advantages, and characteristics of the present disclosure can be combined in any suitable manner in one or more embodiments. As will be recognized by those of skill in the art in light of the present disclosure, the present disclosure can be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the present disclosure. References throughout this specification to "one embodiment," "an embodiment," or similar language mean that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases "one embodiment," "an embodiment," and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

[0033] Figure 2 A cross-section of a portion 200 of a semiconductor device 300 (abstractly shown in Figure 3 is shown) in accordance with one aspect of the present disclosure. The component 200 can include three layers of the semiconductor device 300. The semiconductor device 300 generally includes Figure 2 other layers and / or structures not shown in. Non-limiting examples of such semiconductor devices 300 are Si diode devices for electric vehicles and consumer devices that require a high blocking voltage, such as 400V, 650V, and above.

[0034] Instead of using a non / low doped cap layer directly on the substrate 101 followed by a low doped epitaxy 103 common in the industry, the present disclosure provides a buffer layer 202, which is preferably in the form of a highly doped buffer layer 202 with phosphorus (P) dopant ions between one or more substrates 201 (similar to substrate 101) and one or more epitaxial layers 203 (similar to epitaxial layer 103). Advantageously, the phosphorus doped Si layer 202 can almost completely suppress As autodoping from the As substrate 201.

[0035] Since known cap layers are inherently (ultra-low / no intended doping), they typically unfavorably increase the resistivity. Advantageously, the highly doped buffer layer 202 of the present disclosure does not increase the resistivity significantly.

[0036] When based on high phosphorus doping, the buffer layer 202 is particularly effective. Diffusion of As and P occurs through impurity-vacancy pairs, i.e., As2-V and P-V pairs. For movement, the main factor can be the movement of the vacancy close to the impurity. For phosphorus, the potential energy for vacancy movement is lower compared to the movement close to arsenic. This means that for the phosphorus doped buffer 202, the vacancy will move with / move to the phosphorus impurity, and the diffusion of arsenic atoms is slowed down. In contrast, in the case of an undoped buffer, all Si vacancies are available for arsenic atoms, and the diffusion is less inhibited.

[0037] In an example implementation, the solution of the present disclosure can be used in Si power devices such as the Si diode device described above. In an example implementation, the solution of the present disclosure can be used in silicon-based products using As doped substrates that require a low doped epitaxial layer, such as insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), rectifiers, or Schottky diodes. In particular, high voltage semiconductor devices benefit from the solution of the present disclosure.

[0038] Contrary to an undoped buffer layer, the phosphorus doped buffer layer 202 can be relatively thin, for example having a thickness as low as about 1 μm to 5 μm, for example 2 μm. In Figure 4 Graph 400 shows an example of the doping profiles obtained at the center and at the edge of a wafer, where the profiles of the epitaxial layer with and without the phosphorus buffer layer 202 are compared. Two lines 402 depict the reference process without the buffer layer 202. Two lines 404 depict the process including the buffer layer 202. The x-axis shows the distance from the substrate surface in μm (0 @ N = 1e18 cm -3 ) and includes the markings -20, -15, -10, -5, and 0. The y-axis shows the doping in cm -3 and includes the markings 1×10 14 、2×10 14 、3×1014 and 4×10 14 and 5×10 14 .

[0039] Line 402 shows a large difference between the edge and the center of the wafer. Line 404 shows a minimal to no difference between the edge and the center of the wafer. While the epitaxy without a buffer layer (line 402) shows a doping gradient of about 5 μm to 10 μm at the wafer edge, the doping transition of the epitaxy with buffer layer 202 (line 404) drops to about 1 μm. This in turn results in a narrower profile of the product breakdown voltage, which can be used to keep the wafer yield stable.

[0040] The epitaxial buffer layer 202 can be deposited at the beginning of the epitaxial growth process after completion of the in-situ surface cleaning of the silicon wafer. Figure 5 Four non-limiting block diagrams of exemplary manufacturing processes 500A to 500D for forming the buffer layer 202 are shown. Depending on the actual tool situation, the manufacturing process can be carried out in one or two reaction chambers, or even in two different reactors. All manufacturing variations can lead to the same result, namely a sharp transition from the substrate to the epitaxial doping. A substrate layer 201, such as a highly doped As substrate (not shown), can be formed before each manufacturing process 500A to 500D.

[0041] Exemplary manufacturing process 500A includes wafer lock-in 502, after which the growth of the buffer layer 202 in step 510 is carried out in a first epitaxial reactor. Thus, a highly doped buffer layer 202, such as a highly doped phosphorus-doped Si layer, can be formed on top of the substrate 201 such as a highly arsenic (As)-doped silicon substrate. Wafer lock-out 504 is carried out after step 510. Step 506 includes a wafer surface cleaning process. The next step 502 is wafer lock-in, after which the growth of the epitaxial layer 203 in step 512 is carried out in a second epitaxial reactor. Thus, a low-doped epitaxial layer 203 can be formed on top of the buffer layer 202. Wafer lock-out 504 is carried out after step 512.

[0042] Exemplary manufacturing process 500B is similar to manufacturing process 500A, but skips the wafer surface cleaning step 506.

[0043] Exemplary manufacturing process 500C includes wafer lock-in 502 after the growth of the buffer layer 202 in step 510. Thus, a highly doped buffer layer 202, such as a highly doped phosphorus-doped Si layer, can be formed on top of the substrate 201 such as a highly arsenic (As)-doped silicon substrate. A cleaning process 508 is carried out after step 510. Then, the epitaxial layer 203 is grown in step 512. Steps 510, 508, and 512 of process 500C are carried out in the same epitaxial reactor. Wafer lock-out 504 is carried out after step 512.

[0044] The exemplary manufacturing process 500D is similar to the manufacturing process 500C, but skips the cleaning step 508.

[0045] The process flows of the present disclosure, such as the manufacturing processes 500A to 500D, can suppress the outward diffusion of As during the growth of a high-temperature epitaxial layer on a highly doped wafer. The formation of the epitaxial buffer layer 202 and the epitaxial layer 203 can start from an epitaxy with a highly phosphorus-doped silicon layer 202, grow at an epitaxial temperature, then optionally be cleaned, and continue with a low-doped epitaxy to form the epitaxial layer 203. As Figure 5 shown in the example, the buffer layer epitaxy can be carried out on a different reactor separate from the low-doped growth reactor.

[0046] In the above example, a buffer layer 202 is shown between the substrate layer 201 and the epitaxial layer 203. The buffer layer 202 can include multiple buffer layers, for example, implemented as a multi-buffer layer structure, such as first low-doped and then highly doped.

[0047] By studying the drawings, the present disclosure, and the appended claims, those skilled in the art can understand and implement other variations of the disclosed embodiments when practicing the claimed present disclosure. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used advantageously. Any reference signs in the claims should not be construed as limiting their scope.

Claims

1. A semiconductor device (300), comprising: one or more substrate layers (201); one or more epitaxial layers (203), the one or more epitaxial layers being located above the one or more substrate layers; as well as A buffer layer (202) is directly between the one or more substrate layers and the one or more epitaxial layers.

2. The semiconductor device according to claim 1, wherein the one or more substrate layers are highly doped, wherein the one or more epitaxial layers are low-doped, And wherein the buffer layer is highly doped.

3. The semiconductor device according to claim 1, High doping is higher than 1e15 1 / cm 3 of doping, And the low doping is less than 1e15 1 / cm 3 of doping.

4. A semiconductor device according to any one of the preceding claims, wherein the one or more substrate layers include an arsenic-doped silicon substrate, wherein the one or more epitaxial layers include a silicon epitaxial layer, And wherein the buffer layer comprises a phosphorus-doped silicon layer.

5. A semiconductor device according to any one of the preceding claims, The buffer layer has a thickness of about 1 μm to 5 μm.

6. A semiconductor device according to any one of the preceding claims, wherein the semiconductor device is a silicon based device. 7 . The semiconductor device according to claim 6 , wherein the semiconductor device is a silicon-based power device.

8. The semiconductor device according to claim 6 or claim 7, wherein the semiconductor device is one of the following: Diode devices; Insulated Gate Bipolar Transistor IGBT; Bipolar transistor; Metal Oxide Semiconductor Field Effect Transistor MOSFET; PN rectifier; Schottky diode.

9. A method (500A to 500D) of manufacturing a semiconductor device (300), Providing a substrate layer (201); forming (510) a buffer layer (202) on top of the substrate layer; and An epitaxial layer (203) is formed (512) on top of the buffer layer.

10. The method according to claim 9, wherein the substrate layer is highly doped, wherein the buffer layer is highly doped, And wherein the epitaxial layer is lowly doped.

11. The method according to claim 9 or claim 10, wherein the substrate layer comprises an arsenic-doped silicon substrate, wherein the buffer layer comprises a phosphorus-doped silicon layer, And wherein the epitaxial layer comprises a silicon epitaxial layer.

12. The method according to any one of claims 9 to 11, The buffer layer has a thickness of about 1 μm to 5 μm.

13. The method according to any one of claims 9 to 12, wherein the forming of the buffer layer comprises growing a highly phosphorus-doped silicon layer on the substrate layer at an epitaxial temperature, And wherein said forming of said epitaxial layer comprises growing a low-doped epitaxial layer.

14. The method according to any one of claims 9 to 13, The forming of the buffer layer and the forming of the epitaxial layer are performed in different reactors.

15. The method according to any one of claims 9 to 14, wherein the forming of the buffer layer and the forming of the epitaxial layer are performed in the same reactor.

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