Test structure for flip-chip packaging and preparation method thereof

Abstract

The invention provides a test structure for flip-chip packaging and a preparation method of the test structure. The test structure comprises an interconnection substrate, a flip chip and a data acquisition system, the interconnection substrate sequentially comprises a substrate, a metallization layer and an insulation layer from bottom to top, the metallization layer comprises a metal wiring layer and at least one metal ring structure, each metal ring structure comprises a plurality of metal rings which are concentrically arranged, the insulation layer is formed on the surfaces of the metal wiring layer and the metal ring structures, an opening is formed in the insulation layer, and the metal rings are arranged in the opening. The opening exposes the metal ring structure area, and interconnection solder is deposited at the opening; the flip chip is welded on the interconnection substrate in a flip manner; and the data acquisition system is electrically connected with the metal wiring layer. According to the testing structure, the size and interconnection quality of the interconnection structure are detected through the metal ring, the testing structure can also be used for detecting tiny defects, the detection precision and sensitivity are improved, on-site rapid, lossless and timely detection can be achieved, and the welding quality and the packaging reliability are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a test structure for flip chip packaging and a preparation method thereof. Background Art

[0002] Flip Chip Bonding, as the core interconnection technology of advanced semiconductor packaging, has been widely used in fields such as high-performance computing, 5G communication, and consumer electronics. With the improvement of chip integration and the miniaturization of packaging size, the solder joint size continues to shrink (micrometer level or even sub-micrometer level), and the impact of process quality on interconnection reliability becomes more significant, posing higher requirements for defect detection technology.

[0003] In the existing flip chip process detection, mainly two methods are adopted: non-destructive testing and destructive testing. Non-destructive testing does not require destroying the sample, can perform multiple detections on the packaging module, has a fast detection speed, can quickly evaluate the packaging interconnection quality, and verify the bonding strength. Non-destructive testing usually uses non-contact detection methods such as ultrasonic testing and X-ray testing. Although it can realize the visualization detection of the internal structure of the package, its detection accuracy is limited by the X-ray wavelength and ultrasonic frequency, making it difficult to capture sub-micrometer microcracks or weak interfacial bonding, and unable to detect tiny defects. For example, in ultrasonic testing, accurate detection results cannot be obtained for solder microcracks or poor interfacial effects; however, using high-precision detection equipment will result in high costs and is difficult to popularize. Therefore, for certain types of defects such as microcracks or internal tiny voids, non-destructive testing is not sensitive enough. Destructive testing can provide more detailed defect information, such as the type, location, and size of the defects, and through destructive testing, the ultimate performance and reliability of the packaging module can be verified. For example, during SEM cross-section analysis, accurate analysis of the cross-section of the multi-layer interconnection structure, native holes, and cracks can be achieved. However, destructive testing requires destroying the sample and cannot perform multiple detections on the same sample, resulting in batch differences between the detection samples and mass-produced products, and it is not suitable for immediate rapid non-destructive testing, and the detection process takes a long time and has high costs.

[0004] The non-destructive testing and destructive testing in the prior art each have their own advantages and disadvantages. In practical applications, they often need to be combined to achieve the detection effect. However, the existing detection methods still have certain limitations in terms of timeliness, accuracy, and cost-effectiveness. Especially in high-density and high-reliability flip chip processes, the existing detection methods cannot meet the requirements for timely and rapid detection of tiny defects.

[0005] Therefore, an improved technical solution is needed to address the above deficiencies in the prior art. Summary of the Invention

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a test structure for flip-chip packaging and a preparation method thereof, which are used to solve the deficiencies in the timeliness, accuracy, and cost-effectiveness of flip-chip process detection in the prior art, as well as the problem that it is difficult to meet the on-site timely, rapid, non-destructive, and low-cost detection requirements for micro-defects in high-density and high-reliability flip-chip processes.

[0007] To achieve the above object and other related objects, the present invention provides a preparation method for a test structure for flip-chip packaging, and the preparation method includes the following steps:

[0008] S1. Form an interconnection substrate:

[0009] S11. Provide a substrate, and form a metal wiring layer and at least one metal ring structure on the surface of the substrate. Each metal ring structure includes a plurality of concentrically arranged metal rings;

[0010] S12. Form an insulating layer on the metal wiring layer and the metal ring structure;

[0011] S13. Form an opening in the insulating layer. The opening exposes the metal ring structure area, and the insulating layer covers the metal wiring layer;

[0012] S14. Deposit interconnection solder at the opening;

[0013] S2. Provide a flip chip, form bumps on the pads of the flip chip, and place the flip chip above the interconnection substrate so that the bumps are aligned with the interconnection solder;

[0014] S3. Melt the interconnection solder, and perform flip-chip soldering on the flip chip and the interconnection substrate. The interconnection solder deforms and forms an interconnection structure with the plurality of metal rings;

[0015] S4. Provide a data acquisition system, and electrically connect the data acquisition system to the metal wiring layer to realize the connection between the metal ring and the data acquisition system. The data acquisition system is used to collect the deformation degree and size change of the interconnection solder during the flip-chip soldering process.

[0016] Preferably, in step S11, forming a metal wiring layer and at least one metal ring structure on the surface of the substrate specifically includes the following steps:

[0017] S111. Deposit a metal thin film on the surface of the substrate to form a metallization layer;

[0018] S112. Apply photoresist on the metallization layer, form a patterned photoresist template through exposure and development, and then remove the metallization layer outside the photoresist template through an etching process to form the required metal wiring layer and at least one metal ring structure.

[0019] Preferably, the material of the metallization layer in step S11 includes one or a combination of copper, aluminum, gold, and nickel metals.

[0020] Preferably, the material of the metallization layer in step S11 is a superconducting material, and the superconducting material is niobium or niobium nitride.

[0021] Preferably, in step S11, the multiple metal rings are arranged in a concentric semi-surrounding structure, the distance between each adjacent two metal rings is the same, and the shapes of all the metal rings are the same.

[0022] Preferably, the distance between adjacent two metal rings is not less than 50 nm.

[0023] Preferably, the material of the insulating layer in step S12 includes one of silicon dioxide and silicon nitride.

[0024] Preferably, the material of the insulating layer in step S12 includes one of benzocyclobutene, polyimide, and fluorinated polymer.

[0025] Preferably, the material of the interconnect solder in step S14 includes one of tin, lead, and indium materials or an alloy material of any two of them.

[0026] Preferably, the material of the interconnect solder in step S14 includes one of tin-silver, tin-silver-copper, and indium-bismuth-tin alloy materials.

[0027] The present invention also provides a test structure for flip-chip packaging, and the test structure includes:

[0028] An interconnect substrate, which sequentially includes a substrate, a metallization layer, and an insulating layer from bottom to top. The metallization layer is formed on the surface of the substrate. The metallization layer includes a metal wiring layer and at least one metal ring structure. Each metal ring structure includes multiple concentric metal rings. The insulating layer is formed on the surfaces of the metal wiring layer and the metal ring structure. An opening is formed in the insulating layer, and the opening exposes the metal ring structure area. The insulating layer covers the metal wiring layer, and an interconnect solder is deposited at the opening, and the interconnect solder is deposited in the metal ring structure area;

[0029] A flip chip, and bumps are provided on the pads of the flip chip. The bumps are aligned with the interconnect solder, so that the flip chip is flip-chip welded to the interconnect substrate;

[0030] A data acquisition system, and the data acquisition system is electrically connected to the metal wiring layer.

[0031] Preferably, a plurality of the metal rings are arranged in a concentric semi-surrounding structure, the distance between every two adjacent metal rings is the same, and the shapes of all the metal rings are the same.

[0032] Preferably, the distance between two adjacent metal rings is not less than 50 nm.

[0033] As described above, the test structure for flip-chip packaging and its preparation method according to the present invention have the following beneficial effects:

[0034] In the test structure of the present invention, a metal wiring layer and at least one metal ring structure are formed by microfabrication on a substrate. The metal ring structure includes a plurality of concentric metal rings. The bumps of the flip chip are aligned with the interconnect solder in the metal ring area, and the interconnect solder is melted to flip-chip solder the flip chip to the metal ring area. The interconnect solder deforms and forms an interconnect structure with the metal rings. After flip-chip soldering, the interconnect solder contacts the plurality of metal rings. The degree of deformation and size change of the interconnect solder are collected by the data acquisition system. By designing metal rings with different shapes and arrangements, the size and interconnect quality of the interconnect structure formed after flip-chip soldering can be detected. By setting the distance between two adjacent metal rings, it can be used for the detection of micro-defects, improving the detection accuracy and sensitivity.

[0035] The preparation process of the test structure in the present invention is simple, capable of realizing on-site rapid, non-destructive, and timely detection, simplifying the test process, and being able to timely discover and solve problems during the flip-chip packaging process. Based on the test results, the welding process parameters are analyzed in real time and accurately adjusted to optimize the formation process of the interconnect structure, thereby improving the welding quality and packaging reliability. At the same time, it also avoids the generation of defective packaging modules, improves the product yield, and reduces costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It shows a schematic structural diagram of step S111 in the preparation method of the test structure for flip-chip packaging in a specific embodiment of the present invention.

[0037] Figure 2 It shows a schematic structural diagram of step S112 in the preparation method of the test structure for flip-chip packaging in a specific embodiment of the present invention.

[0038] Figure 3 It shows a schematic structural diagram of step S12 in the preparation method of the test structure for flip-chip packaging in a specific embodiment of the present invention.

[0039] Figure 4It shows a schematic structural diagram of step S13 in the preparation method of the test structure for flip-chip packaging in a specific embodiment of the present invention.

[0040] Figure 5 It shows a schematic structural diagram of step S14 in the preparation method of the test structure for flip-chip packaging in a specific embodiment of the present invention.

[0041] Figure 6 It shows a schematic structural diagram of step S2 in the preparation method of the test structure for flip-chip packaging in a specific embodiment of the present invention.

[0042] Figure 7 It shows a schematic structural diagram of steps S3 and S4 in the preparation method of the test structure for flip-chip packaging in a specific embodiment of the present invention.

[0043] Figure 8 It shows Figure 5 a partial top-view structural diagram of

[0044] Figure 9 It shows Figure 7 a partial top-view structural diagram of

[0045] Figure 10 It shows a schematic diagram of the test principle of the metal ring in a specific embodiment of the present invention.

[0046] Figures 11 to 13 They respectively show the topography prediction diagrams of the interconnect structure in specific embodiments of the present invention.

[0047] Figures 14 to 18 They respectively show the layout schematic diagrams of the metal ring structures in specific embodiments of the present invention.

[0048] Element number description

[0049] 101 Substrate

[0050] 201 Metallization layer

[0051] 202 Metal ring

[0052] 203 Metal wiring layer

[0053] 301 Insulating layer

[0054] 302 Opening

[0055] 401 Interconnect solder

[0056] 402 Interconnect structure

[0057] 501 Data acquisition system

[0058] 601 Flip chip Detailed implementation manners

[0059] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0060] Before further describing the specific embodiments of the present invention, it should be understood that the protection scope of the present invention is not limited to the specific embodiments described below; it should also be understood that the terms used in the embodiments of the present invention are for describing specific embodiments, rather than limiting the protection scope of the present invention. The test methods without specific conditions noted in the following embodiments are generally carried out under conventional conditions or according to the conditions recommended by each manufacturer.

[0061] When an embodiment gives a numerical range, it should be understood that unless otherwise specified in the present invention, any value between the two endpoints of each numerical range and either endpoint can be selected. Unless otherwise defined, all technical and scientific terms used in the present invention have the same meaning as commonly understood by those skilled in the art of this technology. In addition to the specific methods, devices, and materials used in the embodiments, according to the knowledge of those skilled in the art of this technology and the description of the present invention, any methods, devices, and materials of the prior art similar to or equivalent to those described in the embodiments of the present invention can also be used to implement the present invention.

[0062] Please refer to Figures 1 to 18 . It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0063] Based on the limitations of the non-destructive testing and destructive testing of the flip-chip bonding process in terms of timeliness, accuracy, and cost-effectiveness in the prior art, especially in high-density and high-reliability flip-chip bonding processes, where the existing testing methods cannot meet the requirement of timely and rapid detection of micro-defects, the present invention provides a test structure for flip-chip packaging and a preparation method thereof. Specifically, the preparation method of the test structure for flip-chip packaging includes the following steps:

[0064] S1. Form an interconnect substrate 101:

[0065] S11. Provide a substrate 101, and form a metal wiring layer 203 and at least one metal ring structure on the surface of the substrate 101. Each metal ring structure includes a plurality of concentrically arranged metal rings 202;

[0066] S12. Form an insulating layer 301 on the metal wiring layer 203 and the metal ring structure;

[0067] S13. Form an opening 302 on the insulating layer 301. The opening 302 exposes the metal ring structure area, and the insulating layer 301 covers the metal wiring layer 203;

[0068] S14. Deposit an interconnect solder 401 at the opening 302;

[0069] S2. Provide a flip chip 601, form bumps on the pads of the flip chip 601, and place the flip chip 601 above the interconnect substrate 101 so that the bumps are aligned with the interconnect solder 401;

[0070] S3. Melt the interconnect solder 401 to perform flip-chip soldering of the flip chip 601 and the interconnect substrate 101. The interconnect solder 401 deforms and forms an interconnect structure 402 with the plurality of metal rings 202;

[0071] S4. Provide a data acquisition system 501, electrically connect the data acquisition system 501 to the metal wiring layer 203 to realize the connection between the metal rings 202 and the data acquisition system 501. The data acquisition system 501 is used to acquire the deformation degree and size change of the interconnect solder 401 during the flip-chip soldering process.

[0072] First, execute step S1 to form an interconnect substrate 101.

[0073] Refer to Figures 1 to 4 , forming the interconnect substrate 101 includes the following steps:

[0074] S11. Provide a substrate 101, and form a metal wiring layer 203 and at least one metal ring structure on the surface of the substrate 101. Each metal ring structure includes a plurality of concentrically arranged metal rings 202;

[0075] S12. Form an insulating layer 301 on the metal wiring layer 203 and the metal ring structure;

[0076] S13. Form an opening 302 on the insulating layer 301. The opening 302 exposes the metal ring structure area, and the insulating layer 301 covers the metal wiring layer 203;

[0077] S14. Deposit an interconnect solder 401 at the opening 302.

[0078] Specifically, the substrate 101 in step S11 is a substrate 101 material that can be etched and processed. It is necessary to ensure that the surface of the substrate 101 is flat. Preferably, the substrate 101 includes silicon, ceramic, or organic substrate 101, and no further limitations are imposed here.

[0079] Refer to Figure 1 、 Figure 2 , first perform step S11, provide the substrate 101, and form a metal wiring layer 203 and at least one metal ring structure on the surface of the substrate 101. Each metal ring structure includes a plurality of concentrically arranged metal rings 202.

[0080] As an example, forming the metal wiring layer 203 and at least one metal ring structure on the surface of the substrate 101 in step S11 specifically includes the following steps:

[0081] S111, refer to Figure 1 , deposit a metal thin film on the surface of the substrate 101 to form a metallization layer 201;

[0082] S112, refer to Figure 2 , coat a photoresist on the metallization layer 201, expose and develop it to form a patterned photoresist template, and then remove the metallization layer 201 outside the photoresist template through an etching process to form the required metal wiring layer 203 and at least one metal ring structure.

[0083] Specifically, the metallization layer 201 in step S111 can be formed by methods such as sputtering, evaporation plating, or electroless plating. The metallization layer 201 serves as a bridge for electrical interconnection; in step S112, a pre-designed mask is used to expose the pattern onto the photoresist, and after development, a patterned photoresist template is formed. Then, through the etching process, the metallization layer 201 outside the photoresist template is removed. After removing the excess photoresist, the required metal wiring layer 203 and at least one metal ring structure are formed. Each metal ring structure includes a plurality of metal rings 202; in addition, the number of metal ring structures is preferably an even number. The plurality of metal rings 202 in each metal ring structure are concentrically arranged and all have openings 302. The specific direction of the openings 302 can be adjusted according to actual needs, and the spacing between adjacent two metal rings 202 can also be adjusted according to actual situations.

[0084] As an example, the material of the metallization layer 201 in step S11 includes one or a combination of copper, aluminum, gold, and nickel metals.

[0085] As an example, the material of the metallization layer 201 in step S11 is a superconducting material, and the superconducting material is niobium or niobium nitride.

[0086] Specifically, the metallization layer 201, as a bridge for electrical interconnection, can be composed of multiple layers of materials, and the specific number of layers is not overly restricted here; the materials of the metal rings 202 and the metal wiring layer 203 are the same and are the same as the material of the metallization layer 201. The required metal wiring layer 203 and metal ring structure are formed on the metallization layer 201 through microfabrication. Each metal ring 202 in each metal ring structure is electrically connected to the metal wiring layer 203, and the metal wiring layer 203 is used for signal connection.

[0087] As an example, in step S11, multiple metal rings 202 are arranged in a concentric semi-surrounding structure, the distance between every two adjacent metal rings 202 is the same, and the shapes of all metal rings 202 are the same.

[0088] As an example, the distance between two adjacent metal rings 202 is not less than 50 nm.

[0089] Specifically, refer to Figure 10 is the test schematic diagram of the metal ring. Taking site 0 as the reference point, r1 to r n respectively represent the radii of the 1st to the nth metal rings 202 counted from the inside out. When the radius of the interconnection structure 402 is between r1 and r2, then site 1 is conductive to site 0, and so on. Therefore, the distance between two adjacent metal rings 202 is denoted as s, and r n represents a radius equal to n×s. The number of sites n that can form a path with the reference point 0 and the radius R of the interconnection structure 402 satisfy: n×s ≤ R < (n + 1)×s.

[0090] According to the test schematic diagram of the metal ring 202, the size of the interconnection structure 402 can be tested according to the diameter of the metal ring 202. During the flip-chip bonding packaging process, the deformation degree and size change of the interconnection structure 402 can be collected. Finally, after the welding is completed, the size of the interconnection structure 402 can be measured. According to the size, the conduction situation of the flip chip 601 can be known; which layer of metal ring 202 the interconnection structure 402 is connected to, that is, the diameter of the interconnection structure 402 can be correspondingly obtained. The maximum diameter of the entire metal ring structure determines the range of the size of the interconnection structure 402 that can be tested. Of course, the smaller the distance between two adjacent metal rings 202, the denser the arrangement of the metal rings 202 in the metal ring structure, and the higher the test accuracy. In a specific embodiment of the present invention, through good lithography definition, the distance between two adjacent metal rings 202 can be reduced to 50 nm, greatly improving the detection accuracy of the interconnection structure 402. Preferably, the distance between two adjacent metal rings 202 is 1 μm to 1000 μm (such as 1 μm, 5 μm, 10 μm, 50 μm, 100 μm, 500 μm, 1000 μm, etc.). Of course, the distance can also be larger, and it is not overly restricted here.

[0091] After that, step S12 is performed to form an insulating layer 301 on the metal wiring layer 203 and the metal ring structure. Refer to Figure 3 .

[0092] As an example, the material of the insulating layer 301 in step S12 includes one of silicon dioxide and silicon nitride.

[0093] Specifically, the silicon dioxide or silicon nitride insulating layer 301 can be prepared by chemical vapor deposition or sputtering.

[0094] As an example, the material of the insulating layer 301 in step S12 includes one of benzocyclobutene, polyimide, and fluorinated polymer.

[0095] Specifically, the organic materials benzocyclobutene, polyimide, and fluorinated polymer insulating layer 301 can be formed by spin coating or spraying.

[0096] After that, step S13 is performed to form an opening 302 in the insulating layer 301. The opening 302 exposes the metal ring structure area, and the insulating layer 301 covers the metal wiring layer 203. Refer to Figure 4 .

[0097] Specifically, the graphic opening 302 is defined by photolithography, and then the opening 302 exposing the metal ring structure area is obtained by etching or corrosion. The opening 302 only exposes the metal ring structure area, and the metal wiring layer 203 is still covered by the insulating layer 301.

[0098] After that, step S14 is performed to deposit an interconnect solder 401 at the opening 302. Refer to Figure 5 .

[0099] As an example, the material of the interconnect solder 401 in step S14 includes one of tin, lead, and indium materials or an alloy material of any two of them.

[0100] As an example, the material of the interconnect solder 401 in step S14 includes one of tin-silver, tin-silver-copper, and indium-bismuth-tin alloy materials.

[0101] Specifically, the interconnect solder 401 needs to have good wettability with the metal ring 202. The appropriate interconnect solder 401 can be selected according to different flip-chip bonding processes. The flip-chip 601 is connected to the interconnect substrate 101 through the interconnect solder 401 to form a reliable electrical connection. Preferably, the forming method of the interconnect solder 401 includes evaporation plating, electroplating, printing, or ball planting.

[0102] Then, step S2 is executed to provide a flip-chip 601, form bumps on the pads of the flip-chip 601, and place the flip-chip 601 above the interconnect substrate 101 so that the bumps are aligned with the interconnect solder 401. Refer to Figure 6 .

[0103] Next, step S3 is executed to perform flip-chip bonding on the flip-chip 601 and the interconnection substrate 101. The interconnection solder 401 deforms and forms an interconnection structure 402 with the metal ring 202.

[0104] Specifically, the flip-chip 601 and the interconnection substrate 101 are flip-chip bonded by heating the interconnection solder 401 to melt it, or by the form of thermocompression bonding with pressure and heat applied.

[0105] Finally, step S4 is executed to provide a data acquisition system 501, and the data acquisition system 501 is electrically connected to the metal wiring layer 203 to realize the connection between the metal ring 202 and the data acquisition system 501. The data acquisition system 501 is used to collect the deformation degree and dimensional change of the interconnection solder 401 during the flip-chip bonding process.

[0106] Specifically, flip-chip bonding is achieved through the connection between the bumps and the interconnection solder 401 to ensure an electrical connection is formed between the flip-chip 601 and the interconnection substrate 101. During the flip-chip bonding process, the interconnection solder 401 deforms and forms different interconnection structures 402 with the metal ring 202. The data acquisition system 501 promptly and rapidly collects the deformation degree and dimensional change of the interconnection solder 401 during the flip-chip bonding process. The welding process parameters can be adjusted in real time according to the data collected by the data acquisition system 501 to avoid the production of defective products. The adjusted parameters can be used in subsequent flip-chip bonding processes to ensure the consistency and reliability of the process.

[0107] The present invention also provides a test structure for flip-chip bonding packaging. The test structure includes an interconnection substrate 101, a flip-chip 601, and a data acquisition system 501. Among them, the interconnection substrate 101 sequentially includes a substrate 101, a metallization layer 201, and an insulating layer 301 from bottom to top. The metallization layer 201 is formed on the surface of the substrate 101. The metallization layer 201 includes a metal wiring layer 203 and at least one metal ring structure. Each metal ring structure includes a plurality of concentrically arranged metal rings 202. The insulating layer 301 is formed on the surfaces of the metal wiring layer 203 and the plurality of metal ring structures. An opening 302 is provided on the insulating layer 301, and the opening 302 exposes the metal ring structure area. The insulating layer 301 covers the metal wiring layer 203, and the interconnection solder 401 is deposited at the opening 302. The interconnection solder 401 is deposited in the metal ring structure area. Bumps are provided on the pads of the flip-chip 601, and the bumps are aligned with the interconnection solder 401. The flip-chip 601 is flip-chip bonded to the interconnection substrate 101. The data acquisition system 501 is electrically connected to the metal wiring layer 203.

[0108] Specifically, the test structure in the specific embodiment of the present invention forms a metal wiring layer 203 and at least one metal ring structure on a substrate 101 through microfabrication. The metal ring structure includes a plurality of concentrically arranged metal rings 202. The bumps of the flip chip 601 are aligned with the interconnect solder 401 in the metal ring structure area, and the interconnect solder 401 is melted to flip-chip weld the flip chip 601 to the metal ring structure area. The interconnect solder 401 deforms and forms an interconnect structure 402 with the metal rings 202. After flip-chip welding, the interconnect solder 401 contacts the plurality of metal rings 202. The deformation degree and size change of the interconnect solder 401 are collected by a data acquisition system 501. By designing metal ring structures with different shapes and arrangements, the size and interconnect quality of the interconnect structure 402 formed after flip-chip welding are detected. By setting the spacing between adjacent two metal rings 202, it can be used for detecting tiny defects, improving the detection accuracy and sensitivity.

[0109] In addition, the test structure can also be used to predict the morphology of the formed interconnect structure 402, and further evaluate the process quality of flip-chip welding packaging. Refer to Figure 8 、 Figure 9 As a partial top view structural schematic diagram of the test structure, the designed metal ring 202 is semicircular, the metal ring structure has an opening 302, and the interconnect structure 402 can be conducted only when it overflows towards the opening 302. Assuming the consistency of the interconnect structure 402, the openings 302 of the metal ring structure are set in four directions: up, down, left, and right. The maximum test sites that can be conducted on each metal ring structure are X, that is, the maximum test sites of the metal ring structures in the four directions are X1, X2, X3, and X4 respectively. If X1 = X2 = X3 = X4, then the predicted formed interconnect structure 402 is "circular", and the welding process quality is the best at this time; if the maximum test site of any metal ring structure is greater than the other three, such as X1>X2 = X3 = X4, then the predicted interconnect structure 402 is "drop-shaped", refer to Figure 11 as shown; if the maximum test sites of any two metal ring structures are greater than the other two, and the directions of the two larger metal ring structures are opposite, such as X1 = X3>X2 = X4, then the predicted bumps are "fusiform or capsule-shaped", refer to Figure 12 as shown; if the maximum test sites of any two metal ring structures are greater than the other two, and the directions of the two larger metal ring structures are perpendicular to each other, such as X1 = X2>X3 = X4, then the predicted interconnect structure 402 is "bowl-shaped", refer to Figure 13 as shown. Here is only an example, which does not represent the actual arrangement of the metal ring structure. In other examples, every two metal ring structures are arranged opposite to each other, and the directions of the openings 302 are opposite. Specifically, how to arrange and the number of settings are not overly restricted here.

[0110] As an example, multiple metal rings 202 are arranged in a concentric semi - enclosed structure, with a consistent spacing between every two adjacent metal rings 202, and the shapes of all metal rings 202 are the same.

[0111] Specifically, referring to the figure Figures 14 to 18 They are respectively schematic diagrams of the arrangement of the metal ring structure, mainly reflected in the coverage area and graphic shape of the metal ring 202. Different - shaped arrangements of the metal ring structure can be formed through photolithography technology to cope with different interconnect solders 401, ensure good wettability between the metal ring 202 and the interconnect solder 401, and accurate data can be collected through the data acquisition system 501, so as to conduct effective detection.

[0112] The metal ring structure is composed of multiple metal rings 202, and the multiple metal rings 202 are arranged in a concentric semi - enclosed structure. Figure 14 The metal ring 202 presented in [reference] is semicircular, with a consistent spacing between every two adjacent metal rings 202, and the shape of each metal ring 202 remains consistent. Figure 15 The metal ring 202 in the semi - enclosed structure is circular - ring - shaped with a certain opening 302. Of course, in other examples, the metal ring 202 can be a circular ring with an opening 302 at any angle. Figure 16 The metal ring 202 in [reference] also forms a semi - enclosed structure, and this semi - enclosed structure is in the shape of an acute - angled circular ring. Figure 17 The metal ring 202 in the semi - enclosed structure in [reference] is square - shaped with a certain opening 302 formed by enclosing. Figure 18 The metal ring 202 in the semi - enclosed structure in [reference] is a symmetrically arranged ring with a certain opening 302. Figures 14 to 18 Only several schematic diagrams of the arrangement of the metal ring structure are listed in [reference]. Of course, there can be many other arrangement ways, and no excessive restrictions are made here.

[0113] As an example, the spacing between two adjacent metal rings 202 is not less than 50 nm.

[0114] In a specific embodiment of the present invention, through good photolithography definition, the spacing between two adjacent metal rings 202 can be reduced to 50 nm, greatly improving the detection accuracy of the interconnect structure 402. Preferably, the spacing between two adjacent metal rings 202 is 1 μm - 1000 μm (such as 1 μm, 5 μm, 10 μm, 50 μm, 100 μm, 500 μm, 1000 μm, etc.). Of course, the spacing can also be larger, and no excessive restrictions are made here.

[0115] In summary, the test structure in the present invention forms a metal wiring layer and at least one metal ring structure through micromachining on a substrate. The metal ring structure includes a plurality of concentrically arranged metal rings. The bumps of the flip chip are aligned with the interconnect solder in the metal ring region, and the interconnect solder is melted to flip-chip solder the flip chip to the metal ring region. The interconnect solder deforms and forms an interconnect structure with the metal rings. After flip-chip soldering, the interconnect solder contacts the plurality of metal rings. The degree of deformation and size change of the interconnect solder are collected through a data acquisition system. By designing metal rings with different shapes and arrangements, the size and interconnect quality of the interconnect structure formed after flip-chip soldering are detected. By setting the spacing between adjacent metal rings, it can be used for the detection of minute defects, improving the detection accuracy and sensitivity. The preparation process of the test structure in the present invention is simple, capable of realizing rapid, non-destructive, and timely on-site detection, simplifying the test process, and being able to discover and solve problems in a timely manner during the flip-chip soldering packaging process. Based on the test results, the soldering process parameters are analyzed in real time and accurately adjusted to optimize the formation process of the interconnect structure, thereby improving the soldering quality and packaging reliability. At the same time, the generation of defective packaging modules is avoided, the product yield is increased, and the cost is reduced. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0116] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a test structure for flip chip packaging, characterized in that: The preparation method comprises the following steps: S1. Forming an interconnect substrate: S11, providing a substrate, and forming a metal wiring layer and at least one metal ring structure on a surface of the substrate, each of the metal ring structures comprising a plurality of concentrically arranged metal rings; S12, forming an insulating layer on the metal wiring layer and the metal ring structure; S13, forming an opening on the insulating layer, wherein the opening exposes the metal ring structure region, and the insulating layer covers the metal wiring layer; S14, depositing interconnect solder at the opening; S2, providing a flip chip, forming bumps on pads of the flip chip, and placing the flip chip above the interconnect substrate so that the bumps are aligned with the interconnect solder; S3, performing flip-chip soldering on the interconnection substrate, so that the interconnection solder is deformed and forms an interconnection structure between the plurality of metal rings; S4. Provide a data acquisition system, and electrically connect the data acquisition system to the metal wiring layer to achieve connection between the metal ring and the data acquisition system, wherein the data acquisition system is used to collect deformation degree and dimensional change of the interconnect solder during flip-chip welding.

2. The method for preparing a test structure for flip chip packaging according to claim 1, characterized in that: In step S11, a metal wiring layer and at least one metal ring structure are formed on the surface of the substrate, which specifically includes the following steps: S111, depositing a metal film on the surface of the substrate to form a metallization layer; S112, coating photoresist on the metallization layer, exposing and developing to form a patterned photoresist template, and then removing the metallization layer outside the photoresist template by an etching process to form a required metal wiring layer and at least one metal ring structure.

3. The method for preparing a test structure for flip chip packaging according to claim 2, characterized in that: Step S11 includes one or a combination of the following conditions: The material of the metallization layer includes one or a combination of copper, aluminum, gold, and nickel; The material of the metallization layer is a superconducting material, and the superconducting material is niobium or niobium nitride.

4. The method for preparing a test structure for flip chip packaging according to claim 1, characterized in that: In step S11, the plurality of metal rings are concentrically arranged in a semi-enclosed structure, the distance between each two adjacent metal rings is consistent, and the shapes of the metal rings are consistent.

5. The method for preparing a test structure for flip chip packaging according to claim 4, characterized in that: The distance between two adjacent metal rings is not less than 50 nm.

6. The method for preparing a test structure for flip chip packaging according to claim 1, characterized in that: Step S12 includes one or a combination of the following conditions: The material of the insulating layer includes one of silicon dioxide and silicon nitride; The material of the insulating layer includes one of benzocyclobutene, polyimide and fluorinated polymer.

7. The method for preparing a test structure for flip chip packaging according to claim 1, characterized in that: Step S14 includes one or a combination of the following conditions: The material of the interconnect solder includes one of tin, lead, and indium materials or an alloy material of any two; The material of the interconnect solder includes one of tin-silver, tin-silver-copper, and indium-bismuth-tin alloy materials.

8. A test structure for flip chip packaging, characterized in that: The test structure includes: An interconnect substrate, the interconnect substrate comprises a substrate, a metallization layer, and an insulating layer in order from bottom to top, the metallization layer is formed on the surface of the substrate, the metallization layer comprises a metal wiring layer and at least one metal ring structure, each of the metal ring structures comprises a plurality of concentrically arranged metal rings, the insulating layer is formed on the surfaces of the metal wiring layer and the metal ring structure, an opening is formed on the insulating layer, the opening exposes the metal ring structure region, the insulating layer covers the metal wiring layer, and interconnect solder is deposited at the opening, the interconnect solder is deposited in the metal ring structure region; A flip chip, wherein a bump is provided on a pad of the flip chip, the bump is aligned with the interconnect solder, and the flip chip is flip-soldered on the interconnect substrate; A data acquisition system is electrically connected to the metal wiring layer.

9. The test structure for flip chip packaging according to claim 8, characterized in that: The plurality of metal rings are in a concentrically arranged semi-enclosed structure, the spacing between each two adjacent metal rings is consistent, and the shapes of the metal rings are consistent.

10. The test structure for flip chip packaging according to claim 8, characterized in that: The distance between two adjacent metal rings is not less than 50 nm.

Images