Charge pump circuit, chip and electronic equipment

Abstract

The invention provides a charge pump circuit, a chip and electronic equipment. The charge pump circuit comprises a first charge pump branch, a second charge pump branch and a charge transfer control branch, the charge transfer control branch is electrically connected with the first charge pump branch and the second charge pump branch respectively; and the charge transfer control branch is used for transferring a part of charges stored by the parasitic capacitance of the second target switch into the parasitic capacitance of the first target switch in a dead zone period under the first working mode or the second working mode. According to the embodiment of the invention, in the first working mode and the second working mode, partial charges of the parasitic capacitance of the second target switch are transferred to the parasitic capacitance of the first target switch; when the first target switch is used as the second target switch in the next control period, namely the first target switch is switched to the off state, charging is not needed due to the fact that the parasitic capacitor stores charges, and the effect of reducing or eliminating switching loss is achieved.

Description

Technical Field

[0001] The present disclosure relates to the field of control technologies, and in particular, to a charge pump circuit, a chip, and an electronic device. Background Art

[0002] As more and more electrical loads are carried by electronic devices, the capacity of their batteries is getting larger and larger. For this reason, a charge pump circuit is provided in the related art electronic device to charge the battery.

[0003] For example, in the first stage, the charge pump circuit controls a plurality of capacitors to be connected in series, and charges the capacitors with a high voltage and a small current; in the second stage, the charge pump circuit controls the plurality of capacitors to be connected in parallel, and charges the battery with a low voltage and a large current to achieve the effect of fast charging. Based on the above analysis of the working process, during the charging process, the charge pump circuit needs to frequently turn on or off the switching devices, thereby increasing the switching loss. Summary of the Invention

[0004] The present disclosure provides a charge pump circuit, a chip, and an electronic device to solve the above technical problems.

[0005] According to a first aspect of the present disclosure, a charge pump circuit is provided, including: a first charge pump branch, a second charge pump branch, and a charge transfer control branch; the charge transfer control branch is electrically connected to the first charge pump branch and the second charge pump branch respectively;

[0006] The charge transfer control branch is configured to transfer a part of the charge stored in the parasitic capacitance of the second target switch to the parasitic capacitance of the first target switch during the dead time in the first operating mode or the second operating mode;

[0007] The dead time refers to the period during which the switching devices in the first charge pump branch and the second charge pump branch are both in the off state, the first target switch refers to the switching device that was in the on state in the previous control cycle, and the second target switch refers to the switching device that was in the off state in the previous control cycle.

[0008] Optionally, the first charge pump branch includes a first sub-branch and a second sub-branch connected electrically; the second charge pump branch includes a third sub-branch and a fourth sub-branch connected electrically; the first sub-branch and the fourth sub-branch are electrically connected, and the second sub-branch is electrically connected to the third sub-branch; the charge transfer control branch includes a first transfer control sub-branch;

[0009] The first transfer control sub-branch is electrically connected to the first sub-branch and the third sub-branch respectively, and is configured to transfer a part of the charge stored in the parasitic capacitance of the second target switch to the parasitic capacitance of the first target switch during the dead time in the first operating mode.

[0010] Optionally, the first sub-branch includes a first switching device, a fourth switching device, and a sixth switching device; the first transfer control sub-branch includes a first inductor;

[0011] A first end of the first switching device is electrically connected to an input end of the charge pump circuit, and a second end of the first switching device is electrically connected to a first end of the four-switching device; a second end of the fourth switching device is electrically connected to a first end of the sixth switching device, and a second end of the sixth switching device is electrically connected to the fourth sub-branch;

[0012] The third sub-branch includes a second switching device, a third switching device, and a fifth switching device; a first end of the second switching device is electrically connected to an input end of the charge pump circuit, and a second end of the second switching device is electrically connected to a first end of the third switching device; a second end of the third switching device is electrically connected to a first end of the fifth switching device, and a second end of the fifth switching device is electrically connected to the second sub-branch;

[0013] During a sub-phase of the first sub-phase and the second sub-phase of the dead time, a first end of the first inductor is electrically connected to a second end of the first switching device, and a second end of the first inductor is grounded; during the other sub-phase of the dead time, the first end of the first inductor is grounded, and the second end of the first inductor is electrically connected to a second end of the second switching device.

[0014] Optionally, the first transfer control sub-branch includes a first transfer control switch and a second transfer control switch; a first end of the first transfer control switch is electrically connected to a second end of the first switching device, and a second end of the first transfer control switch is electrically connected to a first end of the first inductor; a second end of the first inductor is electrically connected to a first end of the second transfer control switch, and a second end of the second transfer control switch is grounded; control ends of the first transfer control switch and the second transfer control switch are used to receive control signals;

[0015] The first transfer control switch is used to switch to a conducting state when an effective control signal is received during the dead time of the first operating mode, so as to electrically connect the first end of the first inductor to the second end of the first switching device;

[0016] The second transfer control switch is used to switch to a conducting state when an effective control signal is received during the dead time of the first operating mode, so as to ground the second end of the first inductor.

[0017] Optionally, the first transfer control sub-branch further includes a third transfer control switch and a fourth transfer control switch; a first end of the third transfer control switch is electrically connected to a second end of the first inductor, and a second end of the third transfer control switch is electrically connected to a second end of the second switching device; a first end of the fourth transfer control switch is electrically connected to a first end of the first inductor, and a second end of the fourth transfer control switch is grounded;

[0018] The third transfer control switch is configured to switch to a conducting state when receiving an effective control signal during a dead time period of the first operating mode, so as to electrically connect the second end of the first inductor to the second end of the second switching device;

[0019] The fourth transfer control switch is configured to switch to a conducting state when receiving an effective control signal during a dead time period of the first operating mode, so as to ground the first end of the first inductor.

[0020] Optionally, the charge transfer control branch further includes a second transfer control sub-branch; the second transfer control sub-branch is electrically connected to the second sub-branch and the fourth sub-branch respectively;

[0021] The second transfer control sub-branch is configured to transfer a part of the charge stored in the parasitic capacitance of the second target switch to the parasitic capacitance of the first target switch during a dead time period of the second operating mode.

[0022] Optionally, the second transfer control sub-branch includes a seventh transfer control switch; a first end of the seventh transfer control switch is electrically connected to the first sub-branch and the fourth sub-branch respectively, a second end of the seventh transfer control switch is electrically connected to a first end of the first inductor, and a control end of the seventh transfer control switch is configured to receive a control signal;

[0023] The seventh transfer control switch is configured to switch to a conducting state when receiving an effective control signal during a dead time period of the second operating mode, so as to electrically connect the first end of the first inductor to the first sub-branch and the fourth sub-branch respectively; and a second transfer control switch of the first conversion control sub-branch switches to a conducting state, so as to ground the first end of the first inductor.

[0024] Optionally, the second transfer control sub-branch includes an eighth transfer control switch;

[0025] A first end of the eighth transfer control switch is electrically connected to the second sub-branch and the third sub-branch respectively, a second end of the eighth transfer control switch is electrically connected to a second end of the first inductor, and a control end of the eighth transfer control switch is configured to receive a control signal;

[0026] The eighth transfer control switch is configured to switch to the conducting state when receiving a valid control signal during the dead time of the second operating mode, so as to electrically connect the second end of the first inductor to the second sub-branch and the third sub-branch respectively; and the fourth transfer control switch of the first conversion control sub-branch switches to the conducting state to ground the first end of the first inductor.

[0027] Optionally, the first inductance value of the first inductor is less than a target inductance value, where the target inductance value refers to the inductance value that matches the parasitic capacitance of the switching device in the first charge pump branch and / or the second charge pump branch at the switching frequency of the two charge pump branches in the charge pump circuit.

[0028] According to a second aspect of the present disclosure, there is provided a chip including the charge pump circuit according to any one of the first aspect.

[0029] According to a third aspect of the present disclosure, there is provided an electronic device including: a processor, a battery, a charging interface, and the charge pump circuit according to any one of the first aspect; the charge pump circuit is electrically connected to the battery and the charging interface respectively; the processor is electrically connected to the charge pump circuit;

[0030] The processor is configured to control the first target switch of the first charge pump branch and the second charge pump branch to switch to the conducting state and the second target switch to switch to the off state within one control period;

[0031] The processor is configured to switch the charge pump circuit to one of the first operating mode or the second operating mode, and control all the switching devices of the first charge pump branch and the second charge pump branch to switch to the off state during the dead time of the operating mode;

[0032] The processor is further configured to output a valid control signal to the charge transfer control branch of the charge pump circuit during the dead time of the operating mode;

[0033] The charge transfer control branch is configured to transfer a part of the charge stored in the parasitic capacitance of the second target switch in the previous control period to the parasitic capacitance of the first target switch when receiving a valid control signal during the dead time of the operating mode;

[0034] and / or,

[0035] a processor, a battery, a charging interface, and the chip according to the second aspect; the chip is electrically connected to the battery, the charging interface, and the processor respectively;

[0036] The processor is used to control, within one control cycle, the first target switch of the charge pump circuit in the chip to switch to the on state and the second target switch to switch to the off state;

[0037] The processor is used to switch the charge pump circuit to one of the first operating mode or the second operating mode, and control all the switching devices of the first charge pump branch and the second charge pump branch to switch to the off state during the dead time of the operating mode;

[0038] The processor is further used to output a valid control signal to the charge transfer control branch of the charge pump circuit during the dead time of the operating mode;

[0039] The charge transfer control branch is used to transfer a part of the charge stored in the parasitic capacitance of the second target switch in the previous control cycle to the parasitic capacitance of the first target switch when receiving a valid control signal during the dead time of the operating mode.

[0040] The technical solution provided by the embodiment of the present disclosure may include the following beneficial effects:

[0041] The charge pump circuit provided in this embodiment includes a first charge pump branch, a second charge pump branch, and a charge transfer control branch; the charge transfer control branch is electrically connected to the first charge pump branch and the second charge pump branch respectively; the charge transfer control branch is used to transfer a part of the charge stored in the parasitic capacitance of the second target switch to the parasitic capacitance of the first target switch during the dead time in the first operating mode or the second operating mode; the dead time refers to the period when the switching devices in the first charge pump branch and the second charge pump branch are both in the off state, the first target switch refers to the switching device that was in the on state in the previous control cycle, and the second target switch refers to the switching device that was in the off state in the previous control cycle. In this way, in the first operating mode and the second operating mode of this embodiment, by transferring part of the charge of the parasitic capacitance of the second target switch to the parasitic capacitance of the first target switch, when the first target switch is about to switch to the off state as the second target switch in the next control cycle, it does not need to be charged due to the charge stored in the parasitic capacitance, achieving the effect of reducing or eliminating switching losses.

[0042] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. Brief Description of the Drawings

[0043] Figure 1 It is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0044] Figure 2Block diagram of a charge pump circuit according to an embodiment of the present disclosure.

[0045] Figure 3 Block diagram of a charge pump circuit according to an embodiment of the present disclosure.

[0046] Figure 4 Circuit diagram of another charge pump circuit according to an embodiment of the present disclosure.

[0047] Figure 5 Circuit diagram of yet another charge pump circuit according to an embodiment of the present disclosure.

[0048] Figure 6 Circuit diagram of yet another charge pump circuit according to an embodiment of the present disclosure.

[0049] Figure 7 Circuit diagram of yet another charge pump circuit according to an embodiment of the present disclosure.

[0050] Figure 8 Circuit diagram of yet another charge pump circuit according to an embodiment of the present disclosure.

[0051] Figure 9 Circuit diagram of yet another charge pump circuit according to an embodiment of the present disclosure.

[0052] Figure 10 Circuit diagram of yet another charge pump circuit according to an embodiment of the present disclosure.

[0053] Figure 11 Circuit diagram of yet another charge pump circuit according to an embodiment of the present disclosure.

[0054] Figure 12 Circuit diagram of yet another charge pump circuit according to an embodiment of the present disclosure.

[0055] Figure 13 Circuit diagram of yet another charge pump circuit according to an embodiment of the present disclosure.

[0056] Figure 14 Circuit diagram of yet another charge pump circuit according to an embodiment of the present disclosure.

[0057] Figure 15 Circuit diagram of yet another charge pump circuit according to an embodiment of the present disclosure.

[0058] Figure 16 Circuit diagram of yet another charge pump circuit according to an embodiment of the present disclosure.

[0059] Figure 17 Circuit diagram of yet another charge pump circuit according to an embodiment of the present disclosure.

[0060] Figure 18 Block diagram of an electronic device according to an embodiment of the present disclosure. Detailed implementation manners

[0061] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present disclosure. Instead, they are merely examples of devices consistent with some aspects of the present disclosure as detailed in the appended claims.

[0062] To solve the above technical problems, embodiments of the present disclosure provide a charge pump circuit, a chip, and an electronic device. Figure 1 The following is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure. Refer to Figure 1 , an electronic device 10 includes a processor 11, a battery 14, a charging interface 12, and a charge pump circuit 13. The charge pump circuit 13 is electrically connected to the battery 14 and the charging interface 12 respectively; the processor 11 is electrically connected to the charge pump circuit 13.

[0063] In one example, the charging interface 12 may include, but is not limited to, a USB Type-C interface, a MicroUSB, etc. When it can support the charging of the charge pump circuit 13, the corresponding charging interface falls within the protection scope of the present disclosure.

[0064] In one example, refer to Figure 2 , the charge pump circuit 13 includes a first charge pump branch 21, a second charge pump branch 22, and a charge transfer control branch 23. The charge transfer control branch 23 is electrically connected to the first charge pump branch 21 and the second charge pump branch 22 respectively.

[0065] The charge transfer control branch 23 is configured to transfer a part of the charge stored in the parasitic capacitance of the second target switch to the parasitic capacitance of the first target switch during the dead time in the first operating mode or the second operating mode;

[0066] The above dead time refers to the period during which the switching devices in the first charge pump branch 21 and the second charge pump branch 22 are both in the off state. The first target switch refers to the switching device that was in the on state in the previous control cycle, and the second target switch refers to the switching device that was in the off state in the previous control cycle.

[0067] In one example, refer to Figure 2 and Figure 3, the first charge pump branch 21 includes a first sub-branch 211 and a second sub-branch 212 that are electrically connected; the second charge pump branch 22 includes a third sub-branch 221 and a fourth sub-branch 222 that are electrically connected; the first sub-branch 211 and the fourth sub-branch 222 are electrically connected, and the second sub-branch 212 is electrically connected to the third sub-branch 221. It can be understood that the first charge pump branch 21 and the second charge pump branch 22 form a cross-charging architecture, that is, the first charge pump branch 21 and the second charge pump branch 22 form a cross-charging architecture with respect to the first line where the power supply BAT is located.

[0068] In this example, refer to Figure 3 , the charge transfer control branch 23 includes a first transfer control sub-branch 231. The first transfer control sub-branch 231 is electrically connected to the first sub-branch 211 and the third sub-branch 221 respectively, and is used to transfer a part of the charge stored in the parasitic capacitance of the second target switch to the parasitic capacitance of the first target switch during the dead time of the first operating mode of the charge pump circuit;

[0069] It should be noted that the dead time refers to the period during which the switching devices in the first charge pump branch 21 and the second charge pump branch 22 are both in the off state. The first target switch refers to the switching device that was in the on state in the previous control cycle, and the second target switch refers to the switching device that was in the off state in the previous control cycle.

[0070] It should also be noted that in this example, the charge pump circuit includes two operating modes, such as the first operating mode and the second operating mode. The first operating mode may refer to a 4:1 charging mode. For example, when the input voltage is 20V and the input current is 5A, the output voltage is 5V and the output current is 20A; the second operating mode is a 2:1 charging mode. For example, when the input voltage is 10V and the input current is 5A, the output voltage is 5V and the output current is 10A. It can be understood that the operating mode can be adjusted according to the specific charging architecture, and the corresponding solution falls within the protection scope of the present disclosure.

[0071] Continue to refer to Figure 3 , the first sub-branch 211 includes a first switching device Q1, a fourth switching device Q4, and a sixth switching device Q6. The first end of the first switching device Q1 is electrically connected to the input end of the charge pump circuit (this input end is connected to the power supply BAT), and the second end of the first switching device Q1 is electrically connected to the first end of the four-switching device Q4; the second end of the fourth switching device Q4 is electrically connected to the first end of the sixth switching device Q6, and the second end of the sixth switching device Q6 is electrically connected to the fourth sub-branch 222;

[0072] Continue to refer to Figure 3, the second sub-branch 212 includes a first capacitor C1, a third capacitor C3, a seventh switching device Q7, an eighth switching device Q8, an eleventh switching device Q11, a twelfth switching device Q12, and a sixteenth switching device Q16. Among them, the first end of the seventh switching device Q7 is electrically connected to the third capacitor C3, the twelfth switch Q12, and the third sub-branch 221 respectively, and the second end of the seventh switching device Q7 is electrically connected to the second end of the first capacitor C1 and the first end of the eighth switching device Q8 respectively; the first end of the first capacitor is electrically connected to the second end of the first switching device Q1 in the first sub-branch 211; the second end of the eighth switching device Q8 is grounded. The second end of the third capacitor C3 is electrically connected to the second end of the eleventh switching device Q11 and the first end of the sixteenth switching device Q16 respectively, and the second end of the sixteenth switching device Q16 is grounded. The second end of the twelfth switching device Q12 is electrically connected to the output terminal (VOUTA or VOUTB) of the charge pump circuit and the first end of the eleventh switching device Q11 respectively.

[0073] Continue to refer to Figure 3 , the third sub-branch 221 includes a second switching device Q2, a third switching device Q3, and a fifth switching device Q5; the first end of the second switching device Q2 is electrically connected to the input terminal of the charge pump circuit, and the second end of the second switching device Q2 is electrically connected to the first end of the third switching device Q3; the second end of the third switching device Q3 is electrically connected to the first end of the fifth switching device Q5, and the second end of the fifth switching device Q5 is electrically connected to the second sub-branch 212;

[0074] Continue to refer to Figure 3 , the fourth sub-branch 222 includes a second capacitor C2, a fourth capacitor C4, a ninth switching device Q9, a tenth switching device Q10, a thirteenth switching device Q13, a fourteenth switching device Q14, and a fifteenth switching device Q15. Among them, the first end of the tenth switching device Q10 is electrically connected to the first end of the fourth capacitor C4, the first end of the thirteenth switching device Q13, and the second end of the sixth switching device Q6 in the first sub-branch respectively; the second end of the tenth switching device Q10 is electrically connected to the first end of the ninth switching device Q9 and the second end of the second capacitor C2 respectively; the first end of the second capacitor C2 is electrically connected to the second end of the second switching device Q2; the second end of the ninth switching device Q9 is grounded. The second end of the thirteenth switching device Q13 is electrically connected to the output terminal VOUTB of the charge pump circuit and the first end of the fourteenth switching device Q14 respectively. The second end of the fourteenth switching device Q14 is electrically connected to the second end of the fourth capacitor C4 and the first end of the fifteenth switching device Q15 respectively. The second end of the fifteenth switching device Q15 is grounded.

[0075] Continue to refer to Figure 3, the first transfer control sub-branch 231 includes a first inductor L1. During the dead time, in one sub-phase of the first sub-phase and the second sub-phase, the first end of the first inductor L1 is electrically connected to the second end of the first switching device Q1, and the second end of the first inductor L1 is grounded; during the other sub-phase of the dead time, the first end of the first inductor L1 is grounded, and the second end of the first inductor L1 is electrically connected to the second end of the second switching device Q2.

[0076] It should be further noted that the inductance value of the first inductor L1 is less than the target inductance value. The above target inductance value refers to the inductance value that matches the parasitic capacitance of the switching devices in the first charge pump branch and / or the second charge pump branch at the switching frequency of the two charge pump branches in the charge pump circuit. In this way, when the inductance value of the first inductor L1 is small, resonance can be avoided and the dead time can be prevented from being extended. Or, charge transfer can be completed without affecting the duration of the dead time of the two charge pump branches, ensuring the normal operation of the charge pump circuit.

[0077] In one embodiment, referring to Figure 4 , the charge pump circuit further includes a fifth capacitor C5. The first end of the fifth capacitor C5 is electrically connected to the second end of the fourth switching device Q4 and the second end of the third switching device Q3 respectively, and the second end of the fifth capacitor C5 is grounded. At this time, the first end of the fifth capacitor C5 can be used as the second output terminal, and its output voltage is twice the output voltage of the first output terminal VOUT.

[0078] In one embodiment, continue to refer to Figure 4 , the charge pump circuit further includes a sixth capacitor C6, a seventeenth switching device Q17, and an eighteenth switching device Q18. The first end of the seventeenth switching device Q17 is connected to the second end of the eleventh switching device Q11. The second end of the seventeenth switching device Q17 is electrically connected to the first end of the sixth capacitor C6 and the first end of the eighteenth switching device Q18 respectively. The second end of the eighteenth switching device Q18 is electrically connected to the first end of the fifteenth switching device Q15. The second end of the sixth capacitor C6 is grounded. In this way, the first end of the sixth capacitor C6 can be used as the third output terminal, and outputs the same voltage as the first output terminal VOUT.

[0079] In one embodiment, referring to Figure 5, the first transfer control sub-branch 231 includes a first transfer control switch Q20 and a second transfer control switch Q21; the first end of the first transfer control switch Q20 is electrically connected to the second end of the first switching device Q1, and the second end of the first transfer control switch Q20 is electrically connected to the first end of the first inductor L1; the second end of the first inductor L1 is electrically connected to the first end of the second transfer control switch Q21, and the second end of the second transfer control switch Q21 is grounded; the control ends of the first transfer control switch Q20 and the second transfer control switch Q21 are used to receive control signals; the first transfer control switch Q20 is used to switch to the conducting state when an effective control signal is received during the dead time of the first operating mode, so as to electrically connect the first end of the first inductor L1 to the second end of the first switching device Q1; the second transfer control switch Q21 is used to switch to the conducting state when an effective control signal is received during the dead time, so as to ground the second end of the first inductor L1.

[0080] In one embodiment, continue to refer to Figure 5 , the first transfer control sub-branch 231 further includes a third transfer control switch Q22 and a fourth transfer control switch Q23; the first end of the third transfer control switch Q22 is electrically connected to the second end of the first inductor L1, and the second end of the third transfer control switch Q22 is electrically connected to the second end of the second switching device Q2; the first end of the fourth transfer control switch Q23 is electrically connected to the first end of the first inductor L1, and the second end of the fourth transfer control switch Q23 is grounded; the third transfer control switch Q22 is used to switch to the conducting state when an effective control signal is received during the dead time, so as to electrically connect the second end of the first inductor L1 to the second end of the second switching device Q2; the fourth transfer control switch Q23 is used to switch to the conducting state when an effective control signal is received during the dead time of the first operating mode, so as to ground the first end of the first inductor L1.

[0081] In one embodiment, refer to Figure 6 , on the basis that the first transfer control sub-branch 231 includes a first transfer control switch Q20 and a second transfer control switch Q21, it further includes a first diode D1 and a second diode D2; the cathode of the first diode D1 is electrically connected to the first end of the first inductor L1, and the anode of the first diode D1 is grounded; the anode of the second diode D2 is electrically connected to the second charge pump branch (specifically, the second end of the second switching device Q2), and the cathode of the second diode D2 is electrically connected to the second end of the first inductor L1.

[0082] In one embodiment, refer to Figure 7, the first transfer control sub-branch 231 includes a fifth transfer control switch Q24 and a sixth transfer control switch Q25; the first end of the fifth transfer control switch Q24 is electrically connected to the first end of the first inductor L1, and the second end of the fifth transfer control switch Q24 is grounded; the first end of the sixth transfer control switch Q25 is electrically connected to the second end of the first inductor L1, and the second end of the sixth transfer control switch Q25 is electrically connected to the second end of the second switching device Q2; the fifth transfer control switch Q24 is used to switch to the on state when receiving an effective control signal during the dead time, so as to ground the first end of the first inductor L1; the sixth transfer control switch Q25 is used to switch to the on state when receiving an effective control signal during the dead time, so as to electrically connect the second end of the first inductor L1 to the second end of the second switching device Q2.

[0083] In one embodiment, continue to refer to Figure 7 , on the basis that the first transfer control sub-branch 231 includes a fifth transfer control switch Q24 and a sixth transfer control switch Q25, it further includes a third diode D3 and a fourth diode D4; the cathode of the third diode D3 is electrically connected to the second end of the first inductor L1, and the anode of the third diode D3 is grounded; the anode of the fourth diode D4 is electrically connected to the first switching device Q1, and the cathode of the fourth diode D4 is electrically connected to the first end of the first inductor L1.

[0084] It should be noted that at least one of the first transfer control switch, the second transfer control switch, the third transfer control switch, the fourth transfer control switch, the fifth transfer control switch and the sixth transfer control switch is implemented by a field effect transistor, and can be integrated with the switching devices in each sub-branch of the charge pump circuit into the same chip or circuit board, and can also be made by the same process, which is beneficial to reducing the volume and cost of the charge pump circuit.

[0085] In one embodiment, refer to Figure 8 , the charge transfer control branch 23 further includes a second transfer control sub-branch 232. The second transfer control sub-branch 232 is respectively electrically connected to the second sub-branch 212 and the fourth sub-branch 222. The second transfer control sub-branch 232 is used to transfer a part of the charge stored in the parasitic capacitance of the second target switch to the parasitic capacitance of the first target switch during the dead time of the second working mode.

[0086] It is understandable that the first transfer control sub-branch 231 and the second transfer control sub-branch 232 are connected to the first charge pump branch and the second charge pump branch in the charge pump circuit at different positions. Among them, the voltage value at the connection position of the first transfer control sub-branch 231 is higher than that at the connection position of the second transfer control sub-branch 232, and it has a stronger ability to reduce losses. Those skilled in the art can set the number and connection positions of the transfer control sub-branches according to the specific scenario in combination with the working mode of the charge pump to achieve the purpose of transferring the charge of the parasitic capacitance under different working modes.

[0087] In one embodiment, the second transfer control sub-branch 232 can be implemented using the same circuit structure as the first transfer control sub-branch 231.

[0088] In one example, taking Figure 5 the first transfer control sub-branch 231 shown as an example, the first transfer control sub-branch 231 includes 4 transfer switch devices (Q20, Q21, Q22, and Q23) and 1 inductor (L1) for implementation; see Figure 9 , the second transfer control sub-branch 232 can be implemented using 4 switch devices (Q20’, Q21’, Q22’, and Q23’) and 1 inductor (L2).

[0089] In another example, taking Figure 6 the first transfer control sub-branch 231 shown as an example, the first transfer control sub-branch 231 includes 2 transfer switch devices (Q20, Q21), 2 diodes (D1, D2), and 1 inductor (L1); see Figure 10 , the second transfer control sub-branch 232 can be implemented using 2 transfer switch devices (Q20’, Q21’), 2 diodes (D1’, D2’), and 1 inductor (L2).

[0090] In yet another example, taking Figure 7 the first transfer control sub-branch 231 shown as an example, the first transfer control sub-branch 231 includes 2 transfer switch devices (Q24, Q25), 2 diodes (D3, D4), and 1 inductor (L1); see Figure 11 , the second transfer control sub-branch 232 can be implemented using 2 transfer switch devices (Q24’, Q25’), 2 diodes (D3’, D4’), and 1 inductor (L2).

[0091] In yet another example, the second transfer control sub-branch 232 can be implemented by sharing some devices with the first transfer control sub-branch 231. See Figure 12 ,

[0092] See Figure 12, the second transfer control sub-branch 232 includes a seventh transfer control switch Q27; the first end of the seventh transfer control switch Q27 is electrically connected to the first sub-branch 211 and the fourth sub-branch 222 respectively, the second end of the seventh transfer control switch Q27 is electrically connected to the first end of the first inductor L1, and the control end of the seventh transfer control switch Q27 is used to receive a control signal; the seventh transfer control switch Q27 is used to switch to the conducting state when an effective control signal is received during the dead time of the second operating mode, so as to electrically connect the first end of the first inductor L1 to the first sub-branch 211 and the fourth sub-branch 222 respectively; and the second transfer control switch of the first conversion control sub-branch switches to the conducting state to ground the first end of the first inductor.

[0093] Continue to refer to Figure 12 , the second transfer control sub-branch 232 includes an eighth transfer control switch Q28;

[0094] The first end of the eighth transfer control switch Q28 is electrically connected to the second sub-branch 212 and the third sub-branch 221 respectively, the second end of the eighth transfer control switch Q28 is electrically connected to the second end of the first inductor L1, and the control end of the eighth transfer control switch Q28 is used to receive a control signal; the eighth transfer control switch Q28 is used to switch to the conducting state when an effective control signal is received during the dead time of the second operating mode, so as to electrically connect the second end of the first inductor L1 to the second sub-branch 212 and the third sub-branch 221 respectively; and the fourth transfer control switch of the first conversion control sub-branch switches to the conducting state to ground the first end of the first inductor L1.

[0095] In this embodiment, in combination with Figure 12 the charge pump circuit shown describes the charging process and the charge transfer process. It can be understood that when the charging interface 12 of the electronic device is electrically connected to an external charging device (i.e., the power supply BAT), the processor 11 can control the first charge pump branch 21 or the second charge pump branch 22 of the charge pump circuit 13 to charge the battery 14.

[0096] First operating mode, the processor can control the charge pump circuit to switch to the first operating mode, that is, the 4:1 charging mode. Taking the processor controlling the first charge pump branch 21 as an example, the charging process includes:

[0097] The first charging stage: The processor 11 controls the first switching device Q1, the third switching device Q3, the fifth switching device Q5, the seventh switching device Q7, the ninth switching device Q9, the eleventh switching device Q11, the thirteenth switching device Q13, the fifteenth switching device Q15, and the seventeenth switching device Q17 to switch to the conducting state, controls the second switching device Q2, the fourth switching device Q4, the sixth switching device Q6, the eighth switching device Q8, the tenth switching device Q10, the twelfth switching device Q12, the fourteenth switching device Q14, the sixteenth switching device Q16, and the eighteenth switching device Q18 to switch to the off state, and the first transfer control switch Q20, the second transfer control switch Q21, the third transfer control switch Q22, the fourth transfer control switch Q23, the seventh transfer control switch Q27, and the eighth transfer control switch Q28 to switch to the off state. The equivalent circuit is as Figure 13 shown.

[0098] Among them, the first target switches include the first switching device Q1, the third switching device Q3, the fifth switching device Q5, the seventh switching device Q7, and the ninth switching device Q9; the second target switches include the second switching device Q2, the fourth switching device Q4, the sixth switching device Q6, the eighth switching device Q8, and the tenth switching device Q10.

[0099] It should be noted that Figure 13 only the parasitic capacitances of the switching devices Q1 to Q10 participating in charge transfer are exemplified, and the parasitic capacitances of other switching devices are not exemplified. Assuming the power supply voltage is 20V, the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, and the sixth capacitor C6 are all equal.

[0100] See Figure 13 , the current paths include:

[0101] Path 1

[0102] GND -> Q9 -> C2 -> Q3 -> VO1 -> C5 -> GND;

[0103] Path 2

[0104] BAT -> Q1 -> C1 -> Q7 -> Q5 -> C5 -> GND;

[0105] Path 3

[0106] BAT -> Q1 -> C1 -> Q7 -> C3 -> Q11 -> VOUT;

[0107] Path 4

[0108] BAT -> Q1 -> C1 -> Q7 -> C3 -> Q17 -> VO2 -> C6 -> GND.

[0109] During the battery charging process, the second switching device Q2, the fourth switching device Q4, the sixth switching device Q6, the eighth switching device Q8, and the tenth switching device Q10 are charged, and the voltages after charging are 10V, 10V, 10V, 5V, and 5V in sequence.

[0110] Dead time

[0111] In one example, the dead time includes a first sub-stage and a second sub-stage, and the first sub-stage precedes the second sub-stage. Among them, the first inductor L1 is charged during the first sub-stage and discharged during the second sub-stage.

[0112] First sub-stage: The processor controls the first transfer control switch Q20 and the second transfer control switch Q21 to conduct, see Figure 14 . At this time, the parasitic capacitances of the fourth switching device Q4, the sixth switching device Q6, and the eighth switching device Q8 are discharged, and the voltages become 0V; the first inductor L1 is charged, and the voltage rises to 10V. Correspondingly, the parasitic capacitances of the first switching device Q1 and the seventh switching device Q7 are charged, and the voltages rise to 10V and 5V respectively.

[0113] Second sub-stage: The processor controls the first transfer control switch Q20 and the second transfer control switch Q21 to switch to the off state, and other switching devices maintain the states in the first sub-stage unchanged. The equivalent circuit is as shown in Figure 9 . See Figure 15 . At this time, the parasitic capacitances of the first inductor L1, the second switching device Q2, and the tenth switching device Q10 are discharged, and the voltages become 0V; the parasitic capacitances of the third switching device Q3, the fifth switching device Q5, and the ninth switching device Q9 are charged, and the voltages rise to 10V, 10V, and 5V respectively.

[0114] Second charging stage: The processor 11 controls the first switching device Q1, the third switching device Q3, the fifth switching device Q5, the seventh switching device Q7, the ninth switching device Q9, the eleventh switching device Q11, the thirteenth switching device Q13, the fifteenth switching device Q15, and the seventeenth switching device Q17 to switch to the off state respectively, controls the second switching device Q2, the fourth switching device Q4, the sixth switching device Q6, the eighth switching device Q8, the tenth switching device Q10, the twelfth switching device Q12, the fourteenth switching device Q14, the sixteenth switching device Q16, and the eighteenth switching device Q18 to switch to the on state respectively, and the first transfer control switch Q20 and the second transfer control switch Q21 switch to the off state. The equivalent circuit is as shown in Figure 13 . See Figure 13 . At this time, the switching devices with darker colors are conducting and the switching devices with darker colors are off.

[0115] It should be noted that the first charge pump branch 21 and the second charge pump branch 22 are symmetric structures. Therefore, the charging and discharging of the parasitic capacitances of the switching devices at symmetric positions are the same as those in the previous charging stage. The difference is that considering that the charge transfer control branch includes the first diode and the second diode, no charge transfer occurs during the control period of the second charging stage.

[0116] In this embodiment, by transferring part of the charge of the parasitic capacitance of the first switching device to the second switching device, when the second switching device is used as the first switching device in the next control period, it does not need to be charged due to the charge stored in the parasitic capacitance, achieving the effect of reducing or eliminating switching losses.

[0117] Second working mode: The processor can control the charge pump circuit to switch to the second working mode, that is, the 2:1 charging mode. At this time, in the second working mode, the first switching device Q1, the second switching device Q2, the third switching device Q3, and the fourth switching device Q4 remain in the conducting state, and the seventh switching device Q7, the eighth switching device Q8, the ninth switching device Q9, the tenth switching device Q10, the seventeenth switching device Q17, and the eighteenth switching device Q18 remain in the off state. The sixth switching device Q6, the twelfth switching device Q12, the fourteenth switching device Q14, and the sixteenth switching device Q16 serve as the first charge pump branch 21, and the fifth switching device Q5, the thirteenth switching device Q13, the eleventh switching device Q11, and the fifteenth switching device Q15 serve as the second charge pump branch 22. Taking the processor's control of the first charge pump branch 21 as an example, the charging process includes:

[0118] The first charging stage

[0119] The processor controls the sixth switching device Q6, the twelfth switching device Q12, the fourteenth switching device Q14, and the sixteenth switching device Q16 to switch to the conducting state, and the fifth switching device Q5, the thirteenth switching device Q13, the eleventh switching device Q11, and the fifteenth switching device Q15 to switch to the off state. At this time, the parasitic capacitances of the thirteenth switching device Q13 and the fifteenth switching device Q15 are charged to 5V, as Figure 16 shown.

[0120] The first sub-stage of the dead time: The processor controls the first transfer control switch Q20 and the seventh transfer control switch Q27 to conduct, see Figure 16 . At this time, the parasitic capacitances of the thirteenth switching device Q13 and the fifteenth switching device Q15 discharge respectively, and the voltage becomes 0V; the first inductor L1 is charged, and the voltage rises to 5V.

[0121] Second sub - stage of the dead - time: The processor controls the first transfer control switch Q20 and the second transfer control switch Q21 to switch to the off state, and other switching devices maintain the states in the first sub - stage unchanged. The equivalent circuit is as Figure 17 shown. Refer to Figure 17 , at this time, the parasitic capacitances of the first inductor L1, the thirteenth switching device Q13, and the fifteenth switching device Q15 are discharged respectively, and the voltages become 0V; the parasitic capacitances of the twelfth switching device Q12 and the sixteenth switching device Q16 are charged respectively, and the voltages rise to 5V.

[0122] The second charging stage

[0123] The processor controls the sixth switching device Q6, the twelfth switching device Q12, the fourteenth switching device Q14, and the sixteenth switching device Q16 to switch to the off state, and the fifth switching device Q5, the thirteenth switching device Q13, the eleventh switching device Q11, and the fifteenth switching device Q15 to switch to the on state. At this time, the parasitic capacitances of the twelfth switching device Q12 and the sixteenth switching device Q16 are charged to 5V.

[0124] The above process describes the charge transfer scheme during the dead - time after the charging process of the first charge - pump branch 21. The charge transfer scheme during the dead - time of the charging process of the second charge - pump branch 22 is similar to that of the first charge - pump branch 21, and will not be elaborated here. In this embodiment, part of the charge of the parasitic capacitance of the first switching device can be transferred to the second switching device in the second working mode. When the second switching device is used as the first switching device in the next control cycle, it does not need to be charged due to the charge stored in the parasitic capacitance, achieving the effect of reducing or eliminating switching losses. Moreover, this embodiment can take into account the charging efficiency while achieving high - power charging, and shorten the charging time.

[0125] It should be noted that the charge transfer scheme in the second working mode is similar to that in the first working mode. Specifically, it can be analyzed by analogy with the scheme of the first working mode, and the charge transfer scheme in the second working mode can also be understood.

[0126] In some possible embodiments, a chip is further provided, including the charge - pump circuit as Figures 1 to 17 shown in the above example.

[0127] Figure 18 is a block diagram of an electronic device shown according to an exemplary embodiment. For example, the electronic device 1800 can be a smart phone, a computer, a digital broadcast terminal, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0128] Refer to Figure 18, the electronic device 1800 may include one or more of the following components: a processing component 1802, a memory 1804, a power component 1806, a multimedia component 1808, an audio component 1810, an input / output (I / O) interface 1812, a sensor component 1814, a communication component 1816, and an image acquisition component 1818.

[0129] The processing component 1802 generally controls the overall operation of the electronic device 1800, such as operations associated with display, telephone calls, data communication, camera operations, and recording operations. The processing component 1802 may include one or more processors 1820 to execute computer programs. In addition, the processing component 1802 may include one or more modules to facilitate the interaction between the processing component 1802 and other components. For example, the processing component 1802 may include a multimedia module to facilitate the interaction between the multimedia component 1808 and the processing component 1802. In one example, the processor 1820 may control a charge pump circuit to charge the battery.

[0130] The memory 1804 is configured to store various types of data to support the operation of the electronic device 1800. Examples of such data include computer programs for any application or method operating on the electronic device 1800, contact data, phone book data, messages, pictures, videos, etc. The memory 1804 may be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, a magnetic disk, or an optical disk.

[0131] The power component 1806 provides power to various components of the electronic device 1800. The power component 1806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 1800. The power component 1806 may include the above-mentioned charge pump circuit or chip to supply power to the battery.

[0132] The multimedia component 1808 includes a screen that provides an output interface between the electronic device 1800 and a target object.

[0133] In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input information from the target object. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can not only sense the boundaries of touch or swipe actions but also detect the duration and pressure associated with the touch or swipe operations.

[0134] The audio component 1810 is configured to output and / or input audio file information. For example, the audio component 1810 includes a microphone (MIC), which is configured to receive external audio file information when the electronic device 1800 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio file information can be further stored in the memory 1804 or transmitted via the communication component 1816. In some embodiments, the audio component 1810 further includes a speaker for outputting audio file information.

[0135] The I / O interface 1812 provides an interface between the processing component 1802 and a peripheral interface module, which may be a keyboard, a click wheel, buttons, etc.

[0136] The sensor component 1814 includes one or more sensors for providing an assessment of various aspects of the status of the electronic device 1800. For example, the sensor component 1814 can detect the on / off state of the electronic device 1800, the relative positioning of components, such as the display screen and keypad of the electronic device 1800. The sensor component 1814 can also detect a change in the position of the electronic device 1800 or a component, the presence or absence of contact between a target object and the electronic device 1800, the orientation or acceleration / deceleration of the electronic device 1800, and the temperature change of the electronic device 1800. In this example, the sensor component 1814 can include a magnetic sensor, a gyroscope, and a magnetic field sensor, and can also include an inertial sensor, an image sensor, etc. The magnetic field sensor includes at least one of the following: a Hall sensor, a thin-film magnetoresistive sensor, and a magnetic fluid acceleration sensor.

[0137] The communication component 1816 is configured to facilitate communication between the electronic device 1800 and other devices in a wired or wireless manner. The electronic device 1800 can access a wireless network based on communication standards, such as WiFi, 2G, 3G, 4G, 5G, or a combination thereof. In an exemplary embodiment, the communication component 1816 receives broadcast information or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 1816 further includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0138] In an exemplary embodiment, the electronic device 1800 may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components.

[0139] In an exemplary embodiment, a chip is further provided, which includes a processor and an interface for reading a computer program through the interface to implement the method as described above. Wherein, the chip may be a conventional CPU (central processing unit) chip, GPU (graphics processing unit) chip, etc., or may be an acceleration chip dedicated to artificial intelligence technology, such as an AI (Artificial Intelligence) accelerator, etc.

[0140] Those skilled in the art will readily conceive of other embodiments of the present disclosure upon considering the specification and practicing the disclosure herein. The present disclosure is intended to cover any variations, uses, or adaptations of the disclosure, which follow the general principles of the disclosure and include common general knowledge or conventional technical means in the technical field not disclosed by the present disclosure. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of the present disclosure are pointed out by the following claims.

[0141] It should be understood that the present disclosure is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only limited by the appended claims.

Claims

1. A charge pump circuit, characterized in that, Comprising: A first charge pump branch, a second charge pump branch, and a charge transfer control branch; The charge transfer control branch is electrically connected to the first charge pump branch and the second charge pump branch respectively; The charge transfer control branch is configured to transfer a part of the charge stored in the parasitic capacitance of the second target switch into the parasitic capacitance of the first target switch during the dead time in the first operating mode or the second operating mode; The dead time refers to the period during which the switching devices in the first charge pump branch and the second charge pump branch are both in the off state. The first target switch refers to the switching device that was in the on state in the previous control cycle, and the second target switch refers to the switching device that was in the off state in the previous control cycle.

2. The charge pump circuit according to claim 1, wherein The first charge pump branch includes a first sub-branch and a second sub-branch that are electrically connected; the second charge pump branch includes a third sub-branch and a fourth sub-branch that are electrically connected; the first sub-branch and the fourth sub-branch are electrically connected, and the second sub-branch is electrically connected to the third sub-branch; the charge transfer control branch includes a first transfer control sub-branch; The first transfer control sub-branch is electrically connected to the first sub-branch and the third sub-branch respectively, and is configured to transfer a part of the charge stored in the parasitic capacitance of the second target switch into the parasitic capacitance of the first target switch during the dead time of the first operating mode.

3. The charge pump circuit according to claim 2, wherein The first sub-branch includes a first switching device, a fourth switching device, and a sixth switching device; the first transfer control sub-branch includes a first inductor; The first end of the first switching device is electrically connected to the input end of the charge pump circuit, and the second end of the first switching device is electrically connected to the first end of the fourth switching device; the second end of the fourth switching device is electrically connected to the first end of the sixth switching device, and the second end of the sixth switching device is electrically connected to the fourth sub-branch; The third sub-branch includes a second switching device, a third switching device, and a fifth switching device; the first end of the second switching device is electrically connected to the input end of the charge pump circuit, and the second end of the second switching device is electrically connected to the first end of the third switching device; the second end of the third switching device is electrically connected to the first end of the fifth switching device, and the second end of the fifth switching device is electrically connected to the second sub-branch; During one sub-stage of the first sub-stage and the second sub-stage of the dead time, the first end of the first inductor is electrically connected to the second end of the first switching device, and the second end of the first inductor is grounded; during the other sub-stage of the dead time, the first end of the first inductor is grounded, and the second end of the first inductor is electrically connected to the second end of the second switching device.

4. The charge pump circuit according to claim 3, wherein The first transfer control sub-branch includes a first transfer control switch and a second transfer control switch; the first end of the first transfer control switch is electrically connected to the second end of the first switching device, and the second end of the first transfer control switch is electrically connected to the first end of the first inductor; the second end of the first inductor is electrically connected to the first end of the second transfer control switch, and the second end of the second transfer control switch is grounded; the control ends of the first transfer control switch and the second transfer control switch are used to receive control signals; The first transfer control switch is used to switch to the conducting state when an effective control signal is received during the dead time of the first operating mode, so as to electrically connect the first end of the first inductor to the second end of the first switching device; The second transfer control switch is used to switch to the conducting state when an effective control signal is received during the dead time of the first operating mode, so as to ground the second end of the first inductor.

5. The charge pump circuit according to claim 4, wherein The first transfer control sub-branch further includes a third transfer control switch and a fourth transfer control switch; the first end of the third transfer control switch is electrically connected to the second end of the first inductor, and the second end of the third transfer control switch is electrically connected to the second end of the second switching device; the first end of the fourth transfer control switch is electrically connected to the first end of the first inductor, and the second end of the fourth transfer control switch is grounded; The third transfer control switch is used to switch to the conducting state when an effective control signal is received during the dead time of the first operating mode, so as to electrically connect the second end of the first inductor to the second end of the second switching device; The fourth transfer control switch is used to switch to the conducting state when an effective control signal is received during the dead time of the first operating mode, so as to ground the first end of the first inductor.

6. The charge pump circuit according to any one of claims 2 to 5, characterized in that, The charge transfer control branch further includes a second transfer control sub-branch; the second transfer control sub-branch is electrically connected to the second sub-branch and the fourth sub-branch respectively; The second transfer control sub-branch is used to transfer a part of the charge stored in the parasitic capacitance of the second target switch to the parasitic capacitance of the first target switch during the dead time of the second operating mode.

7. The charge pump circuit according to claim 6, wherein The second transfer control sub-branch includes a seventh transfer control switch; the first end of the seventh transfer control switch is electrically connected to the first sub-branch and the fourth sub-branch respectively, the second end of the seventh transfer control switch is electrically connected to the first end of the first inductor, and the control end of the seventh transfer control switch is used to receive a control signal; The seventh transfer control switch is used to switch to the conducting state when an effective control signal is received during the dead time of the second operating mode, so as to electrically connect the first end of the first inductor to the first sub-branch and the fourth sub-branch respectively; and the second transfer control switch of the first conversion control sub-branch switches to the conducting state to ground the first end of the first inductor.

8. The charge pump circuit according to claim 6, wherein The second transfer control sub-branch includes an eighth transfer control switch; The first end of the eighth transfer control switch is electrically connected to the second sub-branch and the third sub-branch respectively. The second end of the eighth transfer control switch is electrically connected to the second end of the first inductor. The control end of the eighth transfer control switch is used to receive a control signal; The eighth transfer control switch is used to switch to the conducting state when an effective control signal is received during the dead time of the second operating mode, so as to electrically connect the second end of the first inductor to the second sub-branch and the third sub-branch respectively; and the fourth transfer control switch of the first conversion control sub-branch switches to the conducting state to ground the first end of the first inductor.

9. The charge pump circuit according to claim 3, wherein The first inductance value of the first inductor is less than the target inductance value. The target inductance value refers to the inductance value that matches the parasitic capacitance of the switching devices in the first charge pump branch and / or the second charge pump branch at the switching frequency of the two charge pump branches in the charge pump circuit.

10. A chip, characterized in that, It includes the charge pump circuit according to any one of claims 1 to 9.

11. An electronic device, characterized in that, It includes: A processor, a battery, a charging interface, and the charge pump circuit according to any one of claims 1 to 9; the charge pump circuit is electrically connected to the battery and the charging interface respectively; The processor is electrically connected to the charge pump circuit; The processor is used to control the first target switch of the first charge pump branch and the second charge pump branch to switch to the conducting state and the second target switch to switch to the off state within one control period; The processor is used to switch the charge pump circuit to one of the first operating mode or the second operating mode, and control all the switching devices of the first charge pump branch and the second charge pump branch to switch to the off state during the dead time of the operating mode; The processor is further used to output an effective control signal to the charge transfer control branch of the charge pump circuit during the dead time of the operating mode; The charge transfer control branch is used to transfer a part of the charge stored in the parasitic capacitance of the second target switch in the previous control period to the parasitic capacitance of the first target switch when an effective control signal is received during the dead time of the operating mode; and / or A processor, a battery, a charging interface, and the chip according to claim 10; the chip is electrically connected to the battery, the charging interface, and the processor respectively; The processor is used to control the first target switch of the charge pump circuit in the chip to switch to the conducting state and the second target switch to switch to the off state within one control period; The processor is used to switch the charge pump circuit to one of the first operating mode or the second operating mode, and control all the switching devices of the first charge pump branch and the second charge pump branch to switch to the off state during the dead time of the operating mode; The processor is further used to output an effective control signal to the charge transfer control branch of the charge pump circuit during the dead time of the operating mode; The charge transfer control branch is used to transfer a part of the charge stored in the parasitic capacitance of the second target switch in the previous control period to the parasitic capacitance of the first target switch when an effective control signal is received during the dead time of the working mode.

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