Low-noise phase discriminator circuit suitable for high-speed sampling clock

Abstract

The invention relates to a low-noise phase discriminator circuit suitable for a high-speed sampling clock. The low-noise phase discriminator circuit comprises a first D trigger, a second D trigger, a first time error amplifier, a second time error amplifier and a second NAND gate. According to the embodiment of the invention, the amplification of the input phase error is realized, the noise contribution of the phase frequency detector is reduced while the phase frequency detector can realize a phase difference gain amplification function, the in-band noise of the phase-locked loop is optimized, and the overall phase noise performance of the phase-locked loop can be better improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of sampling clock systems, and particularly relates to a low-noise phase detector circuit applicable to high-speed sampling clocks. Background Art

[0002] With the rapid development of semiconductor technology and communication technology, modern data acquisition systems have put forward more stringent requirements for the performance of high-speed analog-to-digital converters (ADCs). In a high-speed sampling system, the clock, as the time reference, has a direct impact on the sampling system. The noise of the sampling time will affect the signal-to-noise ratio (SNR) of the high-speed sampling system. To ensure the performance of sampling, a stable and low-noise clock is essential. Therefore, a high-performance phase-locked loop is required to generate a stable and accurate on-chip clock signal. The phase-frequency detector (PFD) is an important part of the phase-locked loop system, and its function is to compare the phase difference between the input reference signal and the feedback signal and convert the phase difference into the pulse width of the output signal. The pulse width output by the phase-frequency detector is used to control the charging and discharging time of the charge pump current.

[0003] For a charge pump phase-locked loop, its output phase noise is mainly determined by the charge pump noise and the noise of the voltage-controlled oscillator (VCO). Among them, the in-band noise is dominated by the charge pump noise, and the out-of-band noise is dominated by the voltage-controlled oscillator noise. How to reduce the noise contributions of both is the key to improving the overall output jitter performance of the phase-locked loop. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a low-noise phase detector circuit applicable to high-speed sampling clocks. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0005] An embodiment of the present invention provides a low-noise phase detector circuit applicable to high-speed sampling clocks, including:

[0006] A first D flip-flop for converting a reference signal into a first pulse signal;

[0007] A second D flip-flop for converting a feedback signal of a frequency divider into a second pulse signal;

[0008] A first NAND gate for extracting the phase difference between the first pulse signal and the second pulse signal to obtain a phase difference signal;

[0009] A first time error amplifier for performing resistive discharge at a first rate when the first pulse signal arrives and the phase difference signal is at a high level, and performing resistive discharge at a second rate when the first pulse signal arrives and the phase difference signal is at a low level to obtain a first output signal;

[0010] A second time error amplifier, which is used to perform resistive discharge at a first rate when the second pulse signal arrives and the phase difference signal is at a high level, and perform resistive discharge at a second rate when the second pulse arrives and the phase difference signal is at a low level, to obtain a second output signal;

[0011] Wherein, the first rate is greater than the second rate, and the phase difference between the first output signal and the second output signal is the amplified phase error.

[0012] In an embodiment of the present invention, a reference signal is input to the input terminal of the first D flip-flop, a power supply voltage signal is input to the D terminal, and the Q terminal is connected to the first input terminal of the first NAND gate and the first input terminal of the first time error amplifier;

[0013] A frequency divider feedback signal is input to the input terminal of the second D flip-flop, a power supply voltage signal is input to the D terminal, and the Q terminal is connected to the second input terminal of the first NAND gate and the first input terminal of the second time error amplifier;

[0014] The output terminal of the first NAND gate is connected to the second input terminal of the first time error amplifier and the second input terminal of the second time error amplifier;

[0015] The output terminal of the first time error amplifier outputs a first output signal, and the output terminal of the second time error amplifier outputs a second output signal.

[0016] In an embodiment of the present invention, a second NAND gate is further included, which is used to generate a reset signal to control the first D flip-flop, the second D flip-flop, the first time error amplifier, and the second time error amplifier to be reset when both the first output signal and the second output signal are at a high level.

[0017] In an embodiment of the present invention, the first input terminal of the second NAND gate is connected to the output terminal of the first time error amplifier; the second input terminal of the second NAND gate is connected to the output terminal of the second time error amplifier;

[0018] The output terminal of the second NAND gate is used to output the reset signal.

[0019] In an embodiment of the present invention, the following are further included: a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, and a sixth inverter, wherein,

[0020] The input terminal of the first inverter is connected to the output terminal of the first time error amplifier, and the output terminal is connected to the input terminal of the second inverter; the output terminal of the second inverter outputs an UP signal;

[0021] The input terminal of the third inverter is connected to the output terminal of the second time error amplifier, and the output terminal is connected to the input terminal of the fourth inverter; the output terminal of the fourth inverter outputs the DN signal;

[0022] The input terminal of the fifth inverter is connected to the output terminal of the second NAND gate, and the output terminal is connected to the input terminal of the sixth inverter; the output terminal of the sixth inverter is connected to the reset terminals of the first time error amplifier, the second time error amplifier, the first D flip-flop, and the second D flip-flop.

[0023] In an embodiment of the present invention, the phase difference between the UP signal and the DN signal is the amplified phase error.

[0024] In an embodiment of the present invention, the first time error amplifier and the second time error amplifier have the same structure.

[0025] In an embodiment of the present invention, both the first time error amplifier and the second time error amplifier include: a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a first resistor, a second resistor, a capacitor, a third NAND gate, and a seventh inverter, where,

[0026] The source electrodes of the first MOS transistor, the second MOS transistor, the first terminal of the capacitor, the source electrode of the fifth MOS transistor, the source electrode of the seventh MOS transistor, and the source electrode of the ninth MOS transistor are connected to the ground terminal;

[0027] The source electrodes of the third MOS transistor, the fourth MOS transistor, the sixth MOS transistor, and the eighth MOS transistor are connected to the power supply;

[0028] The gate of the first MOS transistor inputs a pulse signal, and the drain is connected to the first terminal of the first resistor;

[0029] The first input terminal of the third NAND gate inputs the phase difference signal, the second input terminal inputs the pulse signal, and the output terminal is connected to the input terminal of the seventh inverter;

[0030] The output terminal of the seventh inverter is connected to the gate of the second MOS transistor;

[0031] The drain of the second MOS transistor is connected to the first terminal of the second resistor;

[0032] The second terminal of the first resistor, the second terminal of the second resistor, the second terminal of the capacitor, the drain of the third MOS transistor, the gate of the fourth MOS transistor, and the gate of the fifth MOS transistor are connected;

[0033] The gate of the third MOS transistor serves as the reset terminal of the time error amplifier;

[0034] The drain of the fourth MOS transistor, the drain of the fifth MOS transistor, the gate of the sixth MOS transistor, and the gate of the seventh MOS transistor are connected; the drain of the sixth MOS transistor, the drain of the seventh MOS transistor, the gate of the eighth MOS transistor, and the gate of the ninth MOS transistor are connected;

[0035] The drain of the eighth MOS transistor and the drain of the ninth MOS transistor are connected and serve as the output terminal of the time error amplifier.

[0036] In an embodiment of the present invention, the theoretical amplification factor of the low-noise phase detector circuit is (1 + R1 / R2), where R1 is the resistance value of the first resistor and R2 is the resistance value of the second resistor.

[0037] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0038] The low-noise phase detector circuit of the present invention performs resistive discharges at different rates through the first time error amplifier and the second time error amplifier, realizing the amplification of the input phase error. While ensuring that the frequency discriminator and phase detector can achieve the function of phase difference gain amplification, it reduces the noise contribution of the frequency discriminator and phase detector itself, optimizes the in-band noise of the phase-locked loop, and can better improve the overall phase noise performance of the phase-locked loop. Description of the Drawings

[0039] Figure 1 It is a schematic structural diagram of a low-noise phase detector circuit applicable to a high-speed sampling clock provided by an embodiment of the present invention;

[0040] Figure 2 It is a schematic structural diagram of a time error amplifier provided by an embodiment of the present invention;

[0041] Figure 3 It is a schematic working timing diagram of a low-noise phase detector circuit applicable to a high-speed sampling clock provided by an embodiment of the present invention;

[0042] Figure 4 It is a comparison diagram of output noise obtained by simulating the RD-TAPFD and the traditional TAPFD structures of the embodiment of the present invention under the condition of using the same ideal charge pump. Detailed Embodiments

[0043] The present invention will be further described in detail below in conjunction with specific embodiments, but the embodiments of the present invention are not limited thereto.

[0044] Embodiment 1

[0045] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of a low-noise phase detector circuit suitable for a high-speed sampling clock provided by an embodiment of the present invention.

[0046] The low-noise phase detector is a resistor-discharge time-amplified frequency discriminator and phase detector RD-TAPFD, including: a first D flip-flop DFF1, a second D flip-flop DFF2, a first NAND gate NAND1, a first time error amplifier TA1, and a second time error amplifier TA2. Among them, the first D flip-flop DFF1 is used to convert a reference signal into a first pulse signal. The second D flip-flop DFF2 is used to convert a frequency divider feedback signal into a second pulse signal. The first NAND gate NAND1 is used to extract the phase difference between the first pulse signal and the second pulse signal to obtain a phase difference signal. The first time error amplifier TA1 is used to perform resistor discharge at a first rate when the first pulse signal arrives and the phase difference signal is at a high level, and perform resistor discharge at a second rate when the first pulse signal arrives and the phase difference signal is at a low level, to obtain a first output signal. The second time error amplifier TA2 is used to perform resistor discharge at a first rate when the second pulse signal arrives and the phase difference signal is at a high level, and perform resistor discharge at a second rate when the second pulse arrives and the phase difference signal is at a low level, to obtain a second output signal. Among them, the first rate is greater than the second rate, and the phase difference between the first output signal and the second output signal is the amplified phase error.

[0047] Specifically, the reference signal Ref is input to the input terminal of the first D flip-flop DFF1, the power supply voltage signal is input to the D terminal D1, and the Q terminal Q1 is connected to the first input terminal of the first NAND gate NAND1 and the first input terminal In1 of the first time error amplifier TA1; the frequency divider feedback signal Div is input to the input terminal of the second D flip-flop DFF2, the power supply voltage signal is input to the D terminal D2, and the Q terminal Q2 is connected to the second input terminal of the first NAND gate NAND1 and the first input terminal In2 of the second time error amplifier TA2; the output terminal of the first NAND gate NAND1 is connected to the second input terminal Sw1 of the first time error amplifier TA1 and the second input terminal Sw2 of the second time error amplifier TA2; the output terminal Out1 of the first time error amplifier TA1 outputs the first output signal, and the output terminal Out2 of the second time error amplifier TA2 outputs the second output signal.

[0048] In a specific embodiment, the low-noise phase detector circuit further includes a second NAND gate NAND2, which is used to generate a reset signal to control the reset of the first D flip-flop DFF1, the second D flip-flop DFF2, the first time error amplifier TA1, and the second time error amplifier TA2 when both the first output signal and the second output signal are at a high level.

[0049] Specifically, the first input terminal of the second NAND gate NAND2 is connected to the output terminal Out1 of the first time error amplifier TA1; the second input terminal of the second NAND gate NAND2 is connected to the output terminal Out2 of the second time error amplifier TA2; the output terminal of the second NAND gate NAND2 is used to output the reset signal.

[0050] In a specific embodiment, the low-noise phase detector circuit further includes: a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, and a sixth inverter INV6. Among them, the input terminal of the first inverter INV1 is connected to the output terminal Out1 of the first time error amplifier TA1, and the output terminal is connected to the input terminal of the second inverter INV2; the output terminal of the second inverter INV2 outputs the UP signal. The input terminal of the third inverter INV3 is connected to the output terminal Out2 of the second time error amplifier TA2, and the output terminal is connected to the input terminal of the fourth inverter INV4; the output terminal of the fourth inverter INV4 outputs the DN signal. The input terminal of the fifth inverter INV5 is connected to the output terminal of the second NAND gate NAND2, and the output terminal is connected to the input terminal of the sixth inverter INV6. The output terminal of the sixth inverter INV6 is connected to the reset terminal Set1 of the first time error amplifier TA1, the reset terminal Set2 of the second time error amplifier TA2, the reset terminal Set3 of the first D flip-flop DFF1, and the reset terminal Set4 of the second D flip-flop DFF2.

[0051] Specifically, the phase difference between the UP signal and the DN signal is the amplified phase error.

[0052] Please refer to Figure 2 , Figure 2 FIG. is a schematic structural diagram of a time error amplifier provided by an embodiment of the present invention. The first time error amplifier TA1 and the second time error amplifier TA2 have the same structure, and both include a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, a first resistor R1, a second resistor R2, a capacitor C1, a third NAND gate NAND3, and a seventh inverter INV7.

[0053] Specifically, the source electrodes of the first MOS transistor M1, the second MOS transistor M2, the first terminal of the capacitor C1, the source electrode of the fifth MOS transistor M5, the source electrode of the seventh MOS transistor M7, and the source electrode of the ninth MOS transistor M9 are connected to the ground terminal GND; the source electrodes of the third MOS transistor M3, the fourth MOS transistor M4, the sixth MOS transistor M6, and the eighth MOS transistor M8 are connected to the power supply VDD; the gate electrode of the first MOS transistor M1 inputs a pulse signal, and the drain electrode is connected to the first terminal of the first resistor R1; the first input terminal of the third NAND gate NAND3 inputs a phase difference signal, the second input terminal inputs a pulse signal, and the output terminal is connected to the input terminal of the seventh inverter INV7; the output terminal of the seventh inverter INV7 is connected to the gate electrode of the second MOS transistor M2; the drain electrode of the second MOS transistor M2 is connected to the first terminal of the second resistor R2; the second terminal of the first resistor R1, the second terminal of the second resistor R2, the second terminal of the capacitor C1, the drain electrode of the third MOS transistor M3, the gate electrode of the fourth MOS transistor M4, and the gate electrode of the fifth MOS transistor M5 are connected; the gate electrode of the third MOS transistor M3 serves as the reset terminal of the time error amplifier; the drain electrode of the fourth MOS transistor M4, the drain electrode of the fifth MOS transistor M5, the gate electrode of the sixth MOS transistor M6, and the gate electrode of the seventh MOS transistor M7 are connected; the drain electrode of the sixth MOS transistor M6, the drain electrode of the seventh MOS transistor M7, the gate electrode of the eighth MOS transistor M8, and the gate electrode of the ninth MOS transistor M9 are connected; the drain electrodes of the eighth MOS transistor M8 and the ninth MOS transistor M9 are connected and serve as the output terminal of the time error amplifier.

[0054] Please refer to Figure 3 , Figure 3 which is the working timing diagram of the low-noise phase detector circuit applicable to high-speed sampling clocks provided by the embodiments of the present invention.

[0055] Specifically, the reference signal Ref and the divider feedback signal Div are phase-detected by the first D flip-flop DFF1 and the second D flip-flop DFF2 respectively, and Ref and Div are converted into the first pulse signal and the second pulse signal with pulse widths. The first NAND gate NAND1 is used to extract the phase difference signal between the first pulse signal and the second pulse signal and serve as the input signal Sw of the time error amplifier to control the M2 switches inside TA1 and TA2. In a reference period, taking the case where the reference signal Ref is ahead as an example, when DFF1 outputs a high level and DFF2 outputs a low level, Sw outputs a high level. At this time, both the M1 and M2 switches inside TA1 are turned on, and the charge on the internal capacitor C1 of TA1 is discharged from VDD through the resistors R1 and R2. When DFF2 outputs a high level, the internal switch M1 of TA2 is turned on, and TA2 discharges through R1. At this time, the SW signal is at a low level, and the internal switch M2 of TA1 is turned off, and TA1 discharges only through R1. In the figure, Vx represents the voltage change of the internal node Vx of TA, where the solid line represents TA1 and the dashed line represents TA2. When the voltage Vx on the internal capacitor C1 of TA discharges to the threshold inversion voltage V REF , the output of TA is at a high level. When the outputs of both TA1 and TA2 are at a high level, the NAND gate NAND2 generates a Set signal to control the reset of the two D flip-flops and the two TAs. The internal threshold inversion voltage V REF of TA can be adjusted by changing the size ratio of the inverters M4 and M5. The larger the size ratio of M4 to M5, the lower V REF . The amplification factor of the RD-TAPFD is related to the resistance ratio, and its theoretical amplification factor is K TA = 1 + R1 / R2, and the actual amplification factor is approximately (1 + R1 / R2), where R1 is the resistance value of the first resistor and R2 is the resistance value of the second resistor.

[0056] Please refer to Figure 4 , Figure 4 , which is the comparison diagram of the output noise simulated by the RD-TAPFD and the traditional TAPFD structures of this embodiment of the present invention under the condition of using the same ideal charge pump. The simulation results show that at a 1MHZ frequency offset, the proposed RD-TAPFD has about 3dB lower noise than the traditional TAPFD structure.

[0057] The low-noise phase detector circuit of this embodiment performs resistive discharges at different rates through the first time error amplifier and the second time error amplifier, and amplifies the input phase error by K TAThe suppression ability of charge pump noise is improved by [multiple times]. Compared with the traditional TAPFD, in the RD-TAPFD proposed in this embodiment, the time error amplifier (TA) used inside changes the current source discharge to resistive discharge. While ensuring that the phase frequency detector can achieve the phase difference gain amplification function, the noise contribution of the phase frequency detector itself is reduced. It can better improve the overall phase noise performance of the phase-locked loop.

[0058] In this embodiment, the in-band noise suppression ability of the phase-locked loop clock system is improved by increasing the gain of the phase frequency detector. At the same time, by improving the structure, the noise contribution of this circuit itself is reduced to achieve a lower noise output clock, reducing the impact of the clock on the high-speed sampling system, and it can be applied to the high-speed sampling clock system.

[0059] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A low noise phase detector circuit suitable for high speed sampling clock, characterized in that: include: a first D flip-flop (DFF1), configured to convert a reference signal into a first pulse signal; a second D flip-flop (DFF2), configured to convert the frequency divider feedback signal into a second pulse signal; A first NAND gate (NAND1), used for extracting a phase difference between the first pulse signal and the second pulse signal to obtain a phase difference signal; a first time error amplifier (TA1), configured to perform resistive discharge at a first rate when the first pulse signal arrives and the phase difference signal is at a high level, and to perform resistive discharge at a second rate when the first pulse signal arrives and the phase difference signal is at a low level, so as to obtain a first output signal; a second time error amplifier (TA2), configured to perform resistive discharge at a first rate when the second pulse signal arrives and the phase difference signal is at a high level, and to perform resistive discharge at a second rate when the second pulse arrives and the phase difference signal is at a low level, so as to obtain a second output signal; The first rate is greater than the second rate, and the phase difference between the first output signal and the second output signal is the amplified phase error.

2. The low-noise phase detector circuit suitable for high-speed sampling clock according to claim 1, characterized in that: The reference signal (Ref) is input to the input terminal of the first D flip-flop (DFF1), the power supply voltage signal is input to the D terminal (D1), and the Q terminal (Q1) is connected to the first input terminal of the first NAND gate (NAND1) and the first input terminal (In1) of the first time error amplifier (TA1); The input terminal of the second D flip-flop (DFF2) inputs the divider feedback signal (Div), the D terminal (D2) inputs the power supply voltage signal, and the Q terminal (Q2) is connected to the second input terminal of the first NAND gate (NAND1) and the first input terminal (In2) of the second time error amplifier (TA2); The output end of the first NAND gate (NAND1) is connected to the second input end (Sw1) of the first time error amplifier (TA1) and the second input end (Sw2) of the second time error amplifier (TA2); The output terminal (Out1) of the first time error amplifier (TA1) outputs a first output signal, and the output terminal (Out2) of the second time error amplifier (TA2) outputs a second output signal.

3. The low-noise phase detector circuit suitable for high-speed sampling clock according to claim 1, characterized in that: It also includes a second NAND gate (NAND2) for generating a reset signal to control the first D flip-flop (DFF1), the second D flip-flop (DFF2), the first time error amplifier (TA1), and the second time error amplifier (TA2) to reset when the first output signal and the second output signal are both at a high level.

4. The low-noise phase detector circuit suitable for high-speed sampling clock according to claim 3, characterized in that: The first input end of the second NAND gate (NAND2) is connected to the output end of the first time error amplifier (TA1); the second input end of the second NAND gate (NAND2) is connected to the output end of the second time error amplifier (TA2); The output terminal of the second NAND gate (NAND2) is used to output the reset signal.

5. The low-noise phase detector circuit suitable for high-speed sampling clock according to claim 4, characterized in that: The invention also includes: a first inverter (INV1), a second inverter (INV2), a third inverter (INV3), a fourth inverter (INV4), a fifth inverter (INV5) and a sixth inverter (INV6), wherein: The input end of the first inverter (INV1) is connected to the output end (Out1) of the first time error amplifier (TA1), and the output end is connected to the input end of the second inverter (INV2); the output end of the second inverter (INV2) outputs an UP signal; The input end of the third inverter (INV3) is connected to the output end (Out2) of the second time error amplifier (TA2), and the output end is connected to the input end of the fourth inverter (INV4); the output end of the fourth inverter (INV4) outputs a DN signal; The input end of the fifth inverter (INV5) is connected to the output end of the second NAND gate (NAND2), and the output end is connected to the input end of the sixth inverter (INV6); the output end of the sixth inverter (INV6) is connected to the reset end (Set1) of the first time error amplifier (TA1), the reset end (Set2) of the second time error amplifier (TA2), the reset end (Set3) of the first D flip-flop (DFF1) and the reset end (Set4) of the second D flip-flop (DFF2).

6. The low-noise phase detector circuit suitable for high-speed sampling clock according to claim 5, characterized in that: The phase difference between the UP signal and the DN signal is the amplified phase error.

7. The low-noise phase detector circuit suitable for high-speed sampling clock according to claim 1, characterized in that: The first time error amplifier (TA1) and the second time error amplifier (TA2) have the same structure.

8. The low-noise phase detector circuit suitable for high-speed sampling clock according to claim 7, characterized in that: The first time error amplifier (TA1) and the second time error amplifier (TA2) both include: a first MOS tube (M1), a second MOS tube (M2), a third MOS tube (M3), a fourth MOS tube (M4), a fifth MOS tube (M5), a sixth MOS tube (M6), a seventh MOS tube (M7), an eighth MOS tube (M8), a ninth MOS tube (M9), a first resistor (R1), a second resistor (R2), a capacitor (C1), a third NAND gate (NAND3) and a seventh inverter (INV7), wherein: The source electrode of the first MOS tube (M1), the source electrode of the second MOS tube (M2), the first end of the capacitor (C1), the source electrode of the fifth MOS tube (M5), the source electrode of the seventh MOS tube (M7), and the source electrode of the ninth MOS tube (M9) are connected to a ground terminal (GND); The source of the third MOS tube (M3), the source of the fourth MOS tube (M4), the source of the sixth MOS tube (M6), and the source of the eighth MOS tube (M8) are connected to a power supply (VDD); The gate of the first MOS tube (M1) is input with a pulse signal, and the drain is connected to the first end of the first resistor (R1); The first input terminal of the third NAND gate (NAND3) inputs the phase difference signal, the second input terminal inputs the pulse signal, and the output terminal is connected to the input terminal of the seventh inverter (INV7); The output end of the seventh inverter (INV7) is connected to the gate of the second MOS transistor (M2); The drain of the second MOS tube (M2) is connected to the first end of the second resistor (R2); The second end of the first resistor (R1), the second end of the second resistor (R2), the second end of the capacitor (C1), the drain of the third MOS transistor (M3), the gate of the fourth MOS transistor (M4) and the gate of the fifth MOS transistor (M5) are connected; The gate of the third MOS tube (M3) serves as a reset terminal of the time error amplifier; The drain of the fourth MOS tube (M4), the drain of the fifth MOS tube (M5), the gate of the sixth MOS tube (M6), and the gate of the seventh MOS tube (M7) are connected; the drain of the sixth MOS tube (M6), the drain of the seventh MOS tube (M7), the gate of the eighth MOS tube (M8), and the gate of the ninth MOS tube (M9) are connected; The drain of the eighth MOS transistor (M8) and the drain of the ninth MOS transistor (M9) are connected and serve as the output end of the time error amplifier.

9. The low-noise phase detector circuit suitable for high-speed sampling clock according to claim 8, characterized in that: The theoretical amplification factor of the low-noise phase detector circuit is (1+R1 / R2) times, where R1 is the resistance value of the first resistor and R2 is the resistance value of the second resistor.

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