Digital closed-loop driving circuit of quartz gyroscope

Abstract

The invention discloses a digital closed-loop driving circuit of a quartz gyroscope, which comprises a charge amplifying circuit, a phase compensating circuit, a correlated double sampling circuit, a sigma-delta analog-to-digital converter and a digital signal processing circuit, and the charge amplifying circuit, the phase compensating circuit, the correlated double sampling circuit and the sigma-delta analog-to-digital converter are respectively realized by adopting a differential structure; the charge amplifying circuit is used for converting a charge signal into a voltage signal which is easy to process, the phase compensating circuit is used for adjusting the phase of the voltage signal to obtain an adjusted voltage signal, the correlated double sampling circuit is used for periodically sampling the adjusted voltage signal, and sampling is carried out twice in sequence in each period to obtain a difference sampling voltage signal; the sigma-delta analog-to-digital converter converts the difference sampling voltage signal into a digital signal, and the digital signal processing circuit converts the digital signal into an analog signal; the system has the advantages of high driving precision, high flexibility and high anti-interference capability.

Description

Technical Field

[0001] The present invention relates to a drive circuit, and more particularly to a digital closed-loop drive circuit for a quartz gyroscope. Background Art

[0002] A quartz gyroscope is used to measure angular velocity and is one of the core components in modern inertial navigation systems, widely applied in fields such as aerospace, ships, and vehicles. The measurement accuracy of a quartz gyroscope is directly related to the navigation performance of the inertial navigation system. With the development of navigation technology, the performance requirements for quartz gyroscopes are continuously increasing, especially the growing demand for high resolution, high linearity, and low noise performance.

[0003] The drive circuit of a quartz gyroscope is used to drive the quartz gyroscope to work, and the drive performance of the drive circuit directly affects the performance of the quartz gyroscope.

[0004] A Chinese patent with the patent number CN201910262339.1 discloses a closed-loop phase-locked drive circuit structure for a MEMS gyroscope. This closed-loop phase-locked drive circuit structure uses a phase-locked loop and a PID control circuit to respectively control the loop frequency and amplitude, thereby realizing the drive of the gyroscope. However, this closed-loop phase-locked drive circuit structure is an analog drive circuit, having defects such as low drive accuracy, poor flexibility, and insufficient anti-interference ability. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a digital closed-loop drive circuit for a quartz gyroscope with high drive accuracy, strong flexibility, and strong anti-interference ability.

[0006] The technical solution adopted by the present invention to solve the above technical problems is as follows: A digital closed-loop drive circuit for a quartz gyroscope, comprising a charge amplification circuit, a phase compensation circuit, a correlated double sampling circuit, a Σ-Δ analog-to-digital converter, and a digital signal processing circuit. The charge amplification circuit, the phase compensation circuit, the correlated double sampling circuit, and the Σ-Δ analog-to-digital converter are respectively implemented using a differential structure. The charge amplification circuit is used to obtain in real time the charge signal generated by the charge change caused by the vibration or acceleration of the quartz gyroscope, and convert this charge signal into a voltage signal that is easy to process, and output it to the phase compensation circuit. The phase compensation circuit is used to adjust the phase of the voltage signal output by the charge amplification circuit to it in real time, so that the digital closed-loop drive circuit operates in a negative feedback state, and obtain an adjusted voltage signal and output it to the correlated double sampling circuit. The correlated double sampling circuit is used to periodically sample the adjusted voltage signal output by the phase compensation circuit to it, and perform two successive samplings in each period to obtain two sampled voltage signals, and then subtract the two sampled voltage signals to obtain a differential sampled voltage signal and output it to the Σ-Δ analog-to-digital converter to eliminate the sampling error caused by noise or interference. The Σ-Δ analog-to-digital converter is used to convert the differential sampled voltage signal output by the correlated double sampling circuit to it into a digital signal using high-frequency oversampling technology and noise shaping technology, and output it to the digital signal processing circuit. The digital signal processing circuit is used to first perform filtering processing on the digital signal output by the Σ-Δ analog-to-digital converter to it to obtain a filtered digital signal, and then convert this filtered digital signal into an analog signal and output it to the quartz gyroscope. This analog signal is the drive signal, which is used to control the vibration frequency and amplitude of the quartz gyroscope.

[0007] Further, the charge amplification circuit has a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal; the positive input terminal and the negative input terminal of the charge amplification circuit are respectively connected to the quartz gyroscope, and are used for accessing the charge signals generated by the charge changes caused by the vibration or acceleration of the quartz gyroscope. The positive output terminal and the negative output terminal of the charge amplification circuit are used for outputting a voltage signal; the phase compensation circuit has a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal. The positive input terminal of the phase compensation circuit is connected to the positive output terminal of the charge amplification circuit, and the negative input terminal of the phase compensation circuit is connected to the negative output terminal of the charge amplification circuit; the positive output terminal and the negative output terminal of the phase compensation circuit are used for outputting an adjusted voltage signal; the correlated double sampling circuit has a positive input terminal, a negative input terminal, a positive output terminal, a negative output terminal, a first reference terminal for accessing a positive reference voltage, and a second reference terminal for accessing a negative reference voltage; the positive input terminal of the correlated double sampling circuit is connected to the positive output terminal of the phase compensation circuit, the negative input terminal of the correlated double sampling circuit is connected to the negative output terminal of the phase compensation circuit, and the positive output terminal and the negative output terminal of the correlated double sampling circuit are used for outputting a differential sampling voltage signal; the Σ-Δ analog-to-digital converter has a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal. The positive input terminal of the Σ-Δ analog-to-digital converter is connected to the positive output terminal of the correlated double sampling circuit, the negative input terminal of the Σ-Δ analog-to-digital converter is connected to the negative output terminal of the correlated double sampling circuit, and the positive output terminal and the negative output terminal of the Σ-Δ analog-to-digital converter are used for outputting a digital signal to the digital signal processing circuit.

[0008] Further, the correlated double sampling circuit includes eight electronic switches. Each electronic switch has a control terminal, a first terminal, and a second terminal. When its control terminal is connected to a high level, its first terminal and second terminal are turned on. When its control terminal is connected to a low level, its first terminal and second terminal are turned off. These eight electronic switches are respectively referred to as the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch, and the eighth switch. The first terminal of the first switch is connected to the first terminal of the eighth switch, and the connection terminal is the first reference terminal of the correlated double sampling circuit. The first terminal of the second switch is connected to the first terminal of the seventh switch, and the connection terminal is the second reference terminal of the correlated double sampling circuit. The first terminal of the fourth switch is the positive input terminal of the correlated double sampling circuit. The first terminal of the fifth switch is the negative input terminal of the correlated double sampling circuit. The second terminal of the first switch, the second terminal of the second switch, and the first terminal of the third switch are connected. The second terminal of the third switch is connected to the second terminal of the fourth switch, and the connection terminal is the positive output terminal of the correlated double sampling circuit. The second terminal of the seventh switch, the second terminal of the eighth switch, and the first terminal of the sixth switch are connected. The second terminal of the sixth switch is connected to the second terminal of the fifth switch, and the connection terminal is the negative output terminal of the correlated double sampling circuit. The control terminals of the first switch, the third switch, the fifth switch, and the seventh switch are all connected to the first clock signal clk1. The control terminals of the second switch, the fourth switch, the sixth switch, and the eighth switch are all connected to the second clock signal clk2. The first clock signal clk1 and the second clock signal clk2 have the same period and the same amplitude, but their phases differ by 90 degrees. In each clock cycle, the first clock signal clk1 first controls the first terminal and the second terminal of the first switch, the third switch, the fifth switch, and the seventh switch to be turned on, and the positive reference voltage is connected to the correlated double sampling circuit. The correlated double sampling circuit performs the first sampling, and the sampled voltage signal of the first time is temporarily stored. Then, the second clock signal clk2 controls the first terminal and the second terminal of the second switch, the fourth switch, the sixth switch, and the eighth switch to be turned on, and the negative reference voltage is connected to the correlated double sampling circuit. The correlated double sampling circuit performs the second sampling, and the sampled voltage signal of the second time is temporarily stored. After that, the first sampled voltage signal and the sampled voltage signal of the second time are superimposed and subtracted to form a differential sampled voltage signal for output.

[0009] Further, the Σ-Δ analog-to-digital converter includes twenty capacitors, three operational amplifiers, twenty-seven electronic switches, and a quantizer. The twenty capacitors are respectively referred to as the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the fifth capacitor, the sixth capacitor, the seventh capacitor, the eighth capacitor, the ninth capacitor, the tenth capacitor, the eleventh capacitor, the twelfth capacitor, the thirteenth capacitor, the fourteenth capacitor, the fifteenth capacitor, the sixteenth capacitor, the seventeenth capacitor, the eighteenth capacitor, the nineteenth capacitor, and the twentieth capacitor. The operational amplifier has a non-inverting input terminal, an inverting input terminal, a positive output terminal, and a negative output terminal. The three operational amplifiers are respectively referred to as the first operational amplifier, the second operational amplifier, and the third operational amplifier. The twenty-eight electronic switches are respectively referred to as the ninth switch, the tenth switch, the eleventh switch, the twelfth switch, the thirteenth switch, the fourteenth switch, the fifteenth switch, the sixteenth switch, the seventeenth switch, the eighteenth switch, the nineteenth switch, the twentieth switch, the twenty-first switch, the twenty-second switch, the twenty-third switch, the twenty-fourth switch, the twenty-fifth switch, the twenty-sixth switch, the twenty-seventh switch, the twenty-eighth switch, the twenty-ninth switch, the thirtieth switch, the thirty-first switch, the thirty-second switch, the thirty-third switch, the thirty-fourth switch, the thirty-fifth switch, and the thirty-sixth switch. The quantizer has a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal; One end of the first capacitor is connected to one end of the third capacitor, and the connection end is the positive input terminal of the Σ-Δ analog-to-digital converter. One end of the second capacitor is connected to one end of the sixth capacitor, and the connection end is the negative input terminal of the Σ-Δ analog-to-digital converter. The other end of the first capacitor, the first end of the ninth switch, and the first end of the tenth switch are connected. The second end of the ninth switch is grounded. The second end of the tenth switch, one end of the fourth capacitor, and the non-inverting input terminal of the first operational amplifier are connected. The other end of the fourth capacitor, the positive output terminal of the first operational amplifier, and the first end of the thirteenth switch are connected. The second end of the thirteenth switch, the first end of the fifteenth switch, one end of the seventh capacitor, and one end of the ninth capacitor are connected. The second end of the fifteenth switch is grounded. The other end of the seventh capacitor, the first end of the seventeenth switch, and the first end of the eighteenth switch are connected. The second end of the seventeenth switch is grounded. The second end of the eighteenth switch, one end of the tenth capacitor, and the non-inverting input terminal of the second operational amplifier are connected. The other end of the tenth capacitor, the positive output terminal of the second operational amplifier, and the first end of the twenty-second switch are connected. The second end of the twenty-second switch, the first end of the twenty-first switch, one end of the thirteenth capacitor, and one end of the fifteenth capacitor are connected. The second end of the twenty-first switch is grounded. The other end of the thirteenth capacitor, the first end of the twenty-fifth switch, and the first end of the twenty-sixth switch are connected,The second terminal of the twenty-fifth switch is grounded. The second terminal of the twenty-sixth switch, one end of the sixteenth capacitor, and the non-inverting input terminal of the third operational amplifier are connected. The other end of the sixteenth capacitor, the positive output terminal of the third operational amplifier, and the first terminal of the thirtieth switch are connected. The second terminal of the thirtieth switch, the first terminal of the twenty-ninth switch, and one end of the nineteenth capacitor are connected. The second terminal of the twenty-ninth switch is grounded. The other end of the nineteenth capacitor, the first terminal of the thirty-third switch, the first terminal of the thirty-fifth switch, the other end of the third capacitor, the other end of the ninth capacitor, and the other end of the fifteenth capacitor are connected. The second terminal of the thirty-third switch is grounded. The second terminal of the thirty-fifth switch is connected to the positive input terminal of the quantizer. The positive output terminal of the quantizer is the negative output terminal of the Σ-Δ analog-to-digital converter. The other end of the second capacitor, the first terminal of the twelfth switch, and the first terminal of the eleventh switch are connected. The second terminal of the twelfth switch is grounded. The second terminal of the eleventh switch, one end of the fifth capacitor, and the inverting input terminal of the first operational amplifier are connected. The other end of the fifth capacitor, the negative output terminal of the first operational amplifier, and the first terminal of the fourteenth switch are connected. The second terminal of the fourteenth switch, the first terminal of the sixteenth switch, one end of the eighth capacitor, and one end of the twelfth capacitor are connected. The second terminal of the sixteenth switch is grounded. The other end of the eighth capacitor, the first terminal of the twentieth switch, and the first terminal of the nineteenth switch are connected. The second terminal of the twentieth switch is grounded. The second terminal of the nineteenth switch, one end of the eleventh capacitor, and the inverting input terminal of the second operational amplifier are connected. The other end of the eleventh capacitor, the negative output terminal of the second operational amplifier, and the first terminal of the twenty-third switch are connected. The second terminal of the twenty-third switch, the first terminal of the twenty-fourth switch, one end of the fourteenth capacitor, and one end of the eighteenth capacitor are connected. The second terminal of the twenty-fourth switch is grounded. The other end of the fourteenth capacitor, the first terminal of the twenty-eighth switch, and the first terminal of the twenty-seventh switch are connected. The second terminal of the twenty-eighth switch is grounded. The second terminal of the twenty-seventh switch, one end of the seventeenth capacitor, and the inverting input terminal of the third operational amplifier are connected. The other end of the seventeenth capacitor, the negative output terminal of the third operational amplifier, and the first terminal of the thirty-first switch are connected. The second terminal of the thirty-first switch, the first terminal of the thirty-second switch, and one end of the twentieth capacitor are connected. The second terminal of the thirty-second switch is grounded. The other end of the twentieth capacitor, the first terminal of the thirty-fourth switch, the first terminal of the thirty-sixth switch, the other end of the sixth capacitor, the other end of the twelfth capacitor, and the other end of the eighteenth capacitor are connected.The second terminal of the thirty-fourth switch is grounded. The second terminal of the thirty-sixth switch is connected to the negative input terminal of the quantizer. The negative output terminal of the quantizer is the positive output terminal of the Σ-Δ analog-to-digital converter. The control terminals of the ninth switch, the eleventh switch, the thirteenth switch, the fifteenth switch, the seventeenth switch, the nineteenth switch, the twenty-first switch, the twenty-third switch, the twenty-fifth switch, the twenty-seventh switch, the twenty-ninth switch, the thirty-first switch, the thirty-third switch, and the thirty-fifth switch are all connected to the third clock signal clk3. The control terminals of the tenth switch, the twelfth switch, the fourteenth switch, the sixteenth switch, the eighteenth switch, the twentieth switch, the twenty-second switch, the twenty-fourth switch, the twenty-sixth switch, the twenty-eighth switch, the thirtieth switch, the thirty-second switch, the thirty-fourth switch, and the thirty-sixth switch are all connected to the fourth clock signal clk4. The third clock signal clk3 is the same as the first clock signal clk1, and the fourth clock signal clk4 is the same as the second clock signal clk2. The third clock signal clk3 serves as the Σ-Δ conversion clock to control the oversampling process of the Σ-Δ analog-to-digital converter. When the third clock signal clk3 is at a high level, the Σ-Δ analog-to-digital converter starts to oversample the input analog signal and converts the analog signal into a digital form. The oversampling technique samples the analog signal at a rate higher than the Nyquist sampling rate, thereby reducing quantization noise and improving resolution. The fourth clock signal clk4 is the digitization clock, which is used to control the sampling and data transmission of the output digital signal to ensure that the converted digital signal is read and stored in a timely manner. When the fourth clock signal clk4 is at a high level, the digital signal is transmitted to, for example, a digital signal processing circuit later.

[0010] Further, the charge amplification circuit includes an operational amplifier, two capacitors, and four electronic switches. The operational amplifier is referred to as the fourth operational amplifier, the two capacitors are respectively referred to as the twenty-first capacitor and the twenty-second capacitor, and the four electronic switches are respectively referred to as the thirty-seventh switch, the thirty-eighth switch, the thirty-ninth switch, and the fortieth switch. The first terminal of the thirty-seventh switch is the positive input terminal of the charge amplification circuit, the first terminal of the thirty-eighth switch is the negative input terminal of the charge amplification circuit, the second terminal of the thirty-seventh switch, the first terminal of the thirty-ninth switch, one end of the twenty-first capacitor, and the inverting input terminal of the fourth operational amplifier are connected. The second terminal of the thirty-ninth switch, the other end of the twenty-first capacitor, and the negative output terminal of the fourth operational amplifier are connected, and the connection terminal is the negative output terminal of the charge amplification circuit. The second terminal of the thirty-eighth switch, the first terminal of the fortieth switch, one end of the twenty-second capacitor, and the non-inverting input terminal of the fourth operational amplifier are connected. The second terminal of the fortieth switch, the other end of the twenty-second capacitor, and the positive output terminal of the fourth operational amplifier are connected, and the connection terminal is the positive output terminal of the charge amplification circuit. The control terminals of the thirty-seventh switch and the thirty-ninth switch are connected to the first clock signal clk1, and the control terminals of the thirty-eighth switch and the fortieth switch are connected to the second clock signal clk2.

[0011] Further, the phase compensation circuit includes an operational amplifier, six capacitors, and sixteen electronic switches. The operational amplifier is referred to as the fifth operational amplifier, the six capacitors are respectively referred to as the twenty-third capacitor, the twenty-fourth capacitor, the twenty-fifth capacitor, the twenty-sixth capacitor, the twenty-seventh capacitor, and the twenty-eighth capacitor, and the sixteen electronic switches are respectively referred to as the forty-first switch, the forty-second switch, the forty-third switch, the forty-fourth switch, the forty-fifth switch, the forty-sixth switch, the forty-seventh switch, the forty-eighth switch, the forty-ninth switch, the fiftieth switch, the fifty-first switch, the fifty-second switch, the fifty-third switch, the fifty-fourth switch, the fifty-fifth switch, and the fifty-sixth switch. The first end of the forty-first switch is the positive input terminal of the phase compensation circuit. The second end of the forty-first switch, the first end of the forty-second switch, one end of the twenty-third capacitor, and one end of the twenty-fourth capacitor are connected. The second end of the forty-second switch is grounded. The other end of the twenty-third capacitor, the first end of the forty-seventh switch, and the first end of the forty-eighth switch are connected. The second end of the forty-eighth switch is grounded. The other end of the twenty-fourth capacitor, the first end of the forty-fifth switch, and the first end of the forty-ninth switch are connected. The second end of the forty-fifth switch is grounded. The second end of the forty-seventh switch, the second end of the forty-ninth switch, the first end of the fifty-third switch, one end of the twenty-seventh capacitor, and the inverting input terminal of the fifth operational amplifier are connected. The second end of the fifty-third switch, the other end of the twenty-seventh capacitor, the first end of the fifty-fifth switch, and the positive output terminal of the fifth operational amplifier are connected. The second end of the fifty-fifth switch is the negative output terminal of the phase compensation circuit. The first end of the forty-third switch is the negative input terminal of the phase compensation circuit. The second end of the forty-third switch, the first end of the forty-fourth switch, one end of the twenty-fifth capacitor, and one end of the twenty-sixth capacitor are connected. The second end of the forty-fourth switch is grounded. The other end of the twenty-fifth capacitor, the first end of the fiftieth switch, and the first end of the fifty-first switch are connected. The second end of the fifty-first switch is grounded. The other end of the twenty-sixth capacitor, the first end of the forty-sixth switch, and the first end of the fifty-second switch are connected. The second end of the forty-sixth switch is grounded. The second end of the fiftieth switch, the second end of the fifty-second switch, the first end of the fifty-fourth switch, one end of the twenty-eighth capacitor, and the non-inverting input terminal of the fifth operational amplifier are connected. The second end of the fifty-fourth switch, the other end of the twenty-eighth capacitor, the first end of the fifty-sixth switch, and the negative output terminal of the fifth operational amplifier are connected. The second end of the fifty-sixth switch is the positive output terminal of the phase compensation circuit.The control terminals of the forty-first switch, the forty-third switch, the forty-fifth switch, the forty-seventh switch, the forty-ninth switch, the fifty-first switch, the fifty-third switch, and the fifty-fifth switch are all connected to the first clock signal clk1, and the control terminals of the forty-second switch, the forty-fourth switch, the forty-sixth switch, the forty-eighth switch, the fiftieth switch, the fifty-second switch, the fifty-fourth switch, and the fifty-sixth switch are all connected to the second clock signal clk2.;

[0012] Further, the operational amplifier includes 34 MOS transistors and one resistor. The resistor is referred to as the first resistor, and the 34 MOS transistors are respectively referred to as the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, the ninth MOS transistor, the tenth MOS transistor, the eleventh MOS transistor, the twelfth MOS transistor, the thirteenth MOS transistor, the fourteenth MOS transistor, the fifteenth MOS transistor, the sixteenth MOS transistor, the seventeenth MOS transistor, the eighteenth MOS transistor, the nineteenth MOS transistor, the twentieth MOS transistor, the twenty-first MOS transistor, the twenty-second MOS transistor, the twenty-third MOS transistor, the twenty-fourth MOS transistor, the twenty-fifth MOS transistor, the twenty-sixth MOS transistor, the twenty-seventh MOS transistor, the twenty-eighth MOS transistor, the twenty-ninth MOS transistor, the thirtieth MOS transistor, the thirty-first MOS transistor, the thirty-second MOS transistor, the thirty-third MOS transistor, and the thirty-fourth MOS transistor. The first MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, the ninth MOS transistor, the tenth MOS transistor, the twenty-first MOS transistor, the twenty-second MOS transistor, the twenty-fifth MOS transistor, the twenty-sixth MOS transistor, the twenty-eighth MOS transistor, the twenty-ninth MOS transistor, the thirtieth MOS transistor, the thirty-second MOS transistor, the thirty-third MOS transistor, and the thirty-fourth MOS transistor are all NMOS transistors. The second MOS transistor, the third MOS transistor, the sixth MOS transistor, the eleventh MOS transistor, the twelfth MOS transistor, the thirteenth MOS transistor, the fourteenth MOS transistor, the fifteenth MOS transistor, the sixteenth MOS transistor, the seventeenth MOS transistor, the eighteenth MOS transistor, the nineteenth MOS transistor, the twentieth MOS transistor, the twenty-third MOS transistor, the twenty-fourth MOS transistor, the twenty-seventh MOS transistor, and the thirty-first MOS transistor are all PMOS transistors. The drains of the first MOS transistor, the sources of the third MOS transistor, the drains of the fourth MOS transistor, the drains of the seventh MOS transistor, the drains of the ninth MOS transistor, the sources of the twelfth MOS transistor, the sources of the thirteenth MOS transistor, the sources of the nineteenth MOS transistor, the sources of the twenty-third MOS transistor, the sources of the twenty-seventh MOS transistor, and the sources of the thirty-first MOS transistor are all connected to the power supply voltage. The gates and sources of the first MOS transistor, the gates and sources of the second MOS transistor, and the gates of the third MOS transistor are connected.The drains of the second MOS transistor, the sixth MOS transistor, one end of the first resistor, the drain of the eleventh MOS transistor, the drain of the twelfth MOS transistor, the source of the twenty-second MOS transistor, the source of the twenty-sixth MOS transistor, the source of the thirtieth MOS transistor, and the source of the thirty-fourth MOS transistor are all grounded; the drain of the third MOS transistor, the source of the fifth MOS transistor, and the source of the sixth MOS transistor are connected, the source of the fourth MOS transistor and the drain of the fifth MOS transistor are connected, the gates of the fourth MOS transistor, the seventh MOS transistor, the ninth MOS transistor, the thirteenth MOS transistor, the twentieth MOS transistor, and the twenty-fourth MOS transistor are connected, the gates of the fifth MOS transistor, the eighth MOS transistor, the tenth MOS transistor, the fourteenth MOS transistor, the twenty-first MOS transistor, and the twenty-fifth MOS transistor are connected, the gate of the sixth MOS transistor, the other end of the first resistor, the source of the eighth MOS transistor, the gate of the twenty-second MOS transistor, the gate of the twenty-sixth MOS transistor, the gate of the thirtieth MOS transistor, and the gate of the thirty-fourth MOS transistor are connected, the source of the seventh MOS transistor and the drain of the eighth MOS transistor are connected, the source of the ninth MOS transistor and the drain of the tenth MOS transistor are connected, the source of the tenth MOS transistor, the source and gate of the eleventh MOS transistor, and the gate of the twelfth MOS transistor are connected, the drain of the thirteenth MOS transistor and the source of the fourteenth MOS transistor are connected, the drain of the fourteenth MOS transistor, the source of the fifteenth MOS transistor, and the source of the seventeenth MOS transistor are connected, the gates of the fifteenth MOS transistor and the sixteenth MOS transistor are connected, and the connection end is the non-inverting input terminal of the operational amplifier, the drain of the fifteenth MOS transistor and the source of the sixteenth MOS transistor are connected, the drain of the sixteenth MOS transistor, the source of the twenty-first MOS transistor, and the drain of the twenty-second MOS transistor are connected, the drain of the seventeenth MOS transistor and the source of the eighteenth MOS transistor are connected, the gates of the seventeenth MOS transistor and the eighteenth MOS transistor are connected, and the connection end is the inverting input terminal of the operational amplifier, the drain of the eighteenth MOS transistor, the source of the twenty-fifth MOS transistor, and the drain of the twenty-sixth MOS transistor are connected, the gates of the nineteenth MOS transistor, the twenty-third MOS transistor, the drain of the twenty-ninth MOS transistor, the drain of the thirty-second MOS transistor, and the gate and drain of the thirty-first MOS transistor are connected,The drain of the nineteenth MOS transistor is connected to the source of the twentieth MOS transistor. The drain of the twentieth MOS transistor, the drain of the twenty-first MOS transistor, and the gate of the thirty-third MOS transistor are connected, and their connection terminal is the negative output terminal of the operational amplifier. The drain of the twenty-third MOS transistor is connected to the source of the twenty-fourth MOS transistor. The drain of the twenty-fourth MOS transistor, the drain of the twenty-fifth MOS transistor, and the gate of the twenty-eighth MOS transistor are connected, and their connection terminal is the positive output terminal of the operational amplifier. The gate and drain of the twenty-seventh MOS transistor, the drain of the twenty-eighth MOS transistor, and the drain of the thirty-third MOS transistor are connected. The source of the twenty-eighth MOS transistor, the source of the twenty-ninth MOS transistor, and the drain of the thirtieth MOS transistor are connected. The gate of the twenty-ninth MOS transistor and the gate of the thirty-second MOS transistor are connected. The source of the thirty-second MOS transistor, the source of the thirty-third MOS transistor, and the drain of the thirty-fourth MOS transistor are connected.,

[0013] Further, the electronic switch includes six MOS transistors, which are respectively referred to as the thirty-fifth MOS transistor, the thirty-sixth MOS transistor, the thirty-seventh MOS transistor, the thirty-eighth MOS transistor, the thirty-ninth MOS transistor, and the fortieth MOS transistor. The thirty-fifth MOS transistor, the thirty-sixth MOS transistor, and the thirty-seventh MOS transistor are all NMOS transistors. The thirty-eighth MOS transistor, the thirty-ninth MOS transistor, and the fortieth MOS transistor are all PMOS transistors. The source and drain of the thirty-fifth MOS transistor, the source of the thirty-sixth MOS transistor, the source and drain of the thirty-eighth MOS transistor, and the source of the thirty-ninth MOS transistor are connected, and their connection terminal is the first terminal of the electronic switch. The gate of the thirty-fifth MOS transistor, the gate of the thirty-seventh MOS transistor, and the gate of the thirty-ninth MOS transistor are connected. The gate of the thirty-sixth MOS transistor, the gate of the thirty-eighth MOS transistor, and the gate of the fortieth MOS transistor are connected, and their connection terminal is the control terminal of the electronic switch. The drain of the thirty-sixth MOS transistor, the source and drain of the thirty-seventh MOS transistor, the drain of the thirty-ninth MOS transistor, and the source and drain of the fortieth MOS transistor are connected, and their connection terminal is the second terminal of the electronic switch.

[0014] Compared with the prior art, the advantages of the present invention are as follows: in the digital closed-loop drive circuit, the charge amplification circuit, the phase compensation circuit, the correlated double sampling circuit, and the Σ-Δ analog-to-digital converter are respectively implemented in a differential structure, which can suppress common-mode noise and common-mode interference and improve linearity. The phase compensation circuit adjusts the phase of the voltage signal output by the charge amplification circuit in real time to make the digital closed-loop drive circuit operate in a negative feedback state, thereby being able to eliminate or reduce the phase error caused by circuit components, environmental changes, or circuit delays, compensate for the phase shift generated between the charge signal (i.e., the feedback signal) collected by the charge amplification circuit and the actual required drive signal, ensure the phase consistency between the drive signal and the feedback signal, and thus improve the working accuracy and stability of the quartz gyro. The correlated double sampling circuit can effectively reduce the sampling error caused by noise or interference and improve the accuracy of the sampling signal by collecting two samples of the adjusted voltage signal (at two time points respectively) in each cycle. In addition, through the two samplings within a short time interval, the correlated double sampling circuit can also compensate for the fluctuations caused by the digital closed-loop drive circuit itself or external environmental factors, so that the Σ-Δ analog-to-digital converter can provide a more accurate digital signal (i.e., feedback data) for the digital signal processing circuit. The Σ-Δ analog-to-digital converter can effectively suppress quantization noise through high-frequency oversampling and noise shaping techniques, and thus can provide a high-precision digital signal output. Moreover, during the process of converting the analog signal into a digital signal, the Σ-Δ analog-to-digital converter can improve the resolution and accuracy of the signal, further ensuring the accuracy of the analog signal output to the digital signal processing circuit. Additionally, the present invention adopts a method of converting the feedback signal in the form of an analog signal into a digital signal and then converting the digital signal into a drive signal in the form of an analog signal. Through the conversion of the digital signal, gain adjustment can be achieved, with strong flexibility. Therefore, through the close combination of these four circuits, namely the charge amplification circuit, the phase compensation circuit, the correlated double sampling circuit, and the Σ-Δ analog-to-digital converter, the present invention has high drive precision, strong flexibility, and strong anti-interference ability, and can provide a quartz gyro drive control solution with high precision, stability, strong flexibility, and strong anti-interference ability in a complex environment. Description of the Drawings

[0015] Figure 1 is a structural block diagram of the digital closed-loop drive circuit of the quartz gyro of the present invention;

[0016] Figure 2 is a circuit diagram of the correlated double sampling circuit of the digital closed-loop drive circuit of the quartz gyro of the present invention;

[0017] Figure 3 is a circuit diagram of the Σ-Δ analog-to-digital converter of the digital closed-loop drive circuit of the quartz gyro of the present invention;

[0018] Figure 4Circuit diagram of the charge amplifier circuit of the digital closed-loop drive circuit of the quartz gyroscope of the present invention;

[0019] Figure 5 Circuit diagram of the phase compensation circuit of the digital closed-loop drive circuit of the quartz gyroscope of the present invention;

[0020] Figure 6 Waveform diagram of four clock signals of the digital closed-loop drive circuit of the quartz gyroscope of the present invention;

[0021] Figure 7 Circuit diagram of the operational amplifier of the digital closed-loop drive circuit of the quartz gyroscope of the present invention;

[0022] Figure 8 Circuit diagram of the electronic switch of the digital closed-loop drive circuit of the quartz gyroscope of the present invention;

[0023] Figure 9 Noise spectrum diagram of the digital closed-loop drive circuit of the quartz gyroscope of the present invention. Detailed implementation manners

[0024] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0025] Embodiment 1: As Figure 1As shown in the figure, a digital closed-loop drive circuit for a quartz gyroscope includes a charge amplification circuit, a phase compensation circuit, a correlated double sampling circuit, a Σ-Δ analog-to-digital converter, and a digital signal processing circuit. The charge amplification circuit, the phase compensation circuit, the correlated double sampling circuit, and the Σ-Δ analog-to-digital converter are respectively implemented using a differential structure. The charge amplification circuit is used to obtain in real time the charge signal generated by the charge change of the quartz gyroscope due to vibration or acceleration, and convert this charge signal into a voltage signal that is easy to process, and output it to the phase compensation circuit. The phase compensation circuit is used to adjust the phase of the voltage signal output to it by the charge amplification circuit in real time, so that the digital closed-loop drive circuit operates in a negative feedback state, and obtain an adjusted voltage signal and output it to the correlated double sampling circuit. The correlated double sampling circuit is used to periodically sample the adjusted voltage signal output to it by the phase compensation circuit, and perform two successive samplings in each period to obtain two sampled voltage signals, and then subtract the two sampled voltage signals to obtain a differential sampled voltage signal and output it to the Σ-Δ analog-to-digital converter to eliminate the sampling error caused by noise or interference. The Σ-Δ analog-to-digital converter is used to convert the differential sampled voltage signal output to it by the correlated double sampling circuit into a digital signal using high-frequency oversampling technology and noise shaping technology, and output it to the digital signal processing circuit. The digital signal processing circuit is used to first perform filtering processing on the digital signal output to it by the Σ-Δ analog-to-digital converter to obtain a filtered digital signal, and then convert this filtered digital signal into an analog signal and output it to the quartz gyroscope. This analog signal is the drive signal, which is used to control the vibration frequency and amplitude of the quartz gyroscope.

[0026] In this embodiment, the charge amplification circuit, the phase compensation circuit, the correlated double sampling circuit, and the Σ-Δ analog-to-digital converter are respectively implemented using a differential structure, which can suppress common-mode noise and interference and improve linearity. The phase compensation circuit adjusts the phase of the voltage signal output from the charge amplification circuit in real time to the place where it is located, enabling the digital closed-loop drive circuit to operate in a negative feedback state. As a result, it can eliminate or reduce the phase error caused by circuit components, environmental changes, or circuit delays, compensate for the phase shift between the charge signal (i.e., the feedback signal) collected by the charge amplification circuit and the actual required drive signal, ensure the phase consistency between the drive signal and the feedback signal, thereby improving the working accuracy and stability of the quartz gyroscope. The correlated double sampling circuit can effectively reduce the sampling error caused by noise or interference and improve the accuracy of the sampled signal by collecting two samples of the adjusted voltage signal (at two time points respectively) in each cycle. In addition, through the two samplings within a short time interval, the correlated double sampling circuit can also compensate for the fluctuations caused by the digital closed-loop drive circuit itself or external environmental factors, enabling the Σ-Δ analog-to-digital converter to provide a more accurate digital signal (i.e., feedback data) for the digital signal processing circuit. The Σ-Δ analog-to-digital converter can effectively suppress quantization noise through high-frequency oversampling and noise shaping techniques, thereby providing a high-precision digital signal output. Moreover, during the process of converting the analog signal into a digital signal, the Σ-Δ analog-to-digital converter can improve the resolution and accuracy of the signal, further ensuring the accuracy of the analog signal output to the digital signal processing circuit. Additionally, the present invention adopts the method of converting the feedback signal in the form of an analog signal into a digital signal and then converting the digital signal into a drive signal in the form of an analog signal. Through the conversion of the digital signal, gain adjustment can be achieved, with strong flexibility. Therefore, through the close combination of these four circuits, namely the charge amplification circuit, the phase compensation circuit, the correlated double sampling circuit, and the Σ-Δ analog-to-digital converter, the present invention has high drive precision, strong flexibility, and strong anti-interference ability, and can provide a quartz gyroscope drive control solution with high precision, stability, and strong flexibility and anti-interference ability in a complex environment.

[0027] Embodiment 2: This embodiment is basically the same as Embodiment 1, except that: in this embodiment, the charge amplifier circuit has a positive input terminal, a negative input terminal, a positive output terminal and a negative output terminal; the positive input terminal and the negative input terminal of the charge amplifier circuit are respectively connected to the quartz gyroscope, and are used to access the charge signals generated by the charge changes caused by the vibration or acceleration of the quartz gyroscope. The positive output terminal and the negative output terminal of the charge amplifier circuit are used to output a voltage signal; the phase compensation circuit has a positive input terminal, a negative input terminal, a positive output terminal and a negative output terminal. The positive input terminal of the phase compensation circuit is connected to the positive output terminal of the charge amplifier circuit, and the negative input terminal of the phase compensation circuit is connected to the negative output terminal of the charge amplifier circuit; the positive output terminal and the negative output terminal of the phase compensation circuit are used to output an adjusted voltage signal; the correlated double sampling circuit has a positive input terminal, a negative input terminal, a positive output terminal, a negative output terminal, a first reference terminal for accessing the positive reference voltage V ref+ and a second reference terminal for accessing the negative reference voltage V ref- ; the positive input terminal of the correlated double sampling circuit is connected to the positive output terminal of the phase compensation circuit, the negative input terminal of the correlated double sampling circuit is connected to the negative output terminal of the phase compensation circuit, and the positive output terminal and the negative output terminal of the correlated double sampling circuit are used to output a differential sampling voltage signal; the Σ-Δ analog-to-digital converter has a positive input terminal, a negative input terminal, a positive output terminal and a negative output terminal. The positive input terminal of the Σ-Δ analog-to-digital converter is connected to the positive output terminal of the correlated double sampling circuit, the negative input terminal of the Σ-Δ analog-to-digital converter is connected to the negative output terminal of the correlated double sampling circuit, and the positive output terminal and the negative output terminal of the Σ-Δ analog-to-digital converter are used to output a digital signal to the digital signal processing circuit.

[0028] Embodiment 3: This embodiment is basically the same as Embodiment 2, except that: in this embodiment, as Figure 2 and Figure 6As shown in the figure, the correlated double sampling circuit includes eight electronic switches. Each electronic switch has a control terminal, a first terminal, and a second terminal. When its control terminal is connected to a high level, its first terminal and second terminal are turned on. When its control terminal is connected to a low level, its first terminal and second terminal are turned off. The eight electronic switches are respectively called the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8. The first terminal of the first switch S1 is connected to the first terminal of the eighth switch S8, and their connection terminal is the first reference terminal of the correlated double sampling circuit. The first terminal of the second switch S2 is connected to the first terminal of the seventh switch S7, and their connection terminal is the second reference terminal of the correlated double sampling circuit. The first terminal of the fourth switch S4 is the positive input terminal of the correlated double sampling circuit. The first terminal of the fifth switch S5 is the negative input terminal of the correlated double sampling circuit. The second terminal of the first switch S1, the second terminal of the second switch S2, and the first terminal of the third switch S3 are connected. The second terminal of the third switch S3 is connected to the second terminal of the fourth switch S4, and their connection terminal is the positive output terminal of the correlated double sampling circuit. The second terminal of the seventh switch S7, the second terminal of the eighth switch S8, and the first terminal of the sixth switch S6 are connected. The second terminal of the sixth switch S6 is connected to the second terminal of the fifth switch S5, and their connection terminal is the negative output terminal of the correlated double sampling circuit. The control terminals of the first switch S1, the third switch S3, the fifth switch S5, and the seventh switch S7 are all connected to the first clock signal clk1. The control terminals of the second switch S2, the fourth switch S4, the sixth switch S6, and the eighth switch S8 are all connected to the second clock signal clk2. The first clock signal clk1 and the second clock signal clk2 have the same period and the same amplitude, but their phases differ by 90 degrees. In each clock cycle Ts, the first clock signal clk1 first controls the first terminal and the second terminal of the first switch S1, the third switch S3, the fifth switch S5, and the seventh switch S7 to be turned on, and the positive reference voltage is connected to the correlated double sampling circuit. The correlated double sampling circuit performs the first sampling, and the sampled voltage signal of the first time is temporarily stored. Then, the second clock signal clk2 controls the first terminal and the second terminal of the second switch S2, the fourth switch S4, the sixth switch S6, and the eighth switch S8 to be turned on, and the negative reference voltage is connected to the correlated double sampling circuit. The correlated double sampling circuit performs the second sampling, and the sampled voltage signal of the second time is temporarily stored. After that, the first sampled voltage signal and the sampled voltage signal of the second time are superimposed and subtracted to form a differential sampled voltage signal for output.

[0029] In this embodiment, signals are respectively connected to the positive input terminal and the negative input terminal of the correlated double sampling circuit. The signal V connected to the positive input terminal of the correlated double sampling circuit in+ is connected to the positive reference voltage V ref+ and the negative reference voltage V ref- through the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4. The signal V connected to the negative input terminal of the correlated double sampling circuitin- are connected to the positive reference voltage V through the fifth switch S5, the sixth switch S6, the seventh switch S7 and the eighth switch S8. ref+ and the negative reference voltage V ref- The correlated double sampling circuit controls the on / off of the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7 and the eighth switch S8 through the first clock signal clk1 and the second clock signal clk2, and realizes the sampling and holding process of the signal. The two sampling periods respectively correspond to two different reference voltages (i.e., the positive reference voltage V ref+ and the negative reference voltage V ref- ), so that the signal V input to the positive input terminal of the correlated double sampling circuit and the signal V input to the negative input terminal of the correlated double sampling circuit can be sampled simultaneously, thus realizing "correlated double sampling", that is, capturing the difference of the input signal at two different sampling points. This process can reduce the error caused by the instability or drift of the positive reference voltage V in+ and the negative reference voltage V in- , helps reduce the error caused by the change of the positive reference voltage V ref+ and the negative reference voltage V ref- , and improves the sampling accuracy and signal reliability. ref+ and the negative reference voltage V ref- Example 4: This example is basically the same as Example 3, the difference is that: in this example, such as

[0030] and Figure 3 and Figure 6As shown, the Σ-Δ analog-to-digital converter includes twenty capacitors, three operational amplifiers, twenty-seven electronic switches, and a quantizer U1. The twenty capacitors are respectively called the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, the eighth capacitor C8, the ninth capacitor C9, the tenth capacitor C10, the eleventh capacitor C11, the twelfth capacitor C12, the thirteenth capacitor C13, the fourteenth capacitor C14, the fifteenth capacitor C15, the sixteenth capacitor C16, the seventeenth capacitor C17, the eighteenth capacitor C18, the nineteenth capacitor C19, and the twentieth capacitor C20. The operational amplifier has a non-inverting input terminal, an inverting input terminal, a positive output terminal, and a negative output terminal. The three operational amplifiers are respectively called the first operational amplifier OP1, the second operational amplifier OP2, and the third operational amplifier OP3. The twenty-eight electronic switches are respectively called the ninth switch S9, the tenth switch S10, the eleventh switch S11, the twelfth switch S12, the thirteenth switch S13, the fourteenth switch S14, the fifteenth switch S15, the sixteenth switch S16, the seventeenth switch S17, the eighteenth switch S18, the nineteenth switch S19, the twentieth switch S20, the twenty-first switch S21, the twenty-second switch S22, the twenty-third switch S23, the twenty-fourth switch S24, the twenty-fifth switch S25, the twenty-sixth switch S26, the twenty-seventh switch S27, the twenty-eighth switch S28, the twenty-ninth switch S29, the thirtieth switch S30, the thirty-first switch S31, the thirty-second switch S32, the thirty-third switch S33, the thirty-fourth switch S34, the thirty-fifth switch S35, and the thirty-sixth switch S36. The quantizer U1 has a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal; One end of the first capacitor C1 is connected to one end of the third capacitor C3, and the connection end is the positive input terminal of the Σ-Δ analog-to-digital converter. One end of the second capacitor C2 is connected to one end of the sixth capacitor C6, and the connection end is the negative input terminal of the Σ-Δ analog-to-digital converter. The other end of the first capacitor C1, the first end of the ninth switch S9, and the first end of the tenth switch S10 are connected. The second end of the ninth switch S9 is grounded. The second end of the tenth switch S10, one end of the fourth capacitor C4, and the non-inverting input terminal of the first operational amplifier OP1 are connected. The other end of the fourth capacitor C4, the positive output terminal of the first operational amplifier OP1, and the first end of the thirteenth switch S13 are connected. The second end of the thirteenth switch S13, the first end of the fifteenth switch S15, one end of the seventh capacitor C7, and one end of the ninth capacitor C9 are connected. The second end of the fifteenth switch S15 is grounded. The other end of the seventh capacitor C7, the first end of the seventeenth switch S17, and the first end of the eighteenth switch S18 are connected. The second end of the seventeenth switch S17 is grounded. The second end of the eighteenth switch S18, one end of the tenth capacitor C10, and the non-inverting input terminal of the second operational amplifier OP2 are connected. The other end of the tenth capacitor C10, the positive output terminal of the second operational amplifier OP2, and the first end of the twenty-second switch S22 are connected,The second terminal of the twenty-second switch S22, the first terminal of the twenty-first switch S21, one end of the thirteenth capacitor C13, and one end of the fifteenth capacitor C15 are connected. The second terminal of the twenty-first switch S21 is grounded. The other end of the thirteenth capacitor C13, the first terminal of the twenty-fifth switch S25, and the first terminal of the twenty-sixth switch S26 are connected. The second terminal of the twenty-fifth switch S25 is grounded. The second terminal of the twenty-sixth switch S26, one end of the sixteenth capacitor C16, and the non-inverting input terminal of the third operational amplifier OP3 are connected. The other end of the sixteenth capacitor C16, the positive output terminal of the third operational amplifier OP3, and the first terminal of the thirtieth switch S30 are connected. The second terminal of the thirtieth switch S30, the first terminal of the twenty-ninth switch S29, and one end of the nineteenth capacitor C19 are connected. The second terminal of the twenty-ninth switch S29 is grounded. The other end of the nineteenth capacitor C19, the first terminal of the thirty-third switch S33, the first terminal of the thirty-fifth switch S35, the other end of the third capacitor C3, the other end of the ninth capacitor C9, and the other end of the fifteenth capacitor C15 are connected. The second terminal of the thirty-third switch S33 is grounded. The second terminal of the thirty-fifth switch S35 and the positive input terminal of the quantizer U1 are connected. The positive output terminal of the quantizer U1 is the negative output terminal of the Σ-Δ analog-to-digital converter. The other end of the second capacitor C2, the first terminal of the twelfth switch S12, and the first terminal of the eleventh switch S11 are connected. The second terminal of the twelfth switch S12 is grounded. The second terminal of the eleventh switch S11, one end of the fifth capacitor C5, and the inverting input terminal of the first operational amplifier OP1 are connected. The other end of the fifth capacitor C5, the negative output terminal of the first operational amplifier OP1, and the first terminal of the fourteenth switch S14 are connected. The second terminal of the fourteenth switch S14, the first terminal of the sixteenth switch S16, one end of the eighth capacitor C8, and one end of the twelfth capacitor C12 are connected. The second terminal of the sixteenth switch S16 is grounded. The other end of the eighth capacitor C8, the first terminal of the twentieth switch S20, and the first terminal of the nineteenth switch S19 are connected. The second terminal of the twentieth switch S20 is grounded. The second terminal of the nineteenth switch S19, one end of the eleventh capacitor C11, and the inverting input terminal of the second operational amplifier OP2 are connected. The other end of the eleventh capacitor C11, the negative output terminal of the second operational amplifier OP2, and the first terminal of the twenty-third switch S23 are connected. The second terminal of the twenty-third switch S23, the first terminal of the twenty-fourth switch S24, one end of the fourteenth capacitor C14, and one end of the eighteenth capacitor C18 are connected. The second terminal of the twenty-fourth switch S24 is grounded. The other end of the fourteenth capacitor C14, the first terminal of the twenty-eighth switch S28, and the first terminal of the twenty-seventh switch S27 are connected. The second terminal of the twenty-eighth switch S28 is grounded. The second terminal of the twenty-seventh switch S27, one end of the seventeenth capacitor C17, and the inverting input terminal of the third operational amplifier OP3 are connected. The other end of the seventeenth capacitor C17, the negative output terminal of the third operational amplifier OP3, and the first terminal of the thirty-first switch S31 are connected.The second terminal of the thirty - first switch S31, the first terminal of the thirty - second switch S32, and one end of the twentieth capacitor C20 are connected. The second terminal of the thirty - second switch S32 is grounded. The other end of the twentieth capacitor C20, the first terminal of the thirty - fourth switch S34, the first terminal of the thirty - sixth switch S36, the other end of the sixth capacitor C6, the other end of the twelfth capacitor C12, and the other end of the eighteenth capacitor C18 are connected. The second terminal of the thirty - fourth switch S34 is grounded. The second terminal of the thirty - sixth switch S36 is connected to the negative input terminal of the quantizer U1. The negative output terminal of the quantizer U1 is the positive output terminal of the Σ - Δ analog - to - digital converter. The control terminals of the ninth switch S9, the eleventh switch S11, the thirteenth switch S13, the fifteenth switch S15, the seventeenth switch S17, the nineteenth switch S19, the twenty - first switch S21, the twenty - third switch S23, the twenty - fifth switch S25, the twenty - seventh switch S27, the twenty - ninth switch S29, the thirty - first switch S31, the thirty - third switch S33, and the thirty - fifth switch S35 are all connected to the third clock signal clk3. The control terminals of the tenth switch S10, the twelfth switch S12, the fourteenth switch S14, the sixteenth switch S16, the eighteenth switch S18, the twentieth switch S20, the twenty - second switch S22, the twenty - fourth switch S24, the twenty - sixth switch S26, the twenty - eighth switch S28, the thirtieth switch S30, the thirty - second switch S32, the thirty - fourth switch S34, and the thirty - sixth switch S36 are all connected to the fourth clock signal clk4. The third clock signal clk3 is the same as the first clock signal clk1. The fourth clock signal clk4 is the same as the second clock signal clk2. The third clock signal clk3 serves as the Σ - Δ conversion clock, which is used to control the oversampling process of the Σ - Δ analog - to - digital converter. When the third clock signal clk3 is at a high level, the Σ - Δ analog - to - digital converter starts to oversample the input analog signal and converts the analog signal into digital form. The oversampling technique samples the analog signal at a rate higher than the Nyquist sampling rate, thereby reducing quantization noise and improving resolution. The fourth clock signal clk4 is the digitization clock, which is used to control the sampling and data transmission of the output digital signal, ensuring that the converted digital signal is read and stored in a timely manner. When the fourth clock signal clk4 is at a high level, the digital signal is transmitted to the digital signal processing circuit.

[0031] In this embodiment, when signals are applied to the positive input terminal and the negative input terminal of the relevant double-sampling circuit, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 control the sampling process. When the first switch S1 and the second switch S2 are switched, the relevant double-sampling circuit samples. The signals output from the positive input terminal and the negative input terminal of the relevant double-sampling circuit are sent to the positive input terminal and the negative input terminal of the Σ-Δ analog-to-digital converter and are temporarily stored in the first capacitor C1, the second capacitor C2, and the third capacitor C3, preparing for the next signal modulation process. During the signal modulation process, the first operational amplifier OP1, the second operational amplifier OP2, and the third operational amplifier OP3 are responsible for converting the input signal into a differential signal and processing the signal through integration and feedback. The core of this process is to convert the input signal into a high-frequency modulation signal, improve the resolution through oversampling, and transfer the quantization noise of the signal to a higher frequency. The first operational amplifier OP1 and the second operational amplifier OP2 act as two integrators, which integrate the input signal and convert it into a signal with a higher frequency. The third operational amplifier OP3 acts as the last feedback link in this process, performing the final shaping and adjustment of the signal. Thus, through oversampling and high-frequency modulation, the low-frequency part (quantization noise) of the signal will be transferred to a higher frequency band, making the low-frequency part cleaner. During this process, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, the eighth capacitor C8, the ninth capacitor C9, the tenth capacitor C10, the eleventh capacitor C11, the twelfth capacitor C12, the thirteenth capacitor C13, the fourteenth capacitor C14, the fifteenth capacitor C15, the sixteenth capacitor C16, the seventeenth capacitor C17, the eighteenth capacitor C18, the nineteenth capacitor C19, and the twentieth capacitor C20, as well as the ninth switch S9, the tenth switch S10, the eleventh switch S11, the twelfth switch S12, the thirteenth switch S13, the fourteenth switch S14, the fifteenth switch S15, the sixteenth switch S16, the seventeenth switch S17, the eighteenth switch S18, the nineteenth switch S19, the twentieth switch S20, the twenty-first switch S21, the twenty-second switch S22, the twenty-third switch S23, the twenty-fourth switch S24, the twenty-fifth switch S25, the twenty-sixth switch S26, the twenty-seventh switch S27, the twenty-eighth switch S28, the twenty-ninth switch S29, the thirtieth switch S30, the thirty-first switch S31, the thirty-second switch S32, the thirty-third switch S33, the thirty-fourth switch S34, the thirty-fifth switch S35, and the thirty-sixth switch S36 work together to suppress the noise in the signal through integration and feedback, thereby enhancing the signal-to-noise ratio of the final output signal.After being processed by the first operational amplifier OP1, the second operational amplifier OP2, and the third operational amplifier OP3, the signal will be converted into a digital signal by the quantizer U1. Among them, the signals output from the positive output terminal and the negative output terminal of the Σ-Δ analog-to-digital converter are respectively the positive and negative parts of the signal that has been modulated and processed. Finally, stable digital signal outputs are formed at the positive output terminal and the negative output terminal of the Σ-Δ analog-to-digital converter. At this time, the frequency components of the signal have been modulated to a higher frequency band, and the quantization noise has been greatly suppressed, resulting in a stable low-frequency digital signal output.

[0032] The Σ-Δ analog-to-digital converter of this embodiment has the following characteristics:

[0033] I. High resolution: Through the oversampling and integration processes, the resolution and signal-to-noise ratio (SNR) of the digital closed-loop drive circuit are effectively improved.

[0034] II. Strong anti-noise ability: Through the feedback mechanism of multi-stage integration and modulation, high-frequency noise and quantization noise can be effectively filtered out, maintaining the high quality of the signal.

[0035] III. Simplified digitization: Converting the analog signal into a digital signal simplifies the subsequent digital signal processing process.

[0036] Embodiment 5: This embodiment is basically the same as Embodiment 4, except that: in this embodiment, as Figure 4 and Figure 6 shown, the charge amplification circuit includes an operational amplifier, two capacitors, and four electronic switches. The operational amplifier is called the fourth operational amplifier OP4, the two capacitors are respectively called the twenty-first capacitor C21 and the twenty-second capacitor C22, and the four electronic switches are respectively called the thirty-seventh switch S37, the thirty-eighth switch S38, the thirty-ninth switch S39, and the fortieth switch S40; the first end of the thirty-seventh switch S37 is the positive input terminal of the charge amplification circuit, the first end of the thirty-eighth switch S38 is the negative input terminal of the charge amplification circuit, the second end of the thirty-seventh switch S37, the first end of the thirty-ninth switch S39, one end of the twenty-first capacitor C21, and the inverting input terminal of the fourth operational amplifier OP4 are connected, the second end of the thirty-ninth switch S39, the other end of the twenty-first capacitor C21, and the negative output terminal of the fourth operational amplifier OP4 are connected, and their connection end is the negative output terminal of the charge amplification circuit; the second end of the thirty-eighth switch S38, the first end of the fortieth switch S40, one end of the twenty-second capacitor C22, and the non-inverting input terminal of the fourth operational amplifier OP4 are connected, the second end of the fortieth switch S40, the other end of the twenty-second capacitor C22, and the positive output terminal of the fourth operational amplifier OP4 are connected, and their connection end is the positive output terminal of the charge amplification circuit; the control terminals of the thirty-seventh switch S37 and the thirty-ninth switch S39 are connected to the first clock signal clk1, and the control terminals of the thirty-eighth switch S38 and the fortieth switch S40 are connected to the second clock signal clk2.

[0037] In this embodiment, the charge amplifier circuit is mainly used for signal processing, and is particularly suitable for the front-end readout part of a quartz gyroscope. Its main purpose is to convert a tiny charge signal into a voltage signal for subsequent processing. The specific working process is as follows: When the quartz gyroscope generates a charge change due to vibration or acceleration, a voltage signal is input to the positive input terminal and the negative input terminal of the charge amplifier through the thirty-seventh switch S37 and the thirty-eighth switch S38. When the thirty-seventh switch S37 and the thirty-eighth switch S38 are closed, the input voltage signal is stored through the twenty-first capacitor C21 and the twenty-second capacitor C22. The twenty-first capacitor C21 and the twenty-second capacitor C22 convert the weak voltage signal into a charge signal by accumulating charges, realizing charge injection. The two charge signals converted by the twenty-first capacitor C21 and the twenty-second capacitor C22 are transmitted to the fourth operational amplifier OP4. The fourth operational amplifier OP4 performs gain processing on the two input charge signals, converting the two charge signals into corresponding voltage signals, realizing the charge signal amplification process. At this time, the two obtained voltage signals are voltage signals that are easy to process and are output to the phase compensation circuit through its positive output terminal and negative output terminal.

[0038] The charge amplifier circuit has the following characteristics:

[0039] I. High sensitivity: It can process weak charge signals from a quartz gyroscope, can efficiently amplify weak signals, and enhance the sensitivity of the digital closed-loop drive circuit.

[0040] II. Low noise: Since the charge amplifier circuit accumulates and processes charges through capacitors (the twenty-first capacitor C21 and the twenty-second capacitor C22), it is less sensitive to external noise compared to directly amplifying voltage signals, which helps to improve the measurement accuracy.

[0041] III. High bandwidth: It can provide a high frequency response, is suitable for rapidly changing signals, and can effectively track the changes in the output signal of the quartz gyroscope.

[0042] IV. Linear response: Due to the characteristics of the working principle of this charge amplifier circuit, there is a strong linear relationship between its output and the charge quantity of the input signal, which makes the signal processing more accurate.

[0043] Embodiment Six: This embodiment is basically the same as Embodiment Five, except that: In this embodiment, as Figure 5 and Figure 6As shown, the phase compensation circuit includes an operational amplifier, six capacitors, and sixteen electronic switches. The operational amplifier is referred to as the fifth operational amplifier OP5, the six capacitors are respectively referred to as the twenty-third capacitor C23, the twenty-fourth capacitor C24, the twenty-fifth capacitor C25, the twenty-sixth capacitor C26, the twenty-seventh capacitor C27, and the twenty-eighth capacitor C28, and the sixteen electronic switches are respectively referred to as the forty-first switch S41, the forty-second switch S42, the forty-third switch S43, the forty-fourth switch S44, the forty-fifth switch S45, the forty-sixth switch S46, the forty-seventh switch S47, the forty-eighth switch S48, the forty-ninth switch S49, the fiftieth switch S50, the fifty-first switch S51, the fifty-second switch S52, the fifty-third switch S53, the fifty-fourth switch S54, the fifty-fifth switch S55, and the fifty-sixth switch S56; the first terminal of the forty-first switch S41 is the positive input terminal of the phase compensation circuit, the second terminal of the forty-first switch S41, the first terminal of the forty-second switch S42, one end of the twenty-third capacitor C23, and one end of the twenty-fourth capacitor C24 are connected, the second terminal of the forty-second switch S42 is grounded, the other end of the twenty-third capacitor C23, the first terminal of the forty-seventh switch S47, and the first terminal of the forty-eighth switch S48 are connected, the second terminal of the forty-eighth switch S48 is grounded, the other end of the twenty-fourth capacitor C24, the first terminal of the forty-fifth switch S45, and the first terminal of the forty-ninth switch S49 are connected, the second terminal of the forty-fifth switch S45 is grounded, the second terminal of the forty-seventh switch S47, the second terminal of the forty-ninth switch S49, the first terminal of the fifty-third switch S53, one end of the twenty-seventh capacitor C27, and the inverting input terminal of the fifth operational amplifier OP5 are connected, the second terminal of the fifty-third switch S53, the other end of the twenty-seventh capacitor C27, the first terminal of the fifty-fifth switch S55, and the positive output terminal of the fifth operational amplifier OP5 are connected, and the second terminal of the fifty-fifth switch S55 is the negative output terminal of the phase compensation circuit;The first terminal of the forty-third switch S43 is the negative input terminal of the phase compensation circuit. The second terminal of the forty-third switch S43, the first terminal of the forty-fourth switch S44, one end of the twenty-fifth capacitor C25, and one end of the twenty-sixth capacitor C26 are connected. The second terminal of the forty-fourth switch S44 is grounded. The other end of the twenty-fifth capacitor C25, the first terminal of the fiftieth switch S50, and the first terminal of the fifty-first switch S51 are connected. The second terminal of the fifty-first switch S51 is grounded. The other end of the twenty-sixth capacitor C26, the first terminal of the forty-sixth switch S46, and the first terminal of the fifty-second switch S52 are connected. The second terminal of the forty-sixth switch S46 is grounded. The second terminals of the fiftieth switch S50 and the fifty-second switch S52, the first terminal of the fifty-fourth switch S54, one end of the twenty-eighth capacitor C28, and the non-inverting input terminal of the fifth operational amplifier OP5 are connected. The second terminal of the fifty-fourth switch S54, the other end of the twenty-eighth capacitor C28, the first terminal of the fifty-sixth switch S56, and the negative output terminal of the fifth operational amplifier OP5 are connected. The second terminal of the fifty-sixth switch S56 is the positive output terminal of the phase compensation circuit. The control terminals of the forty-first switch S41, the forty-third switch S43, the forty-fifth switch S45, the forty-seventh switch S47, the forty-ninth switch S49, the fifty-first switch S51, the fifty-third switch S53, and the fifty-fifth switch S55 are all connected to the first clock signal clk1. The control terminals of the forty-second switch S42, the forty-fourth switch S44, the forty-sixth switch S46, the forty-eighth switch S48, the fiftieth switch S50, the fifty-second switch S52, the fifty-fourth switch S54, and the fifty-sixth switch S56 are all connected to the second clock signal clk2.;

[0044] In this embodiment, the signal output from the positive output terminal of the charge amplification circuit is input into the phase compensation circuit through the forty-first switch S41, and the signal output from the negative output terminal of the charge amplification circuit is input into the phase compensation circuit through the forty-third switch S43. Among them, the signal output from the positive output terminal of the charge amplification circuit is sampled and processed through the forty-first switch S41, the forty-second switch S42, the forty-fifth switch S45, the forty-seventh switch S47, the forty-eighth switch S48, the forty-ninth switch S49, the fifty-third switch S53, and the fifty-fifth switch S55, converting the voltage signal into a charge signal, and the charge is stored and transferred through the twenty-third capacitor C23, the twenty-fourth capacitor C24, and the twenty-seventh capacitor C27. The signal output from the negative output terminal of the charge amplification circuit is sampled and processed through the forty-third switch S43, the forty-fourth switch S44, the forty-sixth switch S46, the fiftieth switch S50, the fifty-first switch S51, the fifty-second switch S52, the fifty-fourth switch S54, and the fifty-sixth switch S56, converting the voltage signal into a charge signal, and the charge is stored and transferred through the twenty-fifth capacitor C25, the twenty-sixth capacitor C26, and the twenty-eighth capacitor C28. At the same time, the fifth operational amplifier OP5 realizes phase compensation. The fifth operational amplifier OP5 eliminates the phase error caused by the delay or unsatisfactory frequency response of the digital closed-loop drive circuit by feedback and compensation adjustment of the charge on the twenty-seventh capacitor C27 and the twenty-eighth capacitor C28. The signal that realizes phase compensation through the fifth operational amplifier OP5 is output through the fifty-fifth switch S55 and the fifty-sixth switch S56.

[0045] The charge amplification circuit has the following characteristics:

[0046] I. Improve stability: It can eliminate the phase error caused by component delay or inconsistent frequency response in the digital closed-loop drive circuit, making the digital closed-loop drive circuit more stable.

[0047] II. Improve frequency response: It helps to improve the working performance of the digital closed-loop drive circuit in a wide frequency band, ensuring that the digital closed-loop drive circuit can still maintain good signal processing ability at a relatively high frequency.

[0048] III. Improve signal accuracy: By compensating the phase distortion of the circuit, it avoids the distortion and errors generated in the signal, thereby improving the accuracy and quality of the signal. This is especially crucial for high-precision applications such as quartz gyroscopes.

[0049] IV. Reduce phase error: Since the phase compensation circuit can accurately correct the phase shift in the digital closed-loop drive circuit, it can significantly reduce the measurement error caused by the phase error, especially in high-precision sensors and measurement systems.

[0050] Example 7: This example is basically the same as Example 6, except that: in this example, as Figure 7As shown, the operational amplifier includes 34 MOS transistors and a resistor. This resistor is referred to as the first resistor R1, and the 34 MOS transistors are respectively referred to as the first MOS transistor Q1, the second MOS transistor Q2, the third MOS transistor Q3, the fourth MOS transistor Q4, the fifth MOS transistor Q5, the sixth MOS transistor Q6, the seventh MOS transistor Q7, the eighth MOS transistor Q8, the ninth MOS transistor Q9, the tenth MOS transistor Q10, the eleventh MOS transistor Q11, the twelfth MOS transistor Q12, the thirteenth MOS transistor Q13, the fourteenth MOS transistor Q14, the fifteenth MOS transistor Q15, the sixteenth MOS transistor Q16, the seventeenth MOS transistor Q17, the eighteenth MOS transistor Q18, the nineteenth MOS transistor Q19, the twentieth MOS transistor Q20, the twenty-first MOS transistor Q21, the twenty-second MOS transistor Q22, the twenty-third MOS transistor Q23, the twenty-fourth MOS transistor Q24, the twenty-fifth MOS transistor Q25, the twenty-sixth MOS transistor Q26, the twenty-seventh MOS transistor Q27, the twenty-eighth MOS transistor Q28, the twenty-ninth MOS transistor Q29, the thirtieth MOS transistor Q30, the thirty-first MOS transistor Q31, the thirty-second MOS transistor Q32, the thirty-third MOS transistor Q33, and the thirty-fourth MOS transistor Q34. The first MOS transistor Q1, the fourth MOS transistor Q4, the fifth MOS transistor Q5, the seventh MOS transistor Q7, the eighth MOS transistor Q8, the ninth MOS transistor Q9, the tenth MOS transistor Q10, the twenty-first MOS transistor Q21, the twenty-second MOS transistor Q22, the twenty-fifth MOS transistor Q25, the twenty-sixth MOS transistor Q26, the twenty-eighth MOS transistor Q28, the twenty-ninth MOS transistor Q29, the thirtieth MOS transistor Q30, the thirty-second MOS transistor Q32, the thirty-third MOS transistor Q33, and the thirty-fourth MOS transistor Q34 are all NMOS transistors, and the second MOS transistor Q2, the third MOS transistor Q3, the sixth MOS transistor Q6, the eleventh MOS transistor Q11, the twelfth MOS transistor Q12, the thirteenth MOS transistor Q13, the fourteenth MOS transistor Q14, the fifteenth MOS transistor Q15, the sixteenth MOS transistor Q16, the seventeenth MOS transistor Q17, the eighteenth MOS transistor Q18, the nineteenth MOS transistor Q19, the twentieth MOS transistor Q20, the twenty-third MOS transistor Q23, the twenty-fourth MOS transistor Q24, the twenty-seventh MOS transistor Q27, and the thirty-first MOS transistor Q31 are all PMOS transistors; the drain of the first MOS transistor Q1, the source of the third MOS transistor Q3, the drain of the fourth MOS transistor Q4, the drain of the seventh MOS transistor Q7, the drain of the ninth MOS transistor Q9, the source of the twelfth MOS transistor Q12, the source of the thirteenth MOS transistor Q13, the source of the nineteenth MOS transistor Q19, the source of the twenty-third MOS transistor Q23, the source of the twenty-seventh MOS transistor Q27, and the source of the thirty-first MOS transistor Q31 are all connected to the power supply voltage; the gate and source of the first MOS transistor Q1, the gate and source of the second MOS transistor Q2, and the gate of the third MOS transistor Q3 are connected,The drains of the second MOS transistor Q2, the sixth MOS transistor Q6, one end of the first resistor R1, the drain of the eleventh MOS transistor Q11, the drain of the twelfth MOS transistor Q12, the source of the twenty-second MOS transistor Q22, the source of the twenty-sixth MOS transistor Q26, the source of the thirtieth MOS transistor Q30, and the source of the thirty-fourth MOS transistor Q34 are all grounded; the drain of the third MOS transistor Q3, the source of the fifth MOS transistor Q5, and the source of the sixth MOS transistor Q6 are connected, the source of the fourth MOS transistor Q4 and the drain of the fifth MOS transistor Q5 are connected, the gates of the fourth MOS transistor Q4, the seventh MOS transistor Q7, the ninth MOS transistor Q9, the thirteenth MOS transistor Q13, the twentieth MOS transistor Q20, and the twenty-fourth MOS transistor Q24 are connected, the gates of the fifth MOS transistor Q5, the eighth MOS transistor Q8, the tenth MOS transistor Q10, the fourteenth MOS transistor Q14, the twenty-first MOS transistor Q21, and the twenty-fifth MOS transistor Q25 are connected, the gate of the sixth MOS transistor Q6, the other end of the first resistor R1, the source of the eighth MOS transistor Q8, the gate of the twenty-second MOS transistor Q22, the gate of the twenty-sixth MOS transistor Q26, the gate of the thirtieth MOS transistor Q30, and the gate of the thirty-fourth MOS transistor Q34 are connected, the source of the seventh MOS transistor Q7 and the drain of the eighth MOS transistor Q8 are connected, the source of the ninth MOS transistor Q9 and the drain of the tenth MOS transistor Q10 are connected, the source of the tenth MOS transistor Q10, the source and gate of the eleventh MOS transistor Q11, and the gate of the twelfth MOS transistor Q12 are connected, the drain of the thirteenth MOS transistor Q13 and the source of the fourteenth MOS transistor Q14 are connected, the drain of the fourteenth MOS transistor Q14, the source of the fifteenth MOS transistor Q15, and the source of the seventeenth MOS transistor Q17 are connected, the gate of the fifteenth MOS transistor Q15 and the gate of the sixteenth MOS transistor Q16 are connected, and their connection terminal is the non-inverting input terminal of the operational amplifier, the drain of the fifteenth MOS transistor Q15 and the source of the sixteenth MOS transistor Q16 are connected, the drain of the sixteenth MOS transistor Q16, the source of the twenty-first MOS transistor Q21, and the drain of the twenty-second MOS transistor Q22 are connected, the drain of the seventeenth MOS transistor Q17 and the source of the eighteenth MOS transistor Q18 are connected, the gate of the seventeenth MOS transistor Q17 and the gate of the eighteenth MOS transistor Q18 are connected, and their connection terminal is the inverting input terminal of the operational amplifier, the drain of the eighteenth MOS transistor Q18, the source of the twenty-fifth MOS transistor Q25, and the drain of the twenty-sixth MOS transistor Q26 are connected, the gates of the nineteenth MOS transistor Q19, the twenty-third MOS transistor Q23, the drain of the twenty-ninth MOS transistor Q29, the drain of the thirty-second MOS transistor Q32, and the gate and drain of the thirty-first MOS transistor Q31 are connected, the drain of the nineteenth MOS transistor Q19 and the source of the twentieth MOS transistor Q20 are connected,The drain of the twentieth MOS transistor Q20, the drain of the twenty-first MOS transistor Q21, and the gate of the thirty-third MOS transistor Q33 are connected, and the connection terminal is the negative output terminal of the operational amplifier. The drain of the twenty-third MOS transistor Q23 and the source of the twenty-fourth MOS transistor Q24 are connected. The drain of the twenty-fourth MOS transistor, the drain of the twenty-fifth MOS transistor Q25, and the gate of the twenty-eighth MOS transistor Q28 are connected, and the connection terminal is the positive output terminal of the operational amplifier. The gate and drain of the twenty-seventh MOS transistor Q27, the drain of the twenty-eighth MOS transistor Q28, and the drain of the thirty-third MOS transistor Q33 are connected. The source of the twenty-eighth MOS transistor Q28, the source of the twenty-ninth MOS transistor, and the drain of the thirtieth MOS transistor Q30 are connected. The gate of the twenty-ninth MOS transistor Q29 and the gate of the thirty-second MOS transistor Q32 are connected. The source of the thirty-second MOS transistor Q32, the source of the thirty-third MOS transistor Q33, and the drain of the thirty-fourth MOS transistor Q34 are connected.,

[0051] In this embodiment, the first MOS transistor Q1, the second MOS transistor Q2 and the third MOS transistor Q3 form a startup circuit, the first resistor R1, the fourth MOS transistor Q4, the fifth MOS transistor Q5, the sixth MOS transistor Q6, the seventh MOS transistor Q7, the eighth MOS transistor Q8, the ninth MOS transistor Q9, the tenth MOS transistor Q10, the eleventh MOS transistor Q11 and the twelfth MOS transistor Q12 form a bias circuit, the thirteenth MOS transistor Q13, the fourteenth MOS transistor Q14, the fifteenth MOS transistor Q15, the sixteenth MOS transistor Q16, the seventeenth MOS transistor Q17 and the eighteenth MOS transistor Q18 form a bias circuit. 8. The nineteenth MOS tube Q19, the twentieth MOS tube Q20, the twenty-first MOS tube Q21, the twenty-second MOS tube Q22, the twenty-third MOS tube Q23, the twenty-fourth MOS tube Q24, the twenty-fifth MOS tube Q25 and the twenty-sixth MOS tube Q26 constitute a main operational amplifier circuit, and the twenty-seventh MOS tube Q27, the twenty-eighth MOS tube Q28, the twenty-ninth MOS tube Q29, the thirtieth MOS tube Q30, the thirty-first MOS tube Q31, the thirty-second MOS tube Q32, the thirty-third MOS tube Q33 and the thirty-fourth MOS tube Q34 constitute a common-mode feedback circuit. Under the action of the startup circuit and the bias circuit, the signals connected to the in-phase input and inverting input of the operational amplifier are sent to the main operational amplifier circuit, which amplifies the signals input to the in-phase input and inverting input of the operational amplifier, and adjusts the difference between the two signals and outputs them to the common-mode feedback circuit. The common-mode feedback circuit further processes the signal to ensure the quality of the output signal. The main operational amplifier circuit and the common-mode feedback circuit realize signal modulation and gain adjustment. The modulated and gain-adjusted signal is finally output through the positive output and negative output of the operational amplifier. The function of the startup circuit is to ensure that the operational amplifier can smoothly enter the working state after power-on. In this operational amplifier, the first MOS tube Q1, the second MOS tube Q2 and the third MOS tube Q3 play an initialization role to help the operational amplifier circuit enter a stable state. In actual use, the voltage connected to the in-phase input and inverting input of the operational amplifier ensures the appropriate working point through the switching of the first switch S1 and the second switch S2 during the startup process. The bias circuit is responsible for providing an appropriate static working voltage to ensure that each part of the operational amplifier works in the best state. The fourth MOS tube Q4, the fifth MOS tube Q5, the sixth MOS tube Q6, the seventh MOS tube Q7, the eighth MOS tube Q8, the ninth MOS tube Q9, the tenth MOS tube Q10, the eleventh MOS tube Q11, the twelfth MOS tube Q12 and the first resistor R1 adjust the static operating point of the operational amplifier to ensure the gain, stability and linearity of the signal.The connection terminals of the gates of the fourth MOS transistor Q4, the seventh MOS transistor Q7, the ninth MOS transistor Q9, the thirteenth MOS transistor Q13, the twentieth MOS transistor Q20, and the twenty-fourth MOS transistor Q24 generate a first bias voltage Vb1. The connection terminals of the gates of the fifth MOS transistor Q5, the eighth MOS transistor Q8, the tenth MOS transistor Q10, the fourteenth MOS transistor Q14, the twenty-first MOS transistor Q21, and the twenty-fifth MOS transistor Q25 generate a second bias voltage Vb2. The connection terminals of the gates of the sixth MOS transistor Q6, the other end of the first resistor R1, the source of the eighth MOS transistor Q8, the gate of the twenty-second MOS transistor Q22, the gate of the twenty-sixth MOS transistor Q26, the gate of the thirtieth MOS transistor Q30, and the gate of the thirty-fourth MOS transistor Q34 generate a third bias voltage Vb3. The bias voltages Vb1, Vb2, and Vb3 provide appropriate bias voltages for different parts of the bias circuit. The main operational amplifier circuit is responsible for amplifying the signals applied to the non-inverting input terminal and the inverting input terminal of the operational amplifier (i.e., the differential signal between the non-inverting input terminal and the inverting input terminal of the operational amplifier). Through feedback path and reference voltage control, the main operational amplifier circuit realizes the differential amplification of the input signal. Each transistor in the main operational amplifier circuit provides the ability of high gain and high-precision amplification. The signal Vout output from the positive output terminal of the operational amplifier is feedback-regulated to maintain the gain and stability of the operational amplifier. The common-mode feedback circuit is used to regulate the common-mode signal to ensure that the processing of the input differential signal is not affected by external noise. The twenty-seventh MOS transistor Q27, the twenty-eighth MOS transistor Q28, the twenty-ninth MOS transistor Q29, the thirtieth MOS transistor Q30, the thirty-first MOS transistor Q31, the thirty-second MOS transistor Q32, the thirty-third MOS transistor Q33, and the thirty-fourth MOS transistor Q34 adjust the common-mode part of the output signal, thereby improving the anti-interference ability of the signal. The common-mode feedback circuit avoids errors caused by common-mode noise through dynamic regulation, ensuring the high precision and stability of the operational amplifier.

[0052] This operational amplifier has the following characteristics:

[0053] I. Low noise and high precision: This operational amplifier effectively suppresses common-mode noise through the common-mode feedback circuit, ensuring low-noise amplification. This is crucial for precision measurement applications (such as the processing of quartz gyro signals) and can improve the signal-to-noise ratio in high-precision measurements.

[0054] II. High gain and stability: The main operational amplifier circuit realizes high-gain amplification and controls the gain and stability through the feedback loop. This makes this operational amplifier suitable for processing tiny sensor signals and ensures reliable amplification even in low-signal situations.

[0055] III. Power Consumption Optimization: By optimizing the distribution of current and voltage, the startup circuit and the bias circuit reduce power consumption waste, making it particularly suitable for low-power application scenarios such as wearable devices or portable systems.

[0056] IV. Precise Operating Point Control: Through multiple bias voltages (such as bias voltages Vb1, Vb2, Vb3), the operating point of the operational amplifier can be precisely controlled to ensure high-precision signal amplification under different operating environments, meeting the performance requirements of high-precision sensors (such as quartz gyroscopes).

[0057] V. Suitable for Sensor Interfaces: This circuit is particularly suitable for interface circuits with sensors such as quartz gyroscopes. It can effectively process weak sensor output signals and has good common-mode rejection characteristics, making it perform excellently in applications such as high-precision navigation systems.

[0058] Embodiment 8: This embodiment is basically the same as Embodiment 6, except that: in this embodiment, as Figure 8 shown, the electronic switch includes 6 MOS transistors, which are respectively referred to as the thirty-fifth MOS transistor Q35, the thirty-sixth MOS transistor Q36, the thirty-seventh MOS transistor Q37, the thirty-eighth MOS transistor Q38, the thirty-ninth MOS transistor Q39, and the fortieth MOS transistor Q40. The thirty-fifth MOS transistor Q35, the thirty-sixth MOS transistor Q36, and the thirty-seventh MOS transistor Q37 are all NMOS transistors, and the thirty-eighth MOS transistor Q38, the thirty-ninth MOS transistor Q39, and the fortieth MOS transistor Q40 are all PMOS transistors. The source and drain of the thirty-fifth MOS transistor Q35, the source of the thirty-sixth MOS transistor Q36, the source and drain of the thirty-eighth MOS transistor Q38, and the source of the thirty-ninth MOS transistor Q39 are connected, and their connection end is the first end of the electronic switch. The gates of the thirty-fifth MOS transistor Q35, the thirty-seventh MOS transistor Q37, and the thirty-ninth MOS transistor Q39 are connected. The gates of the thirty-sixth MOS transistor Q36, the thirty-eighth MOS transistor Q38, and the fortieth MOS transistor Q40 are connected, and their connection end is the control end of the electronic switch. The drain of the thirty-sixth MOS transistor Q36, the source and drain of the thirty-seventh MOS transistor Q37, the drain of the thirty-ninth MOS transistor Q39, and the source and drain of the fortieth MOS transistor Q40 are connected, and their connection end is the second end of the electronic switch.

[0059] In this embodiment, the electronic switch adopts a six-transistor switch structure. The thirty-fifth MOS transistor Q35 and the thirty-eighth MOS transistor Q38 form a dual-NMOS parallel structure, and the thirty-seventh MOS transistor Q37 and the fortieth MOS transistor Q40 form a dual-PMOS parallel structure, which can significantly reduce the on-resistance and non-ideal effects of the electronic switch, thereby improving the switching accuracy of the circuit. By simultaneously using NMOS transistors and PMOS transistors, the six-transistor switch structure not only reduces the dependence of the on-resistance on the input signal amplitude, making the signal linearity higher and suitable for high-precision applications, but also can better resist the circuit characteristic changes caused by manufacturing process deviations. At the same time, when the electronic switch is turned off, the NMOS transistor and the PMOS transistor act simultaneously, providing a high impedance, thereby reducing the leakage current and further improving the performance. The addition of the thirty-sixth MOS transistor Q36 and the thirty-ninth MOS transistor Q39 can effectively cancel the clock feedthrough from the clock, thereby reducing the interference to the signal, which is particularly important in high-frequency applications. Thus, the electronic switch of this embodiment has stable performance under a wide range of signal voltages and can well meet the requirements of the Σ-Δ analog-to-digital converter for a wide dynamic range.

[0060] The noise of the digital closed-loop drive circuit of the quartz gyroscope of the present invention was tested. During the test, based on 65,536 data points captured by the quartz gyroscope, an Agilent 16804A logic analyzer was used for testing, and the power spectral density (PSD) was calculated. During the calculation process, the fast Fourier transform (FFT) was adopted and the Hamming window function was applied, and the spectrogram was obtained as Figure 9 shown. Analysis Figure 9 shows that: within the 15 kHz bandwidth range, the digital closed-loop drive circuit of the quartz gyroscope of the present invention achieves a signal-to-noise ratio (SNR) of 105.2 dB, while within the 1 kHz bandwidth, the signal-to-noise ratio is increased to 118.2 dB, and the noise floor is -140 dB. This indicates that the digital closed-loop drive circuit of the quartz gyroscope of the present invention can effectively suppress noise at different bandwidths and ensure the high quality of the signal. In the spectrogram, it can be observed that there is an obvious peak at about 1200 Hz, indicating the existence of significant signal components in this frequency band. The spectrogram also shows that in the higher frequency region exceeding 10^4 Hz, the noise level rises significantly, but the noise in the low-frequency region remains at a low level. Overall, this test verifies the excellent performance of the digital closed-loop drive circuit of the quartz gyroscope of the present invention in noise suppression and signal clarity, and is suitable for high-precision applications.

[0061] In summary, the digital closed-loop drive circuit of the quartz gyroscope of the present invention has the following characteristics:

[0062] I. High-precision drive: Through digital closed-loop control technology, higher drive precision than traditional analog circuits can be achieved. Digital signal processing can effectively reduce system errors and improve the stability and measurement accuracy of quartz gyroscopes.

[0063] II. Strong flexibility: By adopting a digital control system, it can be conveniently adjusted and optimized according to different working requirements, with high flexibility. Compared with traditional hardware circuits, the digital closed-loop drive circuit can quickly adjust parameters to adapt to different operating environments and application requirements.

[0064] III. Strong anti-interference ability: A variety of anti-interference measures, such as high-frequency signal filtering, signal differential transmission, noise suppression, etc., are added to the circuit design, thus effectively enhancing the resistance of the digital closed-loop drive circuit to external electromagnetic interference and noise.

[0065] IV. High system stability: Due to the adoption of a digital feedback mechanism, the entire digital closed-loop drive circuit can adjust and optimize the drive signal in real time, thereby improving the stability of the digital closed-loop drive circuit and maintaining reliable performance even in complex environments.

[0066] V. High integration and low cost: Compared with traditional analog circuits, the present invention can achieve efficient drive at a lower hardware cost, and has a high integration level, which can reduce the volume and design complexity.

Claims

1. A digital closed-loop drive circuit for a quartz gyroscope, characterized in that The invention comprises a charge amplifier circuit, a phase compensation circuit, a correlated double sampling circuit, a Σ-Δ analog-to-digital converter and a digital signal processing circuit. The charge amplifier circuit, the phase compensation circuit, the correlated double sampling circuit and the Σ-Δ analog-to-digital converter are respectively implemented by using a differential structure; the charge amplifier circuit is used to obtain in real time a charge signal generated by a charge change of the quartz gyroscope caused by vibration or acceleration, and convert the charge signal into an easily processable voltage signal, and output it to the phase compensation circuit; the phase compensation circuit is used to adjust the phase of the voltage signal outputted in real time by the charge amplifier circuit, so that the digital closed-loop drive circuit works in a negative feedback state, and obtain an adjusted voltage signal and output it to the correlated double sampling circuit; the correlated double sampling circuit is used to periodically adjust the phase compensation circuit The adjustment voltage signal outputted thereto by the correlated double sampling circuit is sampled, and the sampling is performed twice in succession in each cycle to obtain two sampled voltage signals, and then the two sampled voltage signals are subtracted to obtain a difference sampled voltage signal which is outputted to the Σ-Δ analog-to-digital converter to eliminate the sampling error caused by noise or interference; the Σ-Δ analog-to-digital converter is used to adopt high-frequency oversampling technology and noise shaping technology to convert the difference sampled voltage signal outputted thereto by the correlated double sampling circuit into a digital signal and output it to the digital signal processing circuit; the digital signal processing circuit is used to first filter the digital signal outputted thereto by the Σ-Δ analog-to-digital converter to obtain a filtered digital signal, and then convert the filtered digital signal into an analog signal and output it to the quartz gyroscope, and the analog signal is the driving signal, which is used to control the vibration frequency and amplitude of the quartz gyroscope.

2. A digital closed-loop driving circuit for a quartz gyroscope according to claim 1, characterized in that The charge amplifier circuit has a positive input terminal, a negative input terminal, a positive output terminal and a negative output terminal; the positive input terminal and the negative input terminal of the charge amplifier circuit are respectively connected to the quartz gyroscope, and are used to receive the charge signal generated by the charge change caused by vibration or acceleration of the quartz gyroscope, and the positive output terminal and the negative output terminal of the charge amplifier circuit are used to output the voltage signal; the phase compensation circuit has a positive input terminal, a negative input terminal, a positive output terminal and a negative output terminal, the positive input terminal of the phase compensation circuit is connected to the positive output terminal of the charge amplifier circuit, and the negative input terminal of the phase compensation circuit is connected to the negative output terminal of the charge amplifier circuit; the positive output terminal and the negative output terminal of the phase compensation circuit are used to output the adjustment voltage signal; the correlated double sampling circuit has a positive input terminal, a negative input terminal, a positive output terminal, a negative output terminal, a first reference terminal for accessing a positive reference voltage and a second reference terminal for accessing a negative reference voltage; the positive input terminal of the correlated double sampling circuit is connected to the positive output terminal of the phase compensation circuit, the negative input terminal of the correlated double sampling circuit is connected to the negative output terminal of the phase compensation circuit, and the positive output terminal and the negative output terminal of the correlated double sampling circuit are used to output a difference sampling voltage signal; the Σ-Δ analog-to-digital converter has a positive input terminal, a negative input terminal, a positive output terminal and a negative output terminal, the positive input terminal of the Σ-Δ analog-to-digital converter is connected to the positive output terminal of the correlated double sampling circuit, the negative input terminal of the Σ-Δ analog-to-digital converter is connected to the negative output terminal of the correlated double sampling circuit, and the positive output terminal and the negative output terminal of the Σ-Δ analog-to-digital converter are used to output a digital signal to the digital signal processing circuit.

3. A digital closed-loop driving circuit for a quartz gyroscope according to claim 2, characterized in that The correlated double sampling circuit includes eight electronic switches, each of which has a control terminal, a first terminal, and a second terminal. When the control terminal is connected to a high level, the first terminal and the second terminal are turned on, and when the control terminal is connected to a low level, the first terminal and the second terminal are turned off. The eight electronic switches are respectively referred to as a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, and an eighth switch. The first terminal of the first switch is connected to the first terminal of the eighth switch, and the connection terminal thereof is the first reference terminal of the correlated double sampling circuit. The first terminal of the second switch is connected to the first terminal of the seventh switch, and the connection terminal thereof is the second reference terminal of the correlated double sampling circuit. The first terminal of the fourth switch is the positive input terminal of the correlated double sampling circuit. The first terminal of the fifth switch is the negative input terminal of the correlated double sampling circuit. The second terminal of the first switch, the second terminal of the second switch, and the first terminal of the third switch are connected. The second terminal of the third switch is connected to the second terminal of the fourth switch, and the connection terminal thereof is the positive output terminal of the correlated double sampling circuit. The second terminal of the seventh switch, the second terminal of the eighth switch, and the first terminal of the sixth switch are connected. The second end of the first switch is connected to the second end of the fifth switch, and the connection end is the negative output end of the correlated double sampling circuit; the control ends of the first switch, the third switch, the fifth switch and the seventh switch are all connected to the first clock signal clk1, and the control ends of the second switch, the fourth switch, the sixth switch and the eighth switch are all connected to the second clock signal clk2. The first clock signal clk1 and the second clock signal clk2 have the same period and amplitude, but the phase difference is 90 degrees; in each clock cycle, the first clock signal clk1 first controls the first end and the second end of the first switch, the third switch, the fifth switch and the seventh switch to be turned on, the positive reference voltage is connected to the correlated double sampling circuit, the correlated double sampling circuit performs the first sampling, and the first sampling voltage signal is temporarily stored, and then the second clock signal clk2 controls the first end and the second end of the second switch, the fourth switch, the sixth switch and the eighth switch to be turned on, the negative reference voltage is connected to the correlated double sampling circuit, the correlated double sampling circuit performs the second sampling, and the second sampling voltage signal is temporarily stored, and then the first sampling voltage signal and the second sampling voltage signal are superimposed and subtracted to form a difference sampling voltage signal output.

4. A digital closed-loop driving circuit for a quartz gyroscope according to claim 2, characterized in that The Σ-Δ analog-to-digital converter includes twenty capacitors, three operational amplifiers, twenty-seven electronic switches and a quantizer, the twenty capacitors are respectively referred to as a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, a fourteenth capacitor, a fifteenth capacitor, a sixteenth capacitor, a seventeenth capacitor, an eighteenth capacitor, a nineteenth capacitor and a twentieth capacitor, the operational amplifier has a non-inverting input terminal, an inverting input terminal, a positive output terminal and a negative output terminal, the three operational amplifiers are respectively referred to as a first operational amplifier, a second operational amplifier and a third operational amplifier, the twenty-eight electronic switches are respectively referred to as a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a thirteenth switch, a fourteenth switch, a fifteenth switch, a sixteenth switch, a seventeenth switch, an eighteenth switch, a nineteenth switch, a twentieth switch, a twenty-first switch, a twenty-second switch, a twenty-third switch, a twenty-fourth switch, a twenty-fifth switch, a twenty-sixth switch, a twenty-seventh switch, a twenty-eighth switch, a twenty-ninth switch, a thirtieth switch, a thirty-first switch, a thirty-second switch, a thirty-third switch, a thirty-fourth switch, a thirty-fifth switch and a thirty-sixth switch, wherein the quantizer has a positive input terminal, a negative input terminal, a positive output terminal and a negative output terminal; one end of the first capacitor is connected to one end of the third capacitor, and the connection end thereof is the positive input terminal of the Σ-Δ analog-to-digital converter, and the second capacitor One end of the first capacitor is connected to one end of the sixth capacitor, and the connection end is the negative input end of the Σ-Δ analog-to-digital converter, the other end of the first capacitor, the first end of the ninth switch and the first end of the tenth switch are connected, the second end of the ninth switch is grounded, the second end of the tenth switch, one end of the fourth capacitor and the non-inverting input end of the first operational amplifier are connected, the other end of the fourth capacitor, the positive output end of the first operational amplifier and the first end of the thirteenth switch are connected, the second end of the thirteenth switch, the first end of the fifteenth switch, one end of the seventh capacitor and one end of the ninth capacitor are connected, the second end of the fifteenth switch is grounded, the other end of the seventh capacitor, the The first end of the seventeenth switch is connected to the first end of the eighteenth switch, the second end of the seventeenth switch is grounded, the second end of the eighteenth switch and one end of the tenth capacitor are connected to the non-inverting input end of the second operational amplifier, the other end of the tenth capacitor and the positive output end of the second operational amplifier are connected to the first end of the twenty-second switch, the second end of the twenty-second switch, the first end of the twenty-first switch, one end of the thirteenth capacitor and one end of the fifteenth capacitor are connected, the second end of the twenty-first switch is grounded, the other end of the thirteenth capacitor, the first end of the twenty-fifth switch and the first end of the twenty-sixth switch are connected, and the second end of the twenty-fifth switch is grounded.The second end of the twenty-sixth switch, one end of the sixteenth capacitor and the non-inverting input end of the third operational amplifier are connected, the other end of the sixteenth capacitor, the positive output end of the third operational amplifier and the first end of the thirtieth switch are connected, the second end of the thirtieth switch, the first end of the twenty-ninth switch and one end of the nineteenth capacitor are connected, the second end of the twenty-ninth switch is grounded, the other end of the nineteenth capacitor, the first end of the thirty-third switch, the first end of the thirty-fifth switch, the other end of the third capacitor, the other end of the ninth capacitor and the other end of the fifteenth capacitor are connected, the second end of the thirty-third switch is grounded, the second end of the thirty-fifth switch and The positive input end of the quantizer is connected, the positive output end of the quantizer is the negative output end of the Σ-Δ analog-to-digital converter, the other end of the second capacitor, the first end of the twelfth switch and the first end of the eleventh switch are connected, the second end of the twelfth switch is grounded, the second end of the eleventh switch, one end of the fifth capacitor and the inverting input end of the first operational amplifier are connected, the other end of the fifth capacitor, the negative output end of the first operational amplifier and the first end of the fourteenth switch are connected, the second end of the fourteenth switch, the first end of the sixteenth switch, one end of the eighth capacitor and one end of the twelfth capacitor are connected, the second end of the sixteenth switch is grounded, and the eighth capacitor is connected. The other end of the capacitor, the first end of the twentieth switch and the first end of the nineteenth switch are connected, the second end of the twentieth switch is grounded, the second end of the nineteenth switch, one end of the eleventh capacitor and the inverting input end of the second operational amplifier are connected, the other end of the eleventh capacitor, the negative output end of the second operational amplifier and the first end of the twenty-third switch are connected, the second end of the twenty-third switch, the first end of the twenty-fourth switch, one end of the fourteenth capacitor and one end of the eighteenth capacitor are connected, the second end of the twenty-fourth switch is grounded, the other end of the fourteenth capacitor, the first end of the twenty-eighth switch and the first end of the twenty-seventh switch are connected, and the second end of the twenty-third switch, the first end of the twenty-fourth switch, one end of the fourteenth capacitor and one end of the eighteenth capacitor are connected. The second end of the eighteenth switch is grounded, the second end of the twenty-seventh switch, one end of the seventeenth capacitor and the inverting input end of the third operational amplifier are connected, the other end of the seventeenth capacitor, the negative output end of the third operational amplifier and the first end of the thirty-first switch are connected, the second end of the thirty-first switch, the first end of the thirty-second switch and one end of the twentieth capacitor are connected, the second end of the thirty-second switch is grounded, the other end of the twentieth capacitor, the first end of the thirty-fourth switch, the first end of the thirty-sixth switch, the other end of the sixth capacitor, the other end of the twelfth capacitor and the other end of the eighteenth capacitor are connected, and the second end of the thirty-fourth switch is grounded.The second end of the thirty-sixth switch is connected to the negative input end of the quantizer, the negative output end of the quantizer is the positive output end of the Σ-Δ analog-to-digital converter, the ninth switch, the eleventh switch, the thirteenth switch, the fifteenth switch, the seventeenth switch, the nineteenth switch, the twenty-first switch, the twenty-third switch, the twenty-fifth switch, the twenty-seventh switch, the twenty-ninth switch, the thirty-first switch, the thirty-third switch and the thirty-fifth switch are all connected to the third clock signal clk3, and the tenth switch, the twelfth switch, the fourteenth switch, the sixteenth switch, the eighteenth switch, the twentieth switch, the twenty-second switch, the twenty-fourth switch, the twenty-sixth switch, the twenty-eighth switch, the thirtieth switch, the thirty-second switch The control ends of the switch, the thirty-fourth switch and the thirty-sixth switch are all connected to the fourth clock signal clk4. The third clock signal clk3 is the same as the first clock signal clk1. The fourth clock signal clk4 is the same as the second clock signal clk2. The third clock signal clk3 is used as a Σ-Δ conversion clock to control the oversampling process of the Σ-Δ analog-to-digital converter. When the third clock signal clk3 is at a high level, the Σ-Δ analog-to-digital converter starts to oversample the input analog signal and convert the analog signal into a digital form. The oversampling technology reduces quantization noise and improves resolution by sampling the analog signal at a rate higher than the Nyquist sampling rate; the fourth clock signal clk4 is a digital clock, which is used to control the sampling and data transmission of the output digital signal to ensure that the converted digital signal is read and stored in time. When the fourth clock signal clk4 is at a high level, the digital signal is transmitted to the subsequent digital signal processing circuit. , 5. A digital closed-loop driving circuit for a quartz gyroscope according to claim 4, characterized in that The charge amplifier circuit includes an operational amplifier, two capacitors and four electronic switches, the operational amplifier is called a fourth operational amplifier, the two capacitors are respectively called a twenty-first capacitor and a twenty-second capacitor, and the four electronic switches are respectively called a thirty-seventh switch, a thirty-eighth switch, a thirty-ninth switch and a fortieth switch; the first end of the thirty-seventh switch is the positive input end of the charge amplifier circuit, the first end of the thirty-eighth switch is the negative input end of the charge amplifier circuit, the second end of the thirty-seventh switch, the first end of the thirty-ninth switch, one end of the twenty-first capacitor and the inverting input end of the fourth operational amplifier are connected, the second end of the thirty-ninth switch, the first end of the thirty-eighth switch, and one end of the twenty-first capacitor are connected to the inverting input end of the fourth operational amplifier, and the second end of the thirty-ninth switch, the first end of the thirty-third switch, and the first end of the thirty-third switch are connected to the inverting input end of the fourth operational amplifier. The other end of the twenty-first capacitor is connected to the negative output end of the fourth operational amplifier, and the connection end thereof is the negative output end of the charge amplifier circuit; the second end of the thirty-eighth switch, the first end of the fortieth switch, and one end of the twenty-second capacitor are connected to the non-inverting input end of the fourth operational amplifier, the second end of the fortieth switch, the other end of the twenty-second capacitor are connected to the positive output end of the fourth operational amplifier, and the connection end thereof is the positive output end of the charge amplifier circuit; the control ends of the thirty-seventh switch and the thirty-ninth switch are connected to the first clock signal clk1, and the control ends of the thirty-eighth switch and the fortieth switch are connected to the second clock signal clk2.

6. A digital closed-loop driving circuit for a quartz gyroscope according to claim 5, characterized in that The phase compensation circuit includes an operational amplifier, six capacitors and sixteen electronic switches, the operational amplifier is called a fifth operational amplifier, the six capacitors are respectively called a twenty-third capacitor, a twenty-fourth capacitor, a twenty-fifth capacitor, a twenty-sixth capacitor, a twenty-seventh capacitor and a twenty-eighth capacitor, the sixteen electronic switches are respectively called a forty-first switch, a forty-second switch, a forty-third switch, a forty-fourth switch, a forty-fifth switch, a forty-sixth switch, a forty-seventh switch, a forty-eighth switch, a forty-ninth switch, a fiftieth switch, a fifty-first switch, a fifty-second switch, a fifty-third switch, a fifty-fourth switch, a fifty-fifth switch and a fifty-sixth switch; the first end of the forty-first switch is the phase compensation circuit The positive input end of the circuit, the second end of the forty-first switch, the first end of the forty-second switch, one end of the twenty-third capacitor and one end of the twenty-fourth capacitor are connected, the second end of the forty-second switch is grounded, the other end of the twenty-third capacitor, the first end of the forty-seventh switch and the first end of the forty-eighth switch are connected, the second end of the forty-eighth switch is grounded, the other end of the twenty-fourth capacitor, the first end of the forty-fifth switch and the first end of the forty-ninth switch are connected, the second end of the forty-fifth switch is grounded, the second end of the forty-seventh switch, the second end of the forty-ninth switch, the first end of the fifty-third switch, One end of the twenty-seventh capacitor is connected to the inverting input end of the fifth operational amplifier, the second end of the fifty-third switch, the other end of the twenty-seventh capacitor, and the first end of the fifty-fifth switch are connected to the positive output end of the fifth operational amplifier, and the second end of the fifty-fifth switch is the negative output end of the phase compensation circuit; the first end of the forty-third switch is the negative input end of the phase compensation circuit, the second end of the forty-third switch, the first end of the forty-fourth switch, one end of the twenty-fifth capacitor and one end of the twenty-sixth capacitor are connected, the second end of the forty-fourth switch is grounded, the other end of the twenty-fifth capacitor, the first end of the fiftieth switch and the The first end of the fifty-first switch is connected, the second end of the fifty-first switch is grounded, the other end of the twenty-sixth capacitor, the first end of the forty-sixth switch and the first end of the fifty-second switch are connected, the second end of the forty-sixth switch is grounded, the second end of the fiftieth switch, the second end of the fifty-second switch, the first end of the fifty-fourth switch, one end of the twenty-eighth capacitor and the non-inverting input terminal of the fifth operational amplifier are connected, the second end of the fifty-fourth switch, the other end of the twenty-eighth capacitor, the first end of the fifty-sixth switch and the negative output terminal of the fifth operational amplifier are connected, and the second end of the fifty-sixth switch is the positive output terminal of the phase compensation circuit;The control ends of the 41st switch, the 43rd switch, the 45th switch, the 47th switch, the 49th switch, the 51st switch, the 53rd switch and the 55th switch are all connected to the first clock signal clk1, and the control ends of the 42nd switch, the 44th switch, the 46th switch, the 48th switch, the 50th switch, the 52nd switch, the 54th switch and the 56th switch are all connected to the second clock signal clk2.; 7. A digital closed-loop driving circuit for a quartz gyroscope according to any one of claims 4 to 6, characterized in that The operational amplifier includes 34 MOS tubes and a resistor, the resistor is called a first resistor, and the 34 MOS tubes are respectively called a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, a nineteenth MOS tube, a twentieth MOS tube, a twenty-first MOS tube, a twenty-second MOS tube, a twenty-third MOS tube, a twenty-fourth MOS tube The 25th MOS tube, the 26th MOS tube, the 27th MOS tube, the 28th MOS tube, the 29th MOS tube, the 30th MOS tube, the 31st MOS tube, the 32nd MOS tube, the 33rd MOS tube and the 34th MOS tube, the first MOS tube, the fourth MOS tube, the fifth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, the tenth MOS tube, the 21st MOS tube, the 22nd MOS tube, the 25th MOS tube, the 26th MOS tube, the 28th MOS tube, the 29th MOS tube, the 30th MOS tube, the 32nd MOS tube, the 33rd MOS tube and the 34th MOS tube are all NMOS tubes, the second MOS tube, the third MOS tube, the sixth MOS tube, the 11th MOS tube, the 12th MOS tube, the 13th MOS tube, the 14th MOS tube, the fifteenth MOS tube, the sixteenth MOS tube, the seventeenth MOS tube, the eighteenth MOS tube, the nineteenth MOS tube, the 20th MOS tube, the twenty-third MOS tube, the twenty-fourth MOS tube, the twenty-seventh MOS tube The OS tube and the thirty-first MOS tube are both PMOS tubes; the drain of the first MOS tube, the source of the third MOS tube, the drain of the fourth MOS tube, the drain of the seventh MOS tube, the drain of the ninth MOS tube, the source of the twelfth MOS tube, the source of the thirteenth MOS tube, the source of the nineteenth MOS tube, the source of the twenty-third MOS tube, the source of the twenty-seventh MOS tube and the source of the thirty-first MOS tube are all connected to the power supply voltage; the gate and source of the first MOS tube, the gate and source of the second MOS tube and the gate of the third MOS tube are connected,The drain of the second MOS tube, the drain of the sixth MOS tube, one end of the first resistor, the drain of the eleventh MOS tube, the drain of the twelfth MOS tube, the source of the twenty-second MOS tube, the source of the twenty-sixth MOS tube, the source of the thirtieth MOS tube and the source of the thirty-fourth MOS tube are all grounded; the drain of the third MOS tube, the source of the fifth MOS tube and the source of the sixth MOS tube are connected, the source of the fourth MOS tube and the drain of the fifth MOS tube are connected, the gate of the fourth MOS tube, the gate of the seventh MOS tube, the gate of the ninth MOS tube, the gate of the thirteenth MOS tube are connected. The gate of the S tube, the gate of the twentieth MOS tube and the gate of the twenty-fourth MOS tube are connected, the gate of the fifth MOS tube, the gate of the eighth MOS tube, the gate of the tenth MOS tube, the gate of the fourteenth MOS tube, the gate of the twenty-first MOS tube and the gate of the twenty-fifth MOS tube are connected, the gate of the sixth MOS tube, the other end of the first resistor, the source of the eighth MOS tube, the gate of the twenty-second MOS tube, the gate of the twenty-sixth MOS tube, the gate of the thirtieth MOS tube and the gate of the thirty-fourth MOS tube are connected, the source of the seventh MOS tube and the gate of the eighth MOS tube The drain of the ninth MOS tube is connected to the drain of the tenth MOS tube, the source of the tenth MOS tube, the source and gate of the eleventh MOS tube, and the gate of the twelfth MOS tube are connected, the drain of the thirteenth MOS tube is connected to the source of the fourteenth MOS tube, the drain of the fourteenth MOS tube, the source of the fifteenth MOS tube, and the source of the seventeenth MOS tube are connected, the gate of the fifteenth MOS tube is connected to the gate of the sixteenth MOS tube, and the connection end thereof is the in-phase input end of the operational amplifier, the drain of the fifteenth MOS tube is connected to the source of the sixteenth MOS tube, and the sixteenth MOS The drain of the 21st MOS tube is connected, the source of the 21st MOS tube is connected to the drain of the 22nd MOS tube, the drain of the 17th MOS tube is connected to the source of the 18th MOS tube, the gate of the 17th MOS tube is connected to the gate of the 18th MOS tube, and the connection end thereof is the inverting input end of the operational amplifier, the drain of the 18th MOS tube, the source of the 25th MOS tube and the drain of the 26th MOS tube are connected, the gate of the 19th MOS tube, the gate of the 23rd MOS tube, the drain of the 29th MOS tube, the drain of the 32nd MOS tube, and the gate and drain of the 31st MOS tube are connected,The drain of the nineteenth MOS tube is connected to the source of the twentieth MOS tube, the drain of the twentieth MOS tube, the drain of the twenty-first MOS tube and the gate of the thirty-third MOS tube are connected, and the connection end thereof is the negative output end of the operational amplifier, the drain of the twenty-third MOS tube is connected to the source of the twenty-fourth MOS tube, the drain of the twenty-fourth MOS tube, the drain of the twenty-fifth MOS tube and the gate of the twenty-eighth MOS tube are connected, and the connection end thereof is the positive output end of the operational amplifier, the gate and drain of the twenty-seventh MOS tube, the drain of the twenty-eighth MOS tube and the drain of the thirty-third MOS tube are connected, the source of the twenty-eighth MOS tube, the source of the twenty-ninth MOS tube and the drain of the thirtieth MOS tube are connected, the gate of the twenty-ninth MOS tube and the gate of the thirty-second MOS tube are connected, and the source of the thirty-second MOS tube, the source of the thirty-third MOS tube and the drain of the thirty-fourth MOS tube are connected.

8. A digital closed-loop driving circuit for a quartz gyroscope according to any one of claims 3 to 6, characterized in that The electronic switch includes six MOS tubes, which are respectively referred to as a thirty-fifth MOS tube, a thirty-sixth MOS tube, a thirty-seventh MOS tube, a thirty-eighth MOS tube, a thirty-ninth MOS tube and a fortieth MOS tube. The thirty-fifth MOS tube, the thirty-sixth MOS tube and the thirty-seventh MOS tube are all NMOS tubes, the thirty-eighth MOS tube, the thirty-ninth MOS tube and the fortieth MOS tube are all PMOS tubes, and the source and drain of the thirty-fifth MOS tube, the source of the thirty-sixth MOS tube, the source and drain of the thirty-eighth MOS tube and the thirty-ninth MOS tube are all PMOS tubes. The source of the MOS tube is connected, and the connection end thereof is the first end of the electronic switch, the gate of the thirty-fifth MOS tube, the gate of the thirty-seventh MOS tube and the gate of the thirty-ninth MOS tube are connected, the gate of the thirty-sixth MOS tube, the gate of the thirty-eighth MOS tube and the gate of the fortieth MOS tube are connected, and the connection end thereof is the control end of the electronic switch, the drain of the thirty-sixth MOS tube, the source and drain of the thirty-seventh MOS tube, the drain of the thirty-ninth MOS tube and the source and drain of the fortieth MOS tube are connected, and the connection end thereof is the second end of the electronic switch.

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