DFE-based peaking techniques for high speed transmitters

Abstract

The present disclosure provides DFE-based peaking techniques for high speed transmitters. A circuit for driving a digital-to-analog converter (DAC) includes a serializer configured to combine a plurality of signals into one input signal to drive a forward inverter coupled to a first node having a first impedance in a series configuration and a first capacitance in a shunt configuration. The circuit includes inverter chains coupled in series to transfer the input signal from the first node to a fifth node based on a signal transfer function. The circuit further includes a feedback inverter between a third node and the first node at which a peak in the signal transfer function is added to form a feedback loop having two inverters in the chain. A second feedback inverter may be added between the fifth node and the third node to add a peak in the signal transfer function at the third node.

Description

Technical Field

[0001] The present subject matter relates to an apparatus for supporting high-speed data transmission. Background Art

[0002] In the field of high-speed data transmission circuitry, the tailless CML DAC driver emerged as an evolution of the traditional current-mode logic (CML) topology that is customized to drive a digital-to-analog converter (DAC) at high speed. This design is particularly applicable in high-performance applications such as wired communications, data centers, and advanced RF communication systems. In applications where data rates reach several Gbps or even dozens or hundreds of Gbps, maintaining signal integrity is crucial. The tailless CML DAC driver in a high-speed transmitter typically constructs an architecture consisting of an array of DAC slices, each of which consists of an input source switch and a current source, a serializer configured to minimize clock load and power, and a full-rate pre-driver for bridging the fan-out between the serializer and the switch. The pre-driver is typically implemented using a CMOS inverter chain, which consists of complementary metal-oxide-semiconductor field-effect transistor pairs between the serializer and the switch. Signal bandwidth is typically the bottleneck for the full-rate operation of a high-speed transmitter. Improved techniques for expanding the bandwidth of the CMOS inverter chain are desired. Summary of the Invention

[0003] In one aspect, the present disclosure provides a circuit, comprising: a serializer configured to combine a plurality of signals into one input signal to drive a forward inverter, the forward inverter being coupled to a first node and characterized by a first impedance in series configuration and a first capacitor in parallel configuration; an inverter chain serially coupled from the first node to an mth node, wherein each nth inverter follows the nth node and is configured to transmit the input signal to the last node based on a signal transfer function, where n is an integer variable from 1 to m; a first feedback inverter coupled from at least a third node along the chain to the first node to form a first feedback loop, the first feedback loop including two inverters after the first node and configured to increase bandwidth by adding a peak response of the signal transfer function at the first node and the third node; and a switch coupled to the mth node.

[0004] In another aspect, the present disclosure provides an apparatus comprising: an input inverter configured to receive an input signal from an output of a transmitter stage, the input inverter having a first output impedance coupled in series to a first node and a first capacitor coupled in parallel to the first node; a plurality of inverters coupled in a serial chain and configured to drive the input signal based on a signal transfer function from the first node to an output node; and a feedback inverter coupled between the first node and at least a third node in the serial chain after two inverters to form a feedback loop, the feedback loop configured to increase bandwidth by adding a peak amount in a frequency response of the signal transfer function. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] A further understanding of the nature and advantages of particular embodiments can be realized by reference to the remaining portions of the specification and drawings, wherein like reference numerals are used to refer to like components. In some instances, a sub-label is associated with a reference numeral to denote one of a plurality of like components. When a reference numeral is cited without specifying an existing sub-label, it is intended to refer to all such plurality of like components.

[0006] Figure 1A is a schematic diagram of a pre-driver data path based on a CMOS inverter chain.

[0007] Figure 1B is based on Figure 1A a graph of the eye opening at node E in a pre-driver based on a CMOS inverter chain versus data rate.

[0008] Figure 1C shows the output eye diagrams at the pre-driver output and the downstream driver PAM4 output corresponding to a pre-driver based on Figure 1A and without a peak.

[0009] Figure 2A is a schematic diagram of a pre-driver data path based on a CMOS inverter chain with an active peak.

[0010] Figure 2B is Figure 2A a graph of the eye opening at node E in a pre-driver with an active peak based on

[0011] Figure 2C shows the output eye diagrams at the pre-driver output and the downstream driver PAM4 output corresponding to a pre-driver based on Figure 2A with an active peak.

[0012] Figure 3A is a simplified circuit diagram of a pre-driver without a peak.

[0013] Figure 3Bis a simplified circuit diagram of a pre-driver with a feedback inverter that provides a DFE-based peak, according to an embodiment of the present subject matter technology.

[0014] Figure 4A is a simplified circuit diagram of a pre-driver with a feedback inverter having a varying time constant, according to an embodiment of the present subject matter technology.

[0015] Figure 4B is a graph showing the effect of the inverter chain time constant on the peak in the frequency domain, according to an embodiment of the present subject matter technology.

[0016] Figure 4C is a graph showing the effect of the feedback inverter transconductance on the peak in the frequency domain, according to an embodiment of the present subject matter technology.

[0017] Figure 5A is a simplified circuit diagram of a pre-driver with two feedback inverters, according to an embodiment of the present subject matter technology.

[0018] Figure 5B is a simplified circuit diagram of a feedback inverter with a programmable bias current, according to an embodiment of the present subject matter technology.

[0019] Figure 5C is a simplified circuit diagram of a differential implementation of a pre-driver with two feedback inverters, according to an embodiment of the present subject matter technology

[0020] Figure 5D is a simplified circuit diagram of a differential implementation of a feedback inverter with programmable bias control, according to an embodiment of the present subject matter technology.

[0021] Figure 6A is Figure 5A a graph of the eye opening of node E in a pre-driver with a DFE-based peak versus the data rate.

[0022] Figure 6B shows corresponding to a Figure 5A pre-driver output and the eye diagram at the downstream driver PAM4 output of a pre-driver with a DFE-based peak. Detailed Description

[0023] The present subject matter relates to an apparatus for supporting high-speed data transmission. In an embodiment, a pre-driver circuit is provided for driving a digital-to-analog converter used in a high-speed transmitter. The circuit includes a serializer configured to combine a plurality of signals into one input signal. The circuit includes an inverter chain serially coupled from a first node to a last node and configured to transmit the input signal to the last node based on a signal transfer function. The circuit further includes a feedback inverter configured to add peaks in a frequency response of the signal transfer function at a first node and a third node. There are also other embodiments.

[0024] The following description is presented to enable a person having ordinary skill in the art to make and use the invention and to incorporate it in the context of a particular application. Various modifications, as well as various uses in different applications, will be apparent to those skilled in the art, and the general principles defined herein may be applied to a wide range of embodiments. Thus, the present subject matter is not intended to be limited to the embodiments presented, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0025] In the following detailed description, numerous specific details are set forth to provide a more thorough understanding of the present subject matter. However, it will be apparent to those skilled in the art that the present subject matter may be practiced without necessarily being limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the present subject matter.

[0026] Direct the reader's attention to all papers and documents that are simultaneously filed with this specification and that are publicly available for inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference. Unless otherwise expressly stated, all features disclosed in this specification (including any appended claims, abstract, and drawings) may be replaced by alternative features serving the same, equivalent, or similar purpose. Thus, unless otherwise expressly stated, each feature disclosed is only an example of a generic series of equivalent or similar features.

[0027] Moreover, no element in a claim that does not expressly state "means for" performing a specified function or "step for" performing a particular function should be construed as a "means" or "step" clause as specified in paragraph 6 of section 112 of Title 35 of the United States Code. In particular, the "steps" or "acts" used in the claims herein are not intended to invoke the provisions of paragraph 6 of section 112 of Title 35 of the United States Code.

[0028] When an element is referred to in this document as being "connected" or "coupled" to another element (including but not limited to electrical and communication connections and couplings), it is to be understood that the element can be directly connected to the other element, or there can be intervening elements present between the elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, it is to be understood that there are no intervening elements in the "direct" connection between the elements. However, the existence of a direct connection does not preclude other connections in which intervening elements may be present.

[0029] When an element is referred to in this document as being "disposed" in some manner relative to another element (e.g., disposed on it, disposed between, disposed below, disposed adjacent to, or disposed in some other relative manner), it is to be understood that the element can be directly disposed relative to the other element (e.g., directly disposed on another element), or there can be intervening elements present between the elements. In contrast, when an element is referred to as being "directly disposed" relative to another element, it is to be understood that there are no intervening elements in the "direct" instance. However, the existence of a direct disposition does not preclude other instances in which intervening elements may be present.

[0030] Similarly, when an element is referred to in this document as being "joined" to another element, it is to be understood that the element can be directly joined to the other element (without any intervening elements), or there can be intervening elements present between the joined elements. In contrast, when an element is referred to as being "directly joined" to another element, it is to be understood that there are no intervening elements in the "direct" joining between the elements. However, the existence of a direct joining does not preclude other forms of joining in which intervening elements may be present.

[0031] Likewise, when an element is referred to in this document as being a "circuit", it is to be understood that in particular (a) a circuit can be a path or network through which an electric current can flow, formed by interconnecting different electronic components. Such a network of components can include elements such as resistors, capacitors, inductors, transistors, diodes, and wires and is designed to perform a specific function, such as amplifying a signal, converting the form of energy, processing information, or controlling a system; (b) in the general context of advanced semiconductor and communication technologies, a circuit can include a single device (e.g., a single integrated circuit) or multiple devices (e.g., multiple chips on a single printed circuit board); and (c) a circuit can include hardware that works in conjunction with software or firmware.

[0032] In addition, the terms left, right, front, back, top, bottom, forward, reverse, clockwise, and counterclockwise are for purposes of explanation only and are not limited to any fixed direction or orientation. Instead, they are only used to indicate the relative position and / or orientation between various parts of an object and / or component.

[0033] In addition, for ease of description, the methods and processes described herein may be described in a particular order. However, it should be understood that, unless the context otherwise indicates, intermediate processes may occur before and / or after any part of the described processes, and various other processes may be reordered, added, and / or omitted according to various embodiments.

[0034] Unless otherwise indicated, all numbers used herein to express quantities, dimensions, etc. should be understood to be modified by the term "about" in all instances. In this application, unless otherwise expressly stated, the use of the singular form includes the plural form, and the use of the terms "and" and "or" means "and / or" unless otherwise indicated. In addition, the use of the terms "including" and "having" and other forms (such as includes, included, has, have, and had) should be regarded as non-exclusive. In addition, terms such as "element" or "component" cover both elements and components including a single unit and elements or components including more than one unit, unless otherwise expressly stated.

[0035] As used herein, the phrase "at least one" before a series of items separated by the terms "and" or "or" modifies the list as a whole, rather than each member (i.e., each item) of the list. The phrase "at least one" does not necessarily require selection of at least one of each item listed; rather, the phrase allows the meaning of including at least one of any one of the items, and / or at least one of any combination of the items. For example, the phrases "at least one of A, B, and C" or "at least one of A, B, or C" each refer to only A, only B, or only C; and / or any combination of A, B, and C. In examples where it is intended to select "at least one of each of A, B, and C", or alternatively "at least one of A, at least one of B, and at least one of C", it is expressly described as such.

[0036] For many high-speed signal transmission applications, a tailless CML DAC driver (referred to as a DAC driver in the following specification) is used in a high-speed transmitter. A typical architecture of a DAC driver may include an array of DAC slices, each of the DAC slices consisting of an input source switch and a current source, a serializer (e.g., a 4:1 serializer configured to minimize clock load and power), and a full-rate pre-driver for bridging the fan-out between the serializer and the switch in the DAC driver. The switch may be configured to have its size and bias current determined by the target output (analog) signal swing. The serializer is typically sized to minimize clock power. The pre-driver is implemented using a CMOS inverter chain between the serializer and the switch. Figure 1AIt is a schematic diagram of a pre-driver data path based on a CMOS inverter chain. As shown, serializer 110 may include a multiplexer 112 at its output, that is, converting multiple signals into a serial input signal (each signal is a symbol containing one or more bits). The pre-driver 120 receives this input signal from the first node A and passes it through a data path made up of an inverter chain, which includes a sequence of inverters serially coupled from the first node A to the second node B... and to the last node E. The first node A has the highest fan-out because it is directly coupled to the output of the multiplexer 112. The switch 130 is coupled to the last node E to receive the output signal from the pre-driver data path.

[0037] In the case of the highest fan-out at the first node A, it carries the lowest bandwidth (BW) for signal transmission through the data path. In the framework of advanced 5nm FinFET technology, the highest data rate at which the pre-driver 120 can operate is limited to F ref Gbps (assuming a sequence of four inverters is used in the CMOS inverter chain). Beyond this data rate F ref , the output signal eye opening will suffer a loss, for example, greater than 40%. Figure 1B is based on Figure 1A a graph of the eye opening and data rate of node E in a pre-driver based on a CMOS inverter chain. The eye opening refers to the net space at the center of the eye diagram where the waveform does not enter. The eye width is the width of the eye opening at a specified amplitude (usually half amplitude) and is measured along the time axis. The eye width ratio H with reference to Tbit (bit time, which is the reciprocal of the bit rate) ref is a measure of the timing margin. The eye height is the vertical opening of the eye diagram and is measured along the voltage axis. The eye height ratio V with reference to VDD (power supply voltage) ref is the ratio of the eye height to the maximum swing of the voltage representing the logic level. It indicates the voltage margin; a larger ratio means a larger margin for the signal to overcome voltage noise. As shown, for a data rate of approximately 1.18F ref , at the output node E of the pre-driver 120, the eye height ratio (with reference to the VDD voltage source) is less than 60%, and the eye width ratio with reference to Tbit (bit time) is only 40%. The eye diagram shown in Figure 1C for the output signal swing at the output of the pre-driver 120 clearly shows that the eye opening at a data rate of 1.18F ref almost becomes blurred. The eye diagram at the output of the downstream driver PAM4 modulator ( Figure 1C ) also only shows a clear eye opening at a data rate of F ref (or lower). 1.18F refEye diagram showing the data rate, where due to high interference, the signal pulses are shifted at different delay times, creating a blurred eye. This indicates that the maximum operable data rate is limited to F ref . In such a peakless architecture, possible ways to improve the bandwidth of the pre-driver chain include using a large number of inverter stages, far greater than Figure 1A the 4 stages of, and minimizing the fan-out. While increasing the inverter stages results in an increase in the random impedance mismatches along the data path and higher noise accumulation, minimizing the fan-out is also difficult to implement for small inverter sizes because the addition of each fan-out finger is a large portion of the total size.

[0038] A scheme for improving the bandwidth of a CMOS inverter chain includes using active peaking. Figure 2A is a schematic diagram of a pre-driver data path based on a CMOS inverter chain with active peaking. The pre-driver 220 is coupled between the multiplexer 212 of the serializer 210 (where the input signal is received at the first node A of the data path) and the switch 230 (where the signal is output from the last node E to the DAC driver for controlling the digital-to-analog operation). The pre-driver 220 is still implemented as a sequential chain of CMOS inverters 221, which are coupled from the first node A in the data path through the second node B, the third node C, and the fourth node D to the last node E. As Figure 2A shown, the active peak is implemented using an inverter 222 with a feedback resistor 223 connected to the pre-driver nodes from node A to D. Active peaking means increasing the signal spectral response in the higher frequency range to effectively increase the bandwidth. Specifically, active peaking reduces the DC impedance at the output of the inverter 222. Active peaking also increases the impedance at higher frequencies of the gate parasitic capacitance of the inverter 222 due to shunting the feedback resistor 223. This results in a spectral response peak and bandwidth improvement. Optionally, the amount of peaking can be increased by increasing the size of the peaking inverter 222 and / or increasing the resistance of the feedback resistor 223. However, increasing the peaking inverter size reduces the DC gain, which requires using more stages of the inverter chain 221 to recover. In addition, increasing the feedback resistor increases the R / F time at the input response of the peaking inverter. Therefore, more stages with active peaking are required, which increases the overall power consumption.

[0039] Figure 2B is Figure 2A a graph of the eye opening at node E versus the data rate in the pre-driver 220 with active peaking. With active peaking (assuming four stages of the inverter chain, as Figure 2A shown), the highest operable data rate is enhanced to 1.18F ref . As Figure 2B shown, when the data rate exceeds 1.18F refWhen, the eye width ratio H at the output node E of the pre-driver 220 act drops to approximately 65%, and the eye height ratio V of the reference VDD voltage source act drops to approximately 80%. The operable data rate with the active peak will still be limited to only 1.18F ref or lower. Figure 2C Displays the eye diagrams at the output of the pre-driver 220 and at the downstream DAC driver PAM4 output. As shown, the eye diagram at the pre-driver output with the active peak does improve performance, with a higher data rate (such as 1.18F ref ). At a higher rate of 1.27F ref , the pulse shift becomes more evident. The eye diagram at the DAC driver output shows a visible clear eye opening for data rates up to 1.18F ref , with improved performance over the non-peak pre-driver. But as the data rate increases to 1.27F ref , the signal interference shift becomes evident with poor transmission performance. Therefore, the technique based on the pre-driver with the active peak (assuming it is based on a four-stage inverter chain) can only achieve the performance with the maximum operable rate at 1.18F ref .

[0040] A general aspect of the present disclosure includes a circuit for driving a digital-to-analog converter. The circuit further includes a serializer configured to combine a plurality of signals into an input signal to drive a forward inverter, the forward inverter coupled to a first node and characterized by a first impedance in series configuration and a first capacitor in parallel configuration. The circuit further includes an inverter chain serially coupled from the first node to the m-th node, where each n-th inverter follows immediately after the n-th node and is configured to transmit the input signal to the last node based on a signal transfer function, where n is an integer variable from 1 to m. The circuit further includes a first feedback inverter coupled from at least a third node along the chain to the first node to form a first feedback loop, the first feedback loop including two inverters after the first node and configured to increase the bandwidth by adding a peak response of the signal transfer function at the first node and the third node. The circuit further includes a switch coupled to the m-th node.

[0041] Embodiments may include one or more of the following features. The circuit, wherein the inverter chain may include four inverters, in sequence a first inverter, a second inverter, a third inverter, and a fourth inverter, the first inverter coupled between the first node and the second node, the second inverter coupled between the second node and the third node, the third inverter coupled between the third node and the fourth node, the fourth inverter coupled between the fourth node and the fifth node, where m = 5. The first feedback loop is characterized by a first time constant τ associated with the first inverter coupled to the second inverter included in the inverter chain in the feedback loop, where τ increases its value by adding more inverters in the inverter chain included in the feedback loop. The first feedback inverter is configured to provide a zero at (1 / τ) in the signal transfer function at the first node. The first feedback inverter is configured to reduce the signal transfer function at the third node to a single-pole response by canceling a pole at (1 / τ). The circuit may include a second feedback inverter, the second feedback inverter coupled to the third node to form a second feedback loop, the second feedback loop driven from the fifth node along the chain having two inverters after the third node, the second feedback loop characterized by a second time constant and configured to add a peak amount in the frequency response of the signal transfer function at the third node and the fifth node. The first feedback inverter is characterized by a transconductance g m where the impedance at the first node is 1 / g mfunction. The first feedback inverter is configured to reduce the DC gain of the impedance at the first node and increase the peak amount at high frequencies in the signal transfer function at the first node and the third node, thereby increasing the bandwidth. The first feedback inverter may include a current-starved inverter, and the current-starved inverter may include a first PMOS transistor and a second PMOS transistor having a first common source terminal, a first NMOS transistor and a second NMOS transistor having a second common source terminal. The first PMOS transistor and the first NMOS transistor have a first common drain terminal configured as a first differential output terminal, and the second PMOS transistor and the second NMOS transistor have a second common drain terminal configured as a second differential output terminal. The first PMOS transistor and the first NMOS transistor have a first common gate terminal configured as a first differential input terminal, and the second PMOS transistor and the second NMOS transistor have a second common gate terminal configured as a second differential input terminal. The first common source terminal is coupled to the source voltage VDD via a third PMOS transistor having a first gate controlled by a first voltage, and the second common source terminal is coupled to ground via a third NMOS transistor having a second gate controlled by a second voltage. The first voltage and the second voltage are used for tuning the bias currents flowing from the source to the first common source terminal and from the second common source terminal to ground, respectively, based on additive complementary variations of the source voltage VDD. The first voltage and the second voltage vary independently to adjust the peak amount in the frequency response of the signal transfer function.

[0042] Another general aspect of the present disclosure includes an apparatus having an extended bandwidth for a high-speed serial link. The apparatus further includes an input inverter configured to receive an input signal from an output of a transmitter stage, the input inverter having a first output impedance coupled in series to a first node and a first capacitor coupled in parallel to the first node. The apparatus further includes a plurality of inverters coupled in a serial chain and configured to drive the input signal based on a signal transfer function from the first node to an output node. The apparatus further includes a feedback inverter coupled between the first node and at least a third node in the serial chain after two inverters to form a feedback loop, the feedback loop being configured to increase the bandwidth by adding a peak amount in the frequency response of the signal transfer function.

[0043] The embodiments may include one or more of the following features. The apparatus, wherein the plurality of inverters may include a first inverter, a second inverter, a third inverter, and a fourth inverter, the first inverter being coupled between the first node and the second node, the second inverter being coupled between the second node and the third node, the third inverter being coupled between the third node and the fourth node, and the fourth inverter being coupled between the fourth node and the output node. The feedback loop is characterized by a time constant τ, which is configured to increase its value by adding more inverters in the serial chain included in the feedback loop. The feedback inverter is configured to provide a zero at (1 / τ) in the signal transfer function at the first node and to cancel a pole at (1 / τ) in the signal transfer function at the third node. The first feedback inverter is characterized by a transconductance g m and is configured to reduce the DC gain of the impedance at the first node, wherein the impedance at the first node is 1 / g mfunction, and increase the peak amount at high frequencies in the signal transfer function at the first node and the third node, thereby increasing the bandwidth. The feedback inverter may include a pair of PMOS transistors having a first common source terminal and a pair of NMOS transistors having a second common source terminal. The first of the pair of PMOS transistors is coupled to the first of the pair of NMOS transistors at a first common drain terminal configured to be coupled to the first differential output of the first node, and has a first common gate terminal configured to receive a first differential input from the third node. The second of the pair of PMOS transistors is coupled to the second of the pair of NMOS transistors at a second common drain terminal configured to be coupled to the second differential output of the first node, and has a second common gate terminal configured to receive a second differential input from the third node. The feedback inverter may further include: a third PMOS transistor having a drain terminal coupled to the first common source terminal and a source terminal coupled to a source voltage, and a third NMOS transistor having a drain terminal coupled to the second common source terminal and a source terminal coupled to ground. The third PMOS transistor has a gate terminal provided by a first control voltage, and the third NMOS transistor has a gate terminal provided by a second control voltage. The third PMOS transistor and the third NMOS transistor degrade the drain-source voltage across one of the pair of PMOS transistors or one of the pair of NMOS transistors. The first control voltage and the second control voltage are adjustable, and are limited such that the first control voltage and the second control voltage are additively complementary to the source voltage VDD for tuning the bias currents flowing from the source to the first common source terminal and from the second common source terminal to ground, respectively. The first control voltage and the second control voltage are independently tuned to program the bias currents to control the peak amount in the frequency response of the signal transfer function added by the feedback inverter. The apparatus may include a second feedback inverter coupled between the third node and the output node in the serial chain to form a second feedback loop to increase the bandwidth by adding a peak amount in the frequency response of the signal transfer function at the third node.

[0044] Figure 3AIt is a simplified circuit diagram of a pre-driver without a peak. In a high-speed data communication system, a pre-driver is an intermediate stage that prepares a digital signal for the final drive stage, ensuring that it is optimized for the modulator to correctly encode information onto the transmission medium with minimal error. For advanced modulators (e.g., PAM4 modulators), precise control of the signal amplitude is required because any distortion may lead to errors in interpreting the four different amplitude levels of the signal encoding. In this figure, the input signal to be processed by the pre-driver is a signal V provided by a serializer by combining (usually using a multiplexer) multiple signals. in . A serializer is a component that converts parallel data into serial data. It is used when data needs to be transmitted on a medium that can only handle one bit at a time (e.g., over long distances or through certain types of communication interfaces). From the perspective of the pre-driver that receives the signal V in as an input signal, the inverter 311 is used to simulate the input-stage architecture that delivers the input signal V in to the first node A in the forward path. A node is generally referred to as one of the connection points in a circuit. The inverter 311 is also called the forward inverter M1 because it is placed in the forward path from the input port to the output port to distinguish it from the inverter added in the feedback path from the output port (node) to the input port (node). The forward inverter 311 is coupled to the first node A, having a first output impedance R1 in series configuration in the forward path and a first capacitor C1 in parallel configuration between the first node A and ground. The forward inverter M1 is characterized by a first transconductance g m1 to deliver the input signal V in to the first output signal V1 at the first node A via a signal transfer function. A signal transfer function is a mathematical representation that describes how an input signal is transformed into an output signal by a system or a stage of a system. The transfer function defines the relationship between the output response and the input in the frequency domain, which depends on the specific design of the associated data-path architecture. For example, the first output signal V1 is the output signal of the input stage with the input signal V in . Therefore, the signal transfer function at the first node A can be given as:

[0045]

[0046] where s is the Laplace variable in the frequency domain.

[0047] In addition, the first node A is also the input port of a pre-driver composed of a sequence of CMOS inverter chains, where inverter 321 and inverter 322 are coupled in a serial configuration. Each inverter in the CMOS inverter chain (such as inverter 321) is serially coupled between two nodes, such as the first node A and the second node B, forming one stage of a buffer for the signal. The CMOS inverter chain is characterized by a transfer function H(s) = 1 / (1 + sτ), where τ is the time constant associated with the buffer (depending on the number of stages in the chain). Therefore, for any stage of the CMOS inverter chain 321, the signal transfer function can be obtained by the product of the function (1) and the buffer transfer function H(s). For example, the second output signal at the third node C is V2, and then the signal transfer function at the third node C can be expressed as follows:

[0048]

[0049] Note that the CMOS buffer provides an additional pole for the signal transfer function at .

[0050] In an embodiment, in order to further boost the operating data rate with a greater bandwidth, a feedback inverter M2 is added to couple with the bandwidth-limiting node of the CMOS inverter chain. Figure 3B is a simplified circuit diagram of a pre-driver with a feedback inverter providing a peak according to an embodiment of the present subject matter technology. As shown, an inverter 325 is added between the third node C and the first node A to form a feedback loop. In the feedback loop, the inverter 325 is also referred to as the feedback inverter M2. The first node A is the bandwidth-limiting node of the CMOS inverter chain. The third node C is the node (output port) after two inverters (inverter 321 and inverter 322) starting from the first node A (input port). The feedback inverter M2 is characterized by a second transconductance g m2 . In an embodiment, 1 / g m2 is selected to have a value much smaller than the first output impedance R1. The feedback inverter M2 is added to the main (forward) inverter M1 at the first node A. Since there is an odd number of inverters in the feedback loop, the inter-symbol interference in the data path is subtracted. In this example, by the addition of the feedback inverter 325, the impedance at the first node A is a function of both g m1 and g m2 . Specifically, the impedance at the first node A is a function of 1 / g m2 . By appropriately selecting the transconductance g m2, the impedance at the first node A can be reduced, which creates a gain-bandwidth trade-off by reducing the DC gain (defined as the product of the device transconductance and the device output impedance) while increasing the high-frequency gain (e.g., the peak magnitude) in the signal transfer function. Thus, the signal transfer function at the first node A can be expressed as:

[0051]

[0052] Based on function (3), the feedback loop with the feedback inverter M2 325 combined with the two CMOS chain inverters 321 and 322 introduces a left-hand plane (LHP) zero in the transfer function at (i.e., negative one divided by the time constant in the frequency domain). In an embodiment, the feedback inverter 325 can reduce the DC gain by a large ratio because R1 can be much larger than 1 / g m2 is much larger. At the same time, compared with the transfer function (1), the pole in the frequency response of the transfer function (3) is pushed to a higher value, represented by the change from 1 / R1C1 to g m2 / C1 because R1 is much larger than 1 / g m2 is much larger. This effectively results in an increase in the peak frequency in the signal transfer function at the first node and increases the pre-driver bandwidth at the first node A. The bandwidth extension based on the frequency response can be regarded as a feedback loop that acts similar to a decision feedback equalizer (DFE) to eliminate inter-symbol interference (ISI) based on discrete time to provide a resonance peak to increase the bandwidth. Different from traditional equalizers that attempt to reshape the channel before the decision device (e.g., the DAC slice), the feedback loop is configured to feedback from the previous symbol decision to subtract the expected ISI from the current symbol, thereby allowing a more accurate decision on the current symbol. This bandwidth extension scheme is called DFE-based peaking, which relies on the feedback inverter added to the pre-driver and acts as a DFE to reshape the resonance peak in the forward path. The DFE-based peaking in the transmitter can enhance or boost these high-frequency components to cancel the expected ISI from the current symbol, effectively extending the operating bandwidth. At the third node C, the signal transfer function can also be derived and expressed as:

[0053]

[0054] Note that the feedback loop reduces the signal transfer function (4) at the third node C to a single-pole response by eliminating the extra pole of the signal transfer function (2) at without peaking at the third node C. Once the DFE-based peak is introduced via the feedback inverter M2, the extra pole is eliminated by the LHP zero. The signal transfer function (4) at the third node C becomes a single-pole response function. The pole position is pushed to a higher value g m2 / C1 >> 1 / R1C1 is used to achieve the effect of adding a peak response in the frequency domain, which indicates the bandwidth loss in the peak compensation inverter chain at high frequencies. This results in an increase in the peak amount of the signal transfer function at the third node C and effectively increases the pre-driver bandwidth at the third node C.

[0055] Figure 4A is a simplified circuit diagram of a pre-driver with a feedback inverter having a varying time constant according to an embodiment of the present subject matter technology. In the feedback loop for providing a DFE-based peak, the peak can be optimized in two ways according to the function described above. One way is to vary the feedback loop delay time constant τ. The time constant τ can be varied by the number of inverters in the feedback loop. For example, in Figure 3B , there are three inverters in the main data path of the CMOS inverter chain, including the feedback inverter 325 and two inverters 321 and 322. Associated with Figure 3B the feedback loop in Figure 4A the time constant can be expressed as τ1. In some embodiments, the number of inverters in the feedback loop is kept odd so that inter-symbol interference can be subtracted and a DFE-based peak bandwidth increase can be achieved. As shown in

[0056] m2 , by coupling the feedback inverter 425 between the first node A and the last node E, the feedback loop is extended to 5 inverters, that is, in the CMOS inverter chain, the driving node is shifted by two additional inverters 423, 424 from two inverters 421, 422 after the first node A. Now, the time constant of the feedback loop is expressed as τ2, where τ2 > τ1. This helps to shift the LHP zero position in the frequency response and increase the peak amount.

[0056] Another way to tune the DFE-based peak is to vary the transconductance g m2 of the feedback inverter 425. For a MOSFET, the transconductance g m is proportional to the channel width of the transistor and inversely proportional to the channel length of the transistor. In an inverter composed of a complementary transistor pair (NMOS and PMOS), the transconductance is determined by the on-state transistor in the pair. For example, when the inverter is transitioning and the NMOS is on (and the PMOS is off), the transconductance of the inverter is approximately the transconductance of the NMOS transistor. The transconductance g m2 of the feedback inverter 425 can be varied to optimize the gain-bandwidth product and trade a lower DC gain for a higher peak.

[0057] Figure 4BIt is a graph showing the influence of the time constant on the peak according to an embodiment of the present subject matter technology. As shown, as the time constant τ is adjusted from 3 ps to 5 ps, and even higher to 9 ps, the signal magnitude response in the frequency domain changes accordingly, with its peak shifting towards lower frequencies, but the peak magnitude increasing. The peak magnitude refers to the maximum increase or overshoot in the frequency response of the pre-driver that exceeds its steady-state or DC gain. This is a characteristic feature where the transfer function exhibits resonant behavior. The peak frequency refers to the point where the gain of the pre-driver briefly exceeds its normal level. It typically occurs at or near the resonant frequency of the system. Figure 4C It is a graph showing the influence of the feedback inverter transconductance on the peak according to an embodiment of the present subject matter technology. As shown, as g m2 Referring to g m1 (the transconductance of the input inverter 411) increases from 0.1 to 0.3, the DC gain (represented by ) will decrease, while the peak magnitude response increases and also shifts towards higher frequencies.

[0058] In an alternative embodiment, after a first feedback loop (e.g., the feedback inverter 425 in Figure 4A ) formed in the data path along the CMOS inverter chain, the previously described pre-driver circuit can be modified with additional feedback loops. Figure 5A It is a simplified circuit diagram of a pre-driver 500 having two feedback inverters 525 and 526 according to an embodiment of the present subject matter technology. The pre-driver is an intermediate circuit or component that acts as a bridge between the main signal source and the final (DAC) driver stage and is configured to provide enhanced power transfer with impedance matching to ensure minimum signal reflection. In this current case, the pre-driver is designed to provide the desired signal transfer performance with an enhanced operating bandwidth. In an embodiment, Figure 5A the pre-driver circuit 500 includes a sequence of a plurality of inverters 521, 522, 523, and 524 serially coupled in the data path from the first node A to the fifth node E. The first node A is coupled to a multiplexer 512 associated with a serializer (e.g., a 4:1 serializer) to receive an input signal with a high data rate. The fifth node E is configured to output a signal to the input stage of a driver switch 530 of a digital-to-analog converter (DAC) driver. Optionally, the fifth node E is the output terminal of the pre-driver 500, which is configured to be coupled to any input stage of the CMOS transmit data path.

[0059] The highest fan-out is at the interface between the multiplexer 512 and the pre-driver circuit 500, which is at the first node A configured as the input terminal of the pre-driver. In various embodiments, the first node A of the pre-driver 500 can be coupled to the output of the multiplexer 512 as shown, or the output of an inverter, or any output stage of a CMOS-based transmit data path. Two feedback loop inverters 525 and 526 are added to provide DFE-based peaks in bandwidth expansion. The first feedback inverter 525 is coupled to the first node A to boost the bandwidth at the node with the lowest bandwidth in the data path, and is coupled to the third node C, which serves as the drive node of the first feedback loop. Generally, for a pre-driver with only one stage of feedback loop, the third node C becomes the output of the main path of the pre-driver, which can be coupled to any input switch or inverter, or any input stage of a CMOS-based transmit data path. The first feedback loop 525 is characterized by a first time constant τ1 and a first feedback transconductance. The total number of inverters in the first feedback loop is an odd number 3, configured to ensure cancellation of inter-symbol interference. Optionally, the pre-driver 500 has four inverters in a chain of five nodes, and the fifth node E now becomes the output of the main path, which can be coupled to the driver switch 530, or to an inverter, or any input stage of a CMOS-based transmit data path. The second feedback inverter 526 is coupled between the third node C and the fifth node E, adding a second peak stage at the third node C. The second feedback loop is characterized by a second time constant τ2 and a second feedback transconductance. The total number of inverters in the second feedback loop is also an odd number 3, ensuring cancellation of inter-symbol interference.

[0060] Due to the increased peak amount compared to the conventional active peak ( Figure 2A ), the bandwidth degradation at the second node B, the fourth node D, and the fifth node E is compensated. In Figure 5A , the first feedback inverter 525 is introduced to form a first feedback loop between the first node A and the third node C. The first feedback loop mainly adds a peak to the first node A, which is the bandwidth-limiting node in the inverter chain. In Figure 5A , the second feedback inverter 526 is also introduced to form a second feedback loop between the third node C and the fifth node E, adding an additional peak to the third node C. Therefore, only two nodes are required to reach the peak amount for the entire data path of the pre-driver, reducing the power overhead.

[0061] In some embodiments, Figure 5AThe pre-driver proposed in [reference] may include a CMOS inverter chain having an even number (>4) of inverters. For example, 6 inverters or 8 inverters in the chain from the first node to the last node. It may include only a first feedback inverter coupled between the first node and the drive node to form a feedback loop, where the drive node may be selected from the third node, the fifth node, and the last node. Alternatively, it may include 3 or more feedback inverters, each having two inverters in the chain. In some embodiments, the layout design of these feedback inverters and associated circuitry may be determined by a specific application, as certain trade-offs need to be considered when pursuing wider bandwidth performance, cost savings, and power consumption.

[0062] Figure 5B is a simplified circuit diagram of a feedback inverter with a programmable bias current according to an embodiment of the present subject matter technology. In an embodiment, each of the added feedback inverters may be provided in the form of a current-starved inverter. A current-starved inverter is a variant of the standard CMOS inverter used in digital electronics, designed to allow control of its switching characteristics. The standard CMOS inverter consists of a PMOS (p-type MOSFET) and an NMOS (n-type MOSFET) transistor. In a current-starved inverter, additional transistors (usually NMOS) are added in series with the pull-up (PMOS) and / or pull-down (NMOS) transistors of the inverter. Figure 5A Each feedback inverter 525 or 526 of [circuit] is configured such that its drive current can be adjusted or programmed to control the peak amount of the signal transfer function that the corresponding feedback inverter can add at the corresponding node. For a CMOS implementation, additional transistors can be used to control the drive current, which effectively act as variable resistors such that their resistance (or conductance) can be dynamically adjusted by adjusting their gate voltage.

[0063] In an embodiment, Figure 5A the feedback inverters in the pre-driver of [circuit] may be implemented in a current-starved configuration, where two current sources are added to degenerate the inverter to achieve a reduction in the voltage drop across the inverter transistors to mitigate hot carrier injection (HCI) aging. Figure 5B provides a simplified implementation of a current-starved architecture using a differential configuration to degenerate the transistor transconductance and reduce the transistor gate-to-source voltage or drain-to-source voltage to reduce HCI aging. In Figure 5CMore specifically, reducing the gate-to-source voltage or the drain-to-source voltage by a current-starved circuit system is described more clearly. The pre-driver 500’ includes two feedback inverters configured in a differential implementation. As shown, the pre-driver 500’ has two complementary (differential) main paths, each having four inverters in a series chain. In one main path, the inverter chain has a first node A coupled to the output of the multiplexer 512’ and a fifth node E coupled to the input of the driver switch 530’. In the complementary main path, the inverter chain has a first node coupled to the output of the multiplexer 512” and a fifth node coupled to the input of the driver switch 530” Specifically, the feedback inverters in the pre-driver 500’ are Figure 5A a differential implementation of the current-starved feedback inverter 525 with a common tail in. The differential feedback inverter 525’ includes a first PMOS transistor 5251 and a second PMOS transistor 5252 having a first common source terminal 51, a first NMOS transistor 5253 and a second NMOS transistor 5254 having a second common source terminal 52. The first / second PMOS transistors 5251 / 5252 have a common drain terminal 55 / 56 shared with the first / second NMOS transistors 5253 / 5254. The first common drain terminal 55 can be configured to couple to the first differential output of the node A in the first main path of the pre-driver 500’. The second common drain terminal 56 can be configured to couple to the node in the second main path of the pre-driver 500’ of the second differential output. The first PMOS / NMOS transistors 5251 / 5253 have a first common gate terminal 53 configured to receive a first differential input from the node C in the first main path of the pre-driver 500’. The second PMOS / NMOS transistors 5252 / 5254 have a second common gate terminal 54 configured to receive a second differential input from the node in the second main path of the pre-driver 500’ to receive. The two differential input terminals are configured to receive a differential voltage signal to drive the first feedback inverter characterized by the time constant τ1 to add a peak amount to the node C and at the differential output terminals 55 / 56. A second feedback inverter with a differential implementation is also added between the node C and and between E and .

[0064] Refer to Figure 5B , implement Figure 5AThe current source therein. The first common source terminal 51 is coupled to the source voltage VDD via a third PMOS transistor 5255 (PMOS control transistor), where the first gate is applied with a first control voltage V1 to control the PMOS bias current from the source VDD to the first common source terminal 51 of the first feedback inverter 525. The second common source terminal 52 is coupled to ground via a third NMOS transistor 5256 (NMOS control transistor), where the second gate is applied with a second control voltage V2 to control the NMOS bias current from the second common source terminal 52 to ground of the feedback inverter 525. In an embodiment, the first control voltage V1 and the second control voltage V2 are applied independently such that the PMOS bias current and the NMOS bias current can be adjusted independently to control the peak amount in the signal transfer function. In an alternative embodiment, the first control voltage V1 is given by (VDD - V bg ) and the second control voltage V2 is given by V bg . Here, V bg is a reference voltage that can be dynamically adjusted. In this way, the first control voltage and the second control voltage are additively complementary to the source voltage VDD. Optionally, V bg is the bandgap voltage associated with the CMOS transistor. Optionally, V bg is greater than the threshold voltage of the NMOS transistor 5256. If V bg is close to the threshold voltage, then the NMOS control transistor 5256 may only allow a small current to pass through, effectively starving the inverter. If V bg is much greater than the threshold voltage, then the NMOS control transistor 5256 may allow more current, providing a greater drive strength. When V bg is larger, it moves closer to VDD, making the PMOS control transistor 5255 more conductive. Therefore, the first control voltage V1 and the second control voltage V2 are programmable for bias current control of the feedback inverter 525 to control the added peak amount to the signal transfer function. For the first feedback inverter 525, the bias current supplied to the corresponding source terminal can be tuned or programmed to adjust the peak amount of the transfer function applied to the first node A via the first feedback loop. For the second feedback inverter 526, a similar current-starved circuit system design as shown in Figure 5B can be implemented with programmability regarding adjusting the peak amount in the transfer function at the third node C.

[0065] Transistor self-heating is proportional to power dissipation V DS I DS . For a feedback inverter that does not use an additional transistor for a current-starved design, one of the transistors in the inverter experiences V DS = V GS= VDD. This increases self-heating, resulting in an increase in the junction temperature (proportional to the data duty cycle) and the adjacent metal of the transistor. When V DS and V GS are both high or the duration of the overlap experiencing a high voltage, the HCI aging of the transistor becomes worse. For example, when the input data bit is "1", the NMOS transistor in the feedback inverter has high HCI stress. When the input data bit is "0", the PMOS transistor in the inverter has high HCI stress. The aging of the transistor may cause the transistor threshold voltage V th to gradually increase over time and the reduction of its switching speed. In an embodiment, the high V DS / V GS seen in the single-ended inverter can be reduced by degrading the main inverter device through another transistor connected to each common source 51 / 52 in a current-starved circuit system. Using the degradation of the added bias control transistor for the two common source terminals reduces the V DS / V GS exposure of the main inverter transistor because it is separated between the two transistors. In addition, the differential implementation of the current-starved inverter architecture further provides an advantage in reducing transistor aging by degrading the drain-source voltage V DS and the gate-source voltage V GS . For example, the third PMOS transistor 5255 and the third NMOS transistor 5256 degrade the drain-source voltage V GS across one of the pair of PMOS transistors 5251 / 5252 or one of the pair of NMOS transistors 5253 / 5254. During each duty cycle operation of the current-starved feedback inverter, the decrease in the transistor drain-source voltage directly helps to reduce the HCI stress and the associated transistor aging problems. Figure 5D is a simplified circuit diagram of a differential implementation of a feedback inverter with programmable bias control according to an embodiment of the present subject matter technology. The main path inputs A and are configured to receive differential inputs from two complementary inverters. The outputs C and are configured to provide differential inputs coupled to the feedback inverter. As shown, the degradation of the feedback inverter through the added current source via the differential architecture helps to reduce the V DS / V GS in the corresponding transistors in the two differential branches, further reducing the transistor HCI aging. The common tail transistor with independent bias control (through V1 and V2) is used as a current source to fix the transconductance of the feedback inverter, thereby enabling programmable adjustment of the peak amount added to the pre-driver input port A .

[0066] When using Figure 5AThe pre-driver architecture introduced based on DFE-based peaking improves the highest operable data rate. Figure 6A is Figure 5A A graph of the eye opening of node E in a pre-driver with active peaking versus the data rate. As shown, the eye opening of the signal output at node E of the pre-driver circuit is plotted at different data rates. Even when the data rate is increased to 1.55F ref the ratio of the eye width H dfe to Tbit is also close to 80%, where F ref refers to a reference of the typical maximum operable data rate of a conventional pre-driver. The ratio of the eye height V dfe to VDD also remains above 80% at 1.55F ref At least in some of the embodiments captured within the scope of this application, these performance data of the DFE-based peaking technology confirm an improvement of about 31% or higher compared to conventional active peaking technology. The residual phase peak at the pre-driver output (i.e., node E) can also compensate for the DAC driver bandwidth limitation and help reduce the inter-symbol interference at the PAM4 modulator output downstream of the coupled switch 530. Compared to each node being coupled to a separate feedback segment for active peaking, the pre-driver power consumption can be reduced, for example, by at least about 20% by reducing the number of nodes in the inverter chain of the pre-driver connected to the feedback inverter from 4 to 2.

[0067] Figure 6B Eye diagrams at the output of the pre-driver with DFE-based peaking and at the downstream output of the driver PAM4 are also shown. As the data rate increases from F ref to 1.18F ref 1.27F ref 1.36F ref and 1.55F ref the eye diagrams confirm that for all the above data rates, the signal transmission performance is significantly improved with a clear eye opening. The highest operable data rate of the pre-driver with DFE-based peaking is at least 1.55F ref or higher. The performance is also significantly better than that of the pre-driver with active peaking, which has an operable data rate limited to 1.18F ref . As the demand for high data rates increases, the electrical interface standard uses PAM4 modulation to achieve higher spectral efficiency. The DFE-based pre-driver peaking disclosed in this application confirms that the operable data rate can be enhanced to 1.55F ref . Additionally, even in the case of lower data rates, for example, at F refUnder this condition, the eye diagram is also much clearer and has a smaller lateral shift. This indicates that the performance of the pre-driver based on the DFE peak also enhances the performance at lower data rate operations. Generally speaking, the proposed DFE-based pre-driver peak can be implemented at the output of any high-speed serial link transmitter line and at the input of a high-speed modulator. Such an implementation reduces the power consumption of all high-speed serial link transmitters operating at data rates greater than 100 Gbps or clock rates greater than 50 GHz. Therefore, specific circuit implementations (e.g., Figure 5A and Figure 5B ) can be applied to higher-order PAM-N modulation schemes where N > 4.

[0068] Although the above is a complete description of specific embodiments, various modifications, alternative configurations, and equivalents can be used. Therefore, the above description and illustration should not be regarded as limiting the scope of the subject technology defined by the appended claims (for some embodiments).

Claims

1. A circuit comprising: a serializer configured to combine a plurality of signals into one input signal to drive a forward inverter coupled to a first node and characterized by a first impedance in a series configuration and a first capacitance in a parallel configuration; an inverter chain coupled in series from the first node to an m-th node, wherein each n-th inverter immediately follows the n-th node and is configured to transfer the input signal to a last node based on a signal transfer function, wherein n is an integer variable from 1 to m; a first feedback inverter coupled from at least a third node along the chain to the first node to form a first feedback loop, the first feedback loop comprising two inverters after the first node and configured to increase bandwidth by adding a peak response of the signal transfer function at the first node and the third node; and A switch coupled to the m-th node.

2. The circuit according to claim 1, wherein the inverter chain includes four inverters, namely a first inverter, a second inverter, a third inverter and a fourth inverter, in sequence, the first inverter is coupled between the first node and the second node, the second inverter is coupled between the second node and the third node, the third inverter is coupled between the third node and the fourth node, and the fourth inverter is coupled between the fourth node and the fifth node, wherein m=5.

3. The circuit of claim 2 , wherein the first feedback loop is characterized by a first time constant τ associated with the first inverter coupled to the second inverter in the inverter chain included in the feedback loop, wherein τ increases its value by adding more inverters in the inverter chain included in the feedback loop.

4. The circuit of claim 3, wherein the first feedback inverter is configured to provide a zero at (1 / τ) in the signal transfer function at the first node.

5. The circuit of claim 4, wherein the first feedback inverter is configured to reduce the signal transfer function at the third node to a single-pole response by eliminating one pole at (1 / τ).

6. The circuit according to claim 1, wherein the first feedback inverter is composed of a transconductor g m characterization, where the impedance at the first node is 1 / g m and is configured to reduce the DC gain of the impedance at the first node and increase the peak amount at high frequency in the signal transfer function at the first node and the third node, thereby increasing the bandwidth.

7. The circuit of claim 1 , wherein the first feedback inverter comprises a current starved inverter, the current starved inverter comprising a first PMOS transistor and a second PMOS transistor having a first common source terminal, a first NMOS transistor and a second NMOS transistor having a second common source terminal, the first PMOS transistor and the first NMOS transistor having a first common drain terminal configured as a first differential output terminal, the second PMOS transistor and the second NMOS transistor having a second common drain terminal configured as a second differential output terminal, the first PMOS transistor and the first NMOS transistor having a first common input terminal configured as a first differential input terminal, a common gate terminal, the second PMOS transistor and the second NMOS transistor having a second common gate terminal configured as a second differential input terminal, the first common source terminal being coupled to a source voltage VDD via a third PMOS transistor having a first gate controlled by a first voltage and the second common source terminal being coupled to ground via a third NMOS transistor having a second gate controlled by a second voltage, the current-starved inverter being degraded by the third PMOS transistor connecting the source VDD to the first common source terminal and the third NMOS transistor connecting the second common source terminal to the ground to reduce transistor aging caused by hot carrier injection.

8. The circuit of claim 7, wherein the first voltage and the second voltage are based on additive complementary changes to the source voltage VDD for tuning bias currents flowing from a source to the first common source terminal and from the second common source terminal to ground, respectively.

9. The circuit of claim 7, wherein the first voltage and the second voltage are independently varied for adjusting an amount of peaking in a frequency response of the signal transfer function.

10. The circuit of claim 2, further comprising a second feedback inverter coupled to the third node to form a second feedback loop driven from the fifth node along the chain of two inverters after the third node, the second feedback loop characterized by a second time constant and configured to add a peaking amount in the frequency response of the signal transfer function at the third node and the fifth node.

11. An apparatus comprising: an input inverter configured to receive an input signal from an output of the transmitter stage, the input inverter having a first output impedance coupled in series to a first node and a first capacitance coupled in parallel to the first node; a plurality of inverters coupled in a serial chain and configured to drive the input signal based on a signal transfer function from the first node to an output node; and A feedback inverter is coupled between the first node and at least a third node in the serial chain after two inverters to form a feedback loop configured to increase bandwidth by adding a peak amount in the frequency response of the signal transfer function.

12. The device of claim 11, wherein the plurality of inverters comprises a first inverter coupled between the first node and a second node, a second inverter coupled between the second node and the third node, a third inverter coupled between the third node and a fourth node, and a fourth inverter coupled between the fourth node and the output node.

13. The apparatus of claim 11, wherein the feedback loop is characterized by a time constant τ, which is configured to increase its value by adding more inverters in the serial chain included in the feedback loop.

14. The device of claim 13, wherein the feedback inverter is configured to provide a zero at (1 / τ) in the signal transfer function at the first node and to eliminate a pole at (1 / τ) in the signal transfer function at the third node.

15. The device according to claim 11, wherein the first feedback inverter is composed of a transconductor g m characterized by a DC gain configured to reduce an impedance at the first node, wherein the impedance at the first node is 1 / g m function, and increase the peak amount at high frequency in the signal transfer function at the first node and the third node, thereby increasing the bandwidth.

16. The apparatus of claim 11 , wherein the feedback inverter comprises a pair of PMOS transistors having a first common source terminal and a pair of NMOS transistors having a second common source terminal, a first one of the pair of PMOS transistors being coupled to the first one of the pair of NMOS transistors at a first common drain terminal configured to couple to a first differential output of the first node and having a first common gate terminal configured to receive a first differential input from the third node, a second one of the pair of PMOS transistors being coupled to the second one of the pair of NMOS transistors at a second common drain terminal configured to couple to a second differential output of the first node and having a second common gate terminal configured to receive a second differential input from the third node.

17. The apparatus of claim 16, wherein the feedback inverter further comprises: a third PMOS transistor having a drain terminal coupled to the first common source terminal and a source terminal coupled to a source voltage; and a third NMOS transistor having a drain terminal coupled to the second common source terminal and a source terminal coupled to ground, the third PMOS transistor having a gate terminal provided by a first control voltage, the third NMOS transistor having a gate terminal provided by a second control voltage, the feedback inverter being degraded by the third PMOS transistor connected to the source voltage and the third NMOS transistor connected to the ground to reduce transistor aging caused by hot carrier injection.

18. The device of claim 17, wherein the first control voltage and the second control voltage are adjustable, limited to the first control voltage and the second control voltage being additively complementary to the source voltage VDD for tuning bias currents flowing from the source to the first common source terminal and from the second common source terminal to ground, respectively.

19. The apparatus of claim 17, wherein the first control voltage and the second control voltage are independently tuned to program the bias current to control an amount of peaking in a frequency response of the signal transfer function added by the feedback inverter.

20. The device of claim 11, further comprising a second feedback inverter coupled between the third node in the serial chain and the output node to form a second feedback loop to increase bandwidth by adding a peak amount in a frequency response of the signal transfer function at the third node.

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