Interleaving method and communication device

Abstract

According to the interleaving method and the communication device, in the method, a sending end device carries out sub-block interleaving on a to-be-interleaved codeword sequence to obtain a first codeword sequence, the to-be-interleaved codeword sequence and the first codeword sequence each comprise Y sub-blocks, the Y sub-blocks of the to-be-interleaved codeword sequence are determined based on the number X of bits contained in a preset sub-block, x and Y are integers greater than 1; and then, the transmitting end equipment performs cross-sub-block bit interleaving on bits contained in at least one sub-block group in the L sub-block groups in the corresponding sub-block group to obtain a second codeword sequence, the L sub-block groups are determined based on the Y sub-blocks of the first codeword sequence and the number Z of the sub-blocks contained in a preset sub-block group, and both Z and L are integers greater than 1. According to the method, the hardware overhead required by interleaving can be reduced, and the throughput rate is improved.

Description

Technical Field

[0001] This application relates to the field of channel coding, and more specifically, to an interleaving method and a communication device. Background Art

[0002] In order to achieve a random process, the current channel bit interleaving scheme usually performs large-range interleaving on the entire transmitted codeword. However, because of the large interleaving range and no regular pattern to follow, this interleaving method will consume a large amount of hardware resources during the interleaving process. In addition, this interleaving method will affect the throughput. Therefore, it is not suitable as the channel bit interleaving scheme for the next-generation communication system. Summary of the Invention

[0003] This application provides an interleaving method and a communication device, which can reduce the hardware overhead required for interleaving and improve the throughput.

[0004] In a first aspect, an interleaving method is provided. This method can be executed by a transmitting-end device. Without special instructions, the "transmitting-end device" in this application can refer to the transmitting-end device itself (for example, a network device, a terminal device), or a component in the transmitting-end device (for example, a processor, a chip, or a chip system, etc.), or it can also be a logic module or software that can implement all or part of the functions of the transmitting-end device.

[0005] The method includes: performing sub-block interleaving on the sequence of codewords to be interleaved to obtain a first sequence of codewords. Both the sequence of codewords to be interleaved and the first sequence of codewords include Y sub-blocks. The Y sub-blocks of the sequence of codewords to be interleaved are determined based on the number of bits X included in a preset sub-block. Both X and Y are integers greater than 1; performing cross-sub-block bit interleaving on the bits included in at least one sub-block group among L sub-block groups within the corresponding sub-block group to obtain a second sequence of codewords. The L sub-block groups are determined based on the Y sub-blocks of the first sequence of codewords and the number of sub-blocks Z included in a preset sub-block group. Both Z and L are integers greater than 1.

[0006] In the above technical solution, the interleaving process of the sequence of codewords to be interleaved is divided into two steps. The first step is sub-block interleaving, which disperses the originally concentrated bit positions to different positions in the transmission sequence through sub-block interleaving on a large scale. The second step is cross-sub-block bit interleaving within a small range within the sub-block groups composed of multiple sub-blocks, so as to break the correlation between consecutive bits. In this way, the parallelism can be improved (that is, the throughput is increased) through large-scale sub-block interleaving, and through small-range cross-sub-block bit interleaving within the sub-block groups, it can be obtained through a fixed interconnection relationship itself, and the hardware implementation is easy (that is, the required hardware overhead is small), thus solving the problem of the original interleaving that performs small-granularity bit interleaving within a large range, resulting in irregular deinterleaving, inability to improve the parallelism, and large hardware overhead.

[0007] In certain implementations of the first aspect, cross-subblock bit interleaving is performed on the bits included in at least one subblock group among the L subblock groups within the corresponding subblock group, including: performing cross-subblock bit interleaving on the bits included in the first subblock group among the at least one subblock group within the first subblock group based on a first interleaving method, where the first subblock group includes a first subblock and a second subblock, and the first interleaving method is used to place a first bit included in the first subblock at a first position, where the first position is the position where a second bit included in the second subblock is located.

[0008] In the above technical solution, the first bit included in the first subblock in the first subblock group is swapped from the current position to the position of a bit in the second subblock, thereby achieving cross-subblock bit interleaving within the subblock group. In certain implementations of the first aspect, the remainder of the position number of the first bit after modulo-n operation is the same as the remainder of the position number of the second bit after modulo-n operation, where n is an integer greater than 1.

[0009] Exemplarily, n is a prime number greater than 1.

[0010] The above technical solution can be regarded as the first interleaving method performing interleaving on the bits in a subblock group using congruent positions modulo n. Among them, the position number of a bit (such as the first bit or the second bit) in the first subblock group being S indicates that the bit is the S-th bit among all the bits in the first subblock group.

[0011] Optionally, the offset values corresponding to each bit in the first subblock can be the same or different, and the present application does not limit this. For example, if the remainders of the position numbers of multiple bits in the first subblock group after modulo-n operation are the same as the remainder of the position number of the first bit after modulo-n operation, then the first bit can be offset to the position of any one of the multiple bits.

[0012] In certain implementations of the first aspect, subblock interleaving is performed on the interleaved codeword sequence, including: performing subblock interleaving on the interleaved codeword sequence based on a second interleaving method, where the second interleaving method is used to write each of the Y subblocks of the interleaved codeword sequence by columns and read them out by rows to complete subblock interleaving, d1 is the number of writing columns corresponding to the second interleaving method, and d1 is an integer greater than 1 and less than Y, where represents rounding up. represents rounding up.

[0013] Exemplarily, d1 is a prime number greater than 1 and less than Y, so that the interleaving can mix the coupling between decodings more thoroughly.

[0014] Exemplarily, Z is equal to d1.

[0015] In the above technical solution, block interleaving is implemented by using an interleaving method of writing by column and reading by row, which is simple to use and highly operable.

[0016] In some implementations of the first aspect, sub-block interleaving is performed on the codeword sequence to be interleaved, including: performing sub-block interleaving on the codeword sequence to be interleaved based on a third interleaving method, where the third interleaving method is used to write every d2 sub-blocks out of Y sub-blocks of the codeword sequence to be interleaved by row and read by column to complete sub-block interleaving, and d2 is the number of writing columns corresponding to the third interleaving method, and d2 is an integer greater than 1 and less than Y.

[0017] Exemplarily, d2 is a prime number greater than 1 and less than Y, so that the interleaving can mix the coupling between decodings more thoroughly.

[0018] In the above technical solution, block interleaving is implemented by using an interleaving method of writing by row and reading by column, which is simple to use and highly operable.

[0019] In some implementations of the first aspect, the sub-blocks included in any one of the L sub-block groups are consecutive sub-blocks among the Y sub-blocks of the first codeword sequence.

[0020] In some implementations of the first aspect, the third interleaving method is further used to perform sub-block interleaving on at least one of the d2 sub-block groups within the corresponding sub-block group between writing by row and reading by column, where the d2 sub-block groups are the sub-block groups corresponding to d2 columns of sub-blocks after writing by row.

[0021] In some implementations of the first aspect, the L sub-block groups are the sub-block groups obtained by reading by row after performing sub-block interleaving within the corresponding sub-block groups.

[0022] Exemplarily, Z is equal to d2.

[0023] In some implementations of the first aspect, the third interleaving method is used to perform sub-block interleaving on at least one of the d2 sub-block groups within the corresponding sub-block group, including: the third interleaving method is used to perform sub-block interleaving on at least one of the d2 sub-block groups within the corresponding sub-block group by translating the sub-blocks in the column direction.

[0024] In the above technical solution, without adding interleaving implementation, the interleaving result is more uniform.

[0025] In a second aspect, a deinterleaving method is provided, which can be executed by a receiving-end device. Without special specification, the "receiving-end device" in this application can refer to the receiving-end device itself (for example, a network device, a terminal device), or a component in the receiving-end device (for example, a processor, a chip, or a chip system, etc.), or can also be a logic module or software that can implement all or part of the functions of the receiving-end device.

[0026] The method includes: performing de-bit-interleaving across sub-blocks on the decoding information included in at least one of the L sub-block groups within the corresponding sub-block group to obtain a first de-interleaved sequence, where the L sub-block groups are determined based on the Y sub-blocks of the sequence to be de-interleaved and the number Z of sub-blocks included in a preset sub-block group, the Y sub-blocks are determined based on the number X of decoding information included in a preset sub-block, and X, Y, Z, and L are all integers greater than 1; performing de-sub-block-interleaving on the first de-interleaved sequence to obtain a second de-interleaved sequence.

[0027] In some implementations of the second aspect, performing de-bit-interleaving across sub-blocks on the decoding information included in at least one of the L sub-block groups within the corresponding sub-block group includes: performing cross-sub-block bit-interleaving on the decoding information included in a first sub-block group among at least one of the sub-block groups within the first sub-block group based on a first de-interleaving method, where the first sub-block group includes a first sub-block and a second sub-block, and the first de-interleaving method is used to place the first decoding information included in the second sub-block at a second position, where the second position is the position where the second decoding information is located in the first sub-block.

[0028] In some implementations of the second aspect, the remainder obtained by performing a modulo n operation on the position serial number of the first decoding information is the same as the remainder obtained by performing a modulo n operation on the position serial number of the second decoding information, where n is an integer greater than 1.

[0029] In some implementations of the second aspect, performing de-sub-block-interleaving on the first de-interleaved sequence includes:

[0030] Performing de-sub-block-interleaving on the first de-interleaved sequence based on a second de-interleaving method, where the second de-interleaving method is used to write the Y sub-blocks of the first de-interleaved sequence by rows and read them by columns to complete de-sub-block-interleaving, d1 is the number of write columns corresponding to the second de-interleaving method, and the number of sub-blocks written in each row is determined based on the interleaving method performed according to the columns modulo d1, and d1 is an integer greater than 1 and less than Y.

[0031] In some implementations of the second aspect, Z is equal to d1.

[0032] In some implementations of the second aspect, performing de-sub-block-interleaving on the first de-interleaved sequence includes: performing de-sub-block-interleaving on the first de-interleaved sequence based on a third de-interleaving method, where the third de-interleaving method is used to write the Y sub-blocks of the first de-interleaved sequence by columns and read them by rows to complete de-sub-block-interleaving, d2 is the number of write columns corresponding to the third de-interleaving method, and the number of sub-blocks written in each column is determined based on the interleaving method performed according to the rows modulo d2, and d2 is an integer greater than 1 and less than Y.

[0033] In some implementations of the second aspect, the sub-blocks included in any one of the L sub-block groups are consecutive sub-blocks among the Y sub-blocks of the to-be-deinterleaved sequence.

[0034] In some implementations of the second aspect, the third deinterleaving method is further used to perform sub-block deinterleaving on at least one of the d2 sub-block groups within the corresponding sub-block group between column writing and row reading, where the d2 sub-block groups are the sub-block groups corresponding to d2 columns of sub-blocks after column writing.

[0035] In some implementations of the second aspect, the L sub-block groups are the sub-block groups obtained by row reading before performing sub-block deinterleaving within the corresponding sub-block group.

[0036] Exemplarily, Z is equal to d2.

[0037] In some implementations of the second aspect, the third deinterleaving method is used to perform sub-block deinterleaving on at least one of the d2 sub-block groups within the corresponding sub-block group, including: the third deinterleaving method is used to perform sub-block deinterleaving on at least one of the d2 sub-block groups within the corresponding sub-block group by shifting the sub-blocks in the column direction.

[0038] In a third aspect, an interleaving method is provided. This method can be executed by a transmitting device. Unless otherwise specified, the "transmitting device" in this application can refer to the transmitting device itself (e.g., a network device, a terminal device), or a component in the transmitting device (e.g., a processor, a chip, or a chip system, etc.), or it can also be a logic module or software that can implement all or part of the functions of the transmitting device.

[0039] The method includes: performing cross-sub-block bit interleaving on the bits included in at least one of the L sub-block groups within the corresponding sub-block group to obtain a third codeword sequence, where the L sub-block groups are determined based on the Y sub-blocks of the to-be-interleaved codeword sequence and the number of sub-blocks Z included in a preset sub-block group, the Y sub-blocks are determined based on the number of bits X included in a preset sub-block, and X, Y, Z, and L are all integers greater than 1; performing sub-block interleaving on the Y sub-blocks of the third codeword sequence to obtain a fourth codeword sequence.

[0040] In the above technical solution, the interleaving process of the to-be-interleaved codeword sequence is divided into two steps. The first step is to perform small-range cross-subblock bit interleaving within the subblock group to break the correlation between consecutive bits. The second step is subblock interleaving, which disperses the originally aggregated bit positions to different positions in the transmission sequence through block interleaving on a large scale. In this way, the parallelism can be improved through large-scale subblock interleaving, and through the small-range cross-subblock bit interleaving within the subblock group, it can be obtained through a fixed interconnection relationship, and the hardware implementation is easy, thus solving the problems of the original interleaving, such as the lack of regularity in deinterleaving, the inability to improve parallelism, and the large hardware overhead caused by performing small-granularity bit interleaving on a large scale.

[0041] In some implementations of the third aspect, cross-subblock bit interleaving is performed on the bits included in at least one subblock group among the L subblock groups within the corresponding subblock group, including: performing cross-subblock bit interleaving on the bits included in the first subblock group among the at least one subblock group based on the first interleaving method, where the first subblock group includes a first subblock and a second subblock, and the first interleaving method is used to place the first bit included in the first subblock at the first position, where the first position is the position where the second bit included in the second subblock is located.

[0042] For the beneficial effects of the implementations of the third aspect, refer to the description of the first aspect and will not be elaborated here.

[0043] In some implementations of the third aspect, the remainder obtained by performing modulo-n operation on the position serial number of the first bit is the same as the remainder obtained by performing modulo-n operation on the position serial number of the second bit, where n is an integer greater than 1.

[0044] In some implementations of the third aspect, subblock interleaving is performed on the Y subblocks of the third codeword sequence, including: performing subblock interleaving on the Y subblocks of the third codeword sequence based on the third interleaving method, where the third interleaving method is used to write every d2 subblocks of the Y subblocks of the third codeword sequence row by row and read them column by column to complete subblock interleaving, d2 is the number of write columns corresponding to the third interleaving method, and d2 is an integer greater than 1 and less than Y.

[0045] Exemplarily, Z is equal to d2.

[0046] In some implementations of the third aspect, subblock interleaving is performed on the Y subblocks of the third codeword sequence, including: performing subblock interleaving on the Y subblocks of the third codeword sequence based on the second interleaving method, where the second interleaving method is used to write every subblock of the Y subblocks of the third codeword sequence column by column and read them row by row to complete subblock interleaving, where d1 is the number of write columns corresponding to the second interleaving method, d1 is an integer greater than 1 and less than Y, represents rounding up.

[0047] In some implementations of the third aspect, the sub-blocks included in any one of the L sub-block groups are consecutive sub-blocks among the Y sub-blocks of the to-be-interleaved codeword sequence.

[0048] In a fourth aspect, a deinterleaving method is provided. This method can be executed by a receiving-end device. Without special specification, the "receiving-end device" in this application can refer to the receiving-end device itself (for example, a network device, a terminal device), or a component in the receiving-end device (for example, a processor, a chip, or a chip system, etc.), or can also be a logic module or software that can implement all or part of the functions of the receiving-end device.

[0049] The method includes: performing sub-block deinterleaving on the to-be-deinterleaved sequence to obtain a third deinterleaved sequence. Among them, both the to-be-deinterleaved sequence and the third deinterleaved sequence include Y sub-blocks. The Y sub-blocks of the to-be-deinterleaved sequence are determined based on the number X of decoding information included in a preset sub-block, and both X and Y are integers greater than 1; performing cross-sub-block bit deinterleaving on the decoding information included in at least one of the L sub-block groups within the corresponding sub-block group to obtain a fourth deinterleaved sequence. Among them, the L sub-block groups are determined based on the Y sub-blocks of the third deinterleaved sequence and the number Z of sub-blocks included in a preset sub-block group. The Y sub-blocks are determined based on the number X of decoding information included in a preset sub-block, and both Z and L are integers greater than 1.

[0050] In some implementations of the fourth aspect, performing cross-sub-block bit deinterleaving on the decoding information included in at least one of the L sub-block groups within the corresponding sub-block group includes: performing cross-sub-block bit deinterleaving on the decoding information included in the first sub-block group among at least one sub-block group based on the first deinterleaving method. Among them, the first sub-block group includes a first sub-block and a second sub-block, and the first deinterleaving method is used to place the first decoding information included in the second sub-block at the second position, where the second position is the position where the second decoding information is located in the first sub-block.

[0051] In some implementations of the fourth aspect, the remainder obtained by performing modulo n operation on the position serial number of the first decoding information is the same as the remainder obtained by performing modulo n operation on the position serial number of the second decoding information, where n is an integer greater than 1.

[0052] In some implementations of the fourth aspect, performing sub-block deinterleaving on the to-be-deinterleaved sequence includes: performing sub-block deinterleaving on the to-be-deinterleaved sequence based on the third deinterleaving method. Among them, the third deinterleaving method is used to write the Y sub-blocks of the to-be-deinterleaved sequence by columns and read them out by rows to complete sub-block deinterleaving. d2 is the number of writing columns corresponding to the third deinterleaving method, and the number of sub-blocks written in each column is determined based on the interleaving method of advancing rows modulo d2.

[0053] In some implementations of the fourth aspect, Z is equal to d2.

[0054] In some implementations of the fourth aspect, de-subblock interleaving the to-be-deinterleaved sequence includes: de-subblock interleaving the to-be-deinterleaved sequence based on a second deinterleaving method, where the second deinterleaving method is used to write the Y subblocks of the to-be-deinterleaved sequence row by row and read them column by column to complete de-subblock interleaving. Here, d1 is the number of columns written corresponding to the second deinterleaving method, and the number of subblocks written in each row is determined based on the interleaving method with columns modulo d1. d1 is an integer greater than 1 and less than Y.

[0055] In some implementations of the fourth aspect, the subblocks included in any one of the L subblock groups are consecutive subblocks among the Y subblocks of the third deinterleaved sequence.

[0056] Fifth aspect, an interleaving method is provided. This method can be executed by a transmitting device. Without special instructions, the "transmitting device" in this application can refer to the transmitting device itself (e.g., a network device, a terminal device), or a component in the transmitting device (e.g., a processor, a chip, or a chip system, etc.), or it can also be a logic module or software that can implement all or part of the functions of the transmitting device.

[0057] The method includes: writing every d subblocks out of the Y subblocks row by row. The Y subblocks are obtained by dividing the to-be-interleaved codeword sequence based on the number of bits X included in a preset subblock. Both X and Y are integers greater than 1, and d is an integer greater than 1 and less than Y; performing subblock interleaving on at least one of the d subblock groups within the corresponding subblock group, where the d subblock groups are the subblock groups corresponding to d columns of subblocks after writing row by row; performing cross-subblock bit interleaving on the bits included in at least one of the L subblock groups within the corresponding subblock group, where the L subblock groups are the subblock groups corresponding to the Y subblocks read row by row after performing subblock interleaving within the corresponding subblock group based on the number of subblocks Z included in a preset subblock group. Both Z and L are integers greater than 1; obtaining a second codeword sequence, where the second codeword sequence is the sequence obtained by reading the subblocks column by column.

[0058] It can be understood that in this technical solution, cross-subblock bit interleaving can be regarded as being implemented during the block interleaving process, that is, based on a third interleaving method, between writing row by row and reading column by column, first performing a block interleaving on each column of subblocks, and then dividing the obtained Y subblocks into L subblock groups in the way of reading row by row. It should be noted that the way of reading row by row here is not a real reading, but just a way to describe the division of the L subblock groups. After that, after completing the cross-subblock bit interleaving on the L subblock groups, read the Y subblocks column by column. This method can reduce the hardware overhead required for interleaving and improve the throughput.

[0059] In some implementations of the fifth aspect, Z is equal to d.

[0060] In some implementations of the fifth aspect, cross-subblock bit interleaving is performed on the bits included in at least one sub-block group among the L sub-block groups within the corresponding sub-block group, including: performing cross-subblock bit interleaving on the bits included in the first sub-block group among the at least one sub-block group within the first sub-block group based on a first interleaving method, where the first sub-block group includes a first sub-block and a second sub-block, and the first interleaving method is used to place a first bit included in the first sub-block at a first position, where the first position is the position where a second bit included in the second sub-block is located.

[0061] In some implementations of the fifth aspect, the remainder obtained by performing a modulo-n operation on the position number of the first bit is the same as the remainder obtained by performing a modulo-n operation on the position number of the second bit, where n is an integer greater than 1.

[0062] In some implementations of the fifth aspect, sub-block interleaving is performed on at least one sub-block group among the d sub-block groups within the corresponding sub-block group, including: performing sub-block interleaving on at least one sub-block group among the d sub-block groups by translating the sub-blocks in the column direction within the corresponding sub-block group.

[0063] Sixth aspect, a communication device is provided, and the device is used to execute the method provided in the first aspect or the third aspect or the fifth aspect. Specifically, the device may include units and / or modules for executing the method in any one of the first aspect or the third aspect or the fifth aspect or any possible implementation manner in the first aspect or the third aspect or the fifth aspect, such as a processing unit and / or a communication unit.

[0064] In one implementation, the device is a transmitting-end device. When the device is a transmitting-end device, the communication unit may be a transceiver, or an input / output interface; the processing unit may be at least one processor. Optionally, the transceiver may be a transceiver circuit. Optionally, the input / output interface may be an input / output circuit.

[0065] In another implementation, the device is a chip, a chip system, or a circuit in the transmitting-end device. When the device is a chip, a chip system, or a circuit in the transmitting-end device, the communication unit may be an input / output interface, an interface circuit, an output circuit, an input circuit, a pin, or a related circuit, etc. on the chip, the chip system, or the circuit; the processing unit may be at least one processor, a processing circuit, or a logic circuit, etc.

[0066] In a seventh aspect, a communication device is provided, which is configured to execute the method provided in the second aspect or the fourth aspect above. Specifically, the device may include units and / or modules configured to execute the method in any one of the second aspect or the fourth aspect, or in any possible implementation manner of the second aspect or the fourth aspect, such as a processing unit and / or a communication unit.

[0067] In one implementation manner, the device is a receiving-end device. When the device is a receiving-end device, the communication unit may be a transceiver, or an input / output interface; the processing unit may be at least one processor. Optionally, the transceiver may be a transceiver circuit. Optionally, the input / output interface may be an input / output circuit.

[0068] In another implementation manner, the device is a chip, a chip system or a circuit in a receiving-end device. When the device is a chip, a chip system or a circuit in a sending-end device, the communication unit may be an input / output interface, an interface circuit, an output circuit, an input circuit, a pin or a related circuit, etc. on the chip, the chip system or the circuit; the processing unit may be at least one processor, a processing circuit or a logic circuit, etc.

[0069] In an eighth aspect, a communication device is provided, which includes: at least one processor, the at least one processor is coupled to at least one memory, the at least one memory is configured to store a computer program or instructions, and the at least one processor is configured to call and run the computer program or instructions from the at least one memory, so that the method in any one of the first aspect, the third aspect or the fifth aspect, or in any possible implementation manner of the first aspect, the third aspect or the fifth aspect is executed.

[0070] In one implementation manner, the device is a sending-end device.

[0071] In another implementation manner, the device is a chip, a chip system or a circuit in a sending-end device.

[0072] In a ninth aspect, a communication device is provided, which includes: at least one processor, the at least one processor is coupled to at least one memory, the at least one memory is configured to store a computer program or instructions, and the at least one processor is configured to call and run the computer program or instructions from the at least one memory, so that the method in any one of the second aspect or the fourth aspect, and in any possible implementation manner of the second aspect or the fourth aspect is executed.

[0073] In one implementation manner, the device is a receiving-end device.

[0074] In another implementation manner, the device is a chip, a chip system or a circuit in a receiving-end device.

[0075] In a tenth aspect, a processor is provided for executing the methods provided in the above aspects.

[0076] For operations such as sending, obtaining / receiving, etc. involved in the processor, if there is no special description, or if it does not conflict with its actual role or internal logic in the relevant description, it can be understood as operations such as the processor outputting and receiving, inputting, etc., and can also be understood as operations of sending and receiving performed by the radio frequency circuit and the antenna. This application does not make any limitations in this regard.

[0077] In an eleventh aspect, a computer-readable storage medium is provided. When the computer program or instruction stored in the computer-readable storage medium runs on a computer, the methods in any one of the first aspect to the fourth aspect or any one of the possible implementation manners in the first aspect to the fourth aspect are executed.

[0078] In a twelfth aspect, a computer program product containing instructions is provided. When the computer program product runs on a computer, the methods in any one of the first aspect to the fourth aspect and any one of the possible implementation manners in the first aspect to the fourth aspect are executed.

[0079] In a thirteenth aspect, a chip is provided. The chip includes a processor and a communication interface. The processor reads a computer program or instruction stored on a memory through the communication interface. When the computer program or instruction runs, the methods in any one of the first aspect to the fourth aspect or any one of the possible implementation manners in the first aspect to the fourth aspect are executed.

[0080] Optionally, as an implementation manner, the chip further includes a memory.

[0081] In a fourteenth aspect, a communication system is provided. The communication system includes the communication devices shown in the eighth aspect and the ninth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0082] Figure 1 It is a schematic diagram of the system architecture of a communication system applicable to the technical solution of this application.

[0083] Figure 2 It is a schematic flowchart of the process of a communication system applicable to this application.

[0084] Figure 3 It is a schematic diagram of row-column interleaving in an existing communication standard.

[0085] Figure 4 It is a schematic flowchart of an interleaving method 400 provided by this application.

[0086] Figure 5 It is a schematic diagram of an interleaving manner performed on columns modulo d1.

[0087] Figure 6 Schematic diagram of the interleaving pattern listed for the progression modulo d2.

[0088] Figure 7 Schematic diagram of implementing cross-subblock bit interleaving based on a possible first interleaving pattern.

[0089] Figure 8 Schematic diagram of implementing cross-subblock bit interleaving based on another possible first interleaving pattern.

[0090] Figure 9 Schematic diagram of a specific example of implementing interleaving based on method 400.

[0091] Figure 10 Schematic diagram of another specific example of implementing interleaving based on method 400.

[0092] Figure 11 Schematic flowchart of a deinterleaving method 1100 provided by the present application.

[0093] Figure 12 Schematic flowchart of an interleaving method 1200 provided by the present application.

[0094] Figure 13 Schematic diagram of a specific example of implementing interleaving based on method 1200.

[0095] Figure 14 Schematic flowchart of a deinterleaving method 1400 provided by the present application.

[0096] Figure 15 Schematic block diagram of a communication device 1500 provided by the present application.

[0097] Figure 16 Schematic structural diagram of a communication device 1600 provided by the present application. Detailed implementation manners

[0098] The technical solutions in the present application will be described below in conjunction with the accompanying drawings.

[0099] The technical solutions of the embodiments of the present application can be applied to various communication systems, including but not limited to: satellite communication systems, the 5th generation (5G) systems or new radio (NR) systems, long term evolution (LTE) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, etc. The technical solutions provided by the present application can also be applied to future communication systems, such as the sixth generation mobile communication system. In addition, it can also be applied to device to device (D2D) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), and Internet of Things (IoT) communication systems or other communication systems, which are not limited herein.

[0100] The communication system applicable to the present application may include one or more sending ends and one or more receiving ends. Optionally, one of the sending end and the receiving end may be a terminal device, and the other may be a network device. Or, both the sending end and the receiving end are terminal devices. The sending end can also be regarded as an encoding end or an encoding device, and the receiving end can also be regarded as a decoding end or a decoding device.

[0101] Exemplarily, a terminal device may also be referred to as a user equipment (UE), an access terminal, a user unit, a user station, a mobile station, a mobile device, a mobile terminal (MT), a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a wireless communication device, a user agent, or a user device. The terminal device in the embodiments of the present application may be a device that provides voice and / or data connectivity to a user and can be used to connect people, things, and machines, such as a handheld device with a wireless connection function, a vehicle-mounted device, etc. The terminal device in the embodiments of the present application may be a mobile phone, a tablet computer (pad), a laptop computer, a palm computer, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, etc. Optionally, the UE can be used as a base station. For example, the UE can act as a scheduling entity that provides sidelink signals between UEs in V2X or D2D, etc.

[0102] In the embodiments of the present application, the device for implementing the functions of the terminal may be the terminal or a device capable of supporting the terminal to implement such functions, such as a chip system or a chip, and this device may be installed in the terminal. In the embodiments of the present application, the chip system may be composed of chips or may include chips and other discrete devices. The methods provided in the present application may be executed by the terminal device. Without special explanation, the "terminal device" in the present application may refer to the terminal device itself, a component in the terminal device (such as a processor, a chip, or a chip system, etc.), or may also be a logical module or software that can implement all or part of the functions of the terminal device.

[0103] Exemplarily, the network device may be a device with wireless transceiver functions. The network device may be a device providing wireless communication function services, usually located on the network side, including but not limited to the next-generation base station (gNodeB, gNB) in the fifth-generation (5G) communication system, the base station in the sixth-generation (6G) mobile communication system, the base station in future mobile communication systems, or the access node in a wireless fidelity (Wi-Fi) system, the evolved node B (eNB) in the long term evolution (LTE) system, the radio network controller (RNC), the node B (NB), the base station controller (BSC), the home base station (e.g., home evolved NodeB, or home Node B, HNB), the base band unit (BBU), the transmission reception point (TRP), the transmitting point (TP), the base transceiver station (BTS), etc. In one network structure, the network device may include a centralized unit (CU) node, or include a distributed unit (DU) node, or include a radio access network (RAN) device including a CU node and a DU node, or include a control plane CU node and a user plane CU node, and a RAN device with a DU node. Or, the network device may also be a wireless controller, a relay station, a vehicle-mounted device, and a wearable device, etc. in the cloud radio access network (CRAN) scenario. In addition, the base station may be a macro base station, a micro base station, a relay node, a donor node, or a combination thereof. The base station may also refer to a communication module, a modem, or a chip disposed in the foregoing devices or apparatuses. The base station may also be a mobile switching center and a device undertaking the base station function in D2D, V2X, M2M communications, a network-side device in a 6G network, a device undertaking the base station function in future communication systems, etc. The base station may support networks with the same or different access technologies, without limitation.

[0104] In the embodiments of the present application, the device for implementing the functions of a network device may be a network device, or a device capable of supporting the network device to implement such functions, such as a chip system or a chip, and this device may be installed in the network device. In the embodiments of the present application, the chip system may be composed of chips, or may include chips and other discrete devices. The method provided in the present application may be executed by a network device. Without special indication, the "network device" in the present application may refer to the network device itself, or a component in the network device (such as a processor, a chip, or a chip system, etc.), or may also be a logical module or software capable of implementing all or part of the functions of the network device.

[0105] Figure 1 Schematic diagram of the system architecture of a communication system applicable to the technical solution of the present application. The communication system may include one or more network devices, and one or more terminal devices. As Figure 1 shown, the method provided in the present application may be applicable to the communication between a network device and a terminal, that is, uplink or downlink communication. In this communication scenario, the sending end in this article may be a terminal in uplink communication or a network device in downlink communication, and the receiving end may be a network device in uplink communication or a terminal in downlink communication. In addition, optionally, the technical solution of the present application may also be applied to sidelink communication. In this communication scenario, the sending end is the sending terminal in sidelink communication, and the receiving end is the receiving terminal in sidelink communication. In addition, it may also be applied to other communication scenarios, which will not be elaborated here.

[0106] Communication systems usually adopt channel coding to improve the reliability of data transmission and ensure the quality of communication. Channel coding and decoding is one of the core technologies in the field of wireless communication, and the improvement of its performance will directly improve network coverage and user transmission rate. Polar code is a channel coding scheme that can be strictly proved to achieve the Shannon channel capacity. Polar code has characteristics such as good performance and low complexity. At present, it has been determined by the 3rd generation partnership project (3GPP) to be the control channel coding scheme for the enhanced mobile broadband (eMBB) scenario (uplink / downlink) in the 5th generation (5G) scenario.

[0107] Figure 2 Flow schematic diagram of a communication system applicable to the present application. As Figure 2, Channel coding is located between source coding and modulation and is responsible for channel coding the bits generated by the source. Channel decoding is located between demodulation and source decoding and is responsible for restoring the source bit stream. Taking the use of Polar codes for channel coding as an example, at the transmitting end, the source bit stream from media access control (MAC) is channel-coded using Polar codes, and after modulation according to the codebook, the modulated symbols are sent through a noisy channel to the receiving end for demodulation. Multiple bits of the symbol are demodulated to obtain corresponding multiple decoding information, and the decoding information is sent into the Polar decoder to restore the source bit stream, which is then uploaded to the MAC. For example, the decoding information can be log likelihood ratio (LLR) or log likelihood (LL).

[0108] It can be understood that the interleaving method provided in this application can be regarded as a channel coding scheme, which can be used in dedicated network devices or general devices, can be applied to various network devices as described above (for example, base station devices), and can also be applied to various terminal devices as described above. Specifically, this channel coding scheme is mainly implemented through the channel coding unit in these devices.

[0109] The method provided in the embodiments of this application can also be implemented through application-specific integrated circuit (ASIC), field programmable gate array (FPGA), etc., or can be implemented through software (for example, program code in a memory), without limitation.

[0110] For coding, its basic construction method is considered based on the additive white Gaussian noise (AWGN) channel, so it is defaulted that the capacity of the input sub-channels at each bit position is the same. However, the real situation is that once high-order modulation is used, or there is a fading channel situation, it cannot be guaranteed that the capacity of the input sub-channels at each bit is the same. For example, when high-order modulation is demodulated, after multiple bits in a symbol are demodulated, their signal energies are not the same. It can be understood that the capacities of the sub-channels where multiple bits in a high-order modulation are located are inconsistent. When consecutive bits of a codeword are mapped to a symbol, the demodulation result will show a regular change in the sub-channel capacity of the codeword, thus not conforming to the assumed channel environment during coding construction, and therefore the decoding result will deteriorate. Similarly, a fading channel will also cause similar problems, making the capacity of some consecutive positions of the codeword differ greatly from that of another part of the consecutive positions.

[0111] To solve this problem, it is proposed to randomize the sub-channel differences through channel bit interleaving, so that the capacities of the sub-channels at each position of the entire codeword become uniform. For channel bit interleaving, the best interleaving scheme should be the random interleaving of the entire transmitted codeword. However, random interleaving is difficult to implement in actual engineering. Therefore, some realizable interleaving methods are used to interleave the codeword. For example, the realizable interleaving methods include the row-column interleaving method in existing communication standards and the triangular interleaving in 5G-NR.

[0112] The following is a brief introduction to the row-column interleaving in existing communication standards. In existing communication standards, Polar codes are adopted as the only encoding and decoding scheme for control and data channels, and a channel bit interleaving scheme is designed for Polar codes. The row-column interleaving method modulo 14 is adopted, where the row-column interleaving method modulo 14 is used to input each bit of the E bits (i.e., E is the transmission length of the codeword for this transmission) included in the codeword to be interleaved row by row, where, represents rounding up, where 14 is the fixed number of rows corresponding to writing row by row. The schematic diagram of writing row by row and reading column by column corresponding to the row-column interleaving method modulo 14 is as Figure 3 shown.

[0113] Exemplarily, the codeword sequence to be interleaved is e0, e1, e2, e3, …, e E-1 , and the codeword sequence obtained after interleaving is f0, f1, f2, f3, … f E-1 . f0 is the bit first output by the interleaver corresponding to the row-column interleaving method modulo 14. Its specific pseudo-code is as follows:

[0114]

[0115] In order to achieve a random process, the current channel bit interleaving usually performs a large-range interleaving over the length of the entire transmitted codeword. However, because this interleaving method has a large interleaving range and no rules to follow, the interleaving and de-interleaving processes will consume a lot of hardware resources and it is difficult to improve the parallelism. It is not suitable as the channel bit interleaving scheme in the next-generation communication system.

[0116] In view of this, the present application proposes an interleaving method that can effectively solve the above technical problems. The method proposed by the present application will be described in detail below.

[0117] Figure 4 FIG. 400 is a schematic flowchart of an interleaving method 400 provided by the present application. The method includes the following steps.

[0118] S410, the sending device performs sub-block interleaving on the to-be-interleaved codeword sequence to obtain a first codeword sequence. Both the to-be-interleaved codeword sequence and the first codeword sequence include Y sub-blocks. The Y sub-blocks of the to-be-interleaved codeword sequence are determined based on the number of bits X included in a preset sub-block. Both X and Y are integers greater than 1.

[0119] Optionally, before performing sub-block interleaving, the to-be-interleaved codeword sequence {a0, a1, a2, a3, … a N-2 , a N-1} with length (i.e., the number of bits included) N is sub-block divided. Based on the length X of a preset sub-block, Y sub-blocks {A0, A1, A2, … A (Y-1)} after the division of the to-be-interleaved codeword sequence are obtained, where represents rounding up. It can be understood that if N cannot be divided evenly by X, the length of one of the Y sub-blocks is less than X. For example, when sub-block dividing the to-be-interleaved codeword sequence starting from the first bit according to X, the length of the last sub-block may be less than X.

[0120] After that, sub-block interleaving is performed on the Y sub-blocks obtained by dividing the to-be-interleaved codeword sequence. For example, the block interleaving sequence is I1. Based on I1, sub-block interleaving is performed on the Y sub-blocks of the to-be-interleaved codeword sequence, and the interleaved first codeword sequence obtained is {B0, B1, B2, … B (Y-1)}.

[0121] This application does not make specific restrictions on I1, as long as block interleaving can be achieved based on I1. The method of performing sub-block interleaving based on I1 can refer to the following pseudocode:

[0122]

[0123]

[0124] Exemplarily, the to-be-interleaved codeword sequence {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26} with length 27 is divided. The length of a preset sub-block is X = 3. Therefore, after dividing the to-be-interleaved codeword sequence, Y = 9 sub-blocks are obtained. Among them, the 9 sub-blocks are sub-block 0 = {0, 1, 2}, sub-block 1 = {3, 4, 5}, sub-block 2 = {6, 7, 8}, sub-block 3 = {9, 10, 11}, sub-block 4 = {12, 13, 14}, sub-block 5 = {15, 16, 17}, sub-block 6 = {18, 19, 20}, sub-block 7 = {21, 22, 23}, sub-block 8 = {24, 25, 26}.

[0125] Then, the 9 divided sub-blocks are interleaved based on the block interleaving sequence I1. For example, the sub-block interleaving sequence I1 = {3, 6, 2, 7, 8, 1, 0, 5, 4}, where 3 means placing sub-block 3 at the position of sub-block 0, 6 means placing sub-block 6 at the position of sub-block 1, and 2 means placing sub-block 2 at the position of sub-block 2 (i.e., remaining unchanged). The codeword sequence obtained after sub-block interleaving (i.e., the first codeword sequence) is {9, 10, 11}, {18, 19, 20}, {6, 7, 8}, {21, 22, 23}, {24, 25, 26}, {3, 4, 5}, {0, 1, 2}, {15, 16, 17}, {12, 13, 14}.

[0126] For example, the present application can also implement block interleaving of Y sub-blocks through the following two possible block interleaving methods. One is a column-by-column interleaving method modulo d1 (i.e., writing by column and reading by row), and the other is a row-by-row interleaving method modulo d2 (i.e., writing by row and reading by column), wherein d1 and d2 are both integers greater than 1 and less than Y, and d1 and d2 are fixed numbers of columns or fixed numbers of rows after writing of the corresponding interleaving method. For ease of description, d1 and d2 are described below as fixed numbers of columns after writing of the corresponding interleaving method.

[0127] For example, d1 and d2 can be prime numbers greater than 1 and less than Y. For example, Y=34, the values ​​of d1 and d2 are 3, 5 or 7.

[0128] (1) The columns of the modulo d1 are interleaved (hereinafter referred to as the second interleaving method). This interleaving method is used for each of the Y sub-blocks. The sub-blocks are written in columns and read out in rows to complete the sub-block interleaving. For example, Y = 34, d1 = 5, then the sub-block reading and writing method under this interleaving method is as follows: Figure 5 As shown, specifically, sub-blocks 0 to 33 are read in columns in sequence, and the number of blocks read in each column is That is, the first column reads sub-blocks 0 to 6, the second column reads sub-blocks 7 to 13, and so on. The last column reads the remaining sub-blocks 28 to 33. After that, the sub-blocks corresponding to each column are read out, the sub-blocks {0, 7, 14, 21, 28} of the first row are read out, and the sub-blocks {1, 8, 15, 22, 29} of the second row are read out, until the sub-blocks corresponding to all rows are read out. The sub-blocks read out by row are the interleaved sub-blocks.

[0129] (2) A row-by-row interleaving method modulo d2 (hereinafter referred to as the third interleaving method) is used to write every d2 sub-blocks in Y sub-blocks in rows and read them out in columns to complete sub-block interleaving. For example, Y = 34, d2 = 5, then the reading and writing method of the sub-blocks under this interleaving method is as follows: Figure 6As shown, specifically, sub - blocks 0 to 33 are read in row - by - row, with 5 sub - blocks read in each row. That is, in the first row, sub - blocks 0 to 4 are read in, in the second row, sub - blocks 5 to 9 are read in, and so on. In the last row, the remaining sub - blocks 30 to 33 are read in. Then, the sub - blocks in the first column {0, 5, 10, 15, 20, 25, 30} are read out column - by - column, the sub - blocks in the second column {1, 6, 11, 16, 21, 26, 31} are read out, until all the sub - blocks corresponding to all columns are read out. The sub - blocks read out column - by - column are the interleaved sub - blocks.

[0130] S420, the sending - end device performs cross - sub - block bit interleaving on the bits included in at least one of the L sub - block groups among the L sub - block groups to obtain a second codeword sequence, where the L sub - block groups are determined based on the Y sub - blocks of the first codeword sequence and the number Z of sub - blocks included in a preset sub - block group, and both Z and L are integers greater than 1.

[0131] Optionally, before performing cross - sub - block bit interleaving, the Y sub - blocks of the first codeword sequence {B0, B1, B2…B (Y-1)} are divided into sub - block groups. Based on the number Z of sub - blocks included in a preset sub - block group, L sub - block groups after the division of the first codeword sequence are obtained, where, represents rounding up. It can be understood that if Y cannot be divided evenly by Z, the number of sub - blocks included in one of the L sub - block groups is less than Z. For example, when the first codeword sequence is divided into sub - block groups starting from the first sub - block according to Z, the number of sub - blocks included in the last sub - block group may be less than Z.

[0132] Exemplarily, the sub - blocks included in any one of the L sub - block groups can be consecutive sub - blocks or non - consecutive sub - blocks, and this application does not limit this. It can be understood that the consecutive / non - consecutive sub - blocks here refer to the consecutive / non - consecutive sub - blocks among the Y sub - blocks included in the first codeword sequence.

[0133] After that, cross - sub - block bit interleaving is performed on the bits included in at least one of the L sub - block groups after division to obtain an output sequence {c0, c1, c2, c3,…c N-2 , c N-1}. Among them, performing cross-subblock bit interleaving on the bits included in at least one subblock group among the L subblock groups within the corresponding subblock group includes: performing cross-subblock bit interleaving on the bits included in the first subblock group among at least one subblock group based on the first interleaving method. Among them, the first subblock group includes the first subblock and the second subblock, and the first interleaving method is used to place the first bit included in the first subblock at the first position, where the first position is the position where the second bit included in the second subblock is located. That is to say, placing the first bit in the first subblock at a position different from a bit in the first subblock group (such as the second subblock, another subblock other than the first subblock), that is, realizing cross-subblock bit interleaving. This application does not limit the number of bits for cross-subblock interleaving in the first subblock group. All bits in the first subblock group can be subjected to cross-subblock bit interleaving, or partial bits can be subjected to cross-subblock bit interleaving.

[0134] Optionally, when cross-subblock bit interleaving is performed within the corresponding subblocks of multiple subblock groups among the L subblock groups, the cross-subblock bit interleaving sequences I2 corresponding to each subblock group can be the same or different. This application does not make specific restrictions on I2, as long as cross-subblock bit interleaving within the group can be realized based on I2.

[0135] Exemplarily, here, cross-subblock bit interleaving within the subblock group corresponding to each subblock group among the L subblocks based on the same cross-subblock bit interleaving sequence I2 is described. The method for subblock interleaving based on I2 can refer to the following pseudocode:

[0136]

[0137] Continuing with the example in S410 for illustration, for the codeword sequence (i.e., the first codeword sequence) obtained after subblock interleaving {9, 10, 11}, {18, 19, 20}, {6, 7, 8}, {21, 22, 23}, {24, 25, 26}, {3, 4, 5}, {0, 1, 2}, {15, 16, 17}, {12, 13, 14} (i.e., subblocks {3, 6, 2, 7, 8, 1, 0, 5, 4}) for subblock group division, the number of subblocks Z included in a preset subblock group is 3. Therefore, after dividing the 9 subblocks of the first codeword sequence from front to back with every consecutive 3 subblocks as a subblock group, L = 3 subblock groups are obtained. The 3 subblock groups are subblock group 0 = {{9, 10, 11}, {18, 19, 20}, {6, 7, 8}} (i.e., subblocks {3, 6, 2}), subblock group 1 = {{21, 22, 23}, {24, 25, 26}, {3, 4, 5}} (i.e., subblocks {7, 8, 1}), and subblock group 2 = {{0, 1, 2}, {15, 16, 17}, {12, 13, 14}} (i.e., subblocks {0, 5, 4}).

[0138] After that, cross-block bit interleaving is performed on the divided 3 sub-block groups based on the cross-block bit interleaving sequence I2. It can be seen that the number of bits for cross-block bit interleaving within each sub-block group is X * Z = 9. For example, the cross-block bit interleaving sequence I2 = {3, 8, 1, 6, 0, 2, 7, 5, 4}. Among them, after performing cross-block bit interleaving on sub-block group 0 = {{9, 10, 11}, {18, 19, 20}, {6, 7, 8}}, it becomes {18, 8, 10, 6, 9, 11, 7, 20, 19}. After performing cross-block bit interleaving on sub-block group 1 = {{21, 22, 23}, {24, 25, 26}, {3, 4, 5}}, it becomes {24, 5, 22, 3, 21, 23, 4, 26, 25}. After performing cross-block bit interleaving on sub-block group 2 = {{0, 1, 2}, {15, 16, 17}, {12, 13, 14}}, it becomes {15, 14, 1, 12, 0, 2, 13, 17, 16}. Therefore, the finally obtained codeword sequence (i.e., the second codeword sequence) is {18, 8, 10, 6, 9, 11, 7, 20, 19, 24, 5, 22, 3, 21, 23, 4, 26, 25, 15, 14, 1, 12, 0, 2, 13, 17, 16}.

[0139] Optionally, if the sub-block interleaving is performed in the interleaving manner based on the columns modulo d1 in S410, then Z can be equal to d1, that is, a row of read sub-blocks is divided into a sub-block group.

[0140] Optionally, if the sub-block interleaving is performed in the interleaving manner based on the rows modulo d2 in S410, then Z can be equal to d2, that is, a column of read sub-blocks is divided into a sub-block group.

[0141] A possible specific first interleaving manner is given below. In this first interleaving manner, the bits in a sub-block group are offset by the positions congruent modulo n. The positions congruent modulo n refer to the situation where the remainder obtained by performing modulo n operation on the position serial number of the first bit in the first sub-block of the above first sub-block group is the same as the remainder obtained by performing modulo n operation on the position serial number of the second bit in the second sub-block of the first sub-block group, where n is an integer greater than 1. For example, n is a prime number greater than 1. Among them, the position serial number of a bit (such as the first bit or the second bit) in the first sub-block group is S, indicating that this bit is the S-th bit among all the bits in the first sub-block group.

[0142] Optionally, the offset values corresponding to each bit in the first sub-block can be the same or different, and the present application does not make any limitation in this regard. For example, if there are multiple bits in the first sub-block group whose remainders obtained by performing modulo n operation are the same as the remainder obtained by performing modulo n operation on the position serial number of the first bit, then the first bit can be offset to the position where any one of these multiple bits is located.

[0143] It can be understood that since the cross-sub-block bit interleaving is the bit interleaving within a sub-block group, hereinafter, only one sub-block group will be described. For example, based on Figure 5 the interleaving method derived from the columns modulo 5 shown, the sub-block group A corresponding to the sub-blocks {0, 7, 14, 21, 28} read in the first row will be used as an example for description.

[0144] For example, as Figure 7 shown, the length of each sub-block in the sub-block group A is 4 (i.e., including 4 bits). Among them, 0-0, 0-1, 0-2, 0-3 respectively represent the 0th bit to the 3rd bit of the sub-block 0, and 7-0, 7-1, 7-2, 7-3 respectively represent the 0th bit to the 3rd bit of the sub-block 7. Details will not be elaborated here. Among them, Figure 7 for the offset using the congruence position modulo 3, and the bits with a remainder of 0 after modulo 3 of the position serial number in the sub-block group A are offset by 0 (i.e., 0 * 3) bit positions (i.e., the positions remain unchanged, such as the positions of 0-0, 0-3, 7-2), the bits with a remainder of 1 after modulo 3 of the position serial number in the sub-block group A are offset by 3 (i.e., 1 * 3) bit positions (for example, 0-1 is placed at the position of 7-0 in the sub-block 7, and 7-0 is placed at the position of 7-3 in the sub-block 7), and the bits with a remainder of 2 after modulo 3 of the position serial number in the sub-block group A are offset by 6 (i.e., 2 * 3) bit positions (for example, 0-2 is placed at the position of 14-0 in the sub-block 14, and 7-1 is placed at the position of 14-3 in the sub-block 14).

[0145] For example, as Figure 8 shown, the length of each sub-block in the sub-block group A is 4 (i.e., including 4 bits). Among them, 0-0, 0-1, 0-2, 0-3 respectively represent the 0th bit to the 3rd bit of the sub-block 0, and 7-0, 7-1, 7-2, 7-3 respectively represent the 0th bit to the 3rd bit of the sub-block 7. Details will not be elaborated here. Among them, Figure 8For modulo-5 congruence position offset, the bits with a remainder of 0 after modulo-5 of the position numbers in sub-block group A are offset by 0 (i.e., 0*5) bit positions (e.g., the positions of 0-0 and 7-1 remain unchanged), the bits with a remainder of 1 after modulo-5 of the position numbers in sub-block group A are offset by 5 (1*5) bit positions (e.g., place 0-1 at the position of 7-2 in sub-block 7, and place 7-2 at the position of 14-3 in sub-block 14), the bits with a remainder of 2 after modulo-5 of the position numbers in sub-block group A are offset by 10 (2*5) bit positions (e.g., place 0-2 at the position of 21-0 in sub-block 21, and place 7-3 at the position of 28-1 in sub-block 28), the bits with a remainder of 3 after modulo-5 of the position numbers in sub-block group A are offset by 15 (i.e., 3*5) bit positions (e.g., place 0-3 at the position of 28-2 in sub-block 28, and place 14-0 at the position of 0-3 in sub-block 0), the bits with a remainder of 4 after modulo-5 of the position numbers in sub-block group A are offset by 20 (i.e., 4*5) bit positions (i.e., equivalent to an offset of 0 bit positions) (e.g., the positions of 7-0 and 14-1 remain unchanged).

[0146] In the above technical solution, the interleaving process of the codeword sequence to be interleaved is divided into two steps. The first step is sub-block interleaving, which scatters the originally concentrated bit positions to different positions in the transmission sequence in a large range through sub-block interleaving. The second step is small-range cross-sub-block bit interleaving within the sub-block group composed of multiple sub-blocks, so as to break the correlation between consecutive bits. In this way, the parallelism can be improved through large-range sub-block interleaving, and through small-range cross-sub-block bit interleaving within the sub-block group, which can be obtained through a fixed interconnection relationship and is easy to implement in hardware, thus solving the problems of irregular deinterleaving, inability to improve parallelism, and large hardware overhead caused by small-granularity bit interleaving in a large range in the original interleaving.

[0147] The following combines Figure 9 to give a specific example based on Method 400. As Figure 9 shown, the codeword sequence to be interleaved includes a total of Y = 34 sub-blocks, numbered from sub-block 0 to sub-block 33, and each sub-block includes X = 4 bits. As Figure 9As shown in the figure, (1) Sub - block interleaving is performed on the Y sub - blocks of the codeword sequence to be interleaved based on the interleaving method performed on the columns with modulo d1 = 5. Specifically, the first column reads sub - blocks 0 to sub - block 6, the second column reads sub - blocks 7 to sub - block 13, and so on. The last column reads the remaining sub - blocks 28 to sub - block 33. Then, the sub - blocks corresponding to each column are read out. The sub - blocks of the first row {0, 7, 14, 21, 28} are read out, the sub - blocks of the second row {1, 8, 15, 22, 29} are read out, until all the sub - blocks corresponding to all rows are read out to obtain the first codeword sequence; (2) Then, in this example, Z = d1 = 5 is taken, that is, each row of sub - blocks read out by rows is divided into a sub - block group, and L = 7 sub - block groups are obtained. Cross - sub - block bit interleaving is performed on each sub - block group. In this example, for all bits in each sub - block group, an offset is made at positions congruent modulo 3 to achieve cross - sub - block bit interleaving. Among them, for the sub - blocks {0, 7, 14, 21, 28} read in the first row, the process of cross - sub - block bit interleaving can be referred to Figure 7 the corresponding description. The method of performing cross - sub - block bit interleaving on the sub - block groups corresponding to the second row to the seventh row is the same as that of performing cross - sub - block bit interleaving on the sub - block group corresponding to the first row, and will not be elaborated here; (3) Finally, after all sub - block groups complete cross - sub - block bit interleaving, the final second codeword sequence is obtained.

[0148] Based on the description in S420, it can be known that the sub - blocks included in any one of the L sub - block groups can be consecutive sub - blocks or non - consecutive sub - blocks among the Y sub - blocks of the first codeword sequence. It can be understood that Figure 9 any one of the L sub - block groups includes Z consecutive sub - blocks among the Y sub - blocks of the first codeword sequence. The following specifically describes the implementation method in which one of the L sub - block groups includes non - consecutive sub - blocks among the Y sub - blocks of the first codeword sequence. For example, in this implementation method, the first codeword sequence can be obtained based on the second interleaving method (i.e., the interleaving method performed on the columns with modulo d1), or can be obtained based on the third interleaving method (i.e., the row - by - column interleaving method with modulo d2). For the convenience of description, the following takes the block interleaving of the Y sub - blocks of the codeword sequence to be interleaved based on the third interleaving method as an example for illustration.

[0149] For example, in this implementation method, the third interleaving method is also used to perform sub - block interleaving on at least one of the d2 sub - block groups within the corresponding sub - block group between writing by rows and reading by columns. Among them, the d2 sub - block groups are the sub - block groups corresponding to d2 columns of sub - blocks after writing by rows. Then, the first codeword sequence is the sequence obtained by reading by columns after performing block interleaving within the corresponding sub - block group, and the L sub - block groups can be the L sub - block groups obtained by reading by rows with every Z sub - blocks after performing block interleaving within the corresponding sub - block group. Therefore, any one of the L sub - block groups includes non - consecutive sub - blocks among the Y sub - blocks of the first codeword sequence.

[0150] Optionally, Z is equal to d2, that is, after writing by row, each row of sub-blocks in the sub-block corresponding to the sub-block group corresponding to each column is divided into a sub-block group after sub-block interleaving within the sub-block group.

[0151] Optionally, the third interleaving method is used to perform sub-block interleaving on at least one sub-block group among the d2 sub-block groups within the corresponding sub-block group between writing by row and reading by column, including: the third interleaving method is used to perform sub-block interleaving on at least one sub-block group among the d2 sub-block groups within the corresponding sub-block group by translating the sub-blocks in the column direction between writing by row and reading by column.

[0152] The following is combined with Figure 10 for illustration. As Figure 10 shown, the codeword sequence to be interleaved includes a total of Y = 34 sub-blocks, numbered from sub-block 0 to sub-block 33, and each sub-block includes X = 4 bits. As Figure 10 shown, (1) Perform sub-block interleaving on the Y sub-blocks of the codeword sequence to be interleaved based on the interleaving method listed by rows modulo d2 = 5. Specifically, the number of sub-blocks read in each row is 5, that is, the first row reads sub-blocks 0 to sub-block 4, the first row reads sub-blocks 5 to sub-block 9, and so on, and the last row reads the remaining sub-blocks 30 to sub-block 33; (2) Then, translate (i.e., interleave) each column of sub-blocks in the column direction (i.e., within a sub-block group). For example, the sub-blocks in the first column remain unchanged, the sub-blocks in the second column are translated up by 1 sub-block, the sub-blocks in the third column are translated up by 2 sub-blocks, the sub-blocks in the fourth column are translated up by 3 sub-blocks, and the sub-blocks in the fifth column are translated up by 5 sub-blocks. The positions of the sub-blocks in each column after translation are as Figure 10As shown, the first codeword sequence read by column at this time is the sub-block {0, 5, 10, 15, 20, 25, 30, 31, 1, 6, 11, 16, 21, 26, 27, 32, 2, 7, 12, 17, 22, 13, 18, 23, 28, 33, 3, 8, 9, 14, 19, 24, 29, 4}; (3) In this example, Z = d2 = 5. The sub-blocks obtained by translating each column sub-block in the column direction in (2) are divided into one sub-block group in the way of reading by row, and L = 7 sub-block groups are obtained. The 7 sub-block groups are sub-block group 0 = sub-block {0, 31, 27, 13, 9}, sub-block group 1 = {5, 1, 32, 18, 14}, sub-block group 2 = {10, 6, 2, 23, 19}, sub-block group 3 = {15, 11, 7, 28, 24}, sub-block group 4 = {20, 16, 12, 33, 29}, sub-block group 5 = {25, 21, 17, 3, 4}, sub-block group 6 = {30, 26, 22, 8}. Cross-sub-block bit interleaving is performed on each sub-block group. In this example, all bits in each sub-block group are offset by positions congruent modulo 3 to achieve cross-sub-block bit interleaving. Taking the sub-block group 0 read in the first row (i.e., sub-block {0, 31, 27, 13, 9}) as an example to illustrate, the bits with a remainder of 0 modulo 3 in the position sequence of this sub-block group are offset by 0 sub-blocks (i.e., the positions remain unchanged, for example, the positions of 0-0, 0-3, 31-2 remain unchanged), the bits with a remainder of 1 modulo 3 in the position sequence of this sub-block group are offset by 1 sub-block (for example, 0-1 is placed in the position of 31-0 in sub-block 31, and 31-0 is placed in the position of 31-3 in sub-block 31), the bits with a remainder of 2 modulo 3 in the position sequence of this sub-block group are offset by 2 sub-blocks (for example, 0-2 is placed in the position of 27-0 in sub-block 27, and 31-1 is placed in the position of 27-3 in sub-block 27). The method of cross-sub-block bit interleaving for the sub-block groups corresponding to the second to seventh rows is the same as that for the sub-block group corresponding to the first row, which will not be elaborated here; (4) Finally, after all sub-block groups complete cross-sub-block bit interleaving, the sub-blocks are read by column to obtain the final second codeword sequence.

[0153] It can be understood that in this implementation method, cross-sub-block bit interleaving can be regarded as being implemented during the block interleaving process, that is, based on the third interleaving method, between writing by row and reading by column, first perform a block interleaving on each column sub-block, and then divide the obtained Y sub-blocks into L sub-block groups in the way of reading by row. It should be noted that the way of reading by row here is not a real reading, but only describes a way of dividing L sub-block groups. After that, after completing cross-sub-block bit interleaving on the L sub-block groups, read the Y sub-blocks by column.

[0154] Optionally, the corresponding interleaving method of this implementation method can also be implemented by another interleaving method. The following introduces another interleaving method. This method includes:

[0155] 1) The transmitting device writes every d2 sub - blocks out of Y sub - blocks row - by - row. The Y sub - blocks are obtained by dividing the bit - interleaved codeword sequence based on the number of bits X included in a preset sub - block. Both X and Y are integers greater than 1, and d2 is an integer greater than 1 and less than Y.

[0156] 2) The transmitting device performs sub - block interleaving on at least one sub - block group among d2 sub - block groups within the corresponding sub - block group. Here, the d2 sub - block groups are the sub - block groups corresponding to d2 columns of sub - blocks after being written row - by - row.

[0157] 3) The transmitting device performs cross - sub - block bit interleaving on the bits included in at least one sub - block group among L sub - block groups within the corresponding sub - block group. Here, the L sub - block groups are the sub - block groups corresponding to the Y sub - blocks after sub - block interleaving when reading the Y sub - blocks row - by - row based on the number of sub - blocks Z included in a preset sub - block group. Both Z and L are integers greater than 1.

[0158] 4) The transmitting device obtains a second codeword sequence, where the second codeword sequence is the sequence obtained by reading the sub - blocks column - by - column.

[0159] The above has described in detail the interleaving method shown in method 400. Based on Figure 2 the shown process, after the transmitting end obtains the second codeword sequence, it will modulate according to the codebook and then send the modulated symbols through a noisy channel to the receiving end for demodulation. Specifically, the receiving end demodulates N bits in the symbol simultaneously to obtain a de - interleaving sequence to be de - interleaved including N decoding information bits. Then, the receiving end performs de - interleaving on the de - interleaving sequence. The following describes in detail the method of this de - interleaving.

[0160] Figure 11 This is a schematic flowchart of a de - interleaving method 1100 provided by this application. It can be understood that since Figure 11 the shown de - interleaving method de - interleaves the second codeword sequence determined by method 400, therefore, corresponding to method 400, the receiving end needs to first perform the operation of de - bit - interleaving and then perform the operation of de - sub - block - interleaving. This method includes the following steps.

[0161] S1110. The receiving device performs cross - sub - block de - bit - interleaving on the decoding information included in at least one sub - block group among L sub - block groups within the corresponding sub - block group to obtain a first de - interleaved sequence. Here, the L sub - block groups are determined based on the Y sub - blocks of the de - interleaving sequence to be de - interleaved and the number of sub - blocks Z included in a preset sub - block group. The Y sub - blocks are determined based on the number of decoding information bits X included in a preset sub - block. Both X, Y, Z, and L are integers greater than 1.

[0162] Optionally, before performing cross-subblock deinterleaving, first, it is necessary to perform subblock partitioning on the deinterleaving sequence to be processed that contains N decoding information. Based on the number of decoding information X contained in a preset subblock, Y subblocks are obtained after partitioning the deinterleaving sequence to be processed, where represents rounding up. Then, it is necessary to perform subblock group partitioning on the Y subblocks obtained after partitioning the deinterleaving sequence to be processed. Based on the number of subblocks Z contained in a preset subblock group, L subblock groups are obtained after partitioning the deinterleaving sequence to be processed, where It should be noted that if N cannot be evenly divided by X, the number of decoding information contained in one of the Y subblocks is less than X. Similarly, if Y cannot be evenly divided by Z, the number of subblocks contained in one of the L subblock groups is less than Z.

[0163] After that, cross-subblock deinterleaving is performed on the decoding information contained in at least one subblock group among the L subblock groups obtained after partitioning to obtain a deinterleaved output sequence (i.e., the first deinterleaved sequence), and the first deinterleaved sequence includes Y subblocks.

[0164] It can be understood that the values of the same parameters in the deinterleaving method 1100 and the method 400 are the same.

[0165] It can also be understood that the L subblock groups in S1110 and the L subblock groups in S420 correspond one by one. Specifically, the first subblock group in the L subblock groups in S1110 includes the decoding information corresponding to the multiple bit demodulations of the first subblock group in the L subblock groups in S420, and the first subblock group in S420 and the first subblock group in S1110 are corresponding subblock groups.

[0166] Optionally, performing cross-subblock deinterleaving on the decoding information contained in at least one subblock group among the L subblock groups within the corresponding subblock group includes: performing cross-subblock bit deinterleaving on the decoding information contained in the first subblock group among at least one subblock group based on the first deinterleaving method within the first subblock group, where the first subblock group includes a first subblock and a second subblock, and the first deinterleaving method is used to place the first decoding information contained in the second subblock at the second position, where the second position is the position where the second decoding information is located in the first subblock.

[0167] It can be understood that the first de-interleaving method is the inverse operation of the first interleaving method. That is to say, the transmitting end performs cross-sub-block bit interleaving on the bits in the first sub-block group in S420 based on the first interleaving method, and then the transmitting end de-interleaves the decoded information obtained for the first sub-block group in S1110 based on the first de-interleaving method, that is, performs the inverse operation corresponding to the interleaving operation. Based on the description in S420, the transmitting end places the first bit from the second position to the first position based on the first interleaving method, and then when the receiving end de-interleaves, it places the decoded information at the first position (i.e., the first decoded information corresponding to the first bit) at the second position based on the first de-interleaving method. Optionally, the remainder of the position number at the first position after modulo n operation is the same as the remainder of the position number at the second position after modulo n operation, where n is an integer greater than 1.

[0168] S1120, the receiving end device performs de-sub-block interleaving on the first de-interleaved sequence to obtain a second de-interleaved sequence.

[0169] Specifically, de-sub-block interleaving is performed on the Y sub-blocks of the first de-interleaved sequence to obtain a second de-interleaved sequence.

[0170] It can be understood that the de-block interleaving method is determined based on the corresponding block interleaving method. By way of example, the corresponding de-interleaving method is described below based on the interleaving method given by the columns modulo d1 and the interleaving method given by the rows modulo d2 in S410.

[0171] (1) The second de-interleaving method: This de-interleaving method is the de-interleaving method corresponding to the interleaving method given by the columns modulo d1. The second de-interleaving method is used to write the Y sub-blocks of the first de-interleaved sequence by rows and read them by columns to complete de-sub-block interleaving. d1 is the number of columns written corresponding to the second de-interleaving method, and the number of sub-blocks written in each row is determined based on the interleaving method given by the columns modulo d1.

[0172] Among them, the number of sub-blocks written in each row is determined based on the interleaving method given by the columns modulo d1, and it can also be understood that the number of sub-blocks written in each row needs to be the same as the number of sub-blocks in each row after writing based on the interleaving method given by the columns modulo d1.

[0173] (2) The third de-interleaving method: This de-interleaving method is the de-interleaving method corresponding to the interleaving method given by the rows modulo d2. The third de-interleaving method is used to write the Y sub-blocks of the first de-interleaved sequence by columns and read them by rows to complete de-sub-block interleaving. d2 is the number of columns written corresponding to the third de-interleaving method, and the number of sub-blocks written in each column is determined based on the interleaving method given by the rows modulo d2.

[0174] Among them, the number of sub - blocks written in each column is determined by the interleaving method listed based on modulo d2. It can also be understood that the number of sub - blocks written in each column needs to be the same as the number written in each column by the interleaving method listed based on modulo d2.

[0175] It should be noted that for Figure 10 the example shown, in this example, the cross - sub - block bit interleaving is implemented during the block interleaving process. That is, based on the third interleaving method, between writing by rows and reading by columns, first perform a block interleaving on each column of sub - blocks, and then after dividing the obtained Y sub - blocks into L sub - block groups in the way of reading by rows, after completing the cross - sub - block bit interleaving on the L sub - block groups, read the interleaved Y sub - blocks by columns. Then, correspondingly, during de - interleaving, the third de - interleaving method in S1120 is also used to perform de - sub - block interleaving on at least one sub - block group among the d2 sub - block groups within the corresponding sub - block group. Among them, the d2 sub - block groups are the sub - block groups corresponding to the d2 columns of sub - blocks after writing by columns. Among them, the L sub - block groups in S1110 during de - interleaving are the sub - block groups obtained by reading by rows before performing de - sub - block interleaving on the d2 sub - block groups within the corresponding sub - block group. The others are the same as the description of the above - mentioned de - interleaving method and will not be elaborated here.

[0176] The above has described the interleaving method 400 and the corresponding de - interleaving method 1100 in detail. Next, another interleaving method and the corresponding de - interleaving method will be described in detail.

[0177] Figure 12 It is a schematic flowchart of an interleaving method 1200 provided by this application. The interleaving process of the codeword sequence to be interleaved in method 1200 is also divided into two steps. The difference from method 400 is that the first step in method 1200 is sub - block interleaving, and the second step is to perform a small - range cross - sub - block bit interleaving within the sub - block group composed of multiple sub - blocks. This method includes the following steps.

[0178] S1210, the sending - end device performs cross - sub - block bit interleaving on the bits included in at least one sub - block group among the L sub - block groups within the corresponding sub - block group to obtain a third codeword sequence. Among them, the L sub - block groups are determined based on the Y sub - blocks of the codeword sequence to be interleaved and the number of sub - blocks Z included in a preset sub - block group. The Y sub - blocks are determined based on the number of bits X included in a preset sub - block. X, Y, Z, and L are all integers greater than 1.

[0179] Optionally, before performing cross - sub - block bit interleaving, first, it is necessary to perform operations on the codeword sequence to be interleaved {a0, a1, a2, a3, … a N-2 , a N-1}\nPerform sub - block partitioning. Based on the length X of a preset sub - block, obtain Y sub - blocks {A0, A1, A2…A (Y-1)} after partitioning the to - be - interleaved codeword sequence, where represents rounding up. Then, it is necessary to perform sub - block group partitioning on the Y sub - blocks obtained by partitioning the to - be - interleaved codeword sequence. Based on the number Z of sub - blocks included in a preset sub - block group, obtain L sub - block groups after partitioning the to - be - interleaved codeword sequence, where It should be noted that if N cannot be evenly divided by X, the length of one sub - block among the Y sub - blocks is less than X. Similarly, if Y cannot be evenly divided by Z, the number of sub - blocks included in one sub - block group among the L sub - block groups is less than Z.

[0180] After that, perform cross - sub - block bit interleaving on the bits included in at least one sub - block group among the L sub - block groups obtained after partitioning to obtain an interleaved output sequence {b0, b1, b2, b3,…b N-2 ,b N-1} (i.e., the third codeword sequence). The Y sub - blocks of the third codeword sequence are {B0, B1, B2…B (Y-1)}}. Among them, performing cross - sub - block bit interleaving on the bits included in at least one sub - block group among the L sub - block groups within the corresponding sub - block group includes: performing cross - sub - block bit interleaving on the bits included in the first sub - block group among at least one sub - block group based on the first interleaving method within the first sub - block group. The first sub - block group includes a first sub - block and a second sub - block. The first interleaving method is used to place the first bit included in the first sub - block at the first position, where the first position is the position of the second bit included in the second sub - block. That is, place the first bit in the first sub - block at a position different from a bit in the first sub - block (such as the second sub - block) within the first sub - block group, that is, to achieve cross - sub - block bit interleaving. This application does not limit the number of bits for cross - sub - block interleaving in the first sub - block group. It is possible to perform cross - sub - block bit interleaving on all bits in the first sub - block group, or perform cross - sub - block bit interleaving on some bits.

[0181] Optionally, when multiple sub - block groups among the L sub - block groups perform cross - sub - block bit interleaving within the corresponding sub - blocks, the cross - sub - block bit interleaving sequences I2 corresponding to each sub - block group can be the same or different. This application does not make specific restrictions on I2, as long as cross - sub - block bit interleaving within the group can be achieved based on I2.

[0182] Exemplarily, here it is described by performing cross - sub - block bit interleaving within the sub - block group corresponding to the same cross - sub - block bit interleaving sequence I2 for each sub - block group among the L sub - blocks. The pseudo - code for sub - block interleaving based on I2 is as follows:

[0183]

[0184] The following is an example for illustration. For example, first, the to-be-interleaved codeword sequence of length 27 {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26} is divided into sub-blocks. The preset length of a sub-block is X = 3. Therefore, after dividing the to-be-interleaved codeword sequence, Y = 9 sub-blocks are obtained. Among them, the 9 sub-blocks are sub-block 0 = {0, 1, 2}, sub-block 1 = {3, 4, 5}, sub-block 2 = {6, 7, 8}, sub-block 3 = {9, 10, 11}, sub-block 4 = {12, 13, 14}, sub-block 5 = {15, 16, 17}, sub-block 6 = {18, 19, 20}, sub-block 7 = {21, 22, 23}, sub-block 8 = {24, 25, 26}. Then, the sub-blocks are divided into sub-block groups. The preset number of sub-blocks in a sub-block group is Z = 3. Therefore, after dividing the 9 sub-blocks of the first codeword sequence into sub-block groups in order of every consecutive 3 sub-blocks from front to back, L = 3 sub-block groups are obtained. The 3 sub-block groups are sub-block group 0 = {{0, 1, 2}, {3, 4, 5}, {6, 7, 8}}, sub-block group 1 = {{9, 10, 11}, {12, 13, 14}, {15, 16, 17}}, sub-block group 2 = {{18, 19, 20}, {21, 22, 23}, {24, 25, 26}}.

[0185] After that, based on the cross-sub-block bit interleaving sequence I2, cross-sub-block bit interleaving is performed on the divided 3 sub-block groups. It can be seen that the number of bits for cross-sub-block bit interleaving within each sub-block group is X * Z = 9. For example, the cross-sub-block bit interleaving sequence I2 = {3, 8, 1, 6, 0, 2, 7, 5, 4}. Among them, after performing cross-sub-block bit interleaving on sub-block group 0 = {{0, 1, 2}, {3, 4, 5}, {6, 7, 8}}, {3, 8, 1, 6, 0, 2, 7, 5, 4} is obtained. After performing cross-sub-block bit interleaving on sub-block group 1 = {{9, 10, 11}, {12, 13, 14}, {15, 16, 17}}, {12, 17, 10, 15, 9, 11, 16, 14, 13} is obtained. After performing cross-sub-block bit interleaving on sub-block group 2 = {{18, 19, 20}, {21, 22, 23}, {24, 25, 26}}, {21, 26, 19, 24, 18, 20, 25, 23, 22} is obtained. Therefore, the codeword sequence (i.e., the third codeword sequence) obtained after cross-sub-block bit interleaving is {3, 8, 1}, {6, 0, 2}, {7, 5, 4}, {12, 17, 10}, {15, 9, 11}, {16, 14, 13}, {21, 26, 19}, {24, 18, 20}, {25, 23, 22}.

[0186] Exemplarily, in the first interleaving method of this method, the bits in a sub-block group are interleaved by using the positions congruent modulo n with an offset. For specific descriptions and corresponding examples, refer to S420, which will not be elaborated here.

[0187] S1220, the sending device performs sub-block interleaving on the Y sub-blocks of the third codeword sequence to obtain a fourth codeword sequence.

[0188] The Y sub-blocks of the third codeword sequence are {B0, B1, B2…B (Y-1)}, then sub-block interleaving is performed on the Y sub-blocks of the third codeword sequence. For example, the block interleaving sequence is I1, and based on I1, sub-block interleaving is performed on the Y sub-blocks of the third codeword sequence, and the interleaved fourth codeword sequence obtained is {c0, c1, c2, c3,…c N-2 , c N-1}.

[0189] This application does not make specific restrictions on I1, as long as block interleaving can be achieved based on I1. The method for performing sub-block interleaving based on I1 can refer to the following pseudo-code:

[0190]

[0191] Exemplarily, based on the example in S1210, sub-block interleaving is performed on the 9 sub-blocks of the third codeword sequence through the block interleaving sequence I1. If the sub-block interleaving sequence I1 = {3, 6, 2, 7, 8, 1, 0, 5, 4}, where 3 means placing sub-block 3 in the position of sub-block 0, 6 means placing sub-block 6 in the position of sub-block 1, 2 means placing sub-block 2 in the position of sub-block 2 (i.e., remaining unchanged), which will not be elaborated one by one here. Then the codeword sequence obtained after sub-block interleaving is {12, 17, 10}, {21, 26, 19}, {7, 5, 4}, {24, 18, 20}, {25, 23, 22}, {6, 0, 2}, {3, 8, 1}, {16, 14, 13}, {15, 9, 11}, and the finally obtained codeword sequence (i.e., the fourth codeword sequence) is {12, 17, 10, 21, 26, 19, 7, 5, 4, 24, 18, 20, 25, 23, 22, 6, 0, 2, 3, 8, 1, 16, 14, 13, 112, 9, 11}.

[0192] Exemplarily, in this application, the block interleaving of the Y sub-blocks of the third codeword sequence can also be achieved through the following two possible block interleaving methods. Among them, one is the interleaving method performed by columns modulo d1, and the other is the row-column interleaving method modulo d2, where both d1 and d2 are integers greater than 1 and less than Y, and d1 and d2 are the fixed number of columns or fixed number of rows after writing for the corresponding interleaving method. For ease of description, in the following text, d1 and d2 are used as the fixed number of columns after writing for the corresponding interleaving method for illustration.

[0193] (1) Interleave the columns of modulo d1 (hereinafter referred to as the second interleaving method), which is used to write each of the Y sub-blocks of the third codeword sequence column by column and read them row by row to complete sub-block interleaving. For each sub-block, write by column and read by row to complete sub-block interleaving.

[0194] (2) Interleave the rows and columns of modulo d2 (hereinafter referred to as the third interleaving method), which is used to write every d2 sub-blocks of the Y sub-blocks of the third codeword sequence row by row and read them column by column to complete sub-block interleaving.

[0195] In the above technical solution, the interleaving process of the codeword sequence to be interleaved is divided into two steps. The first step is that a sub-block group composed of multiple sub-blocks performs small-range cross-sub-block bit interleaving within the group to break the correlation between consecutive bits. The second step is sub-block interleaving, which disperses the originally aggregated bit positions to different positions of the transmission sequence in a large range through block interleaving. In this way, the parallelism can be improved through large-range sub-block interleaving, and through the small-range cross-sub-block bit interleaving within the sub-block group, it can be obtained through a fixed interconnection relationship, and the hardware implementation is easy, thus solving the problems of irregular deinterleaving, inability to improve parallelism, and large hardware overhead caused by the original interleaving that performs small-granularity bit interleaving in a large range.

[0196] The following combines Figure 13 to give a specific example based on Method 1200. As Figure 13 shown, the codeword sequence to be interleaved includes a total of Y = 34 sub-blocks, numbered from sub-block 0 to sub-block 33, and each sub-block includes X = 4 bits. As Figure 13 shown, (1) In this example, Z = 5 is taken, that is, every consecutive 5 sub-blocks out of 34 sub-blocks are divided to obtain L = 7 sub-block groups, and cross-sub-block bit interleaving is performed on each sub-block group. In this example, modulo 3 congruent positions are used to offset all the bits in each sub-block group to achieve cross-sub-block bit interleaving. Taking the cross-sub-block bit interleaving of the bits included in sub-blocks {0, 1, 2, 3, 4} in the first sub-block group as an example for illustration, as Figure 13As shown, for the bits with position number modulo 3 equal to 0 in the sub-block group, the bit offset is 0 sub-blocks; for the bits with position number modulo 3 equal to 1 in the sub-block group, the bit offset is 1 sub-block; for the bits with position number modulo 3 equal to 2 in the sub-block group, the bit offset is 2 sub-blocks. The method of performing cross-sub-block bit interleaving on the remaining sub-block groups is the same as that for the first sub-block group, which will not be elaborated here; (2) After all sub-block groups complete cross-sub-block bit interleaving, a third codeword sequence is obtained. The third codeword sequence also includes Y sub-blocks; (3) Based on the interleaving method listed according to modulo d2 = 5, perform sub-block interleaving on the Y sub-blocks of the third codeword sequence. Specifically, the number of sub-blocks read in each row is 5, that is, the first row reads sub-blocks 0 to sub-block 4, the first row reads sub-blocks 5 to sub-block 9, and so on. The last row reads the remaining sub-blocks 30 to sub-block 33. Read out the sub-blocks of the first column {0, 5, 10, 15, 20, 25, 30} by column, read out the sub-blocks of the second row {1, 6, 11, 16, 21, 26, 31}, and so on, until all the sub-blocks corresponding to all columns are read out to obtain the final fourth codeword sequence.

[0197] In the above solution, when E max = 8320 and the deinterleaving throughput capacity reaches 64G, the ASIC circuit area required is only 83% of the ASIC circuit area required by the delta interleaving solution with E max = 8192, and the throughput capacity is 8 times that of the delta interleaving solution, and the area efficiency is 9.6 times.

[0198] The above has described in detail the interleaving method shown in method 1200. Based on Figure 2 the process shown, similarly, after the sending end obtains the fourth codeword sequence, it will be modulated according to the codebook and then the modulated symbols will be sent through a noisy channel to the receiving end for demodulation. Specifically, the receiving end demodulates N bits in the symbol simultaneously to obtain a deinterleaving sequence to be deinterleaved including N decoding information. Then, the receiving end performs deinterleaving on the deinterleaving sequence to be deinterleaved. The following will describe in detail the method of this deinterleaving.

[0199] Figure 14 FIG. is a schematic flowchart of a deinterleaving method 1400 provided by the present application. It can be understood that since Figure 14 the deinterleaving method shown is to deinterleave the fourth codeword sequence determined by method 1200, therefore, corresponding to method 1200, the receiving end needs to first perform the operation of de-sub-block interleaving and then perform the operation of de-bit interleaving. This method includes the following steps.

[0200] S1410. The receiving device performs de-subblock interleaving on the to-be-deinterleaved sequence to obtain a third deinterleaved sequence. Both the to-be-deinterleaved sequence and the third deinterleaved sequence include Y subblocks. The Y subblocks of the to-be-deinterleaved sequence are determined based on the number X of decoding information included in a preset subblock, and both X and Y are integers greater than 1.

[0201] Optionally, before performing de-subblock interleaving, the to-be-deinterleaved sequence containing N decoding information is subblock-divided to obtain Y subblocks after the to-be-deinterleaved sequence is divided, based on the number X of decoding information included in a preset subblock, where, represents rounding up. It should be noted that if N cannot be divided evenly by X, the length of one subblock among the Y subblocks is less than X.

[0202] After that, de-subblock interleaving is performed on the Y subblocks obtained by dividing the to-be-deinterleaved sequence to obtain a deinterleaved output sequence (i.e., the third deinterleaved sequence), and the third deinterleaved sequence includes Y subblocks.

[0203] It can be understood that the values of the same parameters in the deinterleaving method 1400 are the same as those in the method 1200.

[0204] It can also be understood that the de-block interleaving method is determined based on the corresponding block interleaving method. By way of example, the corresponding deinterleaving method is described below based on the interleaving method performed on the columns modulo d1 and the interleaving method performed on the rows modulo d2 given in S1220.

[0205] (1) The second deinterleaving method: This deinterleaving method is the deinterleaving method corresponding to the interleaving method performed on the columns modulo d1. The second deinterleaving method is used to write the Y subblocks of the to-be-deinterleaved sequence by rows and read them by columns to complete de-subblock interleaving. d1 is the number of write columns corresponding to the second deinterleaving method, and the number of subblocks written in each row is determined based on the interleaving method performed on the columns modulo d1.

[0206] (2) The third deinterleaving method: This deinterleaving method is the deinterleaving method corresponding to the interleaving method performed on the rows modulo d2. The third deinterleaving method is used to write the Y subblocks of the to-be-deinterleaved sequence by columns and read them by rows to complete de-subblock interleaving. d2 is the number of write columns corresponding to the third deinterleaving method, and the number of subblocks written in each column is determined based on the interleaving method performed on the rows modulo d2.

[0207] S1420, the receiving device performs de-bit-interleaving across sub-blocks on the decoding information included in at least one of the L sub-block groups within the corresponding sub-block group to obtain a fourth de-interleaved sequence, where the L sub-block groups are determined based on the Y sub-blocks of the third de-interleaved sequence and the number of sub-blocks Z included in a preset sub-block group, the Y sub-blocks are determined based on the number of decoding information X included in a preset sub-block, and both Z and L are integers greater than 1.

[0208] Optionally, before performing de-bit-interleaving across sub-blocks, it is necessary to perform sub-block group partitioning on the Y sub-blocks of the third de-interleaved sequence to obtain L sub-block groups after partitioning the Y sub-blocks of the third de-interleaved sequence based on the number of sub-blocks Z included in a preset sub-block group, where It should be noted that if Y cannot be divided evenly by Z, the number of sub-blocks included in one of the L sub-block groups is less than Z.

[0209] It can be understood that the L sub-block groups in S1420 correspond one-to-one with the L sub-block groups in S1210. Specifically, the first sub-block group in the L sub-block groups in S1420 includes the decoding information corresponding to the multiple bit demodulations of the first sub-block group in the L sub-block groups in S1210, and the first sub-block group in S1210 and the first sub-block group in S1420 are corresponding sub-block groups.

[0210] Optionally, performing de-bit-interleaving across sub-blocks on the decoding information included in at least one of the L sub-block groups within the corresponding sub-block group includes: performing de-bit-interleaving across sub-blocks on the decoding information included in the first sub-block group in at least one of the L sub-block groups within the first sub-block group based on the first de-interleaving method, where the first sub-block group includes a first sub-block and a second sub-block, and the first de-interleaving method is used to place the first decoding information included in the second sub-block at the second position, where the second position is the position where the second decoding information is located in the first sub-block.

[0211] It can be understood that the first de-interleaving method is the inverse operation of the first interleaving method. That is to say, if the transmitting end performs cross-sub-block bit interleaving on the bits within the first sub-block group in S1210 based on the first interleaving method, then the transmitting end performs de-interleaving on the decoding information obtained from the first sub-block group in S1420 based on the first de-interleaving method, that is, performs the inverse operation of the interleaving operation. Based on the description in S1210, if the transmitting end places the first bit from the second position to the first position based on the first interleaving method, then when the receiving end performs de-interleaving, it places the decoding information at the first position (i.e., the first decoding information corresponding to the first bit) at the second position based on the first de-interleaving method. Optionally, the remainder of the position number of the first position after modulo n operation is the same as the remainder of the position number of the second position after modulo n operation, where n is an integer greater than 1.

[0212] It can be understood that each step in the above-mentioned drawings is only an exemplary illustration and is not strictly limited. In addition, the magnitudes of the serial numbers of the above-mentioned processes do not imply the sequence of execution. The execution sequence of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0213] It can also be understood that some optional features in the embodiments of the present application can, in some scenarios, be independent of other features, and in some scenarios, can be combined with other features, without limitation.

[0214] It can also be understood that in the above-mentioned method embodiments, the methods and operations implemented by the device (the sending device or the receiving device) can also be implemented by the components (such as chips or circuits) of the device, without limitation.

[0215] Corresponding to the methods given in the above-mentioned method embodiments, the embodiments of the present application also provide corresponding devices, and the devices include modules for performing the corresponding operations of the above-mentioned method embodiments. The module can be software, hardware, or a combination of software and hardware. It can be understood that the technical features described in the above-mentioned method embodiments also apply to the following device embodiments.

[0216] Figure 15 is a schematic block diagram of the communication device 1500 provided by the embodiments of the present application. As Figure 15 shown, the device 1500 may include a communication unit 1510 and a processing unit 1520. The communication unit 1510 can communicate with the outside, and the processing unit 1520 is used for data processing. The communication unit 1510 can also be referred to as a communication interface or a transceiver unit.

[0217] In a possible design, the device 1500 can implement the steps or processes corresponding to the sending device in the above-mentioned method embodiments. Among them, the processing unit 1520 is used to perform the operations related to the processing of the sending device in the above-mentioned method embodiments, and the communication unit 1510 is used to perform the operations related to the sending of the sending device in the above-mentioned method embodiments.

[0218] In another possible design, the device 1500 can implement the steps or processes corresponding to the receiving device in the above-mentioned method embodiments. Among them, the communication unit 1510 is used to perform the operations related to the receiving of the receiving device in the above-mentioned method embodiments, and the processing unit 1520 is used to perform the operations related to the processing of the receiving device in the above-mentioned method embodiments.

[0219] It can be understood that the device 1500 here is embodied in the form of a functional unit. The term "unit" here may refer to an application specific integrated circuit (ASIC), an electronic circuit, a processor for executing one or more software or firmware programs (such as a shared processor, a proprietary processor, or a group of processors, etc.) and a memory, a combined logic circuit, and / or other suitable components that support the described functions. In an alternative example, those skilled in the art can understand that the device 1500 can specifically be the transmitting device in the above embodiments, and can be used to execute each process and / or step corresponding to the transmitting device in the above method embodiments. Or, the device 1500 can specifically be the receiving device in the above embodiments, and can be used to execute each process and / or step corresponding to the receiving device in the above method embodiments. To avoid repetition, details are not described herein again.

[0220] The device 1500 in each of the above solutions has the function of implementing the corresponding steps executed by the transmitting device in the above method. Or, the device 1500 in each of the above solutions has the function of implementing the corresponding steps executed by the receiving device in the above method. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions. For example, the communication unit can be replaced by a transceiver (for example, the transmitting unit in the communication unit can be replaced by a transmitter, and the receiving unit in the communication unit can be replaced by a receiver). Other units, such as the processing unit, can be replaced by a processor to respectively execute the transceiver operations and related processing operations in each method embodiment.

[0221] In addition, the above communication unit can also be a transceiver circuit (for example, it can include a receiving circuit and a sending circuit), and the processing unit can be a processing circuit. In the embodiments of the present application, Figure 15 the device in can be the receiving device or the transmitting device in the foregoing embodiments, or can be a chip or a chip system, for example: a system on chip (SoC). Among them, the communication unit can be an input / output circuit, a communication interface; the processing unit is a processor, a microprocessor, or an integrated circuit integrated on the chip. This is not limited herein.

[0222] Figure 16 FIG. 12 is a schematic block diagram of a communication device 1600 provided in an embodiment of the present application. The device 1600 includes a processor 1610 and a transceiver 1620. Among them, the processor 1610 and the transceiver 1620 communicate with each other through an internal connection path. The processor 1610 is used to execute instructions to control the transceiver 1620 to send signals and / or receive signals.

[0223] Optionally, the device 1600 may further include a memory 1630, which communicates with the processor 1610 and the transceiver 1620 through an internal connection path. The memory 1630 is used to store instructions, and the processor 1610 can execute the instructions stored in the memory 1630. In a possible implementation, the device 1600 is used to implement the respective processes and steps corresponding to the sending device in the above method embodiments. In another possible implementation, the device 1600 is used to implement the respective processes and steps corresponding to the receiving device in the above method embodiments.

[0224] It can be understood that the device 1600 may specifically be the sending device or the receiving device in the above embodiments, or may be a chip or a chip system. Correspondingly, the transceiver 1620 may be the transceiver circuit of the chip, which is not limited herein. Specifically, the device 1600 may be used to execute the respective steps and / or processes corresponding to the sending device or the receiving device in the above method embodiments.

[0225] Optionally, the memory 1630 may include a read-only memory and a random access memory, and provide instructions and data to the processor. The memory may include a non-volatile random access memory. For example, the memory may further store information about the device type. The processor 1610 may be used to execute the instructions stored in the memory, and when the processor 1610 executes the instructions stored in the memory, the processor 1610 is used to execute the respective steps and / or processes of the above method embodiments corresponding to the sending device or the receiving device.

[0226] In the implementation process, the steps of the above method can be completed by the integrated logic circuit in the hardware of the processor or by instructions in software form. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as being executed by the hardware processor, or executed by a combination of the hardware and software modules in the processor. The software module may be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and combines its hardware to complete the steps of the above method. To avoid repetition, it will not be described in detail here.

[0227] It should be noted that the processor in the embodiments of the present application may be an integrated circuit chip with signal processing capabilities. In the implementation process, the steps of the above method embodiments may be completed by the integrated logic circuit in the hardware of the processor or instructions in the form of software. The above processor may be a general-purpose processor, a digital signal processing (DSP), an ASIC, a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The processor in the embodiments of the present application may implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of the present application may be directly embodied as being executed and completed by a hardware decoding processor, or executed and completed by a combination of hardware and software modules in the decoding processor. The software module may be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. This storage medium is located in the memory, and the processor reads the information in the memory and combines its hardware to complete the steps of the above method.

[0228] It can be understood that the memory in the embodiments of the present application can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include but not be limited to these and any other suitable types of memory

[0229] Optionally, the memory (such as 1630) in the embodiments of the present application can be integrated in the processor (such as 1610).

[0230] In addition, the present application also provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions run on a computer, the operations and / or processes executed by the sending device or the receiving device in the method embodiments of the present application are executed.

[0231] The present application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions run on a computer, the operations and / or processes executed by the sending device or the receiving device in the method embodiments of the present application are executed.

[0232] In addition, the present application also provides a chip, which includes a processor. A memory for storing a computer program is provided separately from the chip, and the processor is configured to execute the computer program stored in the memory, so that the operations and / or processes performed by the sending device or the receiving device in any one of the method embodiments are executed.

[0233] Further, the chip may further include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Further, the chip may further include a memory.

[0234] In addition, the present application also provides a communication system, which includes the sending device and the receiving device in the embodiments of the present application.

[0235] It should also be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0236] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. A professional technician can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated herein. In several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the couplings or direct couplings or communication connections shown or discussed with each other can be through some interfaces, and the indirect couplings or communication connections of the devices or units can be in an electrical, mechanical, or other form. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, the functional units in each embodiment of the present application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0237] When the above-mentioned function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, ROM, RAM, magnetic disks, or optical discs that can store program codes.

[0238] It can be understood that the "embodiments" mentioned throughout the specification mean that specific features, structures, or characteristics related to the embodiments are included in at least one embodiment of this application. Therefore, the various embodiments throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics can be combined in one or more embodiments in any suitable manner.

[0239] It can also be understood that in this application, "when...", "if", and "in case" all mean that the network element will perform corresponding processing under certain objective circumstances, not limited to time, and it is not required that the network element must have a judgment action when implemented, nor does it mean that there are other limitations.

[0240] It can also be understood that in various embodiments of this application, "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it can also be understood that determining B according to A does not mean determining B only according to A, and B can also be determined according to A and / or other information.

Claims

1. A method of interleaving, characterized in that, Including: Performing sub-block interleaving on an interleaving codeword sequence to obtain a first codeword sequence, where both the interleaving codeword sequence and the first codeword sequence include Y sub-blocks, the Y sub-blocks of the interleaving codeword sequence are determined based on the number of bits X included in a preset sub-block, and both X and Y are integers greater than 1; Performing cross-sub-block bit interleaving on the bits included in at least one sub-block group among L sub-block groups within the corresponding sub-block group to obtain a second codeword sequence, where the L sub-block groups are determined based on the Y sub-blocks of the first codeword sequence and the number of sub-blocks Z included in a preset sub-block group, and both Z and L are integers greater than 1.

2. The method according to claim 1, wherein The performing cross-sub-block bit interleaving on the bits included in at least one sub-block group among L sub-block groups within the corresponding sub-block group includes: Performing cross-sub-block bit interleaving on the bits included in a first sub-block group among the at least one sub-block group based on a first interleaving method within the first sub-block group, where the first sub-block group includes a first sub-block and a second sub-block, and the first interleaving method is used to place a first bit included in the first sub-block at a first position, where the first position is the position where a second bit included in the second sub-block is located.

3. The method according to claim 2, characterized in that The remainder obtained by performing modulo n operation on the position serial number of the first bit is the same as the remainder obtained by performing modulo n operation on the position serial number of the second bit, where n is an integer greater than 1.

4. The method according to any one of claims 1 to 3, characterized in that, The performing sub-block interleaving on the interleaving codeword sequence includes: Perform sub-block interleaving on the codeword sequence to be interleaved based on the second interleaving method, where the second interleaving method is used to write each of the Y sub-blocks of the codeword sequence to be interleaved by columns and read out by rows to complete sub-block interleaving. The d1 is the number of writing columns corresponding to the second interleaving method, and the d1 is an integer greater than 1 and less than Y. where represents rounding up. denotes rounding up.

5. The method according to claim 4, characterized in that The Z is equal to the d1.

6. The method according to any one of claims 1 to 3, characterized in that The performing sub-block interleaving on the interleaving codeword sequence includes: Performing sub-block interleaving on the interleaving codeword sequence based on a third interleaving method, where the third interleaving method is used to write every d2 sub-blocks among the Y sub-blocks of the interleaving codeword sequence row by row and read them column by column to complete sub-block interleaving, d2 is the number of writing columns corresponding to the third interleaving method, and d2 is an integer greater than 1 and less than Y.

7. The method according to any one of claims 1 to 6, characterized in that, Any sub-block group among the L sub-block groups includes consecutive sub-blocks among the Y sub-blocks of the first codeword sequence.

8. The method according to claim 6, wherein The third interleaving method is further used to perform sub-block interleaving on at least one sub-block group among d2 sub-block groups within the corresponding sub-block group between row writing and column reading, where the d2 sub-block groups are sub-block groups corresponding to d2 columns of sub-blocks after row writing.

9. The method according to claim 8, wherein The L sub-block groups are sub-block groups obtained by reading row by row after performing sub-block interleaving within the corresponding sub-block group.

10. According to the method described in claim 8 or 9, the Z is equal to the d2.

11. The method according to any one of claims 8 to 10, characterized in that, The third interleaving method is used to perform sub-block interleaving on at least one sub-block group among the d2 sub-block groups within the corresponding sub-block group, including: the third interleaving method is used to perform sub-block interleaving on at least one sub-block group among the d2 sub-block groups within the corresponding sub-block group by translating the sub-blocks in the column direction.

12. A deinterleaving method, characterized in that, Including: Perform de-bit-interleaving across sub-blocks on the decoding information included in at least one of the L sub-block groups within the corresponding sub-block group to obtain a first de-interleaved sequence, where the L sub-block groups are determined based on Y sub-blocks of the sequence to be de-interleaved and the number Z of sub-blocks included in a preset sub-block group, the Y sub-blocks are determined based on the number X of decoding information included in a preset sub-block, and X, Y, Z, and L are all integers greater than 1; Perform de-sub-block-interleaving on the first de-interleaved sequence to obtain a second de-interleaved sequence.

13. The method according to claim 12, wherein The performing de-bit-interleaving across sub-blocks on the decoding information included in at least one of the L sub-block groups within the corresponding sub-block group includes: Based on a first de-interleaving method, perform de-bit-interleaving across sub-blocks on the decoding information included in a first sub-block group among the at least one sub-block group within the first sub-block group, where the first sub-block group includes a first sub-block and a second sub-block, and the first de-interleaving method is used to place first decoding information included in the second sub-block at a second position, where the second position is the position where second decoding information is located in the first sub-block.

14. The method according to claim 13, wherein The remainder obtained by performing modulo-n operation on the position serial number of the first decoding information is the same as the remainder obtained by performing modulo-n operation on the position serial number of the second decoding information, where n is an integer greater than 1.

15. The method according to any one of claims 12 to 14, characterized in that, The performing de-sub-block-interleaving on the first de-interleaved sequence includes: Based on a second de-interleaving method, perform de-sub-block-interleaving on the first de-interleaved sequence, where the second de-interleaving method is used to write the Y sub-blocks of the first de-interleaved sequence by rows and read them by columns to complete de-sub-block-interleaving, d1 is the number of writing columns corresponding to the second de-interleaving method, and the number of sub-blocks written in each row is determined based on the interleaving method performed out of columns modulo d1, and d1 is an integer greater than 1 and less than Y.

16. The method according to claim 15, wherein, Z is equal to d1.

17. The method according to any one of claims 12 to 14, characterized in that, The performing de-sub-block-interleaving on the first de-interleaved sequence includes: Based on a third de-interleaving method, perform de-sub-block-interleaving on the first de-interleaved sequence, where the third de-interleaving method is used to write the Y sub-blocks of the first de-interleaved sequence by columns and read them by rows to complete de-sub-block-interleaving, d2 is the number of writing columns corresponding to the third de-interleaving method, and the number of sub-blocks written in each column is determined based on the interleaving method performed out of rows modulo d2, and d2 is an integer greater than 1 and less than Y.

18. The method according to any one of claims 12 to 17, characterized in that, The sub-blocks included in any one of the L sub-block groups are consecutive sub-blocks among the Y sub-blocks of the sequence to be de-interleaved.

19. The method according to claim 17, wherein The third de-interleaving method is further used to perform de-sub-block-interleaving on at least one of the d2 sub-block groups within the corresponding sub-block group between writing by columns and reading by rows, where the d2 sub-block groups are the sub-block groups corresponding to d2 columns of sub-blocks after writing by columns.

20. The method according to claim 19, characterized in that, The L sub-block groups are the sub-block groups obtained by reading by rows before performing de-sub-block-interleaving within the corresponding sub-block group.

21. According to the method of claim 19 or 20, Z is equal to d2.

22. The method according to any one of claims 19 to 21, characterized in that, The third deinterleaving method is used to perform sub-block deinterleaving on at least one of the d2 sub-block groups within the corresponding sub-block group, including: the third deinterleaving method is used to perform sub-block deinterleaving on at least one of the d2 sub-block groups within the corresponding sub-block group by shifting the sub-blocks in the column direction for deinterleaving.

23. A method of interleaving, characterized in that, Including: Performing cross-sub-block bit interleaving on the bits included in at least one of the L sub-block groups within the corresponding sub-block group to obtain a third codeword sequence, where the L sub-block groups are determined based on the Y sub-blocks of the codeword sequence to be interleaved and the number of sub-blocks Z included in a preset sub-block group, the Y sub-blocks are determined based on the number of bits X included in a preset sub-block, and the X, the Y, the Z, and the L are all integers greater than 1; Performing sub-block interleaving on the Y sub-blocks of the third codeword sequence to obtain a fourth codeword sequence.

24. The method according to claim 23, wherein The performing cross-sub-block bit interleaving on the bits included in at least one of the L sub-block groups within the corresponding sub-block group includes: Performing cross-sub-block bit interleaving on the bits included in the first sub-block group among the at least one sub-block group within the first sub-block group based on the first interleaving method, where the first sub-block group includes a first sub-block and a second sub-block, and the first interleaving method is used to place the first bit included in the first sub-block at a first position, where the first position is the position where the second bit included in the second sub-block is located.

25. The method according to claim 24, wherein The remainder obtained by performing modulo n operation on the position serial number of the first bit is the same as the remainder obtained by performing modulo n operation on the position serial number of the second bit, where n is an integer greater than 1.

26. The method according to any one of claims 23 to 25, characterized in that, The performing sub-block interleaving on the Y sub-blocks of the third codeword sequence includes: Performing sub-block interleaving on the Y sub-blocks of the third codeword sequence based on the third interleaving method, where the third interleaving method is used to write every d2 sub-blocks of the Y sub-blocks of the third codeword sequence row by row and read them column by column to complete sub-block interleaving, and the d2 is the number of writing columns corresponding to the third interleaving method, and the d2 is an integer greater than 1 and less than Y.

27. The method according to claim 26, wherein The Z is equal to the d2.

28. The method according to any one of claims 23 to 25, characterized in that, The performing sub-block interleaving on the Y sub-blocks of the third codeword sequence includes: Perform sub-block interleaving on the Y sub-blocks of the third codeword sequence based on the second interleaving method, where the second interleaving method is used to write each of the Y sub-blocks of the third codeword sequence by column and read out by row to complete sub-block interleaving, where d1 is the number of writing columns corresponding to the second interleaving method, and the d1 is an integer greater than 1 and less than Y, and represents rounding up. denotes rounding up.

29. The method according to any one of claims 23 to 28, characterized in that, The sub-blocks included in any one of the L sub-block groups are consecutive sub-blocks among the Y sub-blocks of the codeword sequence to be interleaved.

30. A deinterleaving method, characterized in that, Including: Performing sub-block deinterleaving on the sequence to be deinterleaved to obtain a third deinterleaved sequence, where the sequence to be deinterleaved and the third deinterleaved sequence both include Y sub-blocks, the Y sub-blocks of the sequence to be deinterleaved are determined based on the number X of decoding information included in a preset sub-block, and the X and the Y are both integers greater than 1; Performing cross-sub-block de-bit interleaving on the decoding information included in at least one of the L sub-block groups within the corresponding sub-block group to obtain a fourth deinterleaved sequence, where the L sub-block groups are determined based on the Y sub-blocks of the third deinterleaved sequence and the number of sub-blocks Z included in a preset sub-block group, the Y sub-blocks are determined based on the number X of decoding information included in a preset sub-block, and the Z and the L are both integers greater than 1.

31. The method according to claim 30, wherein Performing de-bit-interleaving across sub-blocks on the decoding information included in at least one sub-block group among the L sub-block groups includes: Performing de-bit-interleaving across sub-blocks on the decoding information included in a first sub-block group among the at least one sub-block group based on a first de-interleaving method, where the first sub-block group includes a first sub-block and a second sub-block, and the first de-interleaving method is used to place first decoding information included in the second sub-block at a second position, where the second position is the position where second decoding information is located in the first sub-block.

32. The method according to claim 31, wherein The remainder obtained by performing modulo-n operation on the position serial number of the first decoding information is the same as the remainder obtained by performing modulo-n operation on the position serial number of the second decoding information, where n is an integer greater than 1.

33. The method according to any one of claims 30 to 32, characterized in that, Performing de-sub-block-interleaving on the sequence to be de-interleaved includes: Performing de-sub-block-interleaving on the sequence to be de-interleaved based on a third de-interleaving method, where the third de-interleaving method is used to write the Y sub-blocks of the sequence to be de-interleaved column by column and read them row by row to complete de-sub-block-interleaving, d2 is the number of columns written corresponding to the third de-interleaving method, and the number of sub-blocks written in each column is determined based on the interleaving method listed by rows modulo d2.

34. The method according to claim 33, characterized in that, The Z is equal to the d2.

35. The method according to any one of claims 30 to 32, characterized in that, Performing de-sub-block-interleaving on the sequence to be de-interleaved includes: Performing de-sub-block-interleaving on the sequence to be de-interleaved based on a second de-interleaving method, where the second de-interleaving method is used to write the Y sub-blocks of the sequence to be de-interleaved row by row and read them column by column to complete de-sub-block-interleaving, where d1 is the number of columns written corresponding to the second de-interleaving method, and the number of sub-blocks written in each row is determined based on the columns modulo d1 for the listed interleaving method, and the d1 is an integer greater than 1 and less than Y.

36. The method according to any one of claims 30 to 35, characterized in that, The sub-blocks included in any one of the L sub-block groups are consecutive sub-blocks among the Y sub-blocks of the third de-interleaving sequence.

37. A communication device, characterized in that, Including: A processor for executing computer programs or instructions stored in a memory, The memory for storing the computer programs or the instructions, When the computer programs or the instructions run, so that the method according to any one of claims 1 to 11 is executed, or so that the method according to any one of claims 12 to 22 is executed, or so that the method according to any one of claims 23 to 29 is executed, or so that the method according to any one of claims 30 to 36 is executed.

38. A computer program product, characterized in that, The computer program product includes instructions for executing the method according to any one of claims 1 to 11, or the computer program product includes instructions for executing the method according to any one of claims 12 to 22, or the computer program product includes instructions for executing the method according to any one of claims 23 to 29, or the computer program product includes instructions for executing the method according to any one of claims 30 to 36.

39. A computer-readable storage medium, characterized in that, Including: The computer-readable storage medium stores a computer program or instructions; when the computer program or the instructions are run on a computer, the method according to any one of claims 1 to 11 is executed, or the method according to any one of claims 12 to 22 is executed, or the method according to any one of claims 23 to 29 is executed, or the method according to any one of claims 30 to 36 is executed.

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