Semiconductor structure, manufacturing method thereof and electronic equipment
By designing a common word line layer and a conductive layer group in a semiconductor structure, and forming a laminated structure by alternately deposition of materials, the problem of manufacturing multiple device units on a limited substrate is solved, and the effects of area saving and process difficulty reduction are achieved.
Patent Information
- Application Number
- CN202311787062.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-22
- Publication Date
- 2025-06-24
AI Technical Summary
In semiconductor device manufacturing, as device size shrinks and device types increase, small differences in processes have an increasing impact on device performance, and it is difficult to manufacture as many device units as possible on a limited substrate.
A semiconductor structure design is adopted, including a first common word line layer, a conductive layer group and a plurality of first word lines located on the substrate, a stacked structure is formed by alternately depositing an insulating material film and a conductive material film, and a bit line region and a memory cell region are formed by patterning, and the word line is electrically connected to the common word line.
Effectively save area, reduce process difficulty, reduce the number of sub-word line drivers, improve the integration of semiconductor structures, and reduce the manufacturing difficulty of common word lines.
Smart Images
Figure CN120201714A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present disclosure relate to, but are not limited to, semiconductor technology, and in particular to a semiconductor structure, a manufacturing method thereof, and an electronic device. Background Art
[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking day by day, and the types and quantities of devices included in a single chip are increasing accordingly. As a result, any minor difference in the process production may affect the device performance.
[0003] In order to reduce the cost of products as much as possible, people hope to fabricate as many device units as possible on a limited substrate. Since Moore's law came out, various semiconductor structure designs and process optimizations have been proposed in the industry to meet the requirements of current products. Summary of the Invention
[0004] The following is an overview of the subject matter described in detail in this document. This overview is not intended to limit the scope of protection of this application.
[0005] In one aspect, an exemplary embodiment of the present application provides a semiconductor structure, including:
[0006] A first common word line layer located on a substrate, the first common word line layer including a plurality of first common word lines;
[0007] A conductive layer group located on a side of the first common word line layer away from the substrate, the conductive layer group including a plurality of conductive layers arranged along a third direction perpendicular to the substrate, the conductive layer having a bit line region and a first memory cell region including a first memory cell;
[0008] A plurality of first word lines extending along the third direction and connected to the first memory cells in the first memory cell region, the first word lines being electrically connected to a corresponding one of the first common word lines.
[0009] In an exemplary embodiment, the first common word line layer includes a plurality of first common word lines extending along a first direction and spaced apart from each other in a second direction, the first direction intersecting with the second direction and being perpendicular to the third direction.
[0010] In an exemplary embodiment, the conductive layer has a bit line region extending along the second direction, and a first memory cell region and a second memory cell region located on both sides of the bit line region, the first memory cell region and the second memory cell region each including a plurality of memory cells arranged along the second direction.
[0011] In an exemplary embodiment, the plurality of first word lines are arranged in an array in the first memory cell region;
[0012] Further included are: a plurality of second word lines, extending along the third direction and arranged in an array in the second storage unit area.
[0013] In an exemplary embodiment, the first word line and the second word line at the same position in the array are connected to the same first common word line.
[0014] In an exemplary embodiment, the first word line and the second word line are arranged in a staggered manner in the second direction.
[0015] In an exemplary embodiment, the first common word line connected to the first word line and the first common word line connected to the second word line are arranged alternately in the second direction.
[0016] In an exemplary embodiment, the first storage unit area further includes a first word line via hole, and the second storage unit area further includes a second word line via hole. The first word line via hole and the second word line via hole are arranged in a staggered manner in the second direction; the first word line is located within the first word line via hole, and the second word line is located within the second word line via hole.
[0017] In an exemplary embodiment, a second common word line layer is further included between the first common word line layer and the conductive layer group. The second common word line layer includes a plurality of second common word lines extending along the first direction and arranged at intervals in the second direction.
[0018] In an exemplary embodiment, the first word line and the second word line are symmetrically distributed with respect to the bit line area in the first direction.
[0019] In an exemplary embodiment, the first word line is electrically connected to the corresponding first common word line; the second word line is electrically connected to the corresponding second common word line.
[0020] In an exemplary embodiment, the first storage unit area further includes a plurality of common word line via holes, and the common word line via holes penetrate through the second common word line layer along the third direction and communicate with the first word line via holes.
[0021] In an exemplary embodiment, the first word line is located within the first word line via hole and the common word line via hole.
[0022] In an exemplary embodiment, the first storage unit area further includes an annular isolation portion, and the annular isolation portion is located within the common word line via hole and surrounds the first word line.
[0023] In an exemplary embodiment, the distance from the top surface of the annular isolation portion away from the substrate to the substrate is a first height, and the distance from the top surface of the second common word line layer away from the substrate to the substrate is a second height, and the first height is greater than or equal to the second height.
[0024] In an exemplary embodiment, an isolation layer is further included, and the isolation layer is located between the second common word line layer and the conductive layer group.
[0025] In an exemplary embodiment, an isolation layer is further included, and the isolation layer is located between the second common word line layer and the conductive layer group.
[0026] In an exemplary embodiment, a plurality of sense amplifiers are further included, which are arranged at intervals along the second direction and are electrically connected to the bit lines.
[0027] In an exemplary embodiment, a bonding chip is further included, which is located on a side of the conductive layer group away from the substrate and is provided with a plurality of sub-word line drivers; both the first word line and the second word line are electrically connected to the sub-word line drivers.
[0028] In another aspect, an exemplary embodiment of the present application further provides a manufacturing method of a semiconductor structure, including the following steps:
[0029] Deposit a conductive material thin film on the substrate to form a first common word line layer;
[0030] Etch the first common word line layer to form at least one first common word line;
[0031] Alternately deposit an insulating material thin film and a conductive material thin film on a side of the first common word line layer away from the substrate to form a stacked structure including an insulating layer and a conductive layer;
[0032] Pattern the stacked structure to form a bit line region and a first memory cell region in the conductive layer, and the first memory cell region includes at least one first memory cell;
[0033] Form a first word line through hole penetrating the stacked structure, and form a first word line in the first word line through hole to connect the first word line to at least one first memory cell;
[0034] Electrically connect the first word line to a corresponding first common word line.
[0035] In an exemplary embodiment, etching the first common word line layer to form at least one first common word line includes:
[0036] Etch the first common word line layer to form a plurality of first common word lines extending along a first direction and spaced apart in a second direction, the first direction intersecting the second direction and perpendicular to a third direction perpendicular to the substrate.
[0037] In an exemplary embodiment, the patterned stack structure includes: patterning the stack structure to form bit line regions extending along the second direction and first and second storage cell regions on both sides of the bit line regions in each conductive layer, the first and second storage cell regions each including a plurality of storage cells spaced apart along the second direction.
[0038] In an exemplary embodiment, the first word line and the second word line are arranged with a misalignment in the second direction.
[0039] In an exemplary embodiment, the first common word line connected to the first word line and the first common word line connected to the second word line are arranged alternately in the second direction.
[0040] In an exemplary embodiment, an insulating material film and a conductive material film are deposited on the first common word line layer to form a second common word line layer spaced from the first common word line layer by an insulating layer;
[0041] Etch the second common word line layer to form a plurality of second common word lines in the second common word line layer.
[0042] In an exemplary embodiment, the first word line and the second word line are symmetrically distributed with respect to the bit line region in the first direction;
[0043] The first word line is electrically connected to the corresponding first common word line one by one; the second word line is electrically connected to the corresponding second common word line.
[0044] In an exemplary embodiment, a plurality of first word line vias penetrating the stack structure are formed in the first storage cell region, a common word line via penetrating the second common word line layer is formed in the first storage cell region, the common word line via is communicated with the first word line via, and the first word line is formed in the first word line via and the common word line via;
[0045] A plurality of second word line vias penetrating the stack structure are formed in the second storage cell region, and the second word line is formed in the second word line via.
[0046] In an exemplary embodiment, it further includes depositing a thin film of isolation material in the common word line through holes in the first storage cell region to form an annular isolation portion. The distance from the top surface of the annular isolation portion away from the substrate to the substrate is a first height, and the distance from the top surface of the second common word line layer away from the substrate to the substrate is a second height. The first height is greater than or equal to the second height.
[0047] In another aspect, an exemplary embodiment of the present application further provides an electronic device, including the above semiconductor structure.
[0048] The semiconductor structure of the present application can effectively save area and reduce the process difficulty.
[0049] Other features and advantages of the present application will be described in the subsequent specification, and some will be obvious from the specification, or understood by implementing the present application. Other advantages of the present application can be achieved and obtained through the solutions described in the specification and the drawings. Description of the Drawings
[0050] The drawings are used to provide an understanding of the technical solutions of the present application, and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solutions of the present application, and do not constitute a limitation to the technical solutions of the present application.
[0051] Figure 1A A three-dimensional schematic diagram of a semiconductor structure provided for an exemplary embodiment of the present application;
[0052] Figure 1B For Figure 1A A partial top view schematic diagram of the structure shown;
[0053] Figure 2A A three-dimensional schematic diagram of another semiconductor structure provided for an exemplary embodiment of the present application;
[0054] Figure 2B For Figure 2A A partial top view schematic diagram of the structure shown;
[0055] Figure 2C For a cross-sectional schematic diagram perpendicular to the substrate taken along a plane parallel to the second direction in the structure shown; Figure 2A For a cross-sectional schematic diagram perpendicular to the substrate taken along a plane parallel to the first direction in the structure shown;
[0056] Figure 2D For Figure 2A A cross-sectional schematic diagram perpendicular to the substrate taken along a plane parallel to the first direction in the structure shown;
[0057] Figure 3A A three-dimensional structural schematic diagram of a manufacturing method of a semiconductor structure provided for an exemplary embodiment of the present application after forming the common word line layer;
[0058] Figure 3B A cross-sectional view perpendicular to the substrate taken along section C1 in the structure shown; Figure 3A is a schematic cross-sectional view perpendicular to the substrate taken along section C1 in the structure shown;
[0059] Figure 4A is a schematic three-dimensional structure view of a semiconductor structure provided by an exemplary embodiment of the present application after forming multiple common word lines;
[0060] Figure 4B A cross-sectional view parallel to the substrate taken along section C1 in the structure shown; Figure 4A is a schematic cross-sectional view parallel to the substrate taken along section C1 in the structure shown;
[0061] Figure 5A is a schematic three-dimensional structure view of a semiconductor structure provided by an exemplary embodiment of the present application after forming a common word line structure;
[0062] Figure 5B A cross-sectional view perpendicular to the substrate taken along section C1 in the structure shown; Figure 5A is a schematic cross-sectional view perpendicular to the substrate taken along section C1 in the structure shown;
[0063] Figure 6A is a schematic three-dimensional structure view of a semiconductor structure provided by an exemplary embodiment of the present application after forming multiple common word lines;
[0064] Figure 6B A cross-sectional view parallel to the substrate taken along section C1 in the structure shown; Figure 6A is a schematic cross-sectional view parallel to the substrate taken along section C1 in the structure shown;
[0065] Figure 7A is a schematic three-dimensional structure view of a semiconductor structure provided by an exemplary embodiment of the present application after forming an insulating layer;
[0066] Figure 7B A cross-sectional view parallel to the substrate taken along section C1 in the structure shown; Figure 7A is a schematic cross-sectional view parallel to the substrate taken along section C1 in the structure shown;
[0067] Figure 8A is a schematic three-dimensional structure view of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;
[0068] Figure 8B A cross-sectional view parallel to the substrate taken along section C2 in the structure shown; Figure 8A is a schematic cross-sectional view parallel to the substrate taken along section C2 in the structure shown;
[0069] Figure 9A is a schematic three-dimensional structure view of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;
[0070] Figure 9B is Figure 9A a schematic cross-sectional view parallel to the substrate taken along section C1 of the structure shown;
[0071] Figure 10A a schematic three-dimensional structure view of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;
[0072] Figure 10B is along Figure 10A a schematic cross-sectional view parallel to the substrate taken along section C1 in the structure shown;
[0073] Figure 11A a schematic three-dimensional structure view of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;
[0074] Figure 11B is along Figure 11A a schematic cross-sectional view perpendicular to the substrate taken along section C1 in the structure shown;
[0075] Figure 12A a schematic three-dimensional structure view of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;
[0076] Figure 12B is along Figure 12A a schematic cross-sectional view perpendicular to the substrate taken along section C1 in the structure shown;
[0077] Figure 13A a schematic three-dimensional structure view of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;
[0078] Figure 13B is along Figure 13A a schematic cross-sectional view parallel to the substrate taken along section C1 in the structure shown;
[0079] Figure 13C is along Figure 13A a schematic cross-sectional view perpendicular to the substrate taken along section C2 in the structure shown;
[0080] Figure 13D is along Figure 13A a schematic cross-sectional view perpendicular to the substrate taken along section C3 in the structure shown;
[0081] Figure 14A a schematic three-dimensional structure view of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;
[0082] Figure 14B A schematic cross-sectional view parallel to the substrate taken along cross-section C1 in the structure shown; Figure 14A
[0083] Figure 14C A schematic cross-sectional view perpendicular to the substrate taken along cross-section C2 in the structure shown; Figure 14A
[0084] Figure 14D A schematic cross-sectional view perpendicular to the substrate taken along cross-section C3 in the structure shown; Figure 14A
[0085] Figure 15A A schematic three-dimensional structure view of an intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided by an exemplary embodiment of the present application;
[0086] Figure 15B A schematic cross-sectional view parallel to the substrate taken along cross-section C1 in the structure shown; Figure 15A
[0087] Figure 15C A schematic cross-sectional view perpendicular to the substrate taken along cross-section C2 in the structure shown; Figure 15A
[0088] Figure 15D A schematic cross-sectional view perpendicular to the substrate taken along cross-section C3 in the structure shown; Figure 15A
[0089] Figure 16A A schematic three-dimensional structure view of an intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided by an exemplary embodiment of the present application;
[0090] Figure 16B A schematic cross-sectional view parallel to the substrate taken along cross-section C1 in the structure shown; Figure 16A
[0091] Figure 16C A schematic cross-sectional view perpendicular to the substrate taken along cross-section C2 in the structure shown; Figure 16A
[0092] Figure 17A A schematic three-dimensional structure view of an intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided by an exemplary embodiment of the present application;
[0093] Figure 17B A schematic cross-sectional view parallel to the substrate taken along cross-section C1 in the structure shown; and Figure 17A
[0094] Figure 17C A schematic cross-sectional view perpendicular to the substrate taken along cross-section C2 in the structure shown; Figure 17A Schematic cross-sectional view perpendicular to the substrate taken along cross-section C2 in the structure shown. Detailed implementation mode
[0095] To make the objectives, technical solutions, and advantages of this application clearer and more understandable, the embodiments of this application will be described in detail below in conjunction with the accompanying drawings. It should be noted that, without conflict, the embodiments in this application and the features in the embodiments can be arbitrarily combined with each other.
[0096] The implementation modes in this article can be implemented in multiple different forms. It is easy for those of ordinary skill in the art to understand the fact that the implementation methods and content can be transformed into various forms without departing from the gist and scope of this application. Therefore, this application should not be construed as being limited only to the content described in the following implementation modes. Without conflict, the embodiments in this application and the features in the embodiments can be arbitrarily combined with each other.
[0097] The drawing ratios in this application can be used as a reference in actual processes, but are not limited thereto. For example: the aspect ratio of the semiconductor layer, the thickness and spacing of each film layer can be adjusted according to actual needs. The drawings described in this application are only schematic structural diagrams, and one mode of this application is not limited to the shapes or values shown in the drawings, etc.
[0098] In this specification, for convenience, terms indicating orientation or positional relationships such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationships of the constituent elements with reference to the drawings, which are only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, so it should not be construed as a limitation to this application. The positional relationships of the constituent elements are appropriately changed according to the directions describing each constituent element. Therefore, it is not limited to the terms described in the specification and can be appropriately replaced according to the situation.
[0099] In this specification, unless otherwise clearly specified and limited, the terms "arranged" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate member, or the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific situations.
[0100] In the description of this application, ordinal numbers such as "first" and "second" are set to avoid confusion of the constituent elements, rather than to limit the quantity.
[0101] In this specification, "film" and "layer" can be interchanged. For example, sometimes "metal layer" can be replaced with "metal film".
[0102] In the description of this application, a transistor refers to an element that includes at least three terminals: a gate, a drain, and a source. The transistor has a channel layer between the drain (drain terminal, drain region, or drain) and the source (source terminal, source region, or source), and current can flow through the drain, the channel layer, and the source. In this application, the channel layer refers to the region where current mainly flows. In this application, the terms "metal oxide semiconductor channel", "channel", and "semiconductor layer" are interchangeable.
[0103] As used in this application, the term "being an integrated structure" can mean that there is no obvious boundary interface such as a distinct fault or gap between A and B at the microstructural level. Generally, a connected film layer patterned on a film layer is an integrated body. For example, A and B are made of the same material to form a film layer and are simultaneously formed into a structure with a connection relationship through the same patterning process.
[0104] Therefore, an exemplary embodiment of this application provides a semiconductor structure, including: a first common word line layer located on a substrate, the first common word line layer including a plurality of first common word lines; a conductive layer group located on a side of the first common word line layer away from the substrate, the conductive layer group including a plurality of conductive layers arranged along a third direction perpendicular to the substrate, the conductive layer having a bit line region and a first memory cell region including a first memory cell; a plurality of first word lines, the first word lines extending along the third direction and connected to the first memory cells in the first memory cell region, the first word lines being electrically connected to a corresponding one of the first common word lines.
[0105] As used in the embodiments of this disclosure, the term "first direction" X is defined as the direction parallel to the extension direction of the common word line; the term "second direction" Y is defined as intersecting the "first direction" X and is defined as the direction parallel to the extension direction of the bit line; the term "third direction" Z is defined as the direction perpendicular to the substrate, that is, the extension direction of the word line; the plane formed by the first direction X and the second direction Y is parallel to the substrate. The "first direction" X, the "second direction" Y, and the "third direction" Z can be as Figures 1A - 1B 、 Figures 2A - 2D etc. shown.
[0106] The semiconductor structure provided by the embodiments of this application can be a DRAM. Generally, a DRAM includes a plurality of two-dimensionally distributed memory cell arrays to avoid problems such as reduced speed or performance caused by one Array.
[0107] In the 3D DRAM application scenario, multiple Arrays are distributed in different regions of the substrate. Each Array has multiple stacked structures periodically distributed in the direction perpendicular to the substrate, and one stacked structure can be called a MAT.
[0108] To reduce the number of SWDs and save area, 3D DRAM adopts a common word line scheme, where the sub-word lines of several MATs share one SWD. The sub-word lines at the same array position of different MATs are connected together and connected to the common word line in the SWD circuit.
[0109] This application makes improvements based on the above scenario.
[0110] As Figure 1A and 1B shown, the semiconductor structure can include five MATs. Specifically, it includes: substrate 10; a first common word line layer 21 located on the substrate 10, and the first common word line layer 21 includes multiple first common word lines 31; a conductive layer group located on the side of the first common word line layer 21 away from the substrate 10, the conductive layer group includes multiple conductive layers 30 arranged along the third direction Z perpendicular to the substrate 10, the conductive layer has a bit line region 100 and a first storage unit region 200, and the first storage unit region 200 includes at least one first storage unit; at least one first word line 61, the first word line 61 extends along the third direction Z and is connected to the at least one first storage unit, and the first word line 61 is electrically connected to a corresponding first common word line 31. Bit lines 70 can be formed in the bit line region 100.
[0111] Referring to Figure 1B , the first storage unit region 200 can include a capacitor region 210 and a transistor region 220.
[0112] In an exemplary embodiment, the first common word line layer 21 can include multiple first common word lines 31 extending along the first direction X and arranged in the second direction Y. The conductive layer 30 can have a bit line region 100 extending along the second direction Y and a first storage unit region 200 and a second storage unit region 300 located on both sides of the bit line region 100, and the first storage unit region 200 and the second storage unit region 300 each include multiple storage units arranged along the second direction.
[0113] Continuing to refer to Figure 1B, a plurality of first word lines 61 may be located within the first memory cell region 200 and arranged at intervals along the second direction Y; a plurality of second word lines 62 may be located within the second memory cell region 300 and arranged at intervals along the second direction Y. Both the first word line 61 and the second word line 62 extend along the third direction Y and are respectively connected to a plurality of memory cells, and both the first word line 61 and the second word line 62 are electrically connected to corresponding first common word lines 31.
[0114] Continue to refer to Figure 1B , the first word line 61 and the second word line 62 are arranged staggeredly in the second direction Y, that is, the first common word line 31 connected to the first word line 61 and the first common word line 31 connected to the second word line 62 are arranged alternately in the second direction Y.
[0115] In some embodiments, the first word line and the second word line at the same position in the array are connected to the same first common word line.
[0116] In an exemplary embodiment, the first memory cell region 110 further includes a first word line through hole (not shown), the second memory cell region 120 further includes a second word line through hole (not shown), and the first word line through hole and the second word line through hole are arranged staggeredly in the second direction Y; the first word line 61 is located within the first word line through hole, and the second word line 62 is located within the second word line through hole.
[0117] As Figures 2A - 2D shown, the semiconductor structure may further include a second common word line layer 22 located between the first common word line layer 21 and the conductive layer group, and the second common word line layer 22 includes a plurality of second common word lines 32 extending along the first direction X and arranged at intervals in the second direction.
[0118] Continue to refer to Figure 2A and 2B , the first word line 61 and the second word line 62 are symmetrically distributed with respect to the bit line region 100 in the first direction. The first word line 61 is electrically connected to the corresponding first common word line 31; the second word line 62 is electrically connected to the corresponding second common word line 32.
[0119] Continue to refer to FIGS. 1C and 1D. The first memory cell region 200 further includes a plurality of common word line through holes S, and the common word line through holes S penetrate through the second common word line layer 22 along the third direction Z and communicate with the first word line 61 through hole. The first word line 61 is located within the first word line through hole K1 and the common word line through hole S.
[0120] Figures 1C and 1D also show that the first memory cell region 200 further includes an annular isolation portion 50, which is located within the common word line via S and surrounds the first word line 61. The distance from the top surface of the annular isolation portion 50 away from the substrate 10 to the substrate 10 is a first height, and the distance from the top surface of the second common word line layer 22 away from the substrate 10 to the substrate 10 is a second height. The first height is greater than or equal to the second height. Thus, it can be seen that multiple first word lines 61 are insulated from each second common word line 32 in the second word line layer 22 by means of the annular isolation portion 50 and are only electrically connected to each first common word line 31 in the first common word line layer 21.
[0121] Figures 1C and 1D also show that an isolation layer 41 is further included, and the isolation layer 41 is located between the second common word line layer 22 and the conductive layer group.
[0122] Figure 1A and 2A It is also shown that the semiconductor structure may include a plurality of sense amplifiers SA, which are arranged at intervals along the second direction and are electrically connected to the bit lines 70; it further includes a bonding chip, which is located on the side of the conductive layer group away from the substrate and is provided with a plurality of sub-word line drivers SWD; both the first word line 61 and the second word line 62 are electrically connected to the sub-word line driver.
[0123] In this application, by providing at least one layer of common word line layer below the memory array, the number of SWDs is reduced and the planar area is saved, which is beneficial to improving the integration degree of the semiconductor structure. In particular, two layers of common word line layers with multiple common word lines are provided, thereby increasing the spacing between adjacent common word lines, reducing the resistance-capacitance effect, and at the same time reducing the manufacturing difficulty of the common word lines.
[0124] The technical solution of the present application will be further described below through the manufacturing process of the semiconductor structure of the exemplary embodiment of the present application. The "lithography process" mentioned in this exemplary embodiment includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching, and stripping the photoresist, which are mature manufacturing processes in the related art. The "photolithography process" mentioned in this exemplary embodiment includes coating a film layer, mask exposure, and development, which are mature manufacturing processes in the related art. Deposition can use known processes such as sputtering, evaporation, and chemical vapor deposition, coating can use known coating processes, and etching can use known methods, which will not be specifically limited here. In the description of this exemplary embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a lithography process or a photolithography process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" also requires a lithography process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the lithography process and a "layer" after the lithography process. The "layer" after the lithography process or the photolithography process contains at least one "pattern".
[0125] In some exemplary embodiments, the manufacturing process of the semiconductor structure may include:
[0126] S100: Form a common word line layer.
[0127] Exemplary steps may include: providing a substrate 10, depositing a conductive material thin film on the substrate 10 to form a first common word line layer 21, as Figure 3A and 3B shown.
[0128] In an exemplary embodiment, a physical vapor deposition method (PVD), a chemical vapor deposition method (CVD), or a plasma enhanced chemical vapor deposition method (PECVD) may be used to deposit the conductive material thin film.
[0129] In an exemplary embodiment, the substrate may be a semiconductor substrate; for example, it may include at least one elemental semiconductor material (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (such as a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In an exemplary embodiment, the substrate 10 may be a single crystal silicon substrate.
[0130] In an exemplary embodiment, the first common word line layer 21 may be made of a metallic material, including but not limited to tungsten, titanium nitride, polysilicon, etc.
[0131] S200: Form a plurality of first common word lines.
[0132] Exemplary steps may include: performing photolithography and etching on the first common word line layer 21 to form a plurality of trenches that penetrate the first common word line layer 21 and terminate at the upper surface of the substrate 10 and extend along the first direction X; forming a first common word line 31 that extends along the first direction X between two adjacent trenches in the second direction Y; depositing an insulating layer film to fill the trenches to form the insulating layer 40; planarizing the upper surfaces of the first common word line layer 21 and the insulating layer 40 by a chemical mechanical polishing (CMP) process, as Figure 4A and 4B shown.
[0133] In an exemplary embodiment, the size of each first common word line 31 along the second direction Y, i.e., the width of the common word line, can be selected according to different situations.
[0134] Techniques such as Self-aligned Double Patterning (SADP) and Self-Aligned Quadruple Pattern (SAQP) can be used to form the common word lines.
[0135] In an exemplary embodiment, the insulating layer 40 may be made of an oxide material, such as silicon dioxide.
[0136] In an exemplary embodiment, the insulating layer film may be deposited by chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD).
[0137] In some exemplary embodiments, the manufacturing process of the semiconductor structure may include:
[0138] S1000: Form a common word line structure including two layers of common word line layers.
[0139] Exemplary steps may include: providing a substrate 10, and sequentially depositing a conductive material film, an insulating layer film, and a conductive material film on the substrate 10 to form a common word line structure including a first common word line layer 21 and a second common word line layer 22 separated by a first insulating layer 20, as Figure 5A and 5B shown.
[0140] In an exemplary embodiment, a conductive material thin film may be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), or plasma enhanced chemical vapor deposition (PECVD).
[0141] In an exemplary embodiment, the substrate may be a semiconductor substrate; for example, it may include at least one elemental semiconductor material (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (such as a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In an exemplary embodiment, the substrate 10 may be a single crystal silicon substrate.
[0142] In an exemplary embodiment, the first common word line layer 21 and the second common word line layer 22 may be made of a metal material, including but not limited to tungsten, titanium nitride, polysilicon, or a composite material of tungsten and titanium nitride.
[0143] In an exemplary embodiment, the first insulating layer 20 may be made of a low dielectric constant material (low-K material).
[0144] S2000: Form multiple common word lines.
[0145] Exemplary steps may include: lithographically etching a common word line structure to form a plurality of trenches T that penetrate the common word line structure and terminate at the upper surface of the substrate 10 and extend along the first direction X; forming a first common word line 31 in the first common word line layer 21 and a second common word line 32 in the second common word line layer 22 that extend along the first direction X between two adjacent trenches T in the second direction Y, as Figure 6A and 6B shown.
[0146] In an exemplary embodiment, the dimension of each common word line 31 / 32 along the second direction Y, i.e., the width of the common word line, may be selected according to different situations.
[0147] Techniques such as self-aligned double patterning (SADP) and self-aligned quadruple pattern (SAQP) may be used to form the common word lines.
[0148] S3000: Form a second insulating layer.
[0149] Exemplary steps may include: depositing a thin film of an insulating layer on the structure formed in the foregoing steps, filling all the trenches T, and forming a second insulating layer 40; planarizing the upper surface of the second common word line layer 22 and the second insulating layer 40 by a chemical mechanical polishing (CMP) process, thereby forming the semiconductor structure of the present application, as Figure 7A and 7B shown.
[0150] In an exemplary embodiment, the second insulating layer 40 may be made of an oxide material, such as silicon dioxide.
[0151] In an exemplary embodiment, a thin film of the insulating layer may be deposited by chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD).
[0152] S4000: Form a plurality of common word line vias.
[0153] Exemplary steps may include: depositing a thin film of an insulating material on the side of the second common word line layer 22 away from the substrate to form an isolation layer 41 for isolating the second common word line layer 22 from the memory array located above the second common word line layer 22; etching the second common word line layer 22 to form a plurality of common word line vias S corresponding to multiple word lines of the memory array, and the common word line vias S terminate at the side of the first common word line layer 21 away from the substrate 10, that is, the upper surface of the first common word line layer 21 is exposed, as Figure 8A and 8B shown.
[0154] In an exemplary embodiment, the isolation layer 41 may be made of a low K material different from the first insulating layer 20 and the second insulating layer 40, and the isolation layer 41 may be made of a nitride material, such as silicon nitride.
[0155] As Figure 8B shown, the orthographic projection of the common word line via S on the plane of the substrate 10 is rectangular. However, in other exemplary embodiments, the orthographic projection of each common word line via on the plane parallel to the substrate 10 may also be in the shape of a circle, an ellipse, a square, etc.
[0156] S5000: Form an annular isolation portion.
[0157] Exemplary steps may include: depositing a thin film of an insulating layer around the inner wall of each common word line via S to form an annular isolation portion 50, and the annular isolation portion 50 covers the side wall of the second common word line 32 on the second common word line layer 22, as Figure 9A and 9B shown.
[0158] S6000: Fill the common word line vias.
[0159] Exemplary steps may include: Continuing to deposit a thin film of an insulating layer within the common word line vias S to form a second insulating layer 40 and planarizing the second insulating layer with the upper surface of the isolation layer by a CMP process, as Figure 10A and 10B shown.
[0160] S7000: Form a stacked structure.
[0161] Exemplary steps may include: Continuing to alternately deposit thin films of an insulating layer and a sacrificial layer over the isolation layer 41 to form a stacked structure including a second insulating layer 40 and a sacrificial layer 51, as Figure 11A and 11B shown.
[0162] In an exemplary embodiment, the sacrificial layer 51 may be made of a nitride material, such as silicon nitride.
[0163] S8000: Form word line vias and form dummy word lines.
[0164] Exemplary steps may include: Within the first memory cell region 200, by etching the stacked structure and the common word line vias S, a first word line via K1 communicating with the common word line vias S is formed, the first word line via K1 terminates at a side of the first common word line layer 21 away from the substrate 10, and the annular isolation portion 50 within the common word line vias S is not etched away; filling the common word line vias S and the first word line via K1 with a sacrificial material to form a dummy first word line 61', and the sacrificial material may be Al2O3; as Figure 12A and 12B shown.
[0165] S9000: Pattern the stacked structure to form a preset pattern.
[0166] Exemplary steps may include: Forming a preset pattern by etching the stacked structure, and the preset pattern may include forming 1 bit line region 100 extending along the second direction Y and first memory cell regions 200 and second memory cell regions 300 extending along the first direction X on both sides of the bit line region 100, and the first memory cell regions 200 and the second memory cell regions 300 may include a plurality of memory cells spaced apart in the second direction Y, as Figures 13A - 13D shown.
[0167] In an exemplary embodiment, Figure 13DIt is also shown that within the first memory cell region 200 and the second memory cell region 300, a second word line via hole K2 penetrating the stacked structure and the isolation layer 41 can be formed by etching the stacked structure, and the second word line via hole K2 terminates at a side of the second common word line layer 22 away from the substrate 10; the second word line via hole K2 is filled with a sacrificial material to form a dummy second word line 62', and the sacrificial material can be Al2O3.
[0168] S10000: Form a conductive layer.
[0169] Exemplary steps may include: etching away the material of the sacrificial layer 51 to form a plurality of empty grooves (not shown), depositing a conductive metal material by ALD method; removing the conductive metal material on the sidewalls to form a conductive layer 30, completing the replacement of the conductive metal; depositing an oxide material to form a second insulating layer 40; planarizing the upper surface of the stacked structure by CMP, as Figures 14A - 14D shown.
[0170] S11000: Form a second electrode of the capacitor.
[0171] Exemplary steps may include: etching the material of the second insulating layer 40 within the capacitor region 210 and laterally etching the material of the second insulating layer 40 between adjacent conductive layers 30 to expose the first electrode 81 of the capacitor; depositing an insulating material and a conductive metal material around the first electrode 81 by ALD method to form a dielectric layer (not shown) and a second electrode 82; planarizing the upper surface of the stacked structure by CMP, as Figures 15A - 15D shown.
[0172] S12000: Form a second electrode of the capacitor.
[0173] Exemplary steps may include: removing the material in the dummy first word line 61' and the dummy second word line 62' to form the first word line via hole and the second word line via hole again; then laterally etching the conductive layer 30 to form a laterally enlarged first word line via hole K1 and a second word line via hole K2; sequentially depositing a semiconductor material and an insulating material along the sidewalls of the first word line via hole K1 and the second word line via hole K2 and the inner walls of the laterally enlarged first word line via hole K1 and the second word line via hole K2 to form a gate insulating layer 64 and a preset semiconductor layer 63', as Figures 16A - 16C shown.
[0174] S13000: Eliminate parasitic MOS and form a semiconductor layer.
[0175] Exemplary steps may include: removing semiconductor materials and insulating materials on the sidewalls of the first word line via hole K1 and the second word line via hole K2, retaining the materials within the laterally enlarged first word line via hole K1 and the second word line via hole K2, disconnecting the adjacent preset semiconductor layers 63' in the third direction Z to form the semiconductor layer 63 and eliminate parasitic MOS; depositing a conductive material thin film into the first word line via hole K1 and the second word line via hole K2 again to form the first word line 61 and the second word line 62, where the first word line 61 is connected to the first common word line layer 21 and the second word line 62 is connected to the second common word line layer 22, as Figures 17A - 17C shown.
[0176] An exemplary embodiment of the present application further provides an electronic device, including the semiconductor structure provided by the exemplary embodiment of the present application as above.
[0177] In an exemplary embodiment, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.
[0178] Although the disclosed embodiments of the present application are as above, the described content is only an embodiment adopted for facilitating the understanding of the present application and is not used to limit the present application. Any person skilled in the art within the scope of the present application can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present application. However, the protection scope of the present application shall still be subject to the scope defined by the appended claims.
Claims
1. A semiconductor structure, characterized in that, Comprising: A first common word line layer located on a substrate, the first common word line layer including a plurality of first common word lines; A conductive layer group located on a side of the first common word line layer away from the substrate, the conductive layer group including a plurality of conductive layers arranged along a third direction perpendicular to the substrate, the conductive layer having a bit line region and a first memory cell region including a first memory cell; A plurality of first word lines, the first word lines extending along the third direction and connected to the first memory cells in the first memory cell region, the first word lines being electrically connected to a corresponding one of the first common word lines.
2. The semiconductor structure according to claim 1, wherein, The first common word line layer includes a plurality of first common word lines extending along a first direction and spaced apart in a second direction, the first direction intersecting the second direction and being perpendicular to the third direction.
3. The semiconductor structure according to claim 1, wherein The conductive layer has a bit line region extending along the second direction and a first memory cell region and a second memory cell region located on both sides of the bit line region, the first memory cell region and the second memory cell region each including a plurality of memory cells arranged along the second direction.
4. The semiconductor structure according to claim 3, characterized in that, The plurality of first word lines are arranged in an array in the first memory cell region; Further comprising: a plurality of second word lines, extending along the third direction and arranged in an array in the second memory cell region.
5. The semiconductor structure according to claim 4, wherein The first word line and the second word line at the same position in the array are connected to the same one of the first common word lines.
6. The semiconductor structure according to claim 4, wherein, The first word line and the second word line are arranged in a staggered manner in the second direction.
7. The semiconductor structure according to claim 4, wherein The first common word line connected to the first word line and the first common word line connected to the second word line are arranged alternately in the second direction.
8. The semiconductor structure according to claim 4, wherein The first memory cell region further includes a first word line through hole, the second memory cell region further includes a second word line through hole, the first word line through hole and the second word line through hole are arranged in a staggered manner in the second direction; the first word line is located in the first word line through hole, and the second word line is located in the second word line through hole.
9. The semiconductor structure according to claim 1, wherein Further comprising a second common word line layer located between the first common word line layer and the conductive layer group, the second common word line layer including a plurality of second common word lines extending along the first direction and spaced apart in the second direction.
10. The semiconductor structure according to claim 9, wherein The first word line and the second word line are symmetrically distributed with respect to the bit line region in the first direction.
11. The semiconductor structure according to claim 9, wherein The first word line is electrically connected to the corresponding first common word line; the second word line is electrically connected to the corresponding second common word line.
12. The semiconductor structure according to claim 9, wherein The first memory cell region further includes a plurality of common word line through holes, the common word line through holes passing through the second common word line layer along the third direction and communicating with the first word line through holes; the first word line is located in the first word line through holes and the common word line through holes.
13. The semiconductor structure according to claim 12, wherein, The first memory cell region further includes an annular isolation portion, the annular isolation portion being located in the common word line through hole and surrounding the first word line.
14. The semiconductor structure according to claim 13, wherein The distance from the top surface of the annular isolation portion away from the substrate to the substrate is a first height, the distance from the top surface of the second common word line layer away from the substrate to the substrate is a second height, and the first height is greater than or equal to the second height.
15. The semiconductor structure according to claim 1, wherein Further includes an isolation layer, and the isolation layer is located between the second common word line layer and the conductive layer group.
16. The semiconductor structure according to claim 9, wherein, Further includes an isolation layer, and the isolation layer is located between the second common word line layer and the conductive layer group.
17. The semiconductor structure according to claim 1, wherein, Further includes a plurality of sense amplifiers, which are arranged at intervals along the second direction and are electrically connected to the bit lines.
18. The semiconductor structure according to claim 4, wherein Further includes a bonding chip, the bonding chip is located on a side of the conductive layer group away from the substrate, and the bonding chip is provided with a plurality of sub-word line drivers; both the first word line and the second word line are electrically connected to the sub-word line drivers.
19. A manufacturing method of a semiconductor structure, characterized in that, Includes the following steps: Depositing a conductive material thin film on the substrate to form a first common word line layer; Etching the first common word line layer to form at least one first common word line; Alternately depositing an insulating material thin film and a conductive material thin film on a side of the first common word line layer away from the substrate to form a stacked structure including an insulating layer and a conductive layer; Patterning the stacked structure to form a bit line region and a first memory cell region in the conductive layer, and the first memory cell region includes at least one first memory cell; Forming a first word line through hole penetrating the stacked structure, and forming a first word line in the first word line through hole to connect the first word line with at least one first memory cell; Electrically connecting the first word line with a corresponding first common word line.
20. The manufacturing method according to claim 19, characterized in that, Etching the first common word line layer to form at least one first common word line includes: Etching the first common word line layer to form a plurality of first common word lines extending along a first direction and arranged at intervals in a second direction, the first direction intersects with the second direction and is perpendicular to a third direction perpendicular to the substrate.
21. The manufacturing method according to claim 19, characterized in that, Patterning the stacked structure includes: patterning the stacked structure to form a bit line region extending along the second direction and a first memory cell region and a second memory cell region located on both sides of the bit line region in each conductive layer, and the first memory cell region and the second memory cell region each include a plurality of memory cells arranged at intervals along the second direction.
22. The manufacturing method according to claim 19, characterized in that, Includes: Displacing the first word line and the second word line in a staggered manner in the second direction.
23. The manufacturing method according to claim 22, characterized in that, Includes: Alternately arranging the first common word line connected to the first word line and the first common word line connected to the second word line in the second direction.
24. The manufacturing method according to claim 19, wherein, Includes: Depositing an insulating material thin film and a conductive material thin film on the first common word line layer to form a second common word line layer spaced from the first common word line layer by the insulating layer; Etching the second common word line layer to form a plurality of second common word lines in the second common word line layer.
25. The manufacturing method according to claim 24, characterized in that, Includes: Symmetrically distributing the first word line and the second word line with respect to the bit line region in the first direction; Electrically connecting the first word line with the corresponding first common word line one by one; electrically connecting the second word line with the corresponding second common word line.
26. The manufacturing method according to claim 25, characterized in that, Includes: Forming a plurality of first word line through holes penetrating the stacked structure in the first memory cell region, forming a common word line through hole penetrating the second common word line layer in the first memory cell region, connecting the common word line through hole with the first word line through hole, and forming the first word line in the first word line through hole and the common word line through hole; A plurality of second word line vias penetrating the stacked structure are formed in the second storage cell region, and the second word lines are formed in the second word line vias.
27. The manufacturing method according to claim 24, characterized in that, It further includes, in the first storage cell region, depositing an isolation material film in the common word line via to form an annular isolation portion. The distance from the top surface of the annular isolation portion away from the substrate to the substrate is a first height, and the distance from the top surface of the second common word line layer away from the substrate to the substrate is a second height, and the first height is greater than or equal to the second height.
28. An electronic device, characterized in that, It includes a semiconductor structure according to any one of claims 1-18.