Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention relates to a three-dimensional memory, a manufacturing method thereof and electronic equipment. The three-dimensional memory comprises a substrate, a plurality of layers of memory units stacked on the substrate at intervals along a third direction, and word lines extending along the third direction, a bit line extending along a second direction; each layer of storage units comprises a plurality of storage units which are arranged at intervals along a second direction; the storage unit comprises a transistor and a capacitor; wherein the transistor comprises a semiconductor layer extending along a first direction, and a first source / drain electrode and a second source / drain electrode which are positioned on two sides of the semiconductor layer and are connected with the semiconductor layer; the capacitor comprises a first electrode electrically connected with the first source / drain electrode, and the first electrode comprises a material different from that of the first source / drain electrode; the semiconductor device further comprises insulating layers between the adjacent semiconductor layers, and the first electrodes and the insulating layers are overlapped in the first direction. The manufacturing process is simple.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to, but are not limited to, semiconductor technologies, and particularly to a semiconductor device, a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technologies, the critical dimensions of devices are increasingly reduced, and the types and quantities of devices included in a single chip increase accordingly, such that any minor difference in the process production may affect the device performance.

[0003] In order to reduce the cost of products as much as possible, it is desired to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, various semiconductor structure designs and process optimizations have been proposed in the industry to meet the requirements for current products. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in the present disclosure. This overview is not intended to limit the scope of protection of the present application.

[0005] In one aspect, an exemplary embodiment of the present application provides a semiconductor device, including a substrate and a plurality of layers of memory cells stacked at intervals along a third direction perpendicular to the substrate, each layer of memory cells including a plurality of memory cells arranged along a second direction; the memory cells include at least one transistor and at least one capacitor; wherein the transistor includes a semiconductor layer extending along a first direction and a first source / drain and a second source / drain located on both sides of the semiconductor layer and connected to the semiconductor layer; the capacitor includes a first electrode electrically connected to the first source / drain, the first electrode including a material different from that of the first source / drain; further including an insulating layer alternately stacked with the semiconductor layer in the third direction, the first electrode being located between adjacent insulating layers, and the first electrode overlapping with the insulating layer in the first direction; the second direction intersects with the first direction and is parallel to the substrate.

[0006] In an exemplary implementation method, the insulating layer includes a separation layer and a support layer, and the materials of the separation layer and the support layer are different.

[0007] In an exemplary implementation method, both sides of the first electrode in the third direction are in contact with the support layer.

[0008] In an exemplary implementation method, the first source / drain and the second source / drain include single crystal silicon; the first electrode includes titanium nitride.

[0009] In an exemplary implementation method, the dimension of the first source / drain along the third direction is the same as the dimension of the first electrode along the third direction.

[0010] In an exemplary implementation method, there is a metal silicide between the first source / drain and the first electrode, and one side of the second source / drain close to the bit line includes a metal silicide.

[0011] In an exemplary implementation method, the capacitor further includes a second electrode surrounding the first electrode.

[0012] In an exemplary implementation method, the first electrode, the second electrode, and the bit line are made of the same material.

[0013] In an exemplary implementation method, the second electrodes of the capacitors of the memory cells in different layers are interconnected to form an integral structure.

[0014] In an exemplary implementation method, there is a common connection layer between the plurality of second electrodes, and the common connection layer is connected to the second electrodes.

[0015] In an exemplary implementation method, the transistor further includes a gate, the gate is a part of the word line, a gate insulating layer is included between the gate and the semiconductor layer, and the gate at least partially surrounds the semiconductor layer.

[0016] In an exemplary implementation method, the transistors of the plurality of memory cells arranged at intervals along a second direction are connected to the same bit line.

[0017] On the other hand, an exemplary implementation method of the present disclosure provides a method for manufacturing a semiconductor device, including the following steps:

[0018] Provide a substrate;

[0019] Form a sacrificial layer and an initial semiconductor layer alternately along a third direction perpendicular to the substrate to form a stacked structure, the stacked structure including a bit line preset area, a transistor preset area, and a capacitor preset area arranged along a first direction, the first direction being parallel to the substrate;

[0020] Form a semiconductor layer, a first source / drain, a second source / drain, and a word line in the transistor preset area;

[0021] Form a bit line in the bit line preset area;

[0022] In the capacitor preset area, etch away the initial semiconductor layer to form a first lateral groove, and fill the first lateral groove with a conductive material different from the initial semiconductor layer to form a first electrode of the capacitor.

[0023] In an exemplary implementation method, the manufacturing method further includes:

[0024] A support region is established in the preset region of the transistor, and the materials of the sacrificial layers in the support region are replaced with insulating materials to form a support layer;

[0025] The materials of the remaining sacrificial layers are replaced with insulating materials to form a separation layer between two adjacent initial semiconductor layers in the third direction.

[0026] In an exemplary implementation method, the manufacturing method further includes:

[0027] Etch the material of the separation layer removed to form a second lateral groove to expose the peripheral wall of the first electrode;

[0028] Deposit a dielectric film and a conductive film covering the first electrode in sequence along the exposed peripheral wall of the first electrode, thereby forming a second electrode surrounding the first electrode and a dielectric layer between the first electrode and the second electrode.

[0029] In an exemplary implementation method, the manufacturing method further includes:

[0030] Deposit a conductive material on the surface of the second electrode to form a common connection layer.

[0031] In another aspect, an exemplary implementation of the present application provides an electronic device including the above semiconductor device.

[0032] In an exemplary implementation, the above electronic device includes a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.

[0033] In the present disclosure, by manufacturing the first electrode of the capacitor and the semiconductor layer in the same film layer and directly manufacturing the first electrode of each layer of the capacitor independently, the deposition of the first electrode of the capacitor and the isolation between multiple independent capacitors can be avoided, thus eliminating the need for an additional support frame for depositing the first electrode. In addition, in the present disclosure, the first electrode is deposited on an insulating layer (oxide layer), which can also maintain a good shape of the capacitor electrode and release stress, thereby obtaining a capacitor with complete functions.

[0034] In the present disclosure, by making the capacitor include a first electrode electrically connected to the first source / drain, and the first electrode includes a material different from that of the first source / drain, and by making the first electrode located between adjacent insulating layers, the material of the first source / drain can be replaced by the material of the first electrode during the manufacturing process, thus avoiding the deposition of the first electrode of the capacitor and the isolation between multiple independent capacitors, and eliminating the need for an additional support frame for depositing the first electrode.

[0035] By disposing the first electrode between adjacent insulating layers, the first electrode and the insulating layer overlap in the first direction, and the insulating layer can support the first electrode, preventing the first electrode from collapsing due to suspension during the manufacturing process.

[0036] Other features and advantages of the present application will be described in the subsequent specification, and will be partially apparent from the specification or understood by implementing the present application. Other advantages of the present application can be achieved and obtained through the solutions described in the specification and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings are used to provide an understanding of the technical solutions of the present application, and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solutions of the present application, and do not constitute a limitation to the technical solutions of the present application.

[0038] Figure 1A A top view schematic diagram of a semiconductor device provided for an exemplary embodiment of the present application;

[0039] Figure 1B A cross-sectional schematic diagram perpendicular to the substrate taken along the section line bb' of a semiconductor device provided for an exemplary embodiment of the present application; Figure 1A

[0040] Figure 1C A cross-sectional schematic diagram perpendicular to the substrate taken along the section line ee' of a semiconductor device provided for an exemplary embodiment of the present application; Figure 1A

[0041] Figure 1D A cross-sectional schematic diagram perpendicular to the substrate taken along the section line cc' of a semiconductor device provided for an exemplary embodiment of the present application; Figure 1A

[0042] Figure 2A A cross-sectional schematic diagram perpendicular to the substrate taken along the section line bb' of a stacked structure formed in an intermediate step of a manufacturing method of a semiconductor device provided for an exemplary embodiment of the present application; Figure 1A

[0043] Figure 2B A cross-sectional schematic diagram perpendicular to the substrate taken along the section line ee' of a stacked structure formed in an intermediate step of a manufacturing method of a semiconductor device provided for an exemplary embodiment of the present application; Figure 1A

[0044] Figure 3A A cross-sectional schematic diagram perpendicular to the substrate taken along the section line bb' of a stacked structure formed in an intermediate step of a manufacturing method of a semiconductor device provided for an exemplary embodiment of the present application; Figure 1A ​​​​​Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line bb' in

[0045] Figure 3B A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line ee' of a stacked structure formed in an intermediate step of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application; Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line ee' in

[0046] Figure 4A A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line bb' of a stacked structure formed in an intermediate step of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application; Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line bb' in

[0047] Figure 4B A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line ee' of a stacked structure formed in an intermediate step of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application; Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line ee' in

[0048] Figure 5A A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line bb' of a stacked structure formed in an intermediate step of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application; Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line bb' in

[0049] Figure 5B A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line cc' of a stacked structure formed in an intermediate step of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application; Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line cc' in

[0050] Figure 6 A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line bb' of a stacked structure formed in an intermediate step of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application; Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line bb' in

[0051] Figure 7A A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line ee' of a stacked structure formed in an intermediate step of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application; Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line ee' in

[0052] Figure 7B A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line bb' of a stacked structure formed in an intermediate step of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application; Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line bb' in

[0053] Figure 7CA cross-sectional view perpendicular to the substrate of a stacked structure formed in an intermediate step of a method for manufacturing a semiconductor device provided for an exemplary embodiment of the present application, taken along Figure 1A the cross-sectional line ee' in

[0054] Figure 8A A cross-sectional view perpendicular to the substrate of a stacked structure formed in an intermediate step of a method for manufacturing a semiconductor device provided for an exemplary embodiment of the present application, taken along Figure 1A the cross-sectional line bb' in

[0055] Figure 8B A cross-sectional view perpendicular to the substrate of a stacked structure formed in an intermediate step of a method for manufacturing a semiconductor device provided for an exemplary embodiment of the present application, taken along Figure 1A the cross-sectional line ee' in

[0056] Figure 9A A cross-sectional view perpendicular to the substrate of a stacked structure formed in an intermediate step of a method for manufacturing a semiconductor device provided for an exemplary embodiment of the present application, taken along Figure 1A the cross-sectional line bb' in

[0057] Figure 9B A cross-sectional view perpendicular to the substrate of a stacked structure formed in an intermediate step of a method for manufacturing a semiconductor device provided for an exemplary embodiment of the present application, taken along Figure 1A the cross-sectional line ee' in

[0058] Figure 10A A cross-sectional view perpendicular to the substrate of a stacked structure formed in an intermediate step of a method for manufacturing a semiconductor device provided for an exemplary embodiment of the present application, taken along Figure 1A the cross-sectional line bb' in

[0059] Figure 10B A cross-sectional view perpendicular to the substrate of a stacked structure formed in an intermediate step of a method for manufacturing a semiconductor device provided for an exemplary embodiment of the present application, taken along Figure 1A the cross-sectional line ee' in

[0060] Figure 11A A cross-sectional view perpendicular to the substrate of a stacked structure formed in an intermediate step of a method for manufacturing a semiconductor device provided for an exemplary embodiment of the present application, taken along Figure 1A the cross-sectional line bb' in

[0061] Figure 11B A cross-sectional view perpendicular to the substrate of a stacked structure formed in an intermediate step of a method for manufacturing a semiconductor device provided for an exemplary embodiment of the present application, taken along Figure 1ASchematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line ee' in;

[0062] Figure 12A A laminated structure formed in an intermediate step of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application along Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line bb' in; and

[0063] Figure 12B A laminated structure formed in an intermediate step of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application along Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line ee' in. Detailed Embodiments

[0064] To make the objectives, technical solutions and advantages of the present application clearer and more understandable, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that, without conflict, the embodiments and features in the embodiments of the present application can be combined arbitrarily with each other.

[0065] The embodiments herein can be implemented in multiple different forms. Those of ordinary skill in the art can easily understand the fact that the implementation manners and contents can be transformed into various forms without departing from the gist and scope of the present application. Therefore, the present application should not be construed as being limited only to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of the present application can be combined arbitrarily with each other.

[0066] The drawing ratios in the present application can be used as a reference in actual processes, but are not limited thereto. For example: the aspect ratio of the semiconductor layer, the thickness and spacing of each film layer can be adjusted according to actual needs. The drawings described in the present application are only schematic diagrams, and one embodiment of the present application is not limited to the shapes or values shown in the drawings.

[0067] In this specification, for convenience, words indicating orientation or positional relationships such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationships of the constituent elements with reference to the drawings, which are only for facilitating the description of this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application. The positional relationships of the constituent elements are appropriately changed according to the directions describing each constituent element. Therefore, it is not limited to the words described in the specification and can be appropriately replaced according to the situation.

[0068] In this specification, unless otherwise clearly defined and limited, the terms "arrangement" and "connection" shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected, or indirectly connected through an intermediate member, or the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0069] In the description of this application, ordinal numbers such as "first" and "second" are set to avoid confusion of components, rather than for quantitative limitation.

[0070] In this specification, "film" and "layer" can be interchanged with each other. For example, sometimes "metal layer" can be changed to "metal film".

[0071] In the description of this application, a transistor refers to an element including at least three terminals: a gate, a drain, and a source. The transistor has a channel layer between the drain (drain terminal, drain region, or drain) and the source (source terminal, source region, or source), and current can flow through the drain, the channel layer, and the source. In this application, the channel layer refers to the region where current mainly flows. In this application, the terms "metal oxide semiconductor channel", "channel", and "semiconductor layer" are interchangeable.

[0072] Therefore, this application provides a three-dimensional memory, including a substrate and a plurality of stacked memory cells spaced along a third direction perpendicular to the substrate on the substrate. Each layer of memory cells includes a plurality of memory cells arranged along a second direction; the memory cells include at least one transistor and at least one capacitor; wherein the transistor includes a semiconductor layer extending along a first direction, and a first source / drain and a second source / drain located on both sides of the semiconductor layer and connected to the semiconductor layer; the capacitor includes a first electrode electrically connected to the first source / drain, and the first electrode contains a material different from that of the first source / drain; it also includes an insulating layer alternately stacked with the semiconductor layer in the third direction, the first electrode is located between adjacent insulating layers, and the first electrode and the insulating layer overlap in the first direction; the second direction intersects with the first direction and is parallel to the substrate.

[0073] As used in the embodiments of this disclosure, the term "first direction" X is defined as the direction parallel to the extension direction of the semiconductor layer; the term "second direction" Y is defined as intersecting with the "first direction" X and being parallel to the extension direction of the bit line; the term "third direction" Z is defined as the direction perpendicular to the plane where the substrate is located, that is, the extension direction of the word line; the plane formed by the first direction X and the second direction Y is parallel to the substrate. The "first direction" X, the "second direction" Y, and the "third direction" Z can be asFigure 1A - Figure 1D as shown in etc.

[0074] As used in this application, the term "section line bb'" is a line parallel to the first direction X and passing through the transistor region, the bit line region, and the capacitor region; the term "section line cc'" is a line parallel to the second direction Y and passing only through the semiconductor layer of the transistor region; and the term "section line ee'" is a line parallel to the second direction Y and passing only through the capacitor region. The specific positions of these section lines can be as Figure 1A - Figure 1D as shown in etc.

[0075] As used in this application, the term "being an integral structure" may refer to that there is no obvious fault or gap or other obvious boundary interface between A and B in the microstructure. Generally, a connected film layer patterned on a film layer is an integral body. For example, A and B are made of the same material to form a film layer and are simultaneously formed with a connected structure through the same patterning process.

[0076] such as Figure 1A - 1D As shown, the three-dimensional memory may include a substrate 10 and a plurality of stacked memory cells spaced along a third direction on the substrate 10, a word line 70 extending along the third direction Z; a bit line 80 extending along the second direction Y; each layer of memory cells includes a plurality of memory cells arranged at intervals along the second direction Y; the memory cell includes a transistor and a capacitor. The transistor may include a semiconductor layer 50 extending along the first direction X and a first source / drain 51 and a second source / drain 52 located on both sides of the semiconductor layer 50 and connected to the semiconductor layer.

[0077] In an exemplary embodiment, the first source / drain 51 and the second source / drain 52 of the same transistor may be located in the same conductive layer. It can be understood that the first source / drain 51 and the second source / drain 52 are located in the same metal layer, formed by patterning a film layer, and the conductive layer is substantially parallel to the substrate 10.

[0078] Although the first source / drain and the second source / drain are used herein to represent two separate and different source / drains, it is not intended that the source / drains referred to as "first" source / drain and / or "second" source / drain have a unique meaning.

[0079] In an exemplary embodiment, the first source / drain 51 and the second source / drain 52 are independent of each other. In an exemplary embodiment, one of the first source / drain 51 and the second source / drain 52 is the source of the transistor and the other is the drain of the transistor.

[0080] Referring to Figure 1BIt can be known that the capacitor may include a first electrode 61 electrically connected to the first source / drain 51. The first electrode 61 is made of a material different from that of the first source / drain. For example, the first source / drain is made of single-crystalline silicon or polycrystalline silicon, while the first electrode is made of titanium nitride, tungsten, ITO, etc.

[0081] Continuing to refer to Figure 1B , it further includes an insulating layer alternately stacked with the semiconductor layer 50 in the third direction Z. The first electrode 61 is located between adjacent insulating layers, and the first electrode 61 overlaps with the insulating layer in the first direction X; that is, the orthographic projection of the first electrode 61 on the substrate 10 overlaps with the orthographic projection of the insulating layer on the substrate 10. Through the above arrangement, the first electrode can be supported and clamped by the insulating layer, avoiding the collapse caused by the first electrode being suspended during the manufacturing process of the capacitor.

[0082] The insulating layer may include a separation layer 42 and a support layer 40, and the materials of the separation layer 42 and the support layer 40 are different. For example, the separation layer 42 may be made of an oxide material such as silicon oxide, while the support layer 40 may be made of a nitride material such as silicon nitride.

[0083] Continuing to refer to Figure 1B , both sides of the first electrode 61 in the third direction Z are in contact with the support layer 40. Through this arrangement, the first electrode can be clamped by the support layer, avoiding the collapse caused by the first electrode being suspended during the manufacturing process.

[0084] Figure 1B It is also shown that the dimension of the first source / drain 51 along the third direction Z is the same as the dimension of the first electrode 61 along the third direction Z. This reflects that during the manufacturing process, the first electrode replaces the first source / drain, simplifying the formation process of the first electrode.

[0085] There is a metal silicide between the first source / drain 51 and the first electrode 61, and the side of the second source / drain 52 close to the bit line 80 may also include a metal silicide.

[0086] In an exemplary implementation method, the transistors of multiple memory cells arranged along the second direction share a bit line 80.

[0087] As Figure 1C shown, the second electrodes 62 of the capacitors of the memory cells in different layers are interconnected into an integral structure. There is a common connection layer 64 between multiple second electrodes 62, and the common connection layer 64 is connected to the second electrodes 62. In an exemplary implementation method, the capacitor may further include a dielectric layer 63 located between the first electrode 61 and the second electrode 62.

[0088] AsFigure 1D As shown, each of the transistors may further include a gate 72, which is a part of the word line 70, and a gate insulating layer 71 may be provided between the gate 72 and the semiconductor layer 50. From Figure 1D it can be seen that the word line may also at least partially surround the semiconductor layer 50 to form a gate-all-around structure, which is beneficial to improving the control ability of the gate.

[0089] Figure 1D It is also shown that in the extending direction of the word line 70, the semiconductor layers 50 are spaced apart, thereby eliminating the parasitic MOS phenomenon.

[0090] The technical solution of the present application will be further described below through the manufacturing process of a memory according to an exemplary embodiment of the present application. The "lithography process" mentioned in this exemplary embodiment includes depositing a film layer, coating a photoresist, mask exposure, development, etching, stripping the photoresist, etc., which are mature manufacturing processes in the related art. The "lithography process" mentioned in this exemplary embodiment includes coating a film layer, mask exposure, and development, which are mature manufacturing processes in the related art. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, etc., coating can adopt known coating processes, and etching can adopt known methods, which will not be specifically limited here. In the description of this exemplary embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate by using a deposition or coating process. If the "thin film" does not require a lithography process or a lithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" still requires a lithography process or a lithography process during the entire manufacturing process, it is called a "thin film" before the lithography process and a "layer" after the lithography process. The "layer" after the lithography process or the lithography process contains at least one "pattern".

[0091] In an exemplary embodiment, the manufacturing method of the three-dimensional memory of the present application will be described below by taking a three-dimensional DRAM memory as an example.

[0092] S100: Form a stacked structure.

[0093] Exemplary steps may include: providing a substrate 10, and alternately depositing a sacrificial layer thin film and a semiconductor material thin film on the substrate 10 along the third direction Z to form a stacked structure including a sacrificial layer 20 and an initial semiconductor layer 30, as Figure 2A and 2B shown.

[0094] In an exemplary embodiment, methods such as epitaxial growth, chemical vapor deposition, or plasma enhanced chemical vapor deposition (PECVD) can be used to deposit the sacrificial layer film and the semiconductor material film.

[0095] In an exemplary embodiment, the substrate 10 can be a semiconductor substrate, such as a silicon substrate.

[0096] In an exemplary embodiment, the sacrificial layer 20 can be made of SiGe, etc., and SiGe is intrinsically undoped.

[0097] In an exemplary embodiment, the initial semiconductor layer 30 can be made of a semiconductor material, such as silicon. In some exemplary embodiments, the initial semiconductor layer 30 can be Si that is in-situ N-doped, with a doping concentration in the range of 5e 18 cm -3 to 1e 19 cm -3 . In some exemplary embodiments, the initial semiconductor layer 30 can also be Si doped with group V elements (such as phosphorus, arsenic, antimony, etc.).

[0098] Figure 2A and 2B The stacked structure shown in

[0099] can include 3 layers of the sacrificial layer 20 and 3 layers of the initial semiconductor layer 30. In other exemplary embodiments, the stacked structure can also include more or fewer alternately arranged layers of the sacrificial layer and the initial semiconductor layer. Figure 2A and 2B As shown in

[0100] S200: Pattern the stacked structure and form a support layer.

[0101] Exemplary steps may include: etching (which may include anisotropic etching and isotropic etching) the stacked structure to obtain two row trenches T spaced in the second direction Y and extending in the first direction X; then, filling the row trenches T with an insulating material to form an isolation layer 41; finally, processing the stacked structure through a Chemical Mechanical Polishing (CMP) process to make the upper surface of the isolation layer 41 flush with the upper surface of the initial semiconductor layer 30; presetting two support regions 100 in the stacked structure, etching away the sacrificial layer 20 in the support regions 100 to form a plurality of openings; filling these openings with an insulating material to form a plurality of support layers 40 (i.e., within the support regions 100, replacing the material of the sacrificial layer with an insulating material to form the support layer), thereby preventing the initial semiconductor layer 30 in the channel region from collapsing during subsequent processes, such as Figure 3A and 3B shown.

[0102] In this application, by providing the support layer, the initial semiconductor layer can be supported during the process of removing the sacrificial layer, avoiding collapse.

[0103] In an exemplary embodiment, the isolation layer 41 may employ an oxide insulating material, such as SiO2.

[0104] In an exemplary embodiment, the support layer 40 may employ a nitride material, such as SiN.

[0105] S300: Form a separation layer.

[0106] Exemplary steps may include: etching away the material of each sacrificial layer 20 to form a plurality of openings, so that all sides of each initial semiconductor layer 30 outside the support region 100 are exposed; depositing an insulating material thin film into the openings to fill the formed openings, forming a separation layer 42, and making the upper surface of the separation layer 42 flush with the upper surface of the support layer 40 through a CMP process, such as Figure 4A and 4B shown.

[0107] In an exemplary embodiment, the separation layer 42 may also employ an oxide insulating material, such as SiO2.

[0108] In an exemplary embodiment, depositing the insulating material thin film may adopt the Spin on Deposition (SOD) method.

[0109] S400: Form word lines.

[0110] Exemplary steps may include: etching the stacked structure to form a plurality of word line trenches (not shown) extending along the second direction X and penetrating the stacked structure, so as to expose the peripheries of the initial semiconductor layers 30; then growing an insulating material film around the initial semiconductor layers 30 to form a gate insulating layer 71 surrounding the initial semiconductor layers 30, and the region of the initial semiconductor layer 30 surrounded by the gate insulating layer 71 forms a semiconductor layer 50; depositing word line metal by atomic layer deposition to fill each word line trench and cover the surface of the gate insulating layer along the third direction, so as to form a word line 70, and the gate 72 is a part of the word line 70, as Figure 5A and 5B shown.

[0111] In some exemplary embodiments, when depositing the word line metal, the insulating layer between two adjacent initial semiconductors in the third direction may also be replaced with the word line metal, that is, the word line metal covers all side surfaces of the gate insulating layer. It should be noted that the present disclosure does not limit the manner of forming the word line, and other methods known to those skilled in the art may also be used.

[0112] In an exemplary embodiment, the gate insulating layer 71 may be a high-k dielectric layer, that is, a dielectric layer with K≥3.9. The gate insulating layer 71 may be any one or more of silicon oxide, aluminum oxide (Al2O3), hafnium oxide (HfO2).

[0113] In an exemplary embodiment, the word line 70 may be made of metal tungsten W or a composite metal such as TiN / W. For example, the word line 70 may be formed by first depositing TiN metal and then continuously depositing tungsten metal on the TiN metal.

[0114] S500: Form bit lines.

[0115] Exemplary steps may include: disposing a bit line preset region 200 on a side of the support region 100 away from the first direction X; within the bit line preset region 200, etching the stacked structure to form a groove that penetrates the stacked structure and terminates at the upper surface of the substrate 10; depositing an insulating layer film on the substrate 10 until it is flush with the lower surface of the initial semiconductor layer 30 of the first layer, performing bit line sidewall contact region exposure and etching to expose the bit line sidewalls; then, sputtering a metal material along the first direction X, reacting the metal material with a material such as silicon in the initial semiconductor layer 30, and then annealing to form a metal silicide, that is, forming the second source / drain 52 of the first layer; continuing to sputter the bit line metal to form the bit line 80, and back-etching through a CMP process until it is flush with the upper surface of the initial semiconductor layer 30 of the first layer; then, within the bit line preset region 200, depositing an insulating layer film again until it is flush with the lower surface of the initial semiconductor layer 30 of the second layer; then, sputtering a metal material along the first direction X, reacting the metal material with silicon in the initial semiconductor layer 30, and then annealing to form a metal silicide, that is, forming the second source / drain 52 of the second layer; continuing to sputter the metal to form the bit line 80, and back-etching through a CMP process until it is flush with the upper surface of the initial semiconductor layer 30 of the second layer; repeating the foregoing steps to form bit lines 80 extending in the second direction for each layer, as Figure 6 shown.

[0116] In an exemplary embodiment, the metal to be sputtered for the metal silicide may be selected from Ni, Mo, and Co.

[0117] In an exemplary embodiment, when forming the bit line metal by sputtering, TiN may be sputtered first, and then tungsten W metal may be continuously sputtered on the TiN layer to form a composite bit line metal.

[0118] It should be noted that the present disclosure does not limit the manner of forming the bit line, and other methods known to those skilled in the art may also be used.

[0119] S600: Form a first lateral groove.

[0120] Exemplary steps may include: disposing a capacitor preset region 300 on a side of the support region 100 along the first direction X; etching away the material of the isolation layer 41 to reform the row trench T, exposing the side surface of the initial semiconductor layer 30 along the third direction Z, and the row trench T does not expose the bottom substrate 10; within the capacitor preset region 300, laterally etching each initial semiconductor layer 30 by means of the trench to form a first lateral groove S1, and the length of the first lateral groove S1 is consistent with the length of the capacitor preset region 300, as Figure 7A , 7B and shown in 7C.

[0121] In an exemplary embodiment, the length of the first lateral groove S1 may also be greater than the length of the capacitor preset region 300, for example, more towards the transistor side, so that when forming the first electrode of the capacitor subsequently, it can play a role in supporting the first electrode of the capacitor.

[0122] S700: Deposit a material for forming the first electrode of the capacitor.

[0123] Exemplary steps may include: depositing a metal into the first lateral groove S1 by means of the row trench T so as to react with the material of the initial semiconductor layer such as Si to form a silicide (i.e., reduce the contact resistance), and then removing the unreacted metal, thereby forming the first source / drain 51; the deposited metal may be Co; continuing to deposit a metal material into the first lateral groove S1 to fill the first lateral groove S1, and depositing a metal material on the sidewalls of the row trench T along the third direction Z, such as Figure 8A and 8B shown.

[0124] In an exemplary embodiment, a metal may be deposited in the lateral trench by atomic layer deposition.

[0125] In the present application, the first electrode of the capacitor may be formed by depositing a metal on an oxide layer. The oxide layer can absorb the stress during the deposition process, and can better maintain the shape of the capacitor electrode, thereby avoiding affecting the shape of the capacitor electrode due to the large attraction of metal silicides (such as cobalt silicide) in the prior art.

[0126] S800: Form the first electrode of the capacitor.

[0127] Exemplary steps may include: etching away the top of the stacked structure and the metal material at the bottom and sidewalls of the row trench T to form the first electrode 61, such as Figure 9A and 9B shown.

[0128] S900: Form a second lateral groove.

[0129] Exemplary steps may include: etching away the metal material on the sidewalls; within the capacitor preset region 300, laterally etching away the material of the second oxide layer 42 to form a second lateral groove S2 to expose the peripheral wall of the first electrode, such as Figure 10A and 10B shown.

[0130] S1000: Form the second electrode of the capacitor.

[0131] Exemplary steps may include: sequentially depositing a dielectric film and a conductive film covering the first electrode 61 along the exposed peripheral wall of the first electrode, so as to form a second electrode 62 surrounding the first electrode 61 and a dielectric layer 63 located between the first electrode 61 and the second electrode 62, as Figure 11A and 11B shown.

[0132] In an exemplary embodiment, the dielectric film and the conductive film may be deposited by atomic layer deposition.

[0133] In an exemplary embodiment, the dielectric layer 63 may be a high-k dielectric layer, that is, a dielectric layer with K≥3.9. The dielectric layer 63 may be made of one of the following materials: silicon oxide, aluminum oxide (Al2O3), and hafnium oxide.

[0134] In an exemplary embodiment, the materials that the second electrode 62 may adopt include but are not limited to at least one of the following: polysilicon, tungsten, and titanium nitride.

[0135] S1100: Form a common connection layer.

[0136] Exemplary steps may include: depositing a conductive material on the surface of the second electrode 62 to form a common connection layer 64, as Figure 12A and 12B shown.

[0137] An exemplary embodiment of the present application also provides an electronic device, including the storage device provided by the exemplary embodiment of the present application as above.

[0138] In an exemplary embodiment, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.

[0139] Although the disclosed embodiments of the present application are as above, the above content is only an embodiment adopted for the convenience of understanding the present application, and is not intended to limit the present application. Any person skilled in the art within the scope of the present application can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present application. However, the protection scope of the present application shall still be subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, characterized in that, Comprising a substrate and a plurality of stacked memory cells on the substrate at intervals along a third direction perpendicular to the substrate, each layer of memory cells including a plurality of memory cells arranged along a second direction; the memory cells include at least one transistor and at least one capacitor; Wherein the transistor includes a semiconductor layer extending along a first direction and a first source / drain and a second source / drain located on both sides of the semiconductor layer and connected to the semiconductor layer; The capacitor includes a first electrode electrically connected to the first source / drain, and the first electrode comprises a material different from that of the first source / drain; Also included is an insulating layer alternately stacked with the semiconductor layer in the third direction, the first electrode being located between adjacent insulating layers, and the first electrode overlapping with the insulating layer in the first direction; The second direction intersects with the first direction and is parallel to the substrate.

2. The semiconductor device according to claim 1, wherein The insulating layer includes a separating layer and a supporting layer, and the materials of the separating layer and the supporting layer are different.

3. The semiconductor device according to claim 2, wherein, Both sides of the first electrode in the third direction are in contact with the supporting layer.

4. The semiconductor device according to claim 1, wherein The materials of the first source / drain and the second source / drain include single-crystalline silicon; the material of the first electrode includes titanium nitride.

5. The semiconductor device according to claim 1, wherein The size of the first source / drain along the third direction is the same as the size of the first electrode along the third direction.

6. The semiconductor device according to claim 1, wherein Also included is a bit line extending along the second direction; there is a silicide between the first source / drain and the first electrode, and the side of the second source / drain close to the bit line contains silicide.

7. The semiconductor device according to claim 6, wherein The capacitor further includes a second electrode surrounding the first electrode.

8. The semiconductor device according to claim 7, wherein, The first electrode, the second electrode, and the bit line include the same material.

9. The semiconductor device according to claim 7, wherein, The second electrodes of the capacitors of the memory cells in different layers are interconnected into an integral structure.

10. The semiconductor device according to claim 7, wherein, There is a common connection layer between the plurality of second electrodes, and the common connection layer is connected to the second electrodes.

11. The semiconductor device according to claim 1, characterized in that, The transistor further includes a gate and a word line extending along the third direction; the gate is a part of the word line, and a gate insulating layer is included between the gate and the semiconductor layer, and the gate at least partially surrounds the semiconductor layer.

12. The semiconductor device according to claim 6, characterized in that, The transistors of a plurality of memory cells arranged at intervals along the second direction are connected to the same bit line.

13. A method for manufacturing a semiconductor device, characterized in that, Including the following steps: Providing a substrate; Alternately forming a sacrificial layer and an initial semiconductor layer along a third direction perpendicular to the substrate to form a stacked structure, the stacked structure including a bit line preset region, a transistor preset region, and a capacitor preset region arranged along a first direction, the first direction being parallel to the substrate; Forming a semiconductor layer, a first source / drain, a second source / drain, and a word line in the transistor preset region; Forming a bit line in the bit line preset region; In the capacitor preset region, etching away the initial semiconductor layer to form a first lateral groove, and filling the first lateral groove with a conductive material different from the material of the initial semiconductor layer to form a first electrode of the capacitor.

14. The manufacturing method according to claim 13, characterized in that, Also included is: Establishing a support region in the transistor preset region, and replacing the material of each sacrificial layer in the support region with an insulating material to form a support layer; Replace the material of the remaining sacrificial layer with an insulating material to form a separation layer between two adjacent initial semiconductor layers in the third direction.

15. The manufacturing method according to claim 14, characterized in that, Further comprising: Etch away the material of the separation layer to form a second lateral groove to expose the peripheral wall of the first electrode; Deposit a dielectric film and a conductive film covering the first electrode in sequence along the exposed peripheral wall of the first electrode, thereby forming a second electrode surrounding the first electrode and a dielectric layer between the first electrode and the second electrode.

16. The manufacturing method according to claim 15, characterized in that, Further comprising: Deposit a conductive material on the surface of the second electrode to form a common connection layer.

17. An electronic device, characterized in that, Comprising a semiconductor device according to any one of claims 1-12.

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