Semiconductor device

Abstract

A semiconductor device includes: a bit line extending in a first direction on a substrate; a first word line and a second word line extending in the second direction on the bit line, crossing the bit line, and spaced apart from each other in the first direction; and semiconductor patterns spaced apart from each other in a first direction on the bit line with a first word line and a second word line interposed therebetween, where the first word line includes a first portion and a second portion protruding from the first portion and spaced apart from each other in a second direction, and the second word line includes a first portion and a second portion protruding in a direction, one of the semiconductor patterns is interposed between the second portions of the first word lines, and the other of the semiconductor patterns is interposed between the second portions of the second word lines.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices, and more particularly, to semiconductor devices including vertical channel transistors. Background Art

[0002] As semiconductor device dimensions are scaled down, manufacturing techniques that can increase the integration density of semiconductor devices and improve operation speed and production yield are required. Vertical channel transistors can increase the integration density of semiconductor devices and improve the resistance and current drive characteristics of transistors. Summary of the Invention

[0003] The present disclosure provides a semiconductor device having improved electrical characteristics in an oxide semiconductor device having a vertical channel structure.

[0004] In one general aspect, a semiconductor device includes: a substrate; bit lines extending in a first direction on the substrate; a first word line and a second word line, extending in a second direction on the bit lines, crossing the bit lines, and spaced apart from each other in the first direction, the first direction and the second direction being parallel to the upper surface of the substrate and intersecting each other; and semiconductor patterns spaced apart from each other in the first direction on the bit lines and the first word line and the second word line being interposed therebetween, wherein the first word line includes a first portion extending in the second direction and a second portion protruding from the first portion in the first direction and spaced apart from each other in the second direction, the second word line includes a first portion extending in the second direction and a second portion protruding in a direction opposite to the first direction, one of the semiconductor patterns being interposed between the second portions of the first word line, and the other of the semiconductor patterns being interposed between the second portions of the second word line.

[0005] In another general aspect, a semiconductor device includes: a substrate; bit lines extending in a first direction on the substrate and spaced apart from each other in a second direction, the first direction and the second direction being parallel to the upper surface of the substrate and intersecting each other; a first word line crossing the bit lines and including a first portion extending in the second direction and a second portion protruding from the first portion in the first direction and spaced apart from each other in the second direction; and semiconductor patterns respectively disposed on the bit lines, wherein each semiconductor pattern includes a first vertical portion extending in a direction perpendicular to the upper surface of the substrate, the first vertical portion of the semiconductor pattern being interposed between the second portions of the first word line, and the second portions of the first word line and the first vertical portions of the semiconductor pattern being alternately arranged in the second direction.

[0006] In another general aspect, a semiconductor device includes: a substrate; bit lines extending in a first direction on the substrate; a support insulating layer on the bit lines; a first word line and a second word line intersecting the bit lines on the support insulating layer; semiconductor patterns disposed on the bit lines and spaced apart from each other in the first direction with the support insulating layer, the first word line, and the second word line interposed therebetween; a first gate insulating layer between one of the semiconductor patterns and an outer wall of the first word line; and a second gate insulating layer between the other of the semiconductor patterns and an outer wall of the second word line, wherein the first word line includes a first portion extending in a second direction parallel to an upper surface of the substrate and intersecting the first direction and a second portion protruding in the first direction, the second word line includes a first portion extending in the second direction and a second portion protruding in a direction opposite to the first direction, the one of the semiconductor patterns is disposed between the second portions of the first word line, and the other of the semiconductor patterns is disposed between the second portions of the second word line. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of an example of a semiconductor device.

[0008] Figure 2 and Figure 3 is a schematic perspective view of an example of a semiconductor device.

[0009] Figure 4 is a top view of an example of a semiconductor device.

[0010] Figure 5A is a cross-sectional view taken along line A-A' of Figure 4

[0011] Figure 5B is a cross-sectional view taken along line B-B' of Figure 4

[0012] Figure 5C is a cross-sectional view taken along line C-C' of Figure 4

[0013] Figures 6 to 21C is a view for explaining an example of a method of manufacturing a semiconductor device.

[0014] Figures 22 to 28 is a cross-sectional view of an example of a semiconductor device. DETAILED DESCRIPTION

[0015] Figure 1 is a block diagram of an example of a semiconductor device.

[0016] Referring to Figure 1 , the semiconductor memory device includes a memory cell array 1, a row decoder 2, a sense amplifier 3, a column decoder 4, and a control logic 5.​​​

[0017] The memory cell array 1 may include a plurality of memory cells MC arranged in a two-dimensional or three-dimensional manner. Each memory cell MC may be provided between word lines WL and bit lines BL that are cross-set with each other and connected to the word lines WL and bit lines BL that are cross-set with each other.

[0018] Each memory cell MC may include a selection element TR and a data storage element DS. The selection element TR and the data storage element DS may be electrically connected to each other. The selection element TR may be connected to both the word line WL and the bit line BL. That is, the selection element TR may be provided at the point where the word line WL and the bit line BL intersect each other.

[0019] The selection element TR may include a field effect transistor FET. The data storage element DS may include a capacitor, a magnetic tunnel junction pattern, or a variable resistor. As an example, the selection element TR may include a transistor whose gate electrode is connected to the word line WL, and whose drain / source terminals are connected to the bit line BL and the data storage element DS, respectively.

[0020] The row decoder 2 may be configured to decode address information input from the outside and select one of the word lines WL of the memory cell array 1 based on the decoded address information. The address information decoded by the row decoder 2 may be provided to the row driver, and in this case, in response to the control of the control circuit, the row driver may supply corresponding voltages to the selected one of the word lines WL and the unselected word lines in the word lines WL.

[0021] The sense amplifier 3 may be configured to sense, amplify, and output the voltage difference between a bit line selected based on the address information decoded by the column decoder 4 in the bit line BL and a reference bit line.

[0022] The column decoder 4 may provide a data transmission path between the sense amplifier 3 and an external device (for example, a memory controller). The column decoder 4 may be configured to decode address information input from the outside and select one of the bit lines BL based on the decoded address information.

[0023] The control logic 5 may be configured to generate a control signal for controlling the data write or read operation of the memory cell array 1.

[0024] Figure 2 and Figure 3 is a schematic perspective view of a semiconductor device.

[0025] Referring to Figure 2 and Figure 3 , the semiconductor memory device may include a peripheral circuit structure PS on a semiconductor substrate and a cell array structure CS on the peripheral circuit structure PS.

[0026] The peripheral circuit structure PS may include a core and peripheral circuits formed on a substrate SUB. The core and peripheral circuits may include the row decoder 2 and column decoder 4, sense amplifiers 3, and control logic 5 described with reference to Figure 1 .

[0027] The cell array structure CS may include a memory cell array 1 (e.g., see Figure 1 ), where the memory cell array 1 includes memory cells MC (e.g., see Figure 1 ) arranged two-dimensionally or three-dimensionally on a plane parallel to two different directions (e.g., a first direction D1 and a second direction D2). As described above, each memory cell MC (e.g., see Figure 1 ) may include a selection element TR and a data storage element DS.

[0028] In some implementations, a vertical channel transistor (VCT) may be provided as the selection element TR of each memory cell MC (e.g., see Figure 1 ). The vertical channel transistor may include a channel whose longitudinal direction is perpendicular to the upper surface of the substrate SUB. A capacitor may be provided as the data storage element DS of each memory cell MC (e.g., see Figure 1 ).

[0029] In Figure 2 , the peripheral circuit structure PS may be provided on the substrate SUB, and the cell array structure CS may be provided on the peripheral circuit structure PS.

[0030] In Figure 3 , the peripheral circuit structure PS may be provided on a first substrate SUB1, and the cell array structure CS may be provided on a second substrate SUB2. The first substrate SUB1 and the second substrate SUB2 may face each other.

[0031] A first metal pad LMP may be provided at the uppermost part of the peripheral circuit structure PS. The first metal pad LMP may be electrically connected to the core and peripheral circuits 2, 3, 4, and 5 (e.g., in Figure 1 ).

[0032] A second metal pad UMP may be provided at the lowermost part of the cell array structure CS. The second metal pad UMP may be electrically connected to the memory cell array 1 (e.g., in Figure 1 ). The second metal pad UMP may be in direct contact with and bonded to the first metal pad LMP of the peripheral circuit structure PS.

[0033] Figure 4 is a top view of an example of a semiconductor device. Figure 5A is a cross-sectional view taken along line A - A' of Figure 4 .Figure 5B is a cross-sectional view taken along line B-B' of Figure 4 . Figure 5C is a cross-sectional view taken along line C-C' of Figure 4 .

[0034] Referring to Figure 4 and Figures 5A to 5C , a first lower insulating layer 110 is provided on a substrate 100. The substrate 100 may have a shape of a plate extending along a plane defined by a first direction D1 and a second direction D2. In the present specification, the first direction D1 and the second direction D2 may be directions parallel to the upper surface 100a of the substrate 100 and intersecting with each other. A third direction D3 may be a direction perpendicular to the upper surface 100a of the substrate 100. For example, the first direction D1, the second direction D2, and the third direction D3 may be directions orthogonal to each other. The substrate 100 may be a semiconductor substrate (e.g., a silicon substrate, a germanium substrate, and / or a silicon germanium substrate). The first lower insulating layer 110 may include an insulating material. As an example, the first lower insulating layer 110 may include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0035] In some implementations, the peripheral circuit structure PS described with reference to Figure 2 may be provided between the substrate 100 and the first lower insulating layer 110. In some implementations, an integrated circuit such as a logic element may be provided between the substrate 100 and the first lower insulating layer 110.

[0036] A second lower insulating layer 120 may be provided on the first lower insulating layer 110. A plurality of bit lines BL may be provided in the second lower insulating layer 120. The bit lines BL may extend in the first direction D1 and be spaced apart from each other in the second direction D2.

[0037] The bit lines BL may include a conductive material. For example, the bit lines BL may be formed of a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal (e.g., tungsten, titanium, tantalum, etc.), or a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). The bit lines BL may be a single conductive layer or a plurality of conductive layers. The second lower insulating layer 120 may include an insulating material. As an example, the second lower insulating layer 120 may include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0038] The semiconductor pattern SP may be disposed on the bit line BL. The semiconductor patterns SP may be arranged to be spaced apart from each other in a first direction D1 and a second direction D2. A plurality of semiconductor patterns SP may be disposed on one bit line BL. The plurality of semiconductor patterns SP disposed on one bit line BL may be arranged in the first direction D1. The semiconductor patterns SP may be respectively disposed on a plurality of bit lines BL spaced apart from each other in the second direction D2. The semiconductor patterns SP disposed on each of the plurality of bit lines BL may be arranged in the second direction D2.

[0039] The semiconductor pattern SP may include a horizontal portion HC and a vertical portion VC. The horizontal portion HC may be disposed on the upper surface of the bit line BL. The horizontal portion HC may extend in the first direction D1. The vertical portion VC may have a first vertical portion V1 and a second vertical portion V2 facing each other in the first direction D1. The horizontal portion HC may be adjacent to the lower portions of the first vertical portion V1 and the second vertical portion V2, and connect the first vertical portion V1 and the second vertical portion V2. The vertical portion VC may extend in a direction perpendicular to the upper surface 100a of the substrate 100 (e.g., a third direction D3).

[0040] Each vertical portion VC of the semiconductor pattern SP may include an inner wall SPi and an outer wall SPo facing each other in the first direction D1. The inner walls SPi of the vertical portion VC may face each other. The horizontal portion HC of the semiconductor pattern SP may be adjacent to the lower portions of the first vertical portion V1 and the second vertical portion V2, and may connect the inner wall SPi of the first vertical portion V1 and the inner wall SPi of the second vertical portion V2.

[0041] The semiconductor pattern SP may include a semiconductor material. As an example, the semiconductor pattern SP may include an oxide semiconductor material, and the oxide semiconductor material may include at least one of, for example, InGaZnO, InGaSiO, InSnZnO, InZnO, ZnO, ZnSnO, ZnON, ZrZnSnO, SnO, HfInZnO, GaZnSnO, AlZnSnO, YbGaZnO, or InGaO. In some implementations, the semiconductor pattern SP may be a multi-layer including a plurality of material layers. In some implementations, the semiconductor pattern SP may include a two-dimensional material.

[0042] The gate structure GST can be disposed on the bit line BL and the second lower insulating layer 120. A plurality of gate structures GST can be provided. The gate structure GST can extend in the second direction D2. The gate structures GST can be arranged to be spaced apart from each other in the first direction D1. The semiconductor patterns SP can be arranged to be spaced apart from each other in the second direction D2 between the gate structures GST adjacent to each other in the first direction D1. The semiconductor patterns SP adjacent to each other in the first direction D1 can be spaced apart from each other and the gate structure GST is interposed therebetween.

[0043] Each gate structure GST can include a support insulating layer 10, a first word line WL1, a second word line WL2, a first gate insulating layer GI1, a second gate insulating layer GI2, a third gate insulating layer GI3, and a gate covering layer GP.

[0044] The support insulating layer 10 can be disposed on the bit line BL and can be in contact with the upper surface of the bit line BL. The support insulating layer 10 can extend in the second direction D2. The lower surface of the support insulating layer 10 can be coplanar with the lower surface of the horizontal portion HC of the semiconductor pattern SP. The horizontal portion HC of the semiconductor pattern SP can be disposed between the support insulating layers 10 adjacent to each other in the first direction D1. The support insulating layer 10 can include an insulating material. The support insulating layer 10 can include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0045] The first word line WL1 and the second word line WL2 can be disposed on the support insulating layer 10. The lower surface of the first word line WL1 and the lower surface of the second word line WL2 can be in contact with the upper surface of the support insulating layer 10. The first word line WL1 and the second word line WL2 can be spaced apart from each other in the first direction D1. The first word line WL1 and the second word line WL2 can extend in the second direction D2 and can cross the bit line BL.

[0046] The first word line WL1 can include a first portion WL1a extending in the second direction D2 and a second portion WL1b protruding from the first portion WL1a in the first direction D1 and spaced apart from each other in the second direction D2. The second word line WL2 can include a first portion WL2a extending in the second direction D2 and a second portion WL2b protruding from the first portion WL2a in the direction opposite to the first direction D1 and spaced apart from each other in the second direction D2.

[0047] Each second portion WL1b of the first word line WL1 may include a first sidewall S11 and a second sidewall S12 facing each other in a second direction D2, and a third sidewall S13 extending in the second direction D2 between the first sidewall S11 and the second sidewall S12. Each second portion WL2b of the second word line WL2 may include a first sidewall S21 and a second sidewall S22 facing each other in the second direction D2, and a third sidewall S23 extending in the second direction D2 between the first sidewall S21 and the second sidewall S22.

[0048] Each first vertical portion V1 of the semiconductor pattern SP may be disposed between second portions WL1b of the first word line WL1. Specifically, the first vertical portions V1 of the semiconductor pattern SP disposed on a plurality of bit lines BL spaced apart from each other in the second direction D2 may be respectively disposed between second portions WL1b of the first word line WL1. The first vertical portion V1 of each semiconductor pattern SP and the second portion WL1b of the first word line WL1 may be alternately arranged in the second direction D2. The third sidewall S13 of the second portion WL1b of the first word line WL1 and the outer wall SPo of each first vertical portion V1 of the semiconductor pattern SP may be offset from each other in a first direction D1. The first vertical portion V1 of the semiconductor pattern SP may be interposed between second portions WL1b of the first word line WL1 adjacent to each other in the second direction D2. When observed in a top view, the third sidewall S13 of the second portion WL1b of the first word line WL1 and the outer wall SPo of each first vertical portion V1 of the semiconductor pattern SP may be arranged in a zigzag pattern in the second direction D2.

[0049] Each second vertical portion V2 of the semiconductor pattern SP may be disposed between second portions WL2b of the second word line WL2. Specifically, the second vertical portions V2 of the semiconductor pattern SP respectively disposed on a plurality of bit lines BL spaced apart from each other in the second direction D2 may be respectively disposed between second portions WL2b of the second word line WL2. The second vertical portion V2 of each semiconductor pattern SP and the second portion WL2b of the second word line WL2 may be alternately arranged in the second direction D2. The third sidewall S23 of the second portion WL2b of the second word line WL2 and the outer wall SPo of each second vertical portion V2 of the semiconductor pattern SP may be offset from each other in a first direction D1. The second vertical portion V2 of the semiconductor pattern SP may be interposed between second portions WL2b of the second word line WL2 adjacent to each other in the second direction D2. When observed in a top view, the third sidewall S23 of the second portion WL2b of the second word line WL2 and the outer wall SPo of each second vertical portion V2 of the semiconductor pattern SP may be arranged in a zigzag pattern in the second direction D2.

[0050] The gate structure GST can be disposed between semiconductor patterns SP adjacent to each other along a first direction D1. Specifically, semiconductor patterns SP disposed on a single bit line BL and adjacent to each other in the first direction D1 can be spaced apart from each other in the first direction, and a support insulating layer 10, a first word line WL1, a second word line WL2, a first gate insulating layer GI1, a second gate insulating layer GI2, a third gate insulating layer GI3, and a gate covering layer GP are interposed therebetween. For example, one of the semiconductor patterns SP can be disposed between second portions WL1b of the first word line WL1, and another one of the semiconductor patterns SP can be disposed between second portions WL2b of the second word line WL2. A first vertical portion V1 of one of the semiconductor patterns SP can be disposed between second portions WL1b of the first word line WL1. A second vertical portion V2 of another one of the semiconductor patterns SP can be disposed between second portions WL2b of the second word line WL2.

[0051] The first word line WL1 and the second word line WL2 can include a conductive material. For example, the first word line WL1 and the second word line WL2 can include at least one of a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal (e.g., tungsten, titanium, tantalum, etc.), and a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0052] The first word line WL1 can include an inner wall IS1 and an outer wall OS1 facing each other in the first direction D1. For example, the inner wall IS1 of the first word line WL1 can be a sidewall where the second portion WL1b of the first word line WL1 is not disposed. When observed in a top view, the inner wall IS1 of the first word line WL1 can extend linearly in a second direction D2. The outer wall OS1 of the first word line WL1 can be another sidewall where the second portion WL1b of the first word line WL1 is disposed. When observed in a top view, the outer wall OS1 of the first word line WL1 can extend in a winding shape in the second direction D2. Specifically, the outer wall OS1 of the first word line WL1 can include first to third sidewalls S11, S12, and S13 of the second portion WL1b of the first word line WL1. In addition, the outer wall OS1 of the first word line WL1 can include a sidewall of the first portion WL1a of the first word line WL1, which connects the second portion WL1b in the second direction D2 and is between second portions WL1b adjacent to each other in the second direction D2.

[0053] The second word line WL2 may include an inner wall IS2 and an outer wall OS2 facing each other in a first direction D1. For example, the inner wall IS2 of the second word line WL2 may be a side wall where the second part WL2b of the second word line WL2 is not provided. When observed in a top view, the inner wall IS2 of the second word line WL2 may extend linearly in a second direction D2. The outer wall OS2 of the second word line WL2 may be another side wall where the second part WL2b of the second word line WL2 is provided. When observed in a top view, the outer wall OS2 of the second word line WL2 may extend in a bent shape in the second direction D2. Specifically, the outer wall OS2 of the second word line WL2 may include first to third side walls S21, S22, and S23 of the second part WL2b of the second word line WL2. In addition, the outer wall OS2 of the second word line WL2 may include a side wall of the first part WL2a of the second word line WL2, which connects the second part WL2b in the second direction D2 and is between the second parts WL2b adjacent to each other in the second direction D2.

[0054] The inner wall IS1 of the first word line WL1 and the inner wall IS2 of the second word line WL2 may face each other. The semiconductor pattern SP may not exist between the inner wall IS1 of the first word line WL1 and the inner wall IS2 of the second word line WL2.

[0055] The first gate insulating layer GI1 may be interposed between the outer wall OS1 of the first word line WL1 and a first vertical portion V1 of the corresponding semiconductor pattern SP. The first gate insulating layer GI1 may be in contact with the outer wall OS1 of the first word line WL1 and the first vertical portion V1 of the semiconductor pattern SP. The first vertical portion V1 of the semiconductor pattern SP may be spaced apart from the first word line WL1, and the first gate insulating layer GI1 is interposed therebetween. When observed in a top view, the first gate insulating layer GI1 may extend in a bent shape in the second direction D2. When observed in a top view, the first gate insulating layer GI1 may have a shape conformally surrounding the outer wall OS1 of the first word line WL1. Specifically, the first gate insulating layer GI1 may include an inner part GI1a in contact with the outer wall SPo of the first vertical portion V1, an outer part GI1b in contact with a third side wall S13 of the second part WL1b of the first word line WL1, and a connecting portion GI1c connecting the inner part GI1a and the outer part GI1b. The first vertical portion V1 of the semiconductor pattern SP may be spaced apart from the first word line WL1 through the inner part GI1a and the connecting portion GI1c of the first gate insulating layer GI1. The lower surface of the first gate insulating layer GI1 may be in contact with the upper surface of the support insulating layer 10.

[0056] The second gate insulating layer GI2 may be interposed between the outer wall OS2 of the second word line WL2 and the second vertical portion V2 of the corresponding semiconductor pattern SP. The second gate insulating layer GI2 may be in contact with the outer wall OS2 of the second word line WL2 and the second vertical portion V2 of the semiconductor pattern SP. The second vertical portion V2 of the semiconductor pattern SP may be spaced apart from the second word line WL2, and the second gate insulating layer GI2 is therebetween. When observed in a top view, the second gate insulating layer GI2 may extend in a bent shape in the second direction D2. When observed in a top view, the second gate insulating layer GI2 may have a shape that conformally surrounds the outer wall OS2 of the second word line WL2. Specifically, the second gate insulating layer GI2 may include an inner portion GI2a in contact with the outer wall SPo of the second vertical portion V2, an outer portion GI2b in contact with the third sidewall S23 of the second portion WL2b of the second word line WL2, and a connecting portion GI2c connecting the inner portion GI2a and the outer portion GI2b. Each second vertical portion V2 of the semiconductor pattern SP may be spaced apart from the second word line WL2 through the inner portion GI2a and the connecting portion GI2c of the second gate insulating layer GI2. The lower surface of the second gate insulating layer GI2 may be in contact with the upper surface of the support insulating layer 10.

[0057] The third gate insulating layer GI3 may be disposed on the inner wall IS1 of the first word line WL1 and the inner wall IS2 of the second word line WL2. The third gate insulating layer GI3 may extend in the second direction D2. The third gate insulating layer GI3 may include a vertical portion GI3v and a horizontal portion GI3h. The vertical portions GI3v of the third gate insulating layer GI3 may face each other in the first direction D1. The vertical portions GI3v of the third gate insulating layer GI3 may be in contact with the inner wall IS1 of the first word line WL1 and the inner wall IS2 of the second word line WL2, respectively. The horizontal portion GI3h of the third gate insulating layer GI3 may be adjacent to the lower portion of the vertical portion GI3v and connect the vertical portions GI3v. The horizontal portion GI3h of the third gate insulating layer GI3 may be in contact with the upper surface of the support insulating layer 10. The first word line WL1, the second word line WL2, and the third gate insulating layer GI3 may be provided between the first gate insulating layer GI1 and the second gate insulating layer GI2.

[0058] The first to third gate insulating layers GI1, GI2, and GI3 may include at least one of silicon oxide, silicon oxynitride, and a high-k material having a dielectric constant higher than that of silicon oxide. The high-k material may include metal oxide or metal oxynitride. For example, the high-k materials that can be used as the first to third gate insulating layers GI1, GI2, and GI3 may include at least one of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, and Al2O3, but are not limited thereto.

[0059] The gate covering layer GP can be provided over the first word line WL1 and the second word line WL2, and the first to third gate insulating layers GI1, GI2, and GI3. The lower surface of the gate covering layer GP can be in contact with the upper surfaces of the first word line WL1 and the second word line WL2, and the upper surfaces of the first to third gate insulating layers GI1, GI2, and GI3. The upper surfaces of the first word line WL1 and the second word line WL2, and the upper surfaces of the first to third gate insulating layers GI1, GI2, and GI3 can be coplanar. The height of the upper surfaces of the first word line WL1 and the second word line WL2, and the upper surfaces of the first to third gate insulating layers GI1, GI2, and GI3 can be lower than the height of the upper surface of the vertical portion VC of the semiconductor pattern SP. In this specification, the height can be the height measured in the third direction D3 from the upper surface 100a of the substrate 100.

[0060] The sidewall of the gate covering layer GP can be coplanar with the sidewall of the first gate insulating layer GI1 or the sidewall of the second gate insulating layer GI2. The sidewall of the gate covering layer GP can be in contact with the vertical portion VC of the semiconductor pattern SP. The gate covering layer GP can include an insulating material. As an example, the gate covering layer GP can include silicon nitride.

[0061] The cell insulating layer 200 can be disposed in the gate structure GST. The cell insulating layer 200 can be disposed between the first word line WL1 and the second word line WL2. The cell insulating layer 200 can be surrounded by the third gate insulating layer GI3 of the gate structure GST and the gate covering layer GP. The lower surface of the cell insulating layer 200 can be in contact with the upper surface of the horizontal portion GI3h of the third gate insulating layer GI3. The upper surface of the cell insulating layer 200 can be in contact with the lower surface of the gate covering layer GP.

[0062] The cell insulating layer 200 can include a low-k material. The low dielectric material can include an insulating material having a dielectric constant lower than that of the materials included in the first to third gate insulating layers GI1, GI2, and GI3, the support insulating layer 10, and the gate covering layer GP. As an example, the cell insulating layer 200 can include an insulating material having a dielectric constant (k) of about 2.5 or less than 2.0, such as porous SiOC.

[0063] The insulating pattern 210 may be interposed between gate structures GST adjacent to each other along the first direction D1. The insulating pattern 210 may be disposed on semiconductor patterns SP respectively disposed on bit lines BL and may be spaced apart from each other in the first direction D1. The insulating pattern 210 may be in contact with the upper surface of the horizontal portion HC of the semiconductor pattern SP and the inner wall SPi of the vertical portion V1. The insulating pattern 210 may extend in the second direction D2 and may cross the bit line BL. The insulating patterns 210 may be spaced apart from each other in the first direction D1. The insulating pattern 210 may include an insulating material. As an example, the insulating pattern 210 may include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0064] A landing pad LP may be provided on the semiconductor pattern SP. The landing pad LP may be connected to the upper surface of the vertical portion VC of the semiconductor pattern SP. The landing pad LP may be spaced apart from the first to third gate insulating layers GI1, GI2, and GI3. The landing pad LP may include at least one of conductive materials. For example, the landing pad LP may be formed of a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal (e.g., tungsten, titanium, tantalum, etc.), and a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0065] A separation insulating pattern INP may be provided between the landing pads LP. The separation insulating pattern INP may be provided on the gate cover layer GP. The separation insulating pattern INP may separate the landing pads LP. The separation insulating pattern INP may include an insulating material. In some implementations, the separation insulating pattern INP may be a multi-layer including a plurality of insulating layers.

[0066] Data storage patterns DSP may be respectively connected to the landing pads LP. The data storage patterns DSP may be electrically connected to the semiconductor pattern SP through the landing pads LP.

[0067] In some implementations, the data storage pattern DSP may be a capacitor. In this case, the data storage pattern DSP may include a lower electrode, an upper electrode, and a capacitor dielectric layer interposed therebetween. In this case, when viewed in a top view, the lower electrode may be in contact with the landing pad LP, and the lower electrode may have various shapes such as circular, oval, rectangular, square, rhombic, or hexagonal.

[0068] Additionally or alternatively, the data storage pattern DSP may be a variable resistance pattern, which may switch between two resistance states by an electrical pulse applied to the storage element. For example, the data storage pattern DSP may include a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material, whose crystal state changes according to the amount of current.

[0069] An oxide semiconductor having a vertical channel structure may have a transistor form, in which an overlapping region between a semiconductor pattern SP and a word line is relatively small. Accordingly, a region of a channel that can be controlled by a gate may be relatively small, and as a result, there is a problem in that electrical characteristics of a semiconductor device deteriorate.

[0070] Advantageously, the word line may surround a vertical portion VC of the semiconductor pattern SP on three sides. The vertical portion VC of the semiconductor pattern SP may be interposed between a second portion WL1b of a first word line WL1 and a second portion WL2b of a second word line WL2. That is, the semiconductor pattern SP may have a structure in which the word lines WL1 and WL2 surround side surfaces of a channel. Accordingly, an overlapping region between the semiconductor pattern SP and the word line may be increased, and as a result, a region of a channel that can be controlled by a gate may be increased. Accordingly, a semiconductor device having improved electrical characteristics may be provided.

[0071] In addition, a cell insulating layer 200 including a low-k material may be disposed between the first word line WL1 and the second word line WL2. Accordingly, a parasitic capacitance between the first word line WL1 and the second word line WL2 may be reduced, and characteristics of a semiconductor device may be improved. In addition, electrical interference may be reduced, thereby improving integration of wirings.

[0072] Figures 6 to 21C are views for illustrating an example of a method of manufacturing a semiconductor device. For simplicity of description, a repeated description of elements described above is omitted.

[0073] Referring to Figure 6 and Figures 7A to 7C , a first lower insulating layer 110 may be formed on a substrate 100. A second lower insulating layer 120 may be formed on the first lower insulating layer 110. A bit line BL may be formed in the second lower insulating layer 120. Forming the bit line BL may include, for example, forming a mask pattern (not shown) on the second lower insulating layer 120, patterning the second lower insulating layer 120 using the mask pattern as an etch mask pattern to form a trench (not shown), and filling the trench to form the bit line BL.

[0074] An initial support insulating layer 10L may be formed on the bit line BL and the second lower insulating layer 120. The initial support insulating layer 10L may be formed using at least one of physical vapor deposition (PVD), thermal chemical vapor deposition (thermal CVD), low pressure chemical vapor deposition (LP-CVD), plasma enhanced chemical vapor deposition (PE-CVD), and atomic layer deposition (ALD) techniques.

[0075] Referring to Figures 8A to 8C , a word line layer WLL may be formed on the initial support insulating layer 10L. The word line layer WLL may include a conductive material.

[0076] Referring to Figure 9 , Figure 10A and Figure 10B , the first word line WL1 and the second word line WL2 can be formed on the initial support insulating layer 10L. For example, forming the first word line WL1 and the second word line WL2 can include forming a mask pattern (not shown) on the word line layer WLL, patterning the word line layer WLL using the mask pattern as an etching mask pattern, and removing the mask pattern.

[0077] Referring to Figures 11A to 11C , the initial gate insulating layer GIL can be formed. The initial gate insulating layer GIL can be conformally formed on the initial support insulating layer 10L, the first word line WL1, and the second word line WL2. The initial gate insulating layer GIL can be formed using a layer deposition technique with good step coverage (such as physical vapor deposition (PVD), thermal chemical vapor deposition (thermal CVD), low-pressure chemical vapor deposition (LP-CVD), plasma-enhanced chemical vapor deposition (PE-CVD), and atomic layer deposition (ALD)).

[0078] Referring to Figure 12 and Figures 13A to 13C , the first sacrificial layer 20, the second sacrificial layer 21, the initial gate insulating pattern GIP, and the third gate insulating layer GI3 can be formed. The first sacrificial layer 20 can be formed on the third gate insulating layer GI3. The second sacrificial layer 21 can be formed on the initial gate insulating pattern GIP. The first sacrificial layer 20 and the second sacrificial layer 21 can be alternately arranged in the first direction D1. For example, forming the first sacrificial layer 20, the second sacrificial layer 21, the initial gate insulating pattern GIP, and the third gate insulating layer GI3 can include, for example, forming an initial sacrificial layer (not shown) on the initial gate insulating layer GIL and planarizing the upper part of the initial sacrificial layer and the upper part of the initial gate insulating layer GIL until the upper surfaces of the first word line WL1 and the second word line WL2 are exposed. For example, the planarization can be performed by a chemical mechanical polishing (CMP) process or an etch-back process.

[0079] The upper part of the initial gate insulating layer GIL can be removed to divide the initial gate insulating layer GIL into the initial gate insulating pattern GIP and the third gate insulating layer GI3. The upper part of the initial sacrificial layer can be removed to divide the initial sacrificial layer into the first sacrificial layer 20 and the second sacrificial layer 21. The first sacrificial layer 20 and the second sacrificial layer 21 can include an insulating material. As an example, the first sacrificial layer 20 and the second sacrificial layer 21 can include a low-k material.

[0080] Referring to Figures 14A to 14C, an initial gate overlay GPL can be formed. The initial gate overlay GPL can cover the first sacrificial layer 20 and the second sacrificial layer 21, the third gate insulating layer GI, the initial gate insulating pattern GIP, and the first word line WL1 and the second word line WL2.

[0081] Referring to Figure 15A and Figure 15B , a gate overlay GP, a first gate insulating layer GI1, a second gate insulating layer GI2, and a support insulating layer 10 can be formed. For example, forming the gate overlay GP, the first gate insulating layer GI1, the second gate insulating layer GI2, and the support insulating layer 10 can include, for example, forming a mask pattern (not shown) on the initial gate overlay GPL, using the mask pattern as an etch mask to sequentially etch the initial gate overlay GPL, the initial gate insulating pattern GIP, and the initial support insulating layer 10L, and removing the mask pattern.

[0082] The initial gate overlay GPL can be patterned and divided into the gate overlay GP. The initial gate insulating pattern GIP can be patterned and divided into the first gate insulating layer GI1 and the second gate insulating layer GI2. The initial support insulating layer 10L can be patterned and divided into the support insulating layer 10. The initial support insulating layer 10L can be patterned to expose the upper surface of the bit line BL and the upper surface of the second lower insulating layer 120.

[0083] Before or simultaneously with patterning the initial gate insulating pattern GIP, the second sacrificial layer 21 on the initial gate insulating pattern GIP can be removed. The first sacrificial layer 20 can remain on the third gate insulating layer GI3. The first sacrificial layer 20 remaining on the third gate insulating layer GI3 can be referred to as the cell insulating layer 200.

[0084] Referring to Figures 16A to 16C , a first semiconductor layer SL1 can be formed. The first semiconductor layer SL1 can be conformally formed on the second lower insulating layer 120, the bit line BL, the first to third gate insulating layers GI1, GI2, and GI3, the support insulating layer 10, and the gate overlay GP. For example, the first semiconductor layer SL1 can be formed using a layer deposition technique with good step coverage (such as physical vapor deposition (PVD), thermal chemical vapor deposition (thermal CVD), low pressure chemical vapor deposition (LP-CVD), plasma enhanced chemical vapor deposition (PE-CVD), and atomic layer deposition (ALD)).

[0085] Referring to Figures 17A to 17C , a third sacrificial layer 30 can be formed on the first semiconductor layer SL1. The third sacrificial layer 30 can include an insulating material. As an example, the third sacrificial layer 30 can include spin-on hard mask (SOH).

[0086] Referring to Figures 18A to 18C, a fourth sacrificial layer 40 and a second semiconductor layer SL2 can be formed. For example, forming the fourth sacrificial layer 40 and the second semiconductor layer SL2 can include planarizing the upper portions of the third sacrificial layer 30 and the first semiconductor layer SL1 until the upper surface of the gate covering layer GP is exposed. The planarization can be performed, for example, by a chemical mechanical polishing (CMP) process or an etch-back process.

[0087] The upper portion of the third sacrificial layer 30 can be removed and divided into the fourth sacrificial layer 40. The fourth sacrificial layer 40 can be spaced apart from each other in the first direction D1 and can extend in the second direction D2. The upper portion of the first semiconductor layer SL1 can be removed and divided into the second semiconductor layer SL2.

[0088] Referring to Figure 19 、 Figure 20A and Figure 20B , a semiconductor pattern SP can be formed. For example, forming the semiconductor pattern SP can include forming a mask pattern (not shown) that vertically overlaps with the bit line BL, sequentially etching the exposed fourth sacrificial layer 40 and the second semiconductor layer SL2 using the mask pattern as an etch mask, removing the mask pattern, and removing the remaining portion of the fourth sacrificial layer 40.

[0089] Referring to Figures 21A to 21C , an insulating pattern layer 210L can be formed. The insulating pattern layer 210L can cover the semiconductor pattern SP, the gate covering layer GP, and the second lower insulating layer 120.

[0090] Referring again to Figure 4 and Figures 5A to 5C , the upper portion of the insulating pattern layer 210L can be removed to form an insulating pattern 210. Removing the upper portion of the insulating pattern layer 210L can include, for example, planarizing the insulating pattern layer 210L until the upper surface of the gate covering layer GP is exposed.

[0091] A landing pad LP and a separation insulating pattern INP can be formed. The landing pad LP can fill the empty space formed by removing the upper portion of the semiconductor pattern SP. A data storage pattern DSP connected to the landing pad LP can be formed.

[0092] In some implementations, when the first to third gate insulating layers GI1, GI2, and GI3 are protected by the insulating pattern 210 and the semiconductor pattern SP, damage to the first to third gate insulating layers GI1, GI2, and GI3 can be prevented or limited during the formation of the landing pad LP.

[0093] In some implementations, after forming the first word line WL1 and the second word line WL2, the first to third gate insulating layers GI1, GI2, and GI3 can be formed, thereby preventing or limiting damage to the gate insulating layers GI1, GI2, and GI3.

[0094] In some implementations, since the first to third gate insulating layers GI1, GI2, and GI3 are formed by a single deposition process, the number of interfaces of the first to third gate insulating layers GI1, GI2, and GI3 can be relatively small, and the reliability of the first to third gate insulating layers GI1, GI2, and GI3 can be improved.

[0095] Figures 22 to 28 is a cross-sectional view of a semiconductor device. To simplify the description, the content repeated above is omitted.

[0096] Referring to Figure 22 , in some implementations, the cell insulating layer 200 can be disposed between the first word line WL1 and the second word line WL2 of the semiconductor device. The lower surface of the cell insulating layer 200 can be in contact with the upper surface of the support insulating layer 10. The upper surface of the cell insulating layer 200 can be in contact with the lower surface of the gate covering layer GP. In this case, the third gate insulating layer GI3 described with reference to Figure 4 and Figures 5A to 5C can be omitted. Therefore, the cell insulating layer 200 can be in direct contact with the inner wall IS1 of the first word line WL1 and the inner wall IS2 of the second word line WL2.

[0097] Referring to Figure 23 , in some implementations, an air gap AG can be provided on the third gate insulating layer GI3. The air gap AG can be interposed between the vertical portions GI3v of the third gate insulating layer GI3. For example, the boundaries of the vertical portions GI3v of the third gate insulating layer GI3 define the air gap. The air gap AG can expose the horizontal portion GI3h of the third gate insulating layer GI3. For example, the air gap AG can be an empty space filled with air.

[0098] Referring to Figure 24 , in some implementations, the third gate insulating layer GI3 described with reference to Figure 4 and Figures 5A to 5C can be omitted, and an air gap AG can be provided between the first word line WL1 and the second word line WL2. The air gap AG can expose the inner wall IS1 of the first word line WL1 and the inner wall IS2 of the second word line WL2. The air gap AG can expose the upper surface of the support insulating layer 10. The air gap AG can expose the lower surface of the gate covering layer GP.

[0099] In Figure 23 and Figure 24 , instead of the cell insulating layer 200, an air gap AG is provided between the first word line WL1 and the second word line WL2. The air gap AG can have a lower dielectric constant than the cell insulating layer 200. Therefore, the parasitic capacitance between the first word line WL1 and the second word line WL2 can be reduced, and the characteristics of the semiconductor device can be improved. In addition, electrical interference can be reduced, thereby increasing the integration of the wiring.

[0100] Referring to Figure 25 , in some implementations, a fourth gate insulating layer GI4 on a semiconductor pattern SP and a third word line WL3 on the fourth gate insulating layer GI4 may be provided. The third word lines WL3 may be spaced apart from each other in a first direction D1, and an insulating pattern 210 may be interposed therebetween. A first vertical portion V1 of the semiconductor pattern SP may be disposed between the first word line WL1 and the third word line WL3. A second vertical portion V2 of the semiconductor pattern SP may be disposed between the second word line WL2 and the third word line WL3. The fourth gate insulating layer GI4 may be in contact with a landing pad LP.

[0101] Referring to Figure 26 , in some implementations, a fourth gate insulating layer GI4 on a semiconductor pattern SP and a third word line WL3 on the fourth gate insulating layer GI4 may be provided. The third word lines WL3 may be spaced apart from each other in a first direction D1, and an insulating pattern 210 may be interposed therebetween. A first vertical portion V1 of the semiconductor pattern SP may be disposed between the first word line WL1 and the third word line WL3. A second vertical portion V2 of the semiconductor pattern SP may be disposed between the second word line WL2 and the third word line WL3. The fourth gate insulating layer GI4 may be in contact with a landing pad LP. A cell insulating layer 200 may be disposed between the first word line WL1 and the second word line WL2. A lower surface of the cell insulating layer 200 may be in contact with an upper surface of a support insulating layer 10. An upper surface of the cell insulating layer 200 may be in contact with a lower surface of a gate covering layer GP. In this case, the third gate insulating layer GI3 described with reference to Figure 4 and Figures 5A to 5C may be omitted. Accordingly, the cell insulating layer 200 may be in direct contact with an inner wall IS1 of the first word line WL1 and an inner wall IS2 of the second word line WL2.

[0102] Referring to Figure 27 , a fourth gate insulating layer GI4 on a semiconductor pattern SP and a third word line WL3 on the fourth gate insulating layer GI4 may be provided. The third word lines WL3 may be spaced apart from each other in a first direction D1, and an insulating pattern 210 may be interposed therebetween. A first vertical portion V1 of the semiconductor pattern SP may be disposed between the first word line WL1 and the third word line WL3. A second vertical portion V2 of the semiconductor pattern SP may be disposed between the second word line WL2 and the third word line WL3. The fourth gate insulating layer GI4 may be in contact with a landing pad LP.

[0103] An air gap AG may be provided on the third gate insulating layer GI3. The air gap AG may be interposed between vertical portions GI3v of the third gate insulating layer GI3. The air gap AG may expose a horizontal portion GI3h of the third gate insulating layer GI3.

[0104] Referring to Figure 28 , a fourth gate insulating layer GI4 on the semiconductor pattern SP and a third word line WL3 on the fourth gate insulating layer GI4 can be provided. The third word lines WL3 can be spaced apart from each other in a first direction D1, and an insulating pattern 210 is interposed therebetween. A first vertical portion V1 of the semiconductor pattern SP can be disposed between the first word line WL1 and the third word line WL3. A second vertical portion V2 of the semiconductor pattern SP can be disposed between the second word line WL2 and the third word line WL3. The fourth gate insulating layer GI4 can be in contact with the landing pad LP.

[0105] An air gap AG can be provided between the first word line WL1 and the second word line WL2. The air gap AG can expose an inner wall IS1 of the first word line WL1 and an inner wall IS2 of the second word line WL2. The air gap AG can expose an upper surface of the support insulating layer 10. The air gap AG can expose a lower surface of the gate covering layer GP.

[0106] In Figures 24 to 28 , the number of word lines surrounding the channel can be increased by additionally forming the third word line WL3. Accordingly, a region of the channel that can be controlled by the gate can be enlarged, thereby providing a semiconductor device having improved electrical characteristics.

[0107] In some implementations, using the disclosed structure in which the word lines surround the side surfaces of the channel can enlarge the region of the channel that can be controlled by the gate. Accordingly, a semiconductor device having improved electrical characteristics can be provided.

[0108] In some implementations, the disclosed concept can reduce electrical interference between word lines by providing a low-k material or an air gap between the word lines. Accordingly, the electrical characteristics of the semiconductor device can be improved, and the integration of the wiring can be increased.

[0109] Although this disclosure contains many specific implementation details, these should not be construed as limitations on the scope of the claimed subject matter. Certain features described in the context of separate implementations in this disclosure can also be implemented combinatorially in a single implementation. Conversely, various features described in the context of a single implementation can also be implemented separately in multiple implementations or in any suitable sub-combination. Additionally, although the features may be described above as acting in certain combinations, one or more features from a combination can in some cases be deleted from the combination, and the combination can be directed to a sub-combination or a variation of the sub-combination.

[0110] Although the embodiments have been described above, those skilled in the art will understand that many modifications and variations can be made without departing from the spirit and scope of the inventive concept defined in the appended claims. Therefore, the exemplary embodiments of the inventive concept should be considered illustrative rather than restrictive in all respects, and the spirit and scope of the inventive concept are indicated by the appended claims.

[0111] This application claims priority to Korean Patent Application No. 10-2023-0188380, filed with the Korean Intellectual Property Office on December 21, 2023, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: substrate; A bit line extending in a first direction on the substrate; a first word line and a second word line extending in a second direction on the bit line, crossing the bit line, and spaced apart from each other in the first direction, wherein the first direction and the second direction are parallel to the upper surface of the substrate and intersect each other; as well as semiconductor patterns spaced apart from each other in the first direction on the bit lines, the first word lines and the second word lines being interposed between the semiconductor patterns, The first word line comprises: a first portion extending in the second direction, and second portions protruding from the first portion in the first direction and spaced apart from each other in the second direction, wherein the second word line includes a first portion extending in the second direction and a second portion protruding in a third direction opposite to the first direction, and A first semiconductor pattern among the semiconductor patterns is interposed between the second portions of the first word lines, and a second semiconductor pattern among the semiconductor patterns is interposed between the second portions of the second word lines.

2. The semiconductor device according to claim 1 , wherein each of the semiconductor patterns includes a first vertical portion and a second vertical portion facing each other in the first direction, and The first vertical portion of the first semiconductor pattern is disposed between the second portions of the first word lines, and the second vertical portion of the second semiconductor pattern in the semiconductor pattern is disposed between the second portions of the second word lines.

3. The semiconductor device according to claim 1, further comprising: a first gate insulating layer disposed between an outer wall of the first word line and the first semiconductor pattern among the semiconductor patterns; as well as A second gate insulating layer is disposed between an outer wall of the second word line and the second semiconductor pattern of the semiconductor patterns. 4 . The semiconductor device according to claim 3 , further comprising a third gate insulating layer disposed on inner walls of the first word line and inner walls of the second word line.

5. The semiconductor device according to claim 4, wherein the third gate insulating layer comprises: a vertical portion in contact with the inner wall of the first word line and the inner wall of the second word line; as well as A horizontal portion is connected to the vertical portion of the third gate insulating layer.

6. The semiconductor device according to claim 5, further comprising a cell insulating layer on the third gate insulating layer, The cell insulating layer is disposed between the first word line and the second word line. 7 . The semiconductor device of claim 5 , wherein a boundary of the vertical portion of the third gate insulating layer defines an air gap exposing the horizontal portion of the third gate insulating layer.

8. The semiconductor device according to claim 3, further comprising: A supporting insulating layer in contact with an upper surface of the bit line; as well as Gate cover layer, wherein a lower surface of the first word line, a lower surface of the second word line, a lower surface of the first gate insulating layer, and a lower surface of the second gate insulating layer are in contact with an upper surface of the supporting insulating layer, and An upper surface of the first word line, an upper surface of the second word line, an upper surface of the first gate insulating layer, and an upper surface of the second gate insulating layer are in contact with a lower surface of the gate covering layer.

9. The semiconductor device according to claim 8, further comprising an air gap between the first word line and the second word line, The air gap exposes inner walls of the first word line, inner walls of the second word line, and the upper surface of the supporting insulating layer. 10 . The semiconductor device according to claim 9 , wherein the air gap exposes the lower surface of the gate cap layer.

11. The semiconductor device according to claim 8, further comprising a cell insulating layer between the first word line and the second word line, The lower surface of the unit insulating layer contacts the upper surface of the supporting insulating layer, and the upper surface of the unit insulating layer contacts the lower surface of the gate covering layer.

12. A semiconductor device comprising: substrate; bit lines extending in a first direction on the substrate and spaced apart from each other in a second direction, wherein the first direction and the second direction are parallel to an upper surface of the substrate and intersect each other; a first word line crossing the bit line and including a first portion extending in the second direction and a second portion protruding from the first portion in the first direction and spaced apart from each other in the second direction; as well as A semiconductor pattern is disposed on a corresponding bit line among the bit lines, wherein the semiconductor patterns include first vertical portions extending in a direction perpendicular to the upper surface of the substrate, each of the semiconductor patterns having a respective first vertical portion, wherein the first vertical portion of the semiconductor pattern is interposed between the second portions of the first word lines, and The second portions of the first word lines and the first vertical portions of the semiconductor patterns are alternately arranged in the second direction.

13. The semiconductor device according to claim 12, further comprising a first gate insulating layer between the first word line and the semiconductor pattern, The first gate insulating layer contacts the first vertical portion of the semiconductor pattern and contacts an outer wall of the first word line.

14. The semiconductor device according to claim 12, further comprising a second word line crossing the bit line and spaced apart from the first word line in the first direction, wherein the second word line includes a first portion extending in the second direction and a second portion protruding from the first portion in a third direction opposite to the first direction and spaced apart from each other in the second direction, wherein each of the semiconductor patterns extends in the direction perpendicular to the upper surface of the substrate, wherein the semiconductor pattern includes second vertical portions, each of the second vertical portions facing a corresponding first vertical portion in the first direction, wherein the second vertical portion of the semiconductor pattern is interposed between the second portions of the second word lines, and The second portions of the second word lines and the second vertical portions of the semiconductor patterns are alternately arranged in the second direction.

15. The semiconductor device according to claim 14, further comprising: a first gate insulating layer between the first word line and the semiconductor pattern; as well as a second gate insulating layer between the second word line and the semiconductor pattern, wherein the first gate insulating layer contacts the first vertical portion of the semiconductor pattern and contacts an outer wall of the first word line, and The second gate insulating layer contacts the second vertical portion of the semiconductor pattern and contacts an outer wall of the second word line. 16 . The semiconductor device according to claim 15 , further comprising a third gate insulating layer respectively contacting inner walls of the first word line and inner walls of the second word line.

17. The semiconductor device according to claim 15, wherein each of the semiconductor patterns includes a horizontal portion connecting the first vertical portion and the second vertical portion, and The horizontal portion of each of the semiconductor patterns is in contact with an upper surface of the bit line.

18. The semiconductor device according to claim 17, further comprising: a third gate insulating layer contacting the first vertical portion and the second vertical portion of each of the semiconductor patterns and extending onto an upper surface of the horizontal portion of each of the semiconductor patterns; as well as A third word line is on the third gate insulating layer.

19. A semiconductor device comprising: substrate; A bit line extending in a first direction on the substrate; A supporting insulating layer on the bit line; A first word line and a second word line intersecting the bit line on the supporting insulating layer; semiconductor patterns disposed on the bit lines and spaced apart from each other in the first direction, the supporting insulating layer, the first word lines, and the second word lines being interposed between the semiconductor patterns; a first gate insulating layer between the first semiconductor pattern and an outer wall of the first word line; and a second gate insulating layer between the second semiconductor pattern and an outer wall of the second word line, wherein the first word line includes a first portion extending in a second direction parallel to the upper surface of the substrate and intersecting the first direction and a second portion protruding in the first direction, wherein the second word line includes a first portion extending in the second direction and a second portion protruding in a third direction opposite to the first direction, wherein the first semiconductor pattern is disposed between the second portions of the first word lines, and The second semiconductor pattern is disposed between the second portions of the second word lines.

20. The semiconductor device according to claim 19, further comprising: a gate covering layer, contacting upper surfaces of the first word line, the second word line, and the first gate insulating layer and the second gate insulating layer; a landing pad connected to the semiconductor pattern; as well as A data storage pattern is connected to the landing pad.

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