Semiconductor device and manufacturing method thereof

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same, relating to the field of semiconductor technology. The semiconductor device comprises a substrate, a first epitaxial layer, a second epitaxial layer, a P-well region, an N-doped region, a P-doped region, a gate oxide layer, a polysilicon layer, a barrier layer, an ohmic contact layer, a first metal layer, and a second metal layer. A first-level wide trench is provided on the second epitaxial layer, wherein the sidewalls of the gate oxide layer, the sidewalls of the polysilicon layer, and the sidewalls of the first-level wide trench are flush. The barrier layer extends to the bottom wall of the first-level wide trench and simultaneously covers the sidewalls of the polysilicon layer, the sidewalls of the gate oxide layer, and the sidewalls of the first-level wide trench. This prevents liquid Al from penetrating into the gate at high temperatures, thereby avoiding short-circuit failures and surge failures. Furthermore, it prevents liquid Al from penetrating into the channel region, thereby avoiding problems such as increased leakage current, reduced breakdown voltage, threshold voltage (Vth) drift, and increased on-resistance, thereby improving the device's avalanche and thermal reliability and robustness.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] For traditional power MOSFETs, when abnormal problems such as short-circuit current or surge current occur, the device will generate extremely high temperatures, even exceeding the melting point of the source metal Al (660°C). This will cause the source Al metal of the device to melt and form liquid Al, resulting in a sharp change in the thermal expansion coefficient. In this case, the thermal oxidation gate SiO2, which has a certain stress difference, and the deposited ILD will produce a huge thermal mismatch stress difference at the SiO2 interface. This will cause cracks, allowing liquid Al to penetrate into the gate, causing short-circuit failure and surge failure.

[0003] In addition, for the thermally oxidized gate SiO2 with greater stress, larger cracks or gaps are likely to occur, allowing liquid Al to penetrate into the channel area, resulting in electrical performance problems such as increased leakage current, reduced breakdown voltage, threshold voltage Vth drift, increased on-resistance, and reliability and robustness problems such as avalanche and thermal.

[0004] In summary, existing power MOSFETs have problems such as poor reliability and robustness in thermal, short-circuit or surge conditions, and poor electrical characteristic stability. Summary of the Invention

[0005] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can improve the stability of the electrical characteristics of the device as well as the reliability and robustness of the device in terms of thermal, short circuit, surge, etc.

[0006] In a first aspect, the present invention provides a semiconductor device comprising:

[0007] substrate;

[0008] a first epitaxial layer located on the surface of the substrate;

[0009] a second epitaxial layer located on a surface of the first epitaxial layer, wherein the second epitaxial layer is formed with a first-level wide trench;

[0010] a P-well region, an N-doped region, and a P-doped region located on a surface of the second epitaxial layer away from the substrate, wherein two sides of the N-doped region are in contact with the P-well region and the P-doped region, respectively, the N-doped region is in contact with sidewalls and a bottom wall of the first-level wide trench, and the P-doped region is in contact with the bottom wall of the first-level wide trench;

[0011] a gate oxide layer located on a side of the second epitaxial layer away from the substrate and in contact with the N-doped region;

[0012] a polysilicon layer located on a side of the gate oxide layer away from the substrate;

[0013] a barrier layer located on a surface of the polysilicon layer;

[0014] an ohmic contact layer located on the surfaces of the P-doped region and the N-doped region;

[0015] a first metal layer located on surfaces of the barrier layer and the ohmic contact layer;

[0016] a second metal layer located on a surface of the substrate away from the first epitaxial layer;

[0017] The sidewalls of the gate oxide layer, the sidewalls of the polysilicon layer and the sidewalls of the first-level wide trench are flush with each other, and the barrier layer extends to the bottom wall of the first-level wide trench and simultaneously covers the sidewalls of the polysilicon layer, the sidewalls of the gate oxide layer and the sidewalls of the first-level wide trench.

[0018] In an optional embodiment, the second epitaxial layer is further provided with a second-level narrow trench, which is arranged on the bottom wall of the first-level wide trench and located between the P-doped region and the side wall of the first-level wide trench, and the barrier layer extends to the bottom wall of the second-level narrow trench and covers the side wall of the second-level narrow trench.

[0019] In an optional embodiment, the blocking layer includes a first interlayer dielectric layer, a blocking dielectric layer and a second interlayer dielectric layer, the first interlayer dielectric layer covers the surface of the polysilicon layer, the blocking dielectric layer is located on the surface of the first interlayer dielectric layer, and the second interlayer dielectric layer is located on the surface of the blocking dielectric layer.

[0020] In an optional embodiment, the thickness L1 of the first interlayer dielectric layer is the same as the thickness L3 of the second interlayer dielectric layer, and the thickness L2 of the blocking dielectric layer is more than twice the thickness L1 of the first interlayer dielectric layer.

[0021] In an optional embodiment, a first N-type doping region is formed on the surface of the first epitaxial layer away from the substrate, and a second N-type doping region, a third N-type doping region and a fourth N-type doping region are formed in the second epitaxial layer, the second N-type doping region is located on the surface of the second epitaxial layer close to the substrate, the third N-type doping region is in contact with the side of the second N-type doping region away from the substrate, the fourth N-type doping region is in contact with the side of the third N-type doping region away from the substrate, and the P-well region is in contact with the side of the second N-type doping region away from the substrate.

[0022] In an optional embodiment, the P-doped region includes a first P-type doped region and a second P-type doped region, the first P-type doped region is in contact with the first N-type doped region and is located on a surface layer of the second epitaxial layer away from the substrate, and the second P-type doped region is located between the N-doped region and the second N-type doped region, and is in contact with both the first P-type doped region and the P-well region;

[0023] The N-doped region includes a fifth N-type doping region and a sixth N-type doping region, the fifth N-type doping region and the sixth N-type doping region are both located on a side of the second P-type doping region away from the substrate, one side of the fifth N-type doping region contacts the P-well region, and the other side contacts the sixth N-type doping region and a sidewall of the first-level wide trench, a side of the sixth N-type doping region away from the fifth N-type doping region contacts the first P-type doping region, and the sixth N-type doping region contacts a bottom wall of the first-level wide trench;

[0024] The P-well region includes a third P-type doping region and a fourth P-type doping region, the third P-type doping region is located on a side of the second N-type doping region away from the substrate, and one side of the third P-type doping region is in contact with the third N-type doping region, and the other side is in contact with the fifth N-type doping region and the second P-type doping region at the same time, the fourth P-type doping region is located on a side of the third P-type doping region away from the substrate, and one side of the fourth P-type doping region is in contact with the fourth N-type doping region, and the other side is in contact with the fifth N-type doping region.

[0025] In an optional embodiment, a distance H1 between the second P-type doping region and the first N-type doping region and a distance H2 between the third P-type doping region and a surface of the second P-type doping region close to the substrate satisfy the following relationship: H1>3H2.

[0026] In an optional embodiment, the fourth N-type doping region is low-doped, and the height H3 of the third N-type doping region, the height H4 of the fourth N-type doping region, and the width W of the fourth N-type doping region satisfy the following relationship: (H3+H4)>2W.

[0027] In an optional embodiment, the thickness L1 of the first interlayer dielectric layer is the same as the thickness L3 of the second interlayer dielectric layer, the fifth N-type doping region is in contact with the sidewall and bottom wall of the first-level wide trench at the same time, the second-level narrow trench is located in the sixth N-type doping region, the distance L4 between the second-level narrow trench and the fifth N-type doping region is equal to the distance L5 between the second-level narrow trench and the first P-type doping region, the width W1 of the sidewall portion of the fifth N-type doping region joined to the first-level wide trench, the height H6 of the bottom wall portion of the fifth N-type doping region joined to the first-level wide trench, and the depth Hz of the second-level narrow trench are equal to each other, and the height H5 of the sidewall portion of the fifth N-type doping region joined to the first-level wide trench is the same as the width W2 of the bottom wall portion of the fifth N-type doping region joined to the first-level wide trench.

[0028] In a second aspect, the present invention provides a method for manufacturing a semiconductor device, for manufacturing the semiconductor device according to any one of the aforementioned embodiments, the manufacturing method comprising the following steps:

[0029] providing a substrate;

[0030] forming a first epitaxial layer based on the surface of the substrate;

[0031] A second epitaxial layer is formed on the surface of the first epitaxial layer, and a first-level wide trench is formed on the surface of the second epitaxial layer, wherein a P-well region, an N-doped region, and a P-doped region are formed by ion implantation on a surface of the second epitaxial layer away from the substrate, two sides of the N-doped region are in contact with the P-well region and the P-doped region, respectively, the N-doped region is in contact with sidewalls and a bottom wall of the first-level wide trench, and the P-doped region is in contact with the bottom wall of the first-level wide trench;

[0032] Forming a gate oxide layer in contact with the N-doped region based on a surface of the second epitaxial layer away from the substrate;

[0033] A polysilicon layer is formed on a surface of the gate oxide layer away from the substrate, wherein the sidewalls of the gate oxide layer, the sidewalls of the polysilicon layer, and the sidewalls of the first-level wide trench are flush with each other;

[0034] forming a barrier layer based on the surface of the polysilicon layer, wherein the barrier layer extends to the bottom wall of the first-level wide trench and simultaneously covers the sidewalls of the polysilicon layer, the sidewalls of the gate oxide layer, and the sidewalls of the first-level wide trench;

[0035] Fabricating an ohmic contact layer based on the surfaces of the P-doped region and the N-doped region;

[0036] forming a first metal layer based on the surfaces of the barrier layer and the ohmic contact layer;

[0037] A second metal layer is formed based on a surface of the substrate away from the first epitaxial layer.

[0038] The beneficial effects of the embodiments of the present invention include:

[0039] An embodiment of the present invention provides a semiconductor device and a method for manufacturing the same, the semiconductor device comprising: a substrate; a first epitaxial layer located on a surface of the substrate; a second epitaxial layer located on a surface of the first epitaxial layer, wherein the second epitaxial layer is formed with a first-level wide trench; a P-well region, an N-doped region, and a P-doped region located on a surface layer of the second epitaxial layer away from the substrate, wherein both sides of the N-doped region are in contact with the P-well region and the P-doped region, respectively; the N-doped region is in contact with the sidewalls and bottom wall of the first-level wide trench; and the P-doped region is in contact with the bottom wall of the first-level wide trench; a P-well region located on a side of the second epitaxial layer away from the substrate and in contact with the substrate. A gate oxide layer in contact with the N-doped region; a polysilicon layer located on the side of the gate oxide layer away from the substrate; a barrier layer located on the surface of the polysilicon layer; an ohmic contact layer located on the surfaces of the P-doped region and the N-doped region; a first metal layer located on the surfaces of the barrier layer and the ohmic contact layer; and a second metal layer located on the surface of the substrate away from the first epitaxial layer; wherein the sidewalls of the gate oxide layer, the sidewalls of the polysilicon layer, and the sidewalls of the first-level wide trench are flush with each other, and the barrier layer extends to the bottom wall of the first-level wide trench and simultaneously covers the sidewalls of the polysilicon layer, the sidewalls of the gate oxide layer, and the sidewalls of the first-level wide trench.

[0040] Compared to existing technologies, the embodiments of the present invention, by providing a first-level wide trench, prevent the source metal Al from directly contacting the interface between the gate oxide layer and the barrier layer. This prevents liquid Al from penetrating into the gate (polysilicon layer) at high temperatures, thus avoiding short-circuit and surge failures. Furthermore, the barrier layer completely covers the gate oxide layer, preventing direct Al contact and liquid Al from penetrating into the channel region. This prevents electrical performance issues such as increased leakage current, reduced breakdown voltage, threshold voltage (Vth) shift, and increased on-resistance, while also improving the device's reliability and robustness, including avalanche and thermal characteristics.

[0041] At the same time, by setting up a first-level wide trench and making the gate oxide layer flush with the polysilicon layer and the sidewalls of the first-level wide trench, large-area contact between the barrier layer and the gate oxide layer is avoided, thereby minimizing the problems of device threshold voltage Vth drift, increased leakage current, reduced breakdown voltage, increased on-resistance, and even reduced reliability caused by positive and negative charges in the barrier layer.

[0042] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0044] Figure 1 It is a structural diagram of an existing power MOSFET device;

[0045] Figure 2 A schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0046] Figure 3 for Figure 2 A local enlarged schematic diagram of point I in the middle;

[0047] Figure 4 A process diagram of step S2 in the method for manufacturing a semiconductor device provided in an embodiment of the present invention;

[0048] Figure 5 A schematic diagram of the process of the first epitaxial growth in step S3 of the method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0049] Figure 6 A schematic diagram of the process of the second epitaxial growth in step S3 of the method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0050] Figure 7 A schematic diagram of the process of the third epitaxial growth in step S3 of the method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0051] Figure 8 A schematic diagram of the fourth epitaxial growth process in step S3 of the method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0052] Figure 9 A schematic diagram of a process for forming a first-level wide trench in step S3 of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0053] Figure 10 A process diagram of step S4 and step S5 in the method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0054] Figure 11 This is a process diagram of step S6 in the method for manufacturing a semiconductor device provided by an embodiment of the present invention.

[0055] A schematic diagram of the structure of a semiconductor device provided by an embodiment of the present invention;

[0056] Icons: 100-semiconductor device; 110-substrate; 120-first epitaxial layer; 121-first N-type doped region; 130-second epitaxial layer; 131-first wide trench; 132-second narrow trench; 133-second N-type doped region; 134-third N-type doped region; 135-fourth N-type doped region; 136-first growth layer; 137-second growth layer; 138-third growth layer; 139-fourth growth layer; 140-P well region; 141-third P-type doped region Region; 142-fourth P-type doping region; 150-N-doping region; 151-fifth N-type doping region; 152-sixth N-type doping region; 160-P-doping region; 161-first P-type doping region; 162-second P-type doping region; 170-gate oxide layer; 171-polysilicon layer; 172-ohmic contact layer; 173-blocking layer; 174-first interlayer dielectric layer; 175-blocking dielectric layer; 176-second interlayer dielectric layer; 180-first metal layer; 190-second metal layer. DETAILED DESCRIPTION

[0057] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0058] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0059] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0060] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the accompanying drawings, or is the orientation or position relationship in which the product of the invention is usually placed when in use. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be understood as a limitation on the present invention.

[0061] In addition, the terms "first," "second," etc., are used only to distinguish descriptions and should not be understood as indicating or implying relative importance. It should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0062] In the description of this application, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the application is usually placed when in use. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on this application.

[0063] As disclosed in the background art, conventional power MOSFETs have problems such as poor reliability and robustness in thermal, short-circuit, or surge conditions, and poor electrical characteristic stability.

[0064] For example, see Figure 1 , where P+ represents P-type heavy doping, N+ represents N-type heavy doping, Figure 1 This is a cross-sectional diagram of a conventional power MOSFET. When abnormalities such as short-circuit current or surge current occur, the device reaches extremely high temperatures, even exceeding the melting point of the source Al metal (660°C). This causes the source Al metal to melt, forming liquid Al and resulting in a dramatic change in the thermal expansion coefficient. In this case, a significant thermal mismatch stress difference occurs at the SiO2 interface between the thermally oxidized gate SiO2 (which already has a certain stress difference) and the deposited ILD. This can lead to cracks, allowing the liquid Al to penetrate the gate, causing short-circuit and surge failures.

[0065] In addition, for the thermally oxidized gate SiO2 with greater stress, larger cracks or gaps are likely to occur, allowing liquid Al to penetrate into the channel area, resulting in electrical performance problems such as increased leakage current, reduced breakdown voltage, threshold voltage Vth drift, increased on-resistance, and reliability and robustness problems such as avalanche and thermal.

[0066] In addition, due to reasons such as the manufacturing process, positive and negative charges may exist in the interlayer dielectric ILD. Since the interlayer dielectric is looser than the gate oxide layer, positive and negative charges can easily enter the gate oxide layer and even reach the oxide layer-semiconductor interface. At this time, the interface state traps existing at the interface will capture the corresponding positive and negative charges to form interface trap charges, and directly produce electrical effects with the semiconductor (such as Coulomb scattering), seriously affecting the channel mobility uch, and thus causing the device to have problems such as threshold voltage Vth drift, increased leakage current, reduced breakdown voltage, and increased on-resistance.

[0067] To address the above-mentioned issues, embodiments of the present invention provide a novel semiconductor device and a method for manufacturing the same. By designing additional trenches, the device's electrical stability, thermal reliability, short-circuit reliability, and surge robustness can be improved. It should be noted that the features of the embodiments of the present invention may be combined unless they conflict.

[0068] The semiconductor device provided in this application is exemplified below:

[0069] As an optional implementation, see Figure 2 and Figure 3 The semiconductor device 100 includes: a substrate 110; a first epitaxial layer 120 located on the surface of the substrate 110; a second epitaxial layer 130 located on the surface of the first epitaxial layer 120, wherein the second epitaxial layer 130 is formed with a first-level wide trench 131; a P-well region 140, an N-doped region 150, and a P-doped region 160 located on the surface of the second epitaxial layer 130 away from the substrate 110, wherein the two sides of the N-doped region 150 are in contact with the P-well region 140 and the P-doped region 160 respectively, the N-doped region 150 is in contact with the sidewalls and bottom wall of the first-level wide trench 131, and the P-doped region 160 is in contact with the bottom wall of the first-level wide trench 131; and a gate oxide layer located on the side of the second epitaxial layer 130 away from the substrate 110 and in contact with the N-doped region 150. 170; a polysilicon layer 171 located on the side of the gate oxide layer 170 away from the substrate 110; a barrier layer 173 located on the surface of the polysilicon layer 171; an ohmic contact layer 172 located on the surfaces of the P-doped region 160 and the N-doped region 150; a first metal layer 180 located on the surfaces of the barrier layer 173 and the ohmic contact layer 172; a second metal layer 190 located on the surface of the substrate 110 away from the first epitaxial layer 120; wherein the sidewalls of the gate oxide layer 170, the sidewalls of the polysilicon layer 171 and the sidewalls of the first-level wide trench 131 are flush with each other, and the barrier layer 173 extends to the bottom wall of the first-level wide trench 131 and simultaneously covers the sidewalls of the polysilicon layer 171, the sidewalls of the gate oxide layer 170 and the sidewalls of the first-level wide trench 131.

[0070] It should be noted that the semiconductor device 100 may be a MOSFET device, wherein the substrate 110 is an N+ substrate 110 layer, the first epitaxial layer 120 is an N-type epitaxial layer, and both the first epitaxial layer 120 and the second epitaxial layer 130 may be SiC epitaxial layers. It should also be noted that, in the embodiments of the present invention, "X is located on the surface layer of Y" means that X is located within Y and exposed above Y, while "X is located on the surface of Y" means that X and Y are two independent parts, X is located above Y, and X and Y are in contact.

[0071] It is worth noting that the first metal layer 180 of the embodiment of the present invention can be used as the source metal, preferably made of aluminum, and the polysilicon layer 171 can be used as the gate. The first-level wide trench 131 extends from the middle of the second epitaxial layer 130 to both sides, thereby leaving a step structure in the middle of the second epitaxial layer 130. The P-well region 140 and the N-doped region 150 are partially located in the step structure, and the gate oxide layer 170 and the polysilicon layer 171 are sequentially formed on the step structure. By providing the first-level wide trench 131, on the one hand, the first metal layer 180 is prevented from directly contacting the interface between the gate oxide layer 170 and the barrier layer 173, and liquid Al is prevented from penetrating into the polysilicon layer 171 at high temperatures, thereby avoiding short circuit failure and surge failure. On the other hand, the barrier layer 173 completely covers the gate oxide layer 170, preventing the source metal Al from directly contacting the gate oxide layer 170 and preventing liquid Al from penetrating into the channel region. This prevents device electrical performance issues such as increased leakage current, reduced breakdown voltage, threshold voltage Vth shift, and increased on-resistance, while also improving device reliability and robustness, including avalanche and thermal characteristics. Furthermore, by providing the first-level wide trench 131 and ensuring that the gate oxide layer 170 is flush with the polysilicon layer 171 and the sidewalls of the first-level wide trench 131, large-area contact between the barrier layer 173 and the gate oxide layer 170 is avoided, thereby minimizing issues such as device threshold voltage Vth shift, increased leakage current, reduced breakdown voltage, increased on-resistance, and even reduced reliability caused by positive and negative charges in the barrier layer 173.

[0072] In some embodiments, the second epitaxial layer 130 is further provided with a second-level narrow trench 132. The second-level narrow trench 132 is provided on the bottom wall of the first-level wide trench 131 and is located between the P-doped region 160 and the sidewalls of the first-level wide trench 131. The barrier layer 173 extends to the bottom wall of the second-level narrow trench 132 and covers the sidewalls of the second-level narrow trench 132. Specifically, the second-level narrow trench 132 is spaced apart from the P-doped region 160. In actual fabrication, the first-level wide trench 131 can be formed first, and then the second-level narrow trench 132 can be formed on the bottom wall of the first-level wide trench 131. The width of the second-level narrow trench 132 is smaller than the width of the N-doped region 150.

[0073] By setting the second-level narrow groove 132, it is possible to avoid the first metal layer 180 directly contacting the interface position of the deposited barrier layer 173 and the second epitaxial layer 130 when only the first-level wide groove 131 is set, thereby avoiding problems such as cracks or gaps in the deposited barrier layer 173 due to the large stress difference at the interface, further improving the stability of the device's electrical characteristics and the device's thermal, short-circuit, surge and other reliability and robustness.

[0074] In some embodiments, the blocking layer 173 includes a first interlayer dielectric layer 174, a blocking dielectric layer 175, and a second interlayer dielectric layer. The first interlayer dielectric layer 174 covers the surface of the polysilicon layer 171, the blocking dielectric layer 175 is located on the surface of the first interlayer dielectric layer 174, and the second interlayer dielectric layer is located on the surface of the blocking dielectric layer 175. Specifically, the blocking dielectric layer 175 can be made of a dielectric material with high thermal conductivity, excellent thermal stability, and a high failure temperature, such as the new multi-element material SiCH / SiCN. By adopting a three-layer structure and using the blocking dielectric layer 175 as the core layer, on the one hand, the interlayer dielectric material can be further protected, the probability of cracks or gaps can be reduced, and the electrical characteristics stability of the device and the reliability and robustness of the device can be further improved. On the other hand, the heat dissipation capacity of the device can be increased, heat can be prevented from concentrating in the two-level grooves, and the thermal stress of the device can be greatly improved, thereby greatly improving the thermal stability and reliability of the device.

[0075] Furthermore, the thickness L1 of the first interlayer dielectric layer 174 is the same as the thickness L3 of the second interlayer dielectric layer, and the thickness L2 of the blocking dielectric layer 175 is more than twice the thickness L1 of the first interlayer dielectric layer 174. The thicknesses of both the first interlayer dielectric layer 174 and the second interlayer dielectric layer are greater than 0, and L1 = L3, and L2 > 2L1. This ensures that the blocking dielectric layer 175 is thicker, further improving the device's heat dissipation performance while flexibly adjusting thermal stress to balance the device's internal stress, thereby achieving greater device reliability and robustness.

[0076] In some embodiments, a first N-type doping region 121 (N1 region in the figure) is formed on the surface of the first epitaxial layer 120 away from the substrate 110, and a second N-type doping region 133 (N2 region in the figure), a third N-type doping region 134 (N3 region in the figure), and a fourth N-type doping region 135 (N4 region in the figure) are formed in the second epitaxial layer 130. The second N-type doping region 133 is located on the surface of the second epitaxial layer 130 close to the substrate 110, the third N-type doping region 134 is in contact with the side of the second N-type doping region 133 away from the substrate 110, the fourth N-type doping region 135 is in contact with the side of the third N-type doping region 134 away from the substrate 110, and the P-well region 140 is in contact with the side of the second N-type doping region 133 away from the substrate 110. Specifically, the surface layer of the first epitaxial layer 120 away from the substrate 110 is formed into a first N-type doping region 121 by ion implantation. The first N-type doping region 121 can cover the entire surface layer of the first epitaxial layer 120. The second epitaxial layer 130 can be formed by multiple epitaxy processes, and the second N-type doping region 133, the third N-type doping region 134, and the fourth N-type doping region 135 can be formed by multiple ion implantations of different concentrations. At the same time, the P-well region 140 and the P-doping region 160 can also be formed by multiple ion implantations. The specific formation process can refer to the subsequent process description. Among them, the fourth N-type doping region 135 is a low-doping region that can reduce the peak electric field at the center of the gate oxide layer 170. The gate oxide layer 170 is in contact with the fourth N-type doping region 135. When the ion concentration of the fourth N-type doping region 135 is the lowest (which is lower than that of the first N-type doping region 121, the second N-type doping region 133 and the third N-type doping region 134), the peak electric field at the center of the gate oxide layer 170 can be further reduced, thereby improving the gate oxide reliability of the device.

[0077] In some embodiments, the P-doped region 160 includes a first P-type doping region 161 (P1 region in the figure) and a second P-type doping region 162 (P2 region in the figure). The first P-type doping region 161 is located in contact with the first N-type doping region 121 and is located on the surface of the second epitaxial layer 130 away from the substrate 110. The second P-type doping region 162 is located between the N-doping region 150 and the second N-type doping region 133, and is in contact with the first P-type doping region 161 and the P-well region 140 at the same time. The N-doped region 150 includes a fifth N-type doping region 151 (N5 region in the figure) and a sixth N-type doping region 152 (N6 region in the figure). The fifth N-type doping region 151 and the sixth N-type doping region 152 are both located on the side of the second P-type doping region 162 away from the substrate 110. One side of the fifth N-type doping region 151 contacts the P-well region 140, and the other side contacts the sixth N-type doping region 152 and the sidewall of the first-level wide trench 131. The side of the sixth N-type doping region 152 away from the fifth N-type doping region 151 contacts the first P-type doping region 161, and the sixth N-type doping region 152 contacts the bottom wall of the first-level wide trench 131. The P-well region 140 includes a third P-type doping region 141 (P3 region in the figure) and a fourth P-type doping region 142 (P4 region in the figure). The third P-type doping region 141 is located on the side of the second N-type doping region 133 away from the substrate 110, and one side of the third P-type doping region 141 is in contact with the third N-type doping region 134, and the other side is in contact with the fifth N-type doping region 151 and the second P-type doping region 162 at the same time. The fourth P-type doping region 142 is located on the side of the third P-type doping region 141 away from the substrate 110, and one side of the fourth P-type doping region 142 is in contact with the fourth N-type doping region 135, and the other side is in contact with the fifth N-type doping region 151.

[0078] It should be noted that the doping concentrations of the first P-type doping region 161, the second P-type doping region 162, the third P-type doping region 141, and the fourth P-type doping region 142 are different, and the doping concentrations of the first N-type doping region 121, the second N-type doping region 133, the third N-type doping region 134, and the fourth N-type doping region 135 are different. By flexibly adjusting the concentration and size of each doping region, a PN junction depletion region equivalent resistance and capacitance with automatic buffering and suppression can be introduced into the current path. When an abnormal operating condition occurs, the device can automatically and flexibly expand the PN depletion region at different locations, thereby automatically generating depletion layer equivalent resistance and capacitance of different sizes, automatically suppressing EMI electromagnetic interference, oscillation, surge, and other problems. Ultimately, the device has better resistance to electromagnetic interference, oscillation, surge, voltage and current overshoot, stronger short-circuit withstand capability (SCWT), and higher device reliability.

[0079] In some embodiments, the distance H1 between the second P-type doping region 162 and the first N-type doping region 121, and the distance H2 between the third P-type doping region 141 and the surface of the second P-type doping region 162 near the substrate 110, satisfy the following relationship: H1>3H2. Specifically, when H1>3H2, the entire body diode PN junction can form an equivalent arc-surface structure, thereby further dispersing the depletion layer electric lines at the corners of the P-well region 140 and the center of the gate oxide layer, significantly reducing the peak electric field, and achieving a higher gate oxide breakdown voltage and gate oxide reliability for the device.

[0080] In some embodiments, the fourth N-type doping region 135 is a low-doping region, and the ion concentration of the fourth N-type doping region 135 is the lowest. The height H3 of the third N-type doping region 134, the height H4 of the fourth N-type doping region 135, and the width W of the fourth N-type doping region 135 satisfy the following relationship: (H3+H4)>2W. Specifically, when (H3+H4)>2W, and the fourth P-type doping region 142 is low-doped, and the ion concentration of the fourth P-type doping region 142 is the lowest, the peak electric field at the center of the gate oxide layer 170 can be further reduced, further improving the gate oxide reliability of the device.

[0081] In some embodiments, a thickness L1 of the first interlayer dielectric layer 174 is the same as a thickness L3 of the second interlayer dielectric layer, the fifth N-type doping region 151 contacts both the sidewall and the bottom wall of the first-level wide trench 131, the second-level narrow trench 132 is located in the sixth N-type doping region 152, a distance L4 between the second-level narrow trench 132 and the fifth N-type doping region 151 is equal to a distance L5 between the second-level narrow trench 132 and the first P-type doping region 161, a width W1 of the sidewall portion of the fifth N-type doping region 151 joined to the first-level wide trench 131, a height H6 of the bottom wall portion of the fifth N-type doping region 151 joined to the first-level wide trench 131, and a depth Hz of the second-level narrow trench 132 are equal in each other, and a height H5 of the sidewall portion of the fifth N-type doping region 151 joined to the first-level wide trench 131 is the same as a width W2 of the bottom wall portion of the fifth N-type doping region 151 joined to the first-level wide trench 131. Specifically, the fifth N-type doping region 151 and the sixth N-type doping region 152 serve as highly doped sources, and the doping concentrations of the two regions are unequal. The second-level narrow trench 132 is located in the center of the sixth N-type doping region 152. This is to provide the sixth N-type doping region 152 on both the left and right sides of the second-level narrow trench 132. Furthermore, when L1 = L3, L4 = L5, W1 = H6 = Hz, and W2 = H5, the internal stress generated by the semiconductor material lattice distortion after etching the second-level narrow trench 132 can be balanced, thereby improving the electrical stability and reliability of the device.

[0082] Based on the above implementation, an embodiment of the present invention further provides a method for manufacturing a semiconductor device 100, which is used to manufacture the above semiconductor device 100. The method comprises the following steps:

[0083] S1: Provide a substrate 110.

[0084] S2: forming a first epitaxial layer 120 based on the surface of the substrate 110;

[0085] S3 : forming a second epitaxial layer 130 based on the surface of the first epitaxial layer 120 , and forming a first-level wide trench 131 based on the surface of the second epitaxial layer 130 .

[0086] A P-well region 140, an N-doped region 150, and a P-doped region 160 are formed by ion implantation on the surface of the second epitaxial layer 130 away from the substrate 110. The two sides of the N-doped region 150 are in contact with the P-well region 140 and the P-doped region 160, respectively. The N-doped region 150 is in contact with the sidewalls and bottom wall of the first-level wide trench 131, and the P-doped region 160 is in contact with the bottom wall of the first-level wide trench 131.

[0087] S4 : forming a gate oxide layer 170 in contact with the N-doped region 150 based on the surface of the second epitaxial layer 130 away from the substrate 110 .

[0088] S5 : forming a polysilicon layer 171 based on the surface of the gate oxide layer 170 away from the substrate 110 .

[0089] The sidewalls of the gate oxide layer 170 , the sidewalls of the polysilicon layer 171 , and the sidewalls of the first-level wide trench 131 are flush with each other.

[0090] S6 : forming a barrier layer 173 based on the surface of the polysilicon layer 171 .

[0091] The barrier layer 173 extends to the bottom wall of the first-level wide trench 131 and covers the sidewalls of the polysilicon layer 171 , the sidewalls of the gate oxide layer 170 and the sidewalls of the first-level wide trench 131 .

[0092] S7 : forming an ohmic contact layer 172 based on the surfaces of the P-doped region 160 and the N-doped region 150 .

[0093] S8 : forming a first metal layer 180 based on the surfaces of the barrier layer 173 and the ohmic contact layer 172 .

[0094] S9 : forming a second metal layer 190 based on a surface of the substrate 110 away from the first epitaxial layer 120 .

[0095] The following is an exemplary description of the method for manufacturing the semiconductor device 100 provided in this application with reference to the accompanying drawings:

[0096] First, see Figure 4 , a first epitaxial layer 120 is deposited on the substrate 110 , and then a first N-type ion implantation is performed on the surface of the first epitaxial layer 120 away from the substrate 110 to form a first N-type doping region 121 , which is located on the surface of the first epitaxial layer 120 .

[0097] Second, see Figure 5 , a first epitaxial growth is performed on the first epitaxial layer 120 to form a first growth layer 136, and then a second N-type ion implantation is performed on the first growth layer 136 to form a second N-type doped region 133, and then a first P-type ion implantation is performed on the surface layer of the first growth layer 136 away from the substrate 110 to form a portion of the second P-type doped region 162.

[0098] Afterwards, see Figure 6 , a second epitaxial growth is performed on the first growth layer 136 to form a second growth layer 137 , and then a second P-type ion implantation is performed on the second growth layer 137 to contact the P-type ion doped region in the first growth layer 136 to form a second P-type doped region 162 .

[0099] Then, see Figure 7 A third epitaxial growth is performed on the second growth layer 137 to form a third growth layer 138. Then, a third N-type ion implantation is performed in the middle of the third growth layer 138 to a depth reaching the second N-type doping region 133, thereby forming a third N-type doping region 134 in contact with the second N-type doping region 133. A fourth N-type ion implantation is then performed to form a portion of the fifth N-type doping region 151. The fifth N-type doping region 151 is in contact with the second P-type doping region 162. A fifth N-type ion implantation is then performed on the side of the fifth N-type doping region 151 away from the third N-type doping region 134 to form a sixth N-type doping region 152. The sixth N-type doping region 152 is in contact with both the fifth N-type doping region 151 and the second P-type doping region 162. Finally, a third P-type ion implantation is performed on the area between the third N-type doping region 134 and the fifth N-type doping region 151 to form a third P-type doping region 141 , which is in contact with both the fifth N-type doping region 151 and the second P-type doping region 162 .

[0100] Afterwards, see Figure 8A fourth epitaxial growth is performed on the third growth layer 138 to form a fourth growth layer 139. Then, a sixth N-type ion implantation is performed to form a fourth N-type doping region 135. The fourth N-type doping region 135 is in contact with the third N-type doping region 134. A seventh N-type ion implantation is then performed, and the implanted region is bonded to the N-type ion doping region in the third growth layer 138 to form a fifth N-type doping region 151. Finally, a fourth P-type ion implantation is performed in the region between the fifth N-type doping region 151 and the fourth N-type doping region 135 to form a fourth P-type doping region 142. The fourth P-type doping region 142 is in contact with the third P-type doping region 141.

[0101] It should be noted that the first growth layer 136 , the second growth layer 137 , the third growth layer 138 and the fourth growth layer 139 together constitute the second epitaxial layer 130 .

[0102] Then, see Figure 9 A first etching step is performed on the fourth growth layer 139 to form a first-level wide trench 131. The fifth N-type doping region 151 and the sixth N-type doping region 152 can be used as etching boundaries for the first-level wide trench 131. After etching, the fifth N-type doping region 151 contacts both the sidewalls and bottom wall of the first-level wide trench 131, and the sixth N-type doping region 152 contacts the bottom wall of the first-level wide trench 131. A fifth P-type ion implantation step is then performed, using the sixth N-type doping region 152 as the implantation boundary, to form a first P-type doping region 161. The first P-type doping region 161 contacts both the sixth N-type doping region 152 and the second P-type doping region 162. Finally, a second etching step is performed on the bottom wall of the first-level wide trench 131 to form a second-level narrow trench 132. During the etching step, the sixth N-type doping region 152 can be used as an etching guide, so that the second-level narrow trench 132 is located in the center of the sixth N-type doping region 152. After etching, high-temperature furnace annealing is required.

[0103] Afterwards, see Figure 10 After annealing, the second epitaxial layer 130 may be selectively oxidized to form a gate oxide layer 170, and then a polysilicon layer 171 may be deposited and etched according to a predetermined pattern to form a polysilicon layer 171 on the gate oxide layer 170. The polysilicon layer 171 is an N+ type polysilicon layer 171.

[0104] Then, see Figure 11 , the barrier layer 173 can be fabricated. Specifically, a layer of interlayer dielectric material is first deposited and then etched to form a first interlayer dielectric layer; then a layer of dielectric material with high thermal conductivity, excellent thermal stability, and a high failure temperature is deposited and then etched to form a barrier dielectric layer 175; finally, another layer of interlayer dielectric material is deposited and then etched to form a second interlayer dielectric layer 176.

[0105] Finally, please continue to see Figure 2 According to conventional processes, the ohmic contact layer 172 can be prepared on the surface of the P-doped region 160 and the N-doped region 150, and then the front metal is produced to form the first metal layer 180, and finally the back metal is produced to form the back metal layer.

[0106] In summary, an embodiment of the present invention provides a semiconductor device 100 and a manufacturing method thereof, wherein the semiconductor device 100 includes: a substrate 110; a first epitaxial layer 120 located on the surface of the substrate 110; a second epitaxial layer 130 located on the surface of the first epitaxial layer 120, wherein the second epitaxial layer 130 is formed with a first-level wide trench 131; a P-well region 140, an N-doped region 150, and a P-doped region 160 located on the surface of the second epitaxial layer 130 away from the substrate 110, wherein both sides of the N-doped region 150 are in contact with the P-well region 140 and the P-doped region 160, respectively, the N-doped region 150 is in contact with the sidewalls and bottom wall of the first-level wide trench 131, and the P-doped region 160 is in contact with the bottom wall of the first-level wide trench 131; a P-well region 140 located on the surface of the second epitaxial layer 130 away from the substrate 110 and A gate oxide layer 170 in contact with the N-doped region 150; a polysilicon layer 171 located on the side of the gate oxide layer 170 away from the substrate 110; a barrier layer 173 located on the surface of the polysilicon layer 171; an ohmic contact layer 172 located on the surfaces of the P-doped region 160 and the N-doped region 150; a first metal layer 180 located on the surfaces of the barrier layer 173 and the ohmic contact layer 172; and a second metal layer 190 located on the surface of the substrate 110 away from the first epitaxial layer 120; wherein the sidewalls of the gate oxide layer 170, the sidewalls of the polysilicon layer 171, and the sidewalls of the first-level wide trench 131 are flush with each other, and the barrier layer 173 extends to the bottom wall of the first-level wide trench 131 and simultaneously covers the sidewalls of the polysilicon layer 171, the sidewalls of the gate oxide layer 170, and the sidewalls of the first-level wide trench 131.

[0107] By providing first-level wide trenches 131, the present embodiment prevents the source metal Al from directly contacting the interface between the gate oxide layer 170 and the barrier layer 173. This prevents liquid Al from penetrating into the gate (polysilicon layer 171) at high temperatures, thus avoiding short-circuit and surge failures. Furthermore, the barrier layer 173 completely covers the gate oxide layer 170, preventing the source metal Al from directly contacting the gate oxide layer 170 and preventing liquid Al from penetrating into the channel region. This prevents electrical performance issues such as increased leakage current, reduced breakdown voltage, threshold voltage (Vth) shift, and increased on-resistance, while also improving the device's reliability and robustness, including avalanche and thermal characteristics.

[0108] At the same time, by providing the first-level wide trench 131 and the gate oxide layer 170 being flush with the polysilicon layer 171 and the sidewalls of the first-level wide trench 131, large-area contact between the barrier layer 173 and the gate oxide layer 170 is avoided, thereby minimizing the problems of device threshold voltage Vth drift, increased leakage current, reduced breakdown voltage, increased on-resistance, and even reduced reliability caused by positive and negative charges in the barrier layer 173. By adopting a three-layer barrier layer 173 structure and using a blocking dielectric layer 175 as the core layer, on the one hand, the interlayer dielectric material can be further protected, the probability of cracks or gaps being generated can be reduced, and the electrical characteristics stability, reliability, and robustness of the device can be further improved. On the other hand, the device's heat dissipation capacity can be increased, heat can be prevented from concentrating in the two-level trench, and the device's thermal stress can be greatly improved, thereby significantly improving the device's thermal stability and reliability. In addition, by flexibly adjusting the concentration and size of each doped region, a PN junction depletion region equivalent resistance and capacitance with automatic buffering and suppression can be introduced into the current path. When abnormal operating conditions occur, the device can automatically and flexibly expand the PN depletion regions at different positions, thereby automatically generating depletion layer equivalent resistance and capacitance of different sizes, automatically suppressing EMI electromagnetic interference, oscillation, surge and other problems, and ultimately making the device more resistant to electromagnetic interference, oscillation, surge, voltage and current overshoot, and having stronger short-circuit tolerance (SCWT), and the device highly reliable.

[0109] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; a first epitaxial layer located on the surface of the substrate; a second epitaxial layer located on a surface of the first epitaxial layer, wherein the second epitaxial layer is formed with a first-level wide trench; a P-well region, an N-doped region, and a P-doped region located on a surface of the second epitaxial layer away from the substrate, wherein two sides of the N-doped region are in contact with the P-well region and the P-doped region, respectively, the N-doped region is in contact with sidewalls and a bottom wall of the first-level wide trench, and the P-doped region is in contact with the bottom wall of the first-level wide trench; a gate oxide layer located on a side of the second epitaxial layer away from the substrate and in contact with the N-doped region; a polysilicon layer located on a side of the gate oxide layer away from the substrate; a barrier layer located on a surface of the polysilicon layer; an ohmic contact layer located on the surfaces of the P-doped region and the N-doped region; a first metal layer located on surfaces of the barrier layer and the ohmic contact layer; a second metal layer located on a surface of the substrate away from the first epitaxial layer; The sidewalls of the gate oxide layer, the sidewalls of the polysilicon layer and the sidewalls of the first-level wide trench are flush with each other, and the barrier layer extends to the bottom wall of the first-level wide trench and simultaneously covers the sidewalls of the polysilicon layer, the sidewalls of the gate oxide layer and the sidewalls of the first-level wide trench.

2. The semiconductor device according to claim 1, wherein The second epitaxial layer is also provided with a second-level narrow trench, which is arranged on the bottom wall of the first-level wide trench and located between the P-doped region and the side wall of the first-level wide trench. The barrier layer extends to the bottom wall of the second-level narrow trench and covers the side wall of the second-level narrow trench.

3. The semiconductor device according to claim 2, wherein The blocking layer includes a first interlayer dielectric layer, a blocking dielectric layer and a second interlayer dielectric layer, wherein the first interlayer dielectric layer covers the surface of the polysilicon layer, the blocking dielectric layer is located on the surface of the first interlayer dielectric layer, and the second interlayer dielectric layer is located on the surface of the blocking dielectric layer.

4. The semiconductor device according to claim 3, wherein The thickness L1 of the first interlayer dielectric layer is the same as the thickness L3 of the second interlayer dielectric layer, and the thickness L2 of the blocking dielectric layer is more than twice the thickness L1 of the first interlayer dielectric layer.

5. The semiconductor device according to claim 3, wherein A first N-type doping region is formed on the surface of the first epitaxial layer away from the substrate, and a second N-type doping region, a third N-type doping region, and a fourth N-type doping region are formed in the second epitaxial layer. The second N-type doping region is located on the surface of the second epitaxial layer close to the substrate, the third N-type doping region is in contact with the side of the second N-type doping region away from the substrate, the fourth N-type doping region is in contact with the side of the third N-type doping region away from the substrate, and the P-well region is in contact with the side of the second N-type doping region away from the substrate.

6. The semiconductor device according to claim 5, wherein The P-doped region includes a first P-type doped region and a second P-type doped region, the first P-type doped region contacts the first N-type doped region and is located on a surface layer of the second epitaxial layer away from the substrate, the second P-type doped region is located between the N-doped region and the second N-type doped region, and contacts both the first P-type doped region and the P-well region; The N-doped region includes a fifth N-type doping region and a sixth N-type doping region, the fifth N-type doping region and the sixth N-type doping region are both located on a side of the second P-type doping region away from the substrate, one side of the fifth N-type doping region contacts the P-well region, and the other side contacts the sixth N-type doping region and a sidewall of the first-level wide trench, a side of the sixth N-type doping region away from the fifth N-type doping region contacts the first P-type doping region, and the sixth N-type doping region contacts a bottom wall of the first-level wide trench; The P-well region includes a third P-type doping region and a fourth P-type doping region, the third P-type doping region is located on a side of the second N-type doping region away from the substrate, and one side of the third P-type doping region is in contact with the third N-type doping region, and the other side is in contact with the fifth N-type doping region and the second P-type doping region at the same time, the fourth P-type doping region is located on a side of the third P-type doping region away from the substrate, and one side of the fourth P-type doping region is in contact with the fourth N-type doping region, and the other side is in contact with the fifth N-type doping region.

7. The semiconductor device according to claim 6, wherein: A distance H1 between the second P-type doping region and the first N-type doping region and a distance H2 between the third P-type doping region and a surface of the second P-type doping region close to the substrate satisfy the following relationship: H1>3H2.

8. The semiconductor device according to claim 6, wherein: The fourth N-type doping region is low-doped, and a height H3 of the third N-type doping region, a height H4 of the fourth N-type doping region, and a width W of the fourth N-type doping region satisfy the following relationship: (H3+H4)>2W.

9. The semiconductor device according to claim 6, wherein: The thickness L1 of the first interlayer dielectric layer is the same as the thickness L3 of the second interlayer dielectric layer. The fifth N-type doped region is in contact with both the sidewall and bottom wall of the first-level wide trench. The second-level narrow trench is located in the sixth N-type doped region. The distance L4 between the second-level narrow trench and the fifth N-type doped region is equal to the distance L5 between the second-level narrow trench and the first P-type doped region. The width W1 of the sidewall portion of the fifth N-type doped region joined to the first-level wide trench, the height H6 of the bottom wall portion of the fifth N-type doped region joined to the first-level wide trench, and the depth Hz of the second-level narrow trench are equal in each other. The height H5 of the sidewall portion of the fifth N-type doped region joined to the first-level wide trench is the same as the width W2 of the bottom wall portion of the fifth N-type doped region joined to the first-level wide trench.

10. A method for manufacturing a semiconductor device, for manufacturing the semiconductor device according to any one of claims 1 to 9, characterized in that: The production method comprises the following steps: providing a substrate; forming a first epitaxial layer based on the surface of the substrate; A second epitaxial layer is formed on the surface of the first epitaxial layer, and a first-level wide trench is formed on the surface of the second epitaxial layer, wherein a P-well region, an N-doped region, and a P-doped region are formed by ion implantation on a surface of the second epitaxial layer away from the substrate, two sides of the N-doped region are in contact with the P-well region and the P-doped region, respectively, the N-doped region is in contact with sidewalls and a bottom wall of the first-level wide trench, and the P-doped region is in contact with the bottom wall of the first-level wide trench; Forming a gate oxide layer in contact with the N-doped region based on a surface of the second epitaxial layer away from the substrate; A polysilicon layer is formed on a surface of the gate oxide layer away from the substrate, wherein the sidewalls of the gate oxide layer, the sidewalls of the polysilicon layer, and the sidewalls of the first-level wide trench are flush with each other; forming a barrier layer based on the surface of the polysilicon layer, wherein the barrier layer extends to the bottom wall of the first-level wide trench and simultaneously covers the sidewalls of the polysilicon layer, the sidewalls of the gate oxide layer, and the sidewalls of the first-level wide trench; Fabricating an ohmic contact layer based on the surfaces of the P-doped region and the N-doped region; forming a first metal layer based on the surfaces of the barrier layer and the ohmic contact layer; A second metal layer is formed based on a surface of the substrate away from the first epitaxial layer.

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