Enhanced multilayer ceramic silicon carbide VDMOS and preparation method thereof

Abstract

The present invention relates to the field of MOS semiconductor technology and discloses an enhanced multilayer ceramic silicon carbide VDMOS and a preparation method thereof. The invention comprises a plurality of mutually parallel MOS cells, wherein each MOS cell includes a drain, a semiconductor epitaxial layer, a source, and a gate; the semiconductor epitaxial layer includes an N substrate layer, an N drift layer, a P+ layer, a P well layer, and an N well layer; the gate includes a left gate, a ceramic dielectric, and a right gate, wherein the ceramic dielectric is located between the left and right gates; a highly doped N+ layer is formed inside the N drift layer by ion implantation, and the cross-sectional profile of the highly doped N+ layer is "U"-shaped. The present invention utilizes a "U"-shaped highly doped N+ layer design to expand the lateral carrier transmission path, significantly improving the on-state current density and switching speed; combined with a low-doped N-layer, the electric field distribution is balanced, reducing edge distortion, and enhancing the breakdown voltage and device reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of MOS semiconductors, and in particular to an enhanced multilayer ceramic silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide (SiC) VDMOS devices, due to their advantages such as high voltage resistance, high-temperature stability, and low conduction losses, are widely used in new energy and power electronics. However, existing technologies still face difficulties in balancing on-resistance and voltage resistance, as well as insufficient dynamic performance. To address these challenges, an innovative device structure and fabrication method is urgently needed to optimize carrier transport paths, enhance electric field distribution uniformity, and improve insulation performance to meet the demand for efficient and reliable SiC power devices in modern power electronics systems.

[0003] An existing patent discloses a method for manufacturing a shielded-gate trench MOSFET with a high-k dielectric (publication number CN115810546A). The method includes the following steps: growing an epitaxial layer above a substrate; forming a hard mask structure consisting of a first oxide layer, a silicon nitride dielectric layer, and a second oxide layer stacked in sequence; forming a trench by photolithography; depositing a sidewall oxide layer within the trench; depositing and etching back source polysilicon; and wet etching the sidewall oxide layer to a target depth. The technology disclosed in this patent suffers from issues such as heat loss due to current crowding, poor thermal stability of the gate insulation material (e.g., increased SiO2 leakage current at high temperatures), and switching losses caused by parasitic thyristor effects, which limit the device's reliability and efficiency in high-power, high-frequency, and extreme environments. Summary of the Invention

[0004] In order to solve the existing technical problems, the present invention provides an enhanced multi-layer ceramic silicon carbide VDMOS and a preparation method thereof, which solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, an enhanced multilayer ceramic silicon carbide VDMOS is provided, comprising a plurality of mutually parallel MOS cells, wherein each MOS cell comprises a drain, a semiconductor epitaxial layer, a source, and a gate; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P+ layer, a P well layer, and an N well layer; the gate comprises a left gate, a ceramic dielectric, and a right gate, wherein the ceramic dielectric is located between the left and right gates;

[0006] A highly doped N+ layer is formed inside the N drift layer by ion implantation. The cross-section of the highly doped N+ layer is in a U shape, and the left and right ends of the highly doped N+ layer are only in contact with the P well layer.

[0007] Furthermore, the ceramic medium is one of aluminum oxide and silicon nitride.

[0008] Furthermore, a low-doped N-layer 1 is formed inside the high-doped N+ layer by ion implantation, wherein the low-doped N-layer 1 divides the high-doped N+ layer into two parts, a left part and a right part.

[0009] Furthermore, a low-doped N-layer 2 is formed inside the high-doped N+ layer by ion implantation, wherein the low-doped N-layer 2 penetrates to the bottom of the N drift layer and contacts the N substrate layer.

[0010] Furthermore, a low-doped P-layer 2 is formed in the middle region of the N substrate layer in a single MOS cell by ion implantation, wherein the top of the low-doped P-layer 2 is in contact with the N drift layer.

[0011] Furthermore, a low-doped P-layer 1 is formed in the middle region of the N substrate layer in a single MOS cell by ion implantation, wherein the top of the low-doped P-layer 1 penetrates the N drift layer and contacts the high-doped N+ layer.

[0012] A method for preparing an enhanced multilayer ceramic silicon carbide VDMOS includes:

[0013] S1. Growing an N drift layer, a P+ layer, a P well layer, and an N well layer in sequence on the N substrate layer, and using a chemical vapor deposition process to control the thickness and doping concentration of each layer;

[0014] S2. Form a highly doped N+ layer with a U-shaped cross section in the N drift layer by ion implantation technology, and ensure that its left and right ends only contact the P well layer;

[0015] S3, performing ion implantation inside the highly doped N+ layer to form a low doped N- layer 1, thereby separating the highly doped N+ layer into two parts, a left part and a right part;

[0016] S4, further performing ion implantation inside the highly doped N+ layer to form a low doped N- layer 2, so that it penetrates to the bottom of the N drift layer and contacts the N substrate layer;

[0017] S5, performing two ion implantations in the middle region of the N substrate layer;

[0018] S6. Depositing a metal layer on the surface of the P-well layer and the N-well layer to form a left gate and a right gate; depositing aluminum oxide or silicon nitride as a ceramic dielectric between the two, and controlling the uniformity and insulation performance of the dielectric layer by chemical vapor deposition;

[0019] S7. Form electrode contacts of the drain, source and gate through photolithography and metallization processes.

[0020] Furthermore, in step S5, two ion implantations are performed in the middle region of the N substrate layer respectively as follows:

[0021] 1) Form a low-doped P- layer, so that its top penetrates the N drift layer and contacts the highly doped N+ layer;

[0022] 2) Form a low-doped P-layer 2 so that its top contacts the N drift layer.

[0023] The present invention provides an enhanced multilayer ceramic silicon carbide VDMOS and a preparation method thereof. Compared with the prior art, the present method achieves the following effects:

[0024] 1. The present invention adopts a "U"-shaped highly doped N+ layer design to expand the lateral carrier transmission path, significantly improving the on-current density and switching speed; combined with a low-doped N- layer to balance the electric field distribution, reduce edge distortion, and enhance the breakdown voltage and device reliability.

[0025] 2. The present invention optimizes current distribution and reduces current crowding effect during dynamic conduction by introducing a vertical low-resistance path, that is, a low-doped N-layer II penetrating to the substrate, and is suitable for high-power and high-temperature environments.

[0026] 3. The present invention uses aluminum oxide or silicon nitride as a ceramic medium and combines it with a chemical vapor deposition process to improve the insulation between gates, reduce leakage current, optimize the electric field distribution, and avoid the risk of local breakdown.

[0027] 4. The present invention forms a local PN junction through a low-doped P-layer design, which reduces the accumulation of reverse recovery charge and reduces switching losses; at the same time, it optimizes the lateral current distribution, avoids the parasitic thyristor effect, and improves the safety and life in high-voltage applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a schematic structural diagram of Example 1 of the present invention;

[0029] Figure 2 This is a schematic structural diagram of Example 2 of the present invention;

[0030] Figure 3 This is a schematic structural diagram of Example 3 of the present invention;

[0031] Figure 4 This is a schematic structural diagram of Embodiment 4 of the present invention;

[0032] Figure 5 This is a structural diagram of Example 5 of the present invention.

[0033] In the figure: 1. Drain; 2. N substrate layer; 3. N drift layer; 4. Source; 5. P+ layer; 6. P well layer; 7. N well layer; 8. Gate; 9. Highly doped N+ layer; 10. Low-doped N-layer 1; 11. Low-doped N-layer 2; 12. Low-doped P-layer 1; 13. Low-doped P-layer 2; 81. Left gate; 82. Ceramic dielectric; 83. Right gate. DETAILED DESCRIPTION

[0034] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] like Figure 1-5 According to one aspect of the present invention, a method for preparing an enhanced multilayer ceramic silicon carbide VDMOS is provided.

[0036] Step 1: On the N substrate layer 2, the N-drift layer 3, P+ layer 5, P-well layer 6, and N-well layer 7 are sequentially grown using chemical vapor deposition (CVD) to control the thickness and doping concentration of each layer. This step, through layer-by-layer epitaxial growth, ensures the uniformity and interface quality of the semiconductor epitaxial structure, laying the foundation for subsequent processes. The high-precision control capability of the CVD process optimizes the electrical properties of each layer, reducing the on-resistance of the N-drift layer and enhancing the carrier injection efficiency of the P-well layer, thereby improving the overall voltage resistance and switching response speed of the device.

[0037] Step 2: Ion implantation is used to form a highly doped N+ layer 9 with a "U"-shaped cross-section within the N-drift layer 3, ensuring that its left and right ends contact only the P-well layer 6. This "U"-shaped structure significantly increases the on-state current density by expanding the lateral carrier transport path. Furthermore, the precise contact design between the highly doped N+ layer 9 and the P-well layer 6 suppresses leakage current, optimizes the electric field distribution, and avoids the risk of localized breakdown, thereby enhancing the reverse blocking capability and reliability of the device.

[0038] Step 3: Ion implantation is performed within the highly doped N+ layer 9 to form a low-doped N- layer 10, thereby separating the highly doped N+ layer 9 into a left and right portion. The introduction of the low-doped layer balances the electric field strength in the highly doped region, reducing edge electric field distortion and thereby increasing the breakdown voltage. Furthermore, by adjusting the concentration distribution of the low-doped layer, the balance between on-resistance and withstand voltage performance can be optimized, making it suitable for high-frequency, high-power scenarios while also reducing the device's dynamic losses.

[0039] Step 4: Ion implantation is further performed within the highly doped N+ layer 9 to form a low-doped N-layer 2 11, which penetrates to the bottom of the N-drift layer 3 and contacts the N substrate layer 2. This design provides a vertical low-resistance path for current, significantly reducing on-resistance and heat loss. The low-doped N-layer 2 11 also suppresses current crowding during dynamic conduction, improving the device's current sharing capability and high-temperature stability. It is suitable for applications with stringent thermal management requirements, such as electric vehicles and industrial power supplies.

[0040] Step 5: Perform two ion implantations in the middle region of the N substrate layer 2, specifically:

[0041] 1) Form a low-doped P- layer 12, with its top penetrating the N drift layer 3 and contacting the high-doped N+ layer 9;

[0042] 2) forming a low-doped P-layer 13, with its top in contact with the N-drift layer 3;

[0043] The low-doped P-layer 12 creates a continuous carrier transport channel, optimizing lateral current distribution and reducing on-state voltage drop. The low-doped P-layer 2 13 forms a localized PN junction, suppressing reverse recovery charge accumulation and reducing switching losses. The synergistic effect of these two significantly enhances the device's dynamic performance and radiation resistance, making it suitable for high-voltage switching and extreme environment applications.

[0044] Step 6: Deposit a metal layer on the surfaces of the P-well layer 6 and the N-well layer 7 to form the left gate 81 and the right gate 83. Aluminum oxide or silicon nitride is deposited between them as a ceramic dielectric 82. Chemical vapor deposition is used to control the uniformity and insulation properties of the dielectric layer. The high insulation and thermal stability of the ceramic dielectric 82 effectively isolate the left and right gates 8, reducing gate 8 leakage current and optimizing the electric field distribution. Controlling the uniformity of the dielectric layer through chemical vapor deposition further enhances the device's withstand voltage and long-term reliability, while also providing excellent insulation protection for high-frequency operation.

[0045] Step 7: Form electrode contacts of the drain 1 , source 4 and gate 8 through photolithography and metallization processes.

[0046] Example 1

[0047] like Figure 1As shown, the enhanced multilayer ceramic silicon carbide VDMOS is composed of several parallel MOS cells. Each MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 4, and a gate 8. The semiconductor epitaxial layer includes an N substrate layer 2, an N drift layer 3, a P+ layer 5, a P well layer 6, and an N well layer 7. The gate 8 comprises a left gate 81, a ceramic dielectric 82, and a right gate 83. The ceramic dielectric 82 is located between the left and right gates 81 and 83. The ceramic dielectric 82 is composed of either aluminum oxide or silicon nitride. By introducing the ceramic dielectric 82 (aluminum oxide or silicon nitride) into the gate structure, the left gate 81 is isolated from the right gate 83, significantly improving the device's withstand voltage and insulation performance. The high thermal stability and chemical inertness of the ceramic dielectric 82 effectively reduce gate 8 leakage current, while optimizing the electric field distribution and reducing the risk of local electric field concentration.

[0048] A highly doped N+ layer 9 is formed within the N-drift layer 3 through ion implantation. Its cross-section is U-shaped, with its left and right ends contacting only the P-well layer 6. This U-shaped design makes the carrier transport path more efficient, further improving the device's conduction characteristics and switching speed.

[0049] Example 2

[0050] like Figure 2 As shown, a low-doped N-layer 10 is formed inside the highly doped N+ layer 9 by ion implantation, wherein the low-doped N-layer 10 divides the highly doped N+ layer 9 into two parts, left and right. A low-doped N-layer 10 is formed inside the highly doped N+ layer 9 by ion implantation, separating the highly doped region into two parts, left and right. This layered structure can balance the electric field strength and avoid electric field distortion at the edge of the highly doped region, thereby enhancing the breakdown voltage and reliability of the device. At the same time, the introduction of the low-doped layer can adjust the carrier concentration distribution and optimize the balance between on-resistance and withstand voltage performance, making it suitable for high-frequency, high-power applications.

[0051] Example 3

[0052] like Figure 3 As shown, a low-doped N-layer 11 is formed within the highly doped N+ layer 9 through ion implantation. The low-doped N-layer 11 penetrates to the bottom of the N-drift layer 3 and contacts the N substrate layer 11. The low-doped N-layer 11 is implanted within the highly doped N+ layer 9, penetrating to the bottom of the N-drift layer 3 and contacting the N substrate layer 2. This structure provides a vertical low-resistance path for current, significantly reducing on-resistance and heat loss. Furthermore, the low-doped N-layer 11 suppresses current crowding during dynamic conduction, improving the device's current sharing capability and high-temperature stability, making it suitable for high-reliability applications such as electric vehicles and industrial power supplies.

[0053] Example 4

[0054] like Figure 4 As shown, a low-doped P-type layer 13 is formed in the middle region of the N substrate layer 2 in a single MOS cell through ion implantation, with the top of the low-doped P-type layer 13 in contact with the N drift layer 3. The low-doped P-type layer 13 is implanted in the middle region of the N substrate 2, with its top in contact with the N drift layer 3. This P-type layer forms a localized PN junction, effectively suppressing reverse recovery charge accumulation and reducing switching losses. Furthermore, P-type doping regulates the carrier recombination rate between the substrate and the drift layer, reducing leakage current and improving the device's radiation resistance, making it suitable for use in extreme environments such as aerospace and nuclear power.

[0055] Example 5

[0056] like Figure 5 As shown, a low-doped P-layer 12 is formed in the middle region of the N substrate layer 2 in a single MOS cell through ion implantation. The top of the low-doped P-layer 12 penetrates the N drift layer 3 and contacts the highly doped N+ layer 9. A low-doped P-layer 12 is implanted in the middle region of the N substrate 2, with its top penetrating the N drift layer 3 and contacting the highly doped N+ layer 9. This design optimizes lateral current distribution and reduces voltage drop during conduction by forming a continuous carrier transport channel. Furthermore, the contact between the P-type layer and the N+ layer enhances the reverse blocking capability of the device, preventing the parasitic thyristor effect and significantly improving the safety and lifespan of the device in high-voltage switching applications.

[0057] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. An enhanced multilayer ceramic silicon carbide VDMOS, comprising a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain (1), a semiconductor epitaxial layer, a source (4) and a gate (8), wherein the gate (8) is located in a gate trench; the semiconductor epitaxial layer comprises an N substrate layer (2), an N drift layer (3), a P+ layer (5), a P well layer (6) and an N well layer (7), wherein the top of the P+ layer (5) contacts the source (4), the right end of the P+ layer (5) contacts the left end of the P well layer (6), and the right end of the P well layer (6) extends to the left side of the gate (8) and contacts the left side of the gate trench, characterized in that: The gate (8) comprises a left gate (81), a ceramic dielectric (82) and a right gate (83), wherein the ceramic dielectric (82) is located in the middle of the left gate (81) and the right gate (83); A highly doped N+ layer (9) is formed inside the N drift layer (3) by ion implantation, the cross-sectional profile of the highly doped N+ layer (9) being in a "U" shape, the highly doped N+ layer (9) being located below the gate trench and in contact with the bottom of the gate trench, and the left and right ends of the highly doped N+ layer (9) only in contact with the P well layer (6); A low-doped N-layer (10) is formed inside the high-doped N+ layer (9) by ion implantation. The high-doped N+ layer (9) is located directly below the P-well layer (6) and in contact with the P-well layer (6). The low-doped N-layer (10) is located directly below the gate (8) and in contact with the gate trench. The low-doped N-layer (10) divides the high-doped N+ layer (9) into two parts, a left part and a right part.

2. The enhanced multi-layer ceramic silicon carbide VDMOS according to claim 1, characterized in that: The ceramic medium (82) is one of aluminum oxide and silicon nitride.

3. The enhanced multi-layer ceramic silicon carbide VDMOS according to claim 1, wherein: A low-doped N-layer 2 (11) is formed inside the high-doped N+ layer (9) by ion implantation, wherein the low-doped N-layer 2 (11) penetrates to the bottom of the N drift layer (3) and contacts the N substrate layer.

4. The enhanced multi-layer ceramic silicon carbide VDMOS according to claim 1, wherein: A low-doped P-layer 2 (13) is formed in the middle region of the N substrate layer (2) in a single MOS cell by ion implantation, wherein the top of the low-doped P-layer 2 (13) is in contact with the N drift layer (3).

5. The enhanced multi-layer ceramic silicon carbide VDMOS according to claim 1, characterized in that: A low-doped P-layer (12) is formed in the middle region of the N substrate layer (2) in a single MOS cell by ion implantation, wherein the top of the low-doped P-layer (12) penetrates the N drift layer (3) and contacts the high-doped N+ layer (9).

6. A method for preparing an enhanced multilayer ceramic silicon carbide VDMOS, characterized in that: Applicable to the silicon carbide VDMOS according to any one of claims 1 to 5, the preparation method of the enhanced multilayer ceramic silicon carbide VDMOS comprises: S1, sequentially growing an N drift layer (3), a P+ layer (5), a P well layer (6), and an N well layer (7) on an N substrate layer (2), and using a chemical vapor deposition process to control the thickness and doping concentration of each layer; S2. Forming a highly doped N+ layer (9) having a "U"-shaped cross section in the N drift layer (3) by ion implantation technology, and ensuring that the left and right ends thereof are in contact only with the P well layer (6); S3, performing ion implantation inside the highly doped N+ layer (9) to form a low doped N- layer (10), thereby separating the highly doped N+ layer (9) into two parts, the left and the right; S4, performing ion implantation inside the highly doped N+ layer (9) to form a low doped N- layer 2 (11), so that the layer penetrates to the bottom of the N drift layer (3) and contacts the N substrate layer (2); S5, performing two ion implantations in the middle region of the N substrate layer (2); S6, depositing a metal layer on the surface of the P-well layer (6) and the N-well layer (7) to form a left gate (81) and a right gate (83); and depositing aluminum oxide or silicon nitride between the two as a ceramic dielectric (82); S7. Electrode contacts of the drain (1), source (4) and gate (8) are formed by photolithography and metallization processes.

7. The method for preparing the enhanced multi-layer ceramic silicon carbide VDMOS according to claim 6, characterized in that: In step S5, two ion implantations are performed in the middle region of the N substrate layer (2) respectively, specifically: 1) forming a low-doped P- layer (12) so that its top penetrates the N drift layer (3) and contacts the high-doped N+ layer (9); 2) forming a low-doped P-layer 2 (13) so that its top is in contact with the N drift layer (3).

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