Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate; the channel structure is located on the substrate, the channel structure comprises a first middle layer, a channel layer and a second middle layer which are arranged in a stacked mode, and the channel structure comprises a gate region, a source region and a drain region, and the source region and the drain region are located at the two ends of the gate region; the first N-type heavily doped layer is located between the substrate and the channel structure, the second N-type heavily doped layer is located on the side, away from the substrate, of the channel structure, and the first N-type heavily doped layer and the second N-type heavily doped layer are located on the side, away from the substrate, of the channel structure. Projections of the first N-type heavily doped layer and the second N-type heavily doped layer on the channel structure are located in the gate region; and the grid electrode is positioned on the grid electrode region and covers the side walls of the first N-type heavily doped layer, the channel layer and the second N-type heavily doped layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] Gallium nitride (GaN) is a representative of the third-generation wide-bandgap semiconductors and has attracted extensive attention. Its superior properties are mainly manifested in: having a high electron mobility and a high two-dimensional electron gas (2DEG) concentration. In addition, the gallium nitride (GaN) material has stable chemical properties, high temperature resistance, and corrosion resistance, and has innate advantages in the fields of high frequency, high power, and radiation resistance applications.

[0003] In planar devices, the current flows along the plane within the quantum well formed by the heterojunction structure. Under reverse bias conditions, the distribution of the electric field is usually uneven. Generally speaking, serious electric field concentration will occur at the edge of the gate or the drain, and the electric field at this location will increase rapidly with the increase of the reverse voltage. When the critical breakdown field strength is reached, the device is broken down.

[0004] A high breakdown voltage means that the device has a larger operating voltage range, can obtain a higher power density, and the reliability of the device is higher. Therefore, how to improve the gate control ability and breakdown voltage of the device is a key concern for electronic device researchers. Summary of the Invention

[0005] In view of this, the present invention provides a semiconductor structure and a method for manufacturing the same. This semiconductor structure is simpler than the usual fully surrounding gate field effect transistor structure, and the corresponding manufacturing method is also simpler.

[0006] In a first aspect, the present invention provides a semiconductor structure, including:

[0007] A substrate;

[0008] A channel structure located on the substrate, the channel structure including a first intermediate layer, a channel layer, and a second intermediate layer stacked on the substrate, the channel structure including a gate region and a source region and a drain region located at both ends of the gate region;

[0009] A first N-type heavily doped layer and a second N-type heavily doped layer, the first N-type heavily doped layer being located between the substrate and the channel structure, the second N-type heavily doped layer being located on a side of the channel structure away from the substrate, wherein the projections of the first N-type heavily doped layer and the second N-type heavily doped layer on the channel structure are located within the gate region;

[0010] And a gate located within the gate region, the gate covering the sidewalls of the first N-type heavily doped layer, the channel structure, and the second N-type heavily doped layer.

[0011] Optionally, the gate is in ohmic contact with the first N-type heavily doped layer and the second N-type heavily doped layer.

[0012] Optionally, the semiconductor structure includes a plurality of the channel structures and a third N-type heavily doped layer, and the plurality of channel structures are stacked on the substrate;

[0013] The third N-type heavily doped layer is located between two adjacent ones of the plurality of channel structures, and a projection of the third N-type heavily doped layer on the channel structure is located within the gate region.

[0014] Optionally, the plurality of channel structures share the gate, the gate covers sidewalls of the third N-type heavily doped layer, and the gate is in ohmic contact with the third N-type heavily doped layer.

[0015] Optionally, further comprising:

[0016] A dielectric layer located on the gate region, the dielectric layer at least covers sidewalls of the channel layer, and the dielectric layer is located between the gate and the channel layer.

[0017] Optionally, the channel layer is a nanowire or nanosheet structure.

[0018] Optionally, the material of the channel structure is a group III nitride material.

[0019] Optionally, the materials of the first intermediate layer and the second intermediate layer are AlN;

[0020] The material of the channel layer includes any one of GaN, AlGaN, InGaN or AlInGaN.

[0021] Optionally, a source electrode and a drain electrode respectively located in the source region and the drain region, the source electrode and the drain electrode surround and wrap the channel layer.

[0022] Optionally, the channel layer is an N-type lightly doped layer, and the N-type ion doping concentration of the channel layer is less than 1E18.

[0023] According to another aspect of the present invention, there is also provided a method for manufacturing a semiconductor structure, including:

[0024] Providing a substrate;

[0025] A first N-type heavily doped layer, a channel structure, and a second N-type heavily doped layer are sequentially formed on the substrate. The formation of the channel structure includes forming a stacked first intermediate layer, a channel layer, and a second intermediate layer on the first N-type heavily doped layer. The channel structure includes a gate region and source and drain regions located at both ends of the gate region.

[0026] The first N-type heavily doped layer and the second N-type heavily doped layer that are projected onto the source region and the drain region within the channel structure are removed.

[0027] A gate is formed within the gate region, and the gate covers the sidewalls of the first N-type heavily doped layer, the channel structure, and the second N-type heavily doped layer.

[0028] Optionally, before forming the gate within the gate region, a dielectric layer is formed on the sidewalls of the first N-type heavily doped layer, the channel structure, and the second N-type heavily doped layer, and on the top of the second N-type heavily doped layer. The dielectric layer is patterned to expose the first N-type heavily doped layer and the second N-type heavily doped layer within the gate region. The gate is connected to the first N-type heavily doped layer and the second N-type heavily doped layer, and the gate is connected to the channel structure through the dielectric layer.

[0029] Optionally, after forming the dielectric layer on the sidewalls of the first N-type heavily doped layer, the channel structure, and the second N-type heavily doped layer, and on the top of the second N-type heavily doped layer, it includes:

[0030] The dielectric layer is patterned to expose the first N-type heavily doped layer and the second N-type heavily doped layer within the source region and the drain region, and the first N-type heavily doped layer and the second N-type heavily doped layer that are projected onto the source region and the drain region within the channel structure are removed.

[0031] Optionally, before removing the first N-type heavily doped layer and the second N-type heavily doped layer that are projected onto the source region and the drain region within the channel structure,

[0032] The patterning of the dielectric layer to expose the first N-type heavily doped layer and the second N-type heavily doped layer within the source region and the drain region further includes exposing the first intermediate layer and the second intermediate layer within the source region and the drain region.

[0033] After removing the first N-type heavily doped layer and the second N-type heavily doped layer that are projected onto the source region and the drain region within the channel structure, it further includes removing the first intermediate layer and the second intermediate layer within the source region and the drain region.

[0034] Optionally, after removing the first intermediate layer and the second intermediate layer located in the source region and the drain region, the method further includes

[0035] Fabricating a source and a drain in the source region and the drain region respectively, wherein the source and the drain surround the channel layer.

[0036] Optionally, the gate has an ohmic contact with the first N-type heavily doped layer and the second N-type heavily doped layer.

[0037] Optionally, before fabricating the dielectric layer on the sidewalls of the first N-type heavily doped layer, the channel structure, and the second N-type heavily doped layer, and on the top of the second N-type heavily doped layer, the method further includes:

[0038] Patterning the first N-type heavily doped layer, the channel structure, and the second N-type heavily doped layer, such that the channel layer forms a nanowire or nanosheet structure.

[0039] Optionally, fabricating the channel structure includes fabricating a plurality of channel structures, and the plurality of channel structures are stacked on the substrate;

[0040] Fabricating the plurality of channel structures further includes fabricating a third N-type heavily doped layer, the third N-type heavily doped layer is fabricated between two adjacent channel structures among the plurality of channel structures, the gate is connected to the third N-type heavily doped layer, and the gate has an ohmic contact with the third N-type heavily doped layer.

[0041] Optionally, after fabricating the plurality of channel structures, when removing the first N-type heavily doped layer and the second N-type heavily doped layer whose projections on the channel structures are located in the source region and the drain region, the method further includes:

[0042] Removing the third N-type heavily doped layer whose projection on the channel structure is located in the source region and the drain region.

[0043] Optionally, after fabricating the channel layer, the fabrication method further includes:

[0044] Performing N-type doping on the channel layer, and the doping concentration of the N-type ions is less than 1E18.

[0045] In the semiconductor structure provided by the present invention, after the gate is connected to the first N-type heavily doped layer and the second N-type heavily doped layer, a gate structure is formed, and the gate structure surrounds and coats the sidewalls of the channel structure. In this way, the gate control area is increased, the electric field distribution becomes more uniform, the control ability of the gate over the channel layer is greatly improved, the breakdown voltage is effectively increased, the leakage in the gate region is reduced, the dynamic characteristics are improved, and the working efficiency and linearity of the semiconductor structure are improved. Secondly, in the semiconductor structure provided by the present invention, the first intermediate layer, the channel layer, and the second intermediate layer are sequentially formed on the first N-type heavily doped layer to ensure the crystal quality of the channel layer and the device performance. Furthermore, the first N-type heavily doped layer and the second N-type heavily doped layer replace the metal material to act as a part of the gate structure, and the channel structure can be directly formed on the first N-type heavily doped layer. Therefore, the semiconductor structure provided by the present invention greatly reduces the preparation difficulty of the gate structure surrounding and coating the sidewalls of the channel layer and effectively reduces the production cost. Description of the Drawings

[0046] Figure 1 It is a schematic structural diagram of the semiconductor structure provided by Embodiment 1 of the present invention.

[0047] Figure 2 It is a schematic cross-sectional diagram of the gate region of the semiconductor structure provided by Embodiment 1 of the present invention.

[0048] Figure 3 It is a schematic structural diagram of the semiconductor structure provided by Embodiment 2 of the present invention.

[0049] Figure 4 It is a schematic cross-sectional diagram of the gate region of the semiconductor structure provided by Embodiment 2 of the present invention.

[0050] Figures 5 - 11 It is a schematic diagram of the preparation process of the semiconductor structure provided by Embodiment 3 of the present invention.

[0051] Figure 12 It is a schematic diagram of the middle of the preparation process of the semiconductor structure provided by Embodiment 4 of the present invention.

[0052] Figure 13 It is another schematic diagram of the middle of the preparation process of the semiconductor structure provided by Embodiment 4 of the present invention. Detailed Description of the Embodiments

[0053] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present invention as detailed in the appended claims.

[0054] The terms used in the present invention are for the purpose of describing particular embodiments only and are not intended to limit the present invention. The singular forms "a", "the" and "said" used in the present invention and the appended claims are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0055] It should be understood that although the terms first, second, third, etc. may be used in the present invention to describe various elements, these elements should not be limited to these terms. These terms are only used to distinguish elements of the same type from each other. For example, without departing from the scope of the present invention, the first intermediate layer may also be referred to as the second intermediate layer, and similarly, the second intermediate layer may also be referred to as the first intermediate layer.

[0056] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments of the invention. As such, variations due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, embodiments of the present invention should not be construed as limited to the particular shapes of regions shown herein but include deviations in shapes due to, for example, manufacturing. For example, an implantation region shown as rectangular will typically have rounded or curved features at its edges and / or an implantation concentration gradient rather than a binary change from the implanted region to the non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantant passes during implantation. Thus, the regions shown in the figures are substantially schematic in nature, and their shapes are not intended to depict the actual shape of the regions of the device and are not intended to limit the scope of the present invention.

[0057] Embodiment 1

[0058] Embodiment 1 of the present invention provides a semiconductor structure. Figure 1 is a schematic structural view of the semiconductor structure provided by Embodiment 1 of the present invention. As Figure 1As shown, the semiconductor structure includes: a substrate 1; a channel structure 2 located on the substrate 1, the channel structure 2 including a first intermediate layer 21, a channel layer 22, and a second intermediate layer 23 stacked on the substrate 1, the channel structure 2 including a gate region and source and drain regions at both ends of the gate region; a first N-type heavily doped layer 31 and a second N-type heavily doped layer 32, the first N-type heavily doped layer 31 being located between the substrate 1 and the channel structure 2, and the second N-type heavily doped layer 32 being located on the side of the channel structure 2 away from the substrate 1. Among them, the projections of the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 on the channel structure 2 are located within the gate region; a gate 4 located within the gate region, the gate 4 being connected to the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32, that is, the gate 4 covers the sidewalls of the channel structure 2, the sidewalls of the first N-type heavily doped layer 31, and the sidewalls of the second N-type heavily doped layer 32 and the surface of the second N-type heavily doped layer 32 on the side away from the substrate 1. In other embodiments, the gate 4 may not cover the top of the second N-type heavily doped layer 32; or, the semiconductor structure may omit the second N-type heavily doped layer 32, and the gate 4 directly covers the side of the second intermediate layer 23 away from the substrate 1.

[0059] Optionally, the semiconductor structure may further include a dielectric layer 9 located in the gate region, the dielectric layer 9 at least covering the sidewalls of the channel layer 22, and the dielectric layer 9 being located between the gate 4 and the channel structure 2. Further referring to Figure 2 , Figure 2 is a schematic cross-sectional view of the gate region of the semiconductor structure provided in the first embodiment of the present invention. In this embodiment, the dielectric layer 9 covers the sidewalls of the channel structure 2, and the gate 4 is connected to the sidewalls of the channel structure 2 through the dielectric layer 9. The dielectric layer 9 serves as a gate dielectric to reduce gate leakage and increase the breakdown voltage, thereby improving the reliability of the device. Optionally, the material of the dielectric layer 9 may be any one or a plurality of stacked materials of SiO2, SiN, or AlN.

[0060] As Figure 1 shown, the semiconductor structure further includes a source electrode 5 located in the source region and a drain electrode 6 located in the drain region. The first N-type heavily doped layer 31, the first intermediate layer 21, the second intermediate layer 23, and the second N-type heavily doped layer 32 in the source and drain regions at both ends of the channel structure 2 may be removed to expose the channel layer 22 in the source and drain regions, and the source electrode 5 and the drain electrode 6 surrounding and wrapping the channel layer 22 are formed on the exposed channel layer 22.

[0061] In the semiconductor structure provided by the present invention, the gate 4 is connected to the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 to form a gate structure, and the gate structure surrounds and coats the sidewalls of the channel structure 2, thus increasing the gate control area, making the electric field distribution more uniform, greatly improving the control ability of the gate 4 over the channel layer 22, effectively increasing the breakdown voltage, reducing the leakage current in the gate region, improving the dynamic characteristics, and improving the working efficiency and linearity of the semiconductor structure; Secondly, in the semiconductor structure provided by the present invention, the first intermediate layer 21, the channel layer 22, and the second intermediate layer 23 are sequentially formed on the first N-type heavily doped layer 31 to ensure the crystal quality of the channel layer 22 and ensure the device performance; Furthermore, the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 replace the metal material to act as part of the gate structure, and the channel structure 2 can be directly formed on the first N-type heavily doped layer 31. Therefore, the semiconductor structure provided by the present invention greatly reduces the preparation difficulty of the gate structure surrounding and coating the sidewalls of the channel layer 22 and effectively reduces the production cost.

[0062] The material of the substrate 1 can be Si, SiC, sapphire, or SOI (Silicon-On-Insulator), etc., and the present invention does not limit this.

[0063] The channel structure 2 includes a first intermediate layer 21, a channel layer 22, and a second intermediate layer 23 stacked. The first intermediate layer 21 and the second intermediate layer 23 can be dielectric material layers, and the channel layer 22 can be a semiconductor material so that a channel can be formed when the channel structure is working, enabling carriers to communicate between the source 5 and the drain 6 through the channel, realizing the conduction of the channel structure 2. The material of the channel structure 2 can include group III nitride materials. Optionally, the materials of the first intermediate layer 21 and the second intermediate layer 23 can include AlN, and the material of the channel layer 22 can include any one of GaN, AlGaN, InGaN, or AlInGaN. The present invention does not limit the material of the channel structure.

[0064] The materials of the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 are group III nitride materials. Optionally, the materials of the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 are GaN materials doped with heavily doped Si. Optionally, the doping concentration of the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 is greater than 1E18, and the present invention does not limit this. The gate 4, the source 5, and the drain 6 are usually metal materials, such as nickel, nickel-manganese alloy, etc., and the present invention does not limit this. Optionally, the gate 4 forms an ohmic contact with the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 to reduce the ohmic contact resistance and improve the gate control ability.

[0065] The heavy doping of the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 can be achieved by in-situ doping or implanting N-type ions (such as Si ions), and the doping concentration can be greater than or equal to 1E18. The present invention does not limit the implementation method and doping concentration of the heavy doping.

[0066] The channel layer 22 can be an N-type lightly doped layer. Similarly, the N-type lightly doped layer can be achieved by in-situ doping or implanting N-type ions (such as Si ions) to improve the electron transport rate. The doping concentration of the N-type ions can be less than 1E18, and the present invention does not limit this.

[0067] The first N-type heavily doped layer 31, the second N-type heavily doped layer 32 and the gate 4 are conductively connected to form a gate structure, and the gate structure forms a fully enclosed structure for the channel structure 2 to control the conduction and disconnection of the channel structure 2 by applying a voltage to the gate 4.

[0068] The projections of the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 on the channel structure 2 are located within the gate region. The first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 are conductively connected to the gate 4 to control the conduction and disconnection of the channel structure 2 by applying a voltage to the gate 4. Therefore, the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 act as part of the gate structure, and the first N-type heavily doped layer 31, the second N-type heavily doped layer 32 and the gate 4 are combined to form a gate structure to control the conduction and closing of the channel structure 2.

[0069] Optionally, the channel layer 22 is a nanowire or nanosheet structure.

[0070] In some embodiments, the semiconductor structure may further include a nucleation layer and / or a buffer layer between the substrate 1 and the first N-type heavily doped layer 31. The material of the nucleation layer can be, for example, AlN, AlGaN, etc., and the material of the buffer layer can include at least one of AlN, GaN, AlGaN, and AlInGaN. The nucleation layer can alleviate problems such as lattice mismatch and thermal mismatch between the epitaxially grown semiconductor layer and the substrate material, and the buffer layer can reduce the dislocation density and defect density of the epitaxially grown semiconductor layer and improve the crystal quality.

[0071] Embodiment 2

[0072] The content of Embodiment 2 is substantially the same as that of Embodiment 1, and the difference is only that, as Figure 3 and Figure 4 shown, Figure 3 is a schematic structural diagram of the semiconductor structure provided by Embodiment 2 of the present invention, Figure 4It is a schematic cross-sectional view of the gate region of the semiconductor structure provided in the second embodiment of the present invention. The semiconductor structure provided in the second embodiment includes a plurality of channel structures 2, and the plurality of channel structures 2 are stacked on the substrate 1. The number of the channel structures 2 can be two or more, and the present invention does not limit this.

[0073] The plurality of channel structures 2 stacked can save the space occupied by the structure, which is beneficial to fabricating devices with smaller sizes. Moreover, the multi-channel structure is beneficial to improving the channel electron transport efficiency of the semiconductor structure, and improving the linearity and stability of the device.

[0074] Specifically, the semiconductor structure further includes a third N-type heavily doped layer 33, and the third N-type heavily doped layer 33 is located between two adjacent channel structures 2 among the plurality of channel structures 2 (that is, above the second intermediate layer 23 of the lower channel structure 2 and below the first intermediate layer 21 of the upper channel structure 2), and the projection of the third N-type heavily doped layer 33 on the channel structure 2 is located within the gate region.

[0075] In this embodiment, the plurality of channel structures 2 share the gate 4, the gate 4 is connected to the third N-type heavily doped layer 33, and the gate 4 and the third N-type heavily doped layer 33 are in ohmic contact. The first N-type heavily doped layer 31, the second N-type heavily doped layer 32, and the third N-type heavily doped layer 33 act as part of the gate structure. The first N-type heavily doped layer 31, the second N-type heavily doped layer 32, and the third N-type heavily doped layer 33 are connected to the gate 4 to form a gate structure that surrounds and wraps each channel structure in the multi-channel structure, forming a fully enclosed structure for each channel structure 2, so as to control the conduction and cut-off of each channel structure 2 by the voltage applied on the gate 4.

[0076] The material of the third N-type heavily doped layer 33 can be the same as that of the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32.

[0077] As Figure 3 shown, in some embodiments, the plurality of channel structures share one gate, one source, and one drain.

[0078] In the semiconductor structure provided in this embodiment, after the gate 4 is connected to the first N-type heavily doped layer 31, the second N-type heavily doped layer 32, and the third N-type heavily doped layer 33, a gate structure is formed, and the gate structure surrounds and covers the sidewalls of each channel structure 2, thus increasing the gate control area, making the electric field distribution of each channel structure 2 more uniform, greatly improving the control ability of the gate 4 over each channel layer 22, effectively increasing the breakdown voltage, reducing the leakage in the gate region, improving the dynamic characteristics, and enhancing the working efficiency and linearity of the semiconductor structure; secondly, in the semiconductor structure provided by the present invention, the first intermediate layer 21, the channel layer 22, and the second intermediate layer 23 are sequentially formed on the first N-type heavily doped layer 31 to ensure the crystal quality of the channel layer 22 and the device performance; furthermore, the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 replace the metal material to act as a part of the gate structure, and the channel structure 2 can be directly formed on the first N-type heavily doped layer 31. Therefore, the semiconductor structure provided by the present invention greatly reduces the preparation difficulty of the gate structure surrounding and covering the sidewalls of the channel layer 22 and effectively reduces the production cost.

[0079] Embodiment III

[0080] Embodiment III provides a preparation method of the semiconductor structure provided in Embodiment I above, as Figures 5 to 11 shown Figures 5 - 11 FIG. is a schematic flowchart of the preparation process of the semiconductor structure provided in Embodiment III of the present invention. The preparation method includes: providing a substrate 1; sequentially preparing a first N-type heavily doped layer 31, a channel structure 2, and a second N-type heavily doped layer 32 on the substrate 1. Preparing the channel structure 2 includes preparing a first intermediate layer 21, a channel layer 22, and a second intermediate layer 23 which are stacked on the first N-type heavily doped layer 31; the channel structure 2 includes a gate region and source regions and drain regions located at both ends of the gate region; removing the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 whose projections on the channel structure 2 are located in the source regions and the drain regions; preparing a gate 4 in the gate region, the gate 4 covering the sidewalls of the first N-type heavily doped layer 31, the channel structure 2, and the second N-type heavily doped layer 32, and the gate 4 being connected to the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32. Optionally, the gate 4 may also cover the surface of the second N-type heavily doped layer 32 away from the substrate 1.

[0081] As Figure 5, a substrate 1 is provided; a first N-type heavily doped layer 31, a channel structure 2, and a second N-type heavily doped layer 32 are sequentially formed on the substrate 1. The channel structure 2 includes a first intermediate layer 21, a channel layer 22, and a second intermediate layer 23 which are stacked. The preparation processes of the first N-type heavily doped layer 31, the first intermediate layer 21, the channel layer 22, the second intermediate layer 23, and the second N-type heavily doped layer 32 may include: atomic layer deposition (ALD, Atomic layer deposition), or chemical vapor deposition (CVD, Chemical Vapor Deposition), or molecular beam epitaxy (MBE, Molecular Beam Epitaxy), or plasma enhanced chemical vapor deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition), or low pressure chemical vapor deposition (LPCVD, Low Pressure Chemical Vapor Deposition), or metal-organic chemical vapor deposition (MOCVD, Metal-Organic Chemical Vapor Deposition), or a combination thereof, and the present invention is not limited thereto. Optionally, when preparing the channel layer 22, the channel layer 22 may be N-type doped, and the doping concentration of N-type ions is less than 1E18, and the doping method may be in-situ doping or ion implantation, and this embodiment is not limited herein. The materials of the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 may be GaN materials with heavily doped Si. Optionally, the doping concentrations of the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 are greater than 1E18, and the present invention is not limited thereto.

[0082] See Figure 6 , optionally, after the first N-type heavily doped layer 31, the channel structure 2, and the second N-type heavily doped layer 32 are sequentially formed on the substrate 1, and the channel structure 2 includes a first intermediate layer 21, a channel layer 22, and a second intermediate layer 23 which are stacked, the first N-type heavily doped layer 31, the channel structure 2, and the second N-type heavily doped layer 32 are patterned so that the channel layer 22 forms a nanowire or nanosheet structure. In this embodiment, the material of the channel structure 2 is a group III nitride material. The materials of the first intermediate layer 21 and the second intermediate layer 23 may be dielectric materials. The materials of the first intermediate layer 21 and the second intermediate layer 23 are AlN, and the material of the channel layer 22 includes any one of GaN, AlGaN, InGaN, or AlInGaN. The present invention is not limited to the material of the channel structure 2.

[0083] See Figure 7, before forming the gate 4 in the gate region, a dielectric layer 9 is formed on the sidewalls of the first N-type heavily doped layer 31, the channel structure 2, and the second N-type heavily doped layer 32, as well as on the top of the second N-type heavily doped layer 32.

[0084] Further, referring to Figure 8 , the dielectric layer 9 is patterned to expose the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 located in the source region and the drain region. As Figure 9 shown, after patterning the dielectric layer 9 to expose the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 located in the source region and the drain region, the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 projected on the channel structure 2 in the source region and the drain region are removed. The first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 can be removed by wet etching.

[0085] Optionally, referring to Figure 8 , patterning the dielectric layer 9 to expose the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 located in the source region and the drain region further includes exposing the first intermediate layer 21 and the second intermediate layer 23 located in the source region and the drain region; further, as Figure 10 shown, after removing the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 projected on the channel structure 2 in the source region and the drain region, the first intermediate layer 21 and the second intermediate layer 23 located on the channel structure 2 in the source region and the drain region are also removed. The first intermediate layer 21 and the second intermediate layer 23 can be removed by dry etching.

[0086] As Figure 11 shown, after removing the first N-type heavily doped layer 31, the second N-type heavily doped layer 32, the first intermediate layer 21, and the second intermediate layer 23 located on the channel structure 2 in the source region and the drain region, the dielectric layer 9 is further patterned to expose the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 located in the gate region on the channel structure 2. Then, further referring to Figure 1 , the gate 4 is formed in the gate region. The gate 4 is connected to the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32, and the contact between the gate 4 and the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 is an ohmic contact. The gate 4 is connected to the channel structure 2 through the dielectric layer 9. The source 5 and the drain 6 are respectively formed in the source region and the drain region, and the source 5 and the drain 6 respectively surround the channel layer 22.

[0087] The manufacturing processes of the gate 4, the source 5, and the drain 6 can include electron beam evaporation, such as thermal evaporation, sputtering, etc., and the present invention is not limited thereto.

[0088] The material of the dielectric layer 9 can be any one or more laminated materials of SiO2, SiN or AlN. In this embodiment, the dielectric layer 9 can serve as a gate dielectric layer to further improve the gate electric field control ability. In addition, in the preparation process of the semiconductor structure, the dielectric layer 9 can also serve as an etching mask layer for the first N-type heavily doped layer 31, the second N-type heavily doped layer 32, the first intermediate layer 21 and the second intermediate layer 23, effectively simplifying the preparation process of the semiconductor structure, improving the preparation efficiency, and effectively reducing the preparation cost of the semiconductor structure.

[0089] The gate 4 is usually made of a metal material, such as nickel, nickel-manganese alloy, etc., and the present invention does not limit this. Optionally, the gate 4 forms an ohmic contact with the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 to reduce the ohmic contact resistance and improve the gate control ability.

[0090] In some embodiments, before epitaxially growing the first N-type heavily doped layer 31, a nucleation layer and a buffer layer can be sequentially grown on one side of the substrate 1 close to the first N-type heavily doped layer 31. The material of the nucleation layer can be, for example, AlN, AlGaN, etc., and the material of the buffer layer can include at least one of AlN, GaN, AlGaN, and AlInGaN. The preparation processes of the nucleation layer and the buffer layer can be similar to those of the first N-type heavily doped layer 31, the first intermediate layer 21, the channel layer 22, the second intermediate layer 23, and the second N-type heavily doped layer 32. The nucleation layer can alleviate problems such as lattice mismatch and thermal mismatch between the epitaxially grown semiconductor layer and the substrate, and the buffer layer can reduce the dislocation density and defect density of the epitaxially grown semiconductor layer and improve the crystal quality.

[0091] Embodiment 4

[0092] Embodiment 4 provides the preparation process of the semiconductor structure provided in Embodiment 2. The content of Embodiment 4 is substantially the same as that of Embodiment 3, and the difference is only that, as Figure 12 shown, Figure 12 is a schematic intermediate diagram of the preparation process of the semiconductor structure provided in Embodiment 4 of the present invention. Combining Figures 3 - 4 , preparing the channel structure 2 includes preparing a plurality of channel structures 2, and the plurality of channel structures 2 are stacked on the substrate 1.

[0093] The preparation processes of the plurality of channel structures 2 are similar to those of the first N-type heavily doped layer 31, the first intermediate layer 21, the channel layer 22, the second intermediate layer 23, and the second N-type heavily doped layer 32, and will not be repeated here.

[0094] In some embodiments, preparing multiple channel structures 2 further includes preparing at least one third N-type heavily doped layer 33, which is prepared between two adjacent channel structures 2 among the multiple channel structures 2 (i.e., above the second intermediate layer 23 of the lower layer of channel structures 2 and below the first intermediate layer 21 of the upper layer of channel structures 2). After preparing the multiple channel structures 2, when removing the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 whose projections on the channel structures 2 are located in the source region and the drain region, the third N-type heavily doped layer 33 whose projection on the channel structures 2 is located in the source region and the drain region can also be removed. The gate 4 is connected to the third N-type heavily doped layer 33, and the gate 4 and the third N-type heavily doped layer 33 are in ohmic contact.

[0095] The preparation process of the third N-type heavily doped layer 33 is similar to that of the first N-type heavily doped layer 31, the first intermediate layer 21, the channel layer 22, the second intermediate layer 23, and the second N-type heavily doped layer 32. The implementation method of etching the third N-type heavily doped layer 33 whose projection on the channel structures 2 is located in the source region and the drain region is similar to that of etching the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 whose projections on the channel structures 2 are located in the source region and the drain region, and will not be repeated here.

[0096] As Figure 13 shown, Figure 13 is another intermediate schematic diagram of the preparation process of the semiconductor structure provided in the fourth embodiment of the present invention. When removing the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 whose projections on the channel structures are located in the source region and the drain region, it further includes removing the third N-type heavily doped layer 33 whose projection on the channel structures 2 is located in the source region and the drain region. Specifically, when patterning the dielectric layer 9 to expose the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 located in the source region and the drain region on the channel structures 2, the third N-type heavily doped layer 33 located in the source region and the drain region on the channel structures 2 can be exposed simultaneously, so that the third N-type heavily doped layer 33 and the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 are removed simultaneously.

[0097] In addition, when further patterning the dielectric layer 9 to expose the first N-type heavily doped layer 31 and the second N-type heavily doped layer 32 located in the gate region on the channel structures 2, the third N-type heavily doped layer 33 located in the gate region on the channel structures 2 is exposed simultaneously, so that when the gate 4 is prepared subsequently, the gate 4 can be connected to the third N-type heavily doped layer 33.

[0098] The specific structures, principles, functions, and effects in the embodiments of the preparation method are similar to those described in the embodiments of the above semiconductor structure, and reference can be made to the content described in the structure embodiments, which will not be repeated here.

[0099] It should be noted that in the embodiments of the present invention, chemical elements are used to represent certain materials, but the molar ratios of the chemical elements in the materials are not limited. For example, in the GaN material, it contains Ga element and N element, but the molar ratios of Ga element and N element are not limited; in the AlGaN material, it contains three elements of Al, Ga, and N, but the molar ratio magnitudes of each are not limited.

[0100] It should be noted that although this specification contains many embodiments, these embodiments should not be construed as limiting the scope of any invention or the scope of what is claimed, but rather as describing the features of specific embodiments of a particular invention. In this specification, certain features described in a single embodiment can also be implemented in combination in other embodiments. On the other hand, the various features described in each embodiment can also be implemented in any suitable combination. In addition, although the features may function in certain combinations as described above and are even initially claimed as such, one or more features from the claimed combination can in some cases be removed from the combination, and the claimed combination can be directed to a sub - combination or a variation of the sub - combination.

[0101] Thus, specific embodiments of the present invention have been described. Other embodiments are within the scope of the appended claims. In some cases, the features recited in the claims can be performed in a different order and still achieve the desired result. In addition, the order of the features depicted in the drawings is not necessarily a specific or sequential order required to achieve the desired result. In some implementations, multitasking parallel processing may also be possible.

[0102] The above are only some embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate (1); A channel structure (2) located on the substrate (1), the channel structure (2) including a first intermediate layer (21), a channel layer (22), and a second intermediate layer (23) stacked on the substrate (1), the channel structure (2) including a gate region and a source region and a drain region located at both ends of the gate region; A first N-type heavily doped layer (31) and a second N-type heavily doped layer (32), the first N-type heavily doped layer (31) being located between the substrate (1) and the channel structure (2), the second N-type heavily doped layer (32) being located on a side of the channel structure (2) away from the substrate (1), wherein projections of the first N-type heavily doped layer (31) and the second N-type heavily doped layer (32) on the channel structure (2) are located within the gate region; And a gate (4) located within the gate region, the gate (4) covering sidewalls of the first N-type heavily doped layer (31), the channel structure (2), and the second N-type heavily doped layer (32).

2. The semiconductor structure according to claim 1, wherein: The gate (4) is in ohmic contact with the first N-type heavily doped layer (31) and the second N-type heavily doped layer (32).

3. The semiconductor structure according to claim 1, wherein: The semiconductor structure includes a plurality of the channel structures (2) and a third N-type heavily doped layer (33), the plurality of channel structures (2) being stacked on the substrate (1); The third N-type heavily doped layer (33) is located between two adjacent ones of the plurality of channel structures (2), and a projection of the third N-type heavily doped layer (33) on the channel structure (2) is located within the gate region.

4. The semiconductor structure according to claim 3, wherein: The plurality of channel structures (2) share the gate (4), the gate (4) covering sidewalls of the third N-type heavily doped layer (33), and the gate (4) being in ohmic contact with the third N-type heavily doped layer (33).

5. The semiconductor structure according to any one of claims 1-4, characterized in that, Further comprising: A dielectric layer (9) located on the gate region, the dielectric layer (9) at least covering sidewalls of the channel layer (22), and the dielectric layer (9) being located between the gate (4) and the channel layer (22).

6. The semiconductor structure according to any one of claims 1-4, wherein: The channel layer (22) is a nanowire or nanosheet structure.

7. The semiconductor structure according to any one of claims 1-4, wherein: The material of the channel structure (2) is a group III nitride material.

8. The semiconductor structure according to claim 1, wherein: The materials of the first intermediate layer (21) and the second intermediate layer (23) are AlN; The material of the channel layer (22) includes any one of GaN, AlGaN, InGaN, or AlInGaN.

9. The semiconductor structure according to claim 1, wherein Further comprising A source electrode (5) and a drain electrode (6) respectively located in the source region and the drain region, and the source electrode (5) and the drain electrode (6) surround and wrap the channel layer (22).

10. The semiconductor structure according to claim 1, wherein the channel layer (22) is an N-type lightly doped layer, and the N-type ion doping concentration of the channel layer is less than 1E18.

11. A method for preparing a semiconductor structure, characterized in that, Comprising: Providing a substrate (1); Successively preparing a first N-type heavily doped layer (31), a channel structure (2), and a second N-type heavily doped layer (32) on the substrate (1). The preparation of the channel structure (2) includes preparing a first intermediate layer (21), a channel layer (22), and a second intermediate layer (23) stacked on the first N-type heavily doped layer (31); the channel structure (2) includes a gate region and a source region and a drain region located at both ends of the gate region; Removing the first N-type heavily doped layer (31) and the second N-type heavily doped layer (32) whose projections on the channel structure (2) are located in the source region and the drain region; Preparing a gate electrode (4) in the gate region, and the gate electrode (4) covers the side walls of the first N-type heavily doped layer (31), the channel structure (2), and the second N-type heavily doped layer (32).

12. The method for manufacturing a semiconductor structure according to claim 11, wherein Before preparing the gate electrode (4) in the gate region, a dielectric layer (9) is prepared on the side walls of the first N-type heavily doped layer (31), the channel structure (2), and the second N-type heavily doped layer (32) and on the top of the second N-type heavily doped layer (32), and the dielectric layer (9) is patterned to expose the first N-type heavily doped layer (31) and the second N-type heavily doped layer (32) located in the gate region. The gate electrode (4) is connected to the first N-type heavily doped layer (31) and the second N-type heavily doped layer (32), and the gate electrode (4) is connected to the channel structure (2) through the dielectric layer (9).

13. The method for preparing a semiconductor structure according to claim 12, wherein, After preparing the dielectric layer (9) on the side walls of the first N-type heavily doped layer (31), the channel structure (2), and the second N-type heavily doped layer (32) and on the top of the second N-type heavily doped layer (32), it includes: Pattern the dielectric layer (9) to expose the first N-type heavily doped layer (31) and the second N-type heavily doped layer (32) located in the source region and the drain region, and remove the first N-type heavily doped layer (31) and the second N-type heavily doped layer (32) whose projections on the channel structure (2) are located in the source region and the drain region.

14. The method for manufacturing a semiconductor structure according to claim 13, wherein Before removing the first N-type heavily doped layer (31) and the second N-type heavily doped layer (32) whose projections on the channel structure (2) are located in the source region and the drain region, Said patterning the dielectric layer (9) to expose the first N-type heavily doped layer (31) and the second N-type heavily doped layer (32) located in the source region and the drain region further includes exposing a first intermediate layer (21) and a second intermediate layer (23) located in the source region and the drain region; After removing the first N-type heavily doped layer (31) and the second N-type heavily doped layer (32) located in the source region and the drain region and projected on the channel structure (2), it further includes removing the first intermediate layer (21) and the second intermediate layer (23) located in the source region and the drain region.

15. The method for manufacturing a semiconductor structure according to claim 14, wherein After removing the first intermediate layer and the second intermediate layer located in the source region and the drain region, it further includes Preparing a source electrode (5) and a drain electrode (6) in the source region and the drain region respectively, and the source electrode (5) and the drain electrode (6) surround and wrap the channel layer (22).

16. The method for manufacturing a semiconductor structure according to claim 11, wherein The gate electrode (4) is in ohmic contact with the first N-type heavily doped layer (31) and the second N-type heavily doped layer (32).

17. The method for preparing a semiconductor structure according to claim 12, wherein Before preparing the dielectric layer on the sidewalls of the first N-type heavily doped layer, the channel structure and the second N-type heavily doped layer and the top of the second N-type heavily doped layer, it further includes: Patterning the first N-type heavily doped layer (31), the channel structure (2) and the second N-type heavily doped layer (32) such that the channel layer (22) forms a nanowire or nanosheet structure.

18. The method for manufacturing a semiconductor structure according to any one of claims 11-17, characterized in that, Said preparing the channel structure (2) includes preparing a plurality of channel structures (2), and the plurality of channel structures (2) are stacked on the substrate (1); Said preparing the plurality of channel structures (2) further includes preparing a third N-type heavily doped layer (33), the third N-type heavily doped layer (33) is prepared between two adjacent channel structures (2) among the plurality of channel structures (2), the gate electrode (4) is connected to the third N-type heavily doped layer (33), and the gate electrode (4) is in ohmic contact with the third N-type heavily doped layer (33).

19. The method for preparing a semiconductor structure according to claim 18, wherein, After preparing the plurality of channel structures, when removing the first N-type heavily doped layer and the second N-type heavily doped layer located in the source region and the drain region and projected on the channel structure, it further includes: Removing the third N-type heavily doped layer (33) located in the source region and the drain region and projected on the channel structure (2).

20. The method for preparing a semiconductor structure according to claim 11, wherein After preparing the channel layer (22), the manufacturing method further includes: Performing N-type doping on the channel layer (22), and the doping concentration of the N-type ions is less than 1E18.

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