Semiconductor circuit with selective backside power and ground distribution and maximum area decoupling capacitor

Abstract

The invention relates to a semiconductor circuit with selective backside power and ground distribution and maximum area decoupling capacitors. A backside power and ground distribution network is formed on a semiconductor wafer by providing a decoupling capacitor on a backside of a semiconductor substrate layer; selectively etching a TSV opening through the decoupling capacitor and the backside of the semiconductor substrate layer to contact an integrated device connection feature; then forming a ground TSV conductor in the TSV opening, the ground TSV conductor providing a direct electrical connection between a first capacitor plate and a first integrated device connection feature formed in the semiconductor substrate layer; and also forming a power TSV conductor that provides a direct electrical connection between a second capacitor plate and a second integrated device connection feature formed in the semiconductor substrate layer, where the ground TSV conductor is not directly electrically connected to the second capacitor plate, and where the ground TSV conductor is not directly electrically connected to the second integrated device connection feature. And wherein the power TSV conductor is not directly electrically connected to the first capacitor plate.

Description

Field of the Technology

[0001] The present disclosure generally relates to the field of semiconductor devices. In one aspect, the present disclosure relates to power and ground connector structures formed on and through a semiconductor device. Background Art

[0002] Conventionally, integrated circuits use conductive interconnect layers or levels formed on the front side of a wafer to provide connection signals and power delivery routes to the integrated circuit. However, as semiconductor manufacturing processes advance towards future nodes, the interconnect stack continues to shrink, and when using conductive interconnects on the front side of the wafer for power and signal routes, more and more resistance, capacitance, and power consumption issues arise. When the power demand becomes too large, existing solutions have attempted to enhance the conductivity of the conductive power supply interconnects, such as by adding more metal levels, making the Alucap (AP) final metallization thicker, or switching to a copper pillar arrangement, thereby allowing power to be delivered more directly throughout the die, as opposed to wire bonding which typically only comes from the chip periphery. In recent years, power delivery on the chip has been improved by decoupling signals, and the power delivery route to the integrated circuit can be decoupled by moving the power routing to the back side of the wafer while keeping the signal routes on the conventional front side of the wafer. However, introducing power signal routes on the back side of the wafer poses challenges, including potential interference to back side circuit elements (e.g., decoupling capacitors), processing challenges in creating through-silicon via (TSV) interconnect structures in the semiconductor substrate material, process compatibility with the front-end-of-line (FEOL) and back-end-of-line (BEOL) wafer manufacturing, or alternatively process compatibility for silicon-based packaging solutions. After reviewing the remainder of this application with reference to the accompanying drawings and detailed description, additional limitations and disadvantages of conventional processes and techniques will become apparent to those skilled in the art. Summary of the Invention

[0003] It should be understood that a semiconductor wafer with a backside power and ground distribution network connection and an associated manufacturing method are provided. In the disclosed method, a semiconductor wafer is provided, which includes a plurality of integrated circuit (IC) devices formed on the front side of a semiconductor substrate layer, and integrated device connection features are formed in the semiconductor substrate layer. In selected embodiments, the integrated device connection features can be formed in the semiconductor substrate layer as highly doped semiconductor connection regions or buried power rail connection regions formed in the semiconductor substrate layer. The disclosed method further includes forming a decoupling capacitor on the backside of the semiconductor substrate layer, the decoupling capacitor including a first capacitor plate, a capacitor dielectric layer, and a second capacitor plate. In selected embodiments, the decoupling capacitor can include a first decoupling capacitor plate formed to cover the backside of the semiconductor substrate layer, a high-k capacitor dielectric layer formed to cover the first decoupling capacitor plate, and a second decoupling capacitor plate formed to cover the high-k capacitor dielectric layer. Additionally, the disclosed method includes selectively etching a plurality of through-semiconductor via (TSV) openings through the decoupling capacitor and the backside of the semiconductor substrate layer to contact the integrated device connection features. The disclosed method also includes forming a first voltage supply (e.g., ground) TSV conductor in the first TSV opening of each IC device, the first voltage supply TSV conductor providing a direct electrical connection between the first capacitor plate and a first integrated device connection feature formed in the semiconductor substrate layer. Additionally, the disclosed method includes forming a second voltage supply (e.g., power) TSV conductor in the second TSV opening of each IC device, the second voltage supply TSV conductor providing a direct electrical connection between the second capacitor plate and a second integrated device connection feature formed in the semiconductor substrate layer. As formed, the ground TSV conductor is not directly electrically connected to the second capacitor plate, and the power TSV conductor is not directly electrically connected to the first capacitor plate. The disclosed method can further include singulating the semiconductor wafer into a plurality of integrated circuit dies. In selected embodiments, the plurality of TSV openings are selectively etched through the decoupling capacitor and the backside of the semiconductor substrate layer to sequentially form a first TSV opening and a second TSV opening to contact the integrated device connection features. In such embodiments, the ground TSV conductor can be formed by: partially filling the first TSV opening with one or more first conductive layers to form at least a portion of the ground TSV conductor that provides a direct electrical connection between the first capacitor plate and the first integrated device connection feature; selectively forming an insulating dielectric layer in the unfilled portion of the first TSV opening; and filling the unfilled portion of the first TSV opening with one or more second conductive layers, wherein the insulating dielectric layer prevents a direct electrical connection between the ground TSV conductor and the second capacitor plate.In other such embodiments, a power TSV conductor can be formed by: selectively forming a conformal dielectric layer on the sidewalls rather than the bottom of the second TSV opening to expose the second integrated device connection feature; partially filling the second TSV opening with one or more first conductive layers to form at least a portion of the power TSV conductor; and filling the second TSV opening with one or more second conductive layers to form the power TSV conductor, wherein the conformal dielectric layer prevents a direct electrical connection between the power TSV conductor and the first capacitor plate. In other selected embodiments, a plurality of TSV openings are etched in sequence through the backside of the decoupling capacitor and the semiconductor substrate layer while forming the first TSV opening and the second TSV opening to contact the integrated device connection feature. In such embodiments, a ground TSV conductor can be formed by: selectively forming a conformal dielectric layer on the sidewalls rather than the bottom of the first TSV opening to expose the first integrated device connection feature; partially filling the first TSV opening with one or more first conductive layers to form at least a portion of the ground TSV conductor that provides a direct electrical connection between the first capacitor plate and the first integrated device connection feature; selectively etching the conformal dielectric layer from a portion of the sidewalls of the first TSV opening to expose the first capacitor plate; and filling the first TSV opening with one or more second conductive layers, wherein the unetched portion of the conformal dielectric layer prevents a direct electrical connection between the ground TSV conductor and the second capacitor plate. In other such embodiments, a power TSV conductor can be formed by: selectively forming a conformal dielectric layer on the sidewalls rather than the bottom of the second TSV opening to expose the second integrated device connection feature; partially filling the second TSV opening with one or more first conductive layers to form at least a portion of the power TSV conductor; and filling the second TSV opening with one or more second conductive layers to form the power TSV conductor, wherein the conformal dielectric layer prevents a direct electrical connection between the power TSV conductor and the first capacitor plate.

[0004] In another form, a semiconductor device having a backside power and ground distribution conductor and an associated manufacturing method are provided. In the disclosed method, a first decoupling capacitor plate and a second decoupling capacitor plate separated by a capacitor dielectric layer are formed on the backside of the semiconductor device. In a selected embodiment, the first decoupling capacitor plate and the second decoupling capacitor plate may form an electromagnetic interference (EMI) shield on the backside of the semiconductor device. Additionally, conductive through-silicon via (TSV) structures are selectively formed in the semiconductor device. As formed, the conductive TSV structures include a conductive first voltage supply (e.g., power) TSV structure that directly electrically connects a Vdd power connection feature formed in the semiconductor device to the second decoupling capacitor plate rather than the first decoupling capacitor plate. Additionally, the conductive TSV structures include a conductive second voltage supply (e.g., ground) TSV structure that directly electrically connects a Vss ground connection feature formed in the semiconductor device to the first decoupling capacitor plate rather than the second decoupling capacitor plate. In a selected embodiment, the Vdd power connection feature formed in the semiconductor device may be a highly doped semiconductor substrate connection region or an embedded power rail connection region or a metal wire conductor layer formed in one or more interlayer dielectric (ILD) connection layers of the semiconductor device. Alternatively, the Vdd power connection feature and the VSS ground connection feature may each be formed with an embedded metal layer formed in the semiconductor device. In a selected embodiment, the conductive TSV structures may be selectively formed by: selectively etching a first TSV opening and a second TSV opening through the first decoupling capacitor plate and the second decoupling capacitor plate separated by a capacitor dielectric layer on the backside of the semiconductor device to contact the Vdd power connection feature and the Vss ground connection feature, respectively; forming a conductive power TSV structure in the first TSV opening to provide a direct electrical connection between the first decoupling capacitor plate and the Vdd power connection feature formed in the semiconductor device; and forming a conductive ground TSV structure in the second TSV opening to provide a direct electrical connection between the second decoupling capacitor plate and the Vss ground connection feature formed in the semiconductor device. In such embodiments, the conductive power TSV structure may be formed by: selectively forming a conformal dielectric layer on the sidewalls rather than the bottom of the first TSV opening to expose the Vdd power connection feature; partially filling the first TSV opening with one or more first conductive layers to form at least a portion of the conductive power TSV structure; and filling the first TSV opening with one or more second conductive layers to form the conductive power TSV structure, wherein the conformal dielectric layer prevents a direct electrical connection between the conductive power TSV structure and the first decoupling capacitor plate.In other such embodiments, a conductive ground TSV structure can be formed by: partially filling a second TSV opening with one or more first conductive layers to form at least a portion of a conductive ground TSV structure that provides a direct electrical connection between a first decoupling capacitor plate and a Vss ground connection feature; selectively forming an insulating dielectric layer in the unfilled portion of the second TSV opening; and filling the unfilled portion of the second TSV opening with one or more second conductive layers, wherein the insulating dielectric layer prevents a direct electrical connection between the conductive ground TSV structure and a second decoupling capacitor plate. In selected embodiments, the first TSV opening and the second TSV opening can be etched simultaneously through a first decoupling capacitor plate and a second decoupling capacitor plate separated by a capacitor dielectric layer and through the backside of the semiconductor device to contact a Vdd power connection feature and a Vss ground connection feature, respectively. In such embodiments, a conductive ground TSV structure can be formed by: selectively forming a conformal dielectric layer on the sidewalls rather than the bottom of the second TSV opening to expose the Vss ground connection feature; partially filling the second TSV opening with one or more first conductive layers to form at least a portion of the conductive ground TSV structure; selectively etching the conformal dielectric layer from a portion of the sidewalls of the second TSV opening to expose the first decoupling capacitor plate; and filling the second TSV opening with one or more second conductive layers that are directly electrically connected to the first decoupling capacitor plate and the one or more first conductive layers, wherein the unetched portion of the conformal dielectric layer prevents a direct electrical connection between the conductive ground TSV structure and the second decoupling capacitor plate. In other such embodiments, a conductive power TSV structure can be formed by: selectively forming a conformal dielectric layer on the sidewalls rather than the bottom of the first TSV opening to expose the Vdd power connection feature; partially filling the first TSV opening with one or more first conductive layers to form at least a portion of the conductive power TSV structure; and filling the first TSV opening with one or more second conductive layers to form the conductive power TSV structure, wherein the conformal dielectric layer prevents a direct electrical connection between the conductive power TSV structure and a first decoupling conductive power TSV structure capacitor plate.

[0005] In yet another form, an integrated circuit and an associated manufacturing method are provided. As disclosed, the integrated circuit includes a semiconductor substrate having a plurality of integrated circuit (IC) devices formed on a front side of the semiconductor substrate and first and second integrated connection features formed in or above the semiconductor substrate. Additionally, the integrated circuit includes a capacitor formed on a back side of the semiconductor substrate, the capacitor including a first capacitor plate and a second capacitor plate separated by a capacitor dielectric layer. In a selected embodiment, the capacitor may be a decoupling capacitor covering the entire semiconductor substrate, but in other embodiments, the first and second capacitor plates may also be patterned and etched to form other circuit capacitors. The integrated circuit further includes a first conductive TSV structure formed through the back side of the semiconductor substrate to directly electrically connect the first integrated connection feature to the second capacitor plate rather than the first capacitor plate. Additionally, the integrated circuit includes a second TSV structure formed through the back side of the semiconductor substrate to directly electrically connect the second integrated connection feature to the first capacitor plate rather than the second capacitor plate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention and many of its objects, features, and advantages obtained thereby can be understood when the following detailed description of the preferred embodiments is considered in conjunction with the following drawings.

[0007] Figures 1-12 A cross-sectional view showing different manufacturing stages of a semiconductor structure having separate back-side ground and power connection lines according to a selected first embodiment of the present disclosure.

[0008] Figures 13-14 A cross-sectional view showing different manufacturing stages of a semiconductor structure having separate back-side ground and power connection lines according to a selected second embodiment of the present disclosure.

[0009] Figures 15-27 A cross-sectional view showing different manufacturing stages of a semiconductor structure having separate back-side ground and power connection lines according to a selected third embodiment of the present disclosure.

[0010] Figure 28 A simplified process flow for manufacturing separate back-side ground and power connection lines according to a selected embodiment of the present disclosure. DETAILED DESCRIPTION

[0011] Describes an integrated circuit manufacturing process and the resulting integrated circuit for fabricating selective backside power and ground distribution conductors with backside conductive through-silicon via (TSV) structures, which are integrated with decoupling capacitor plates to maximize power and ground distribution in the die and decoupling capacitor regions while providing efficient electromagnetic interference (EMI) shielding. In a selected embodiment, after the FEOL and BEOL wafer processing steps are substantially completed, the backside power and ground distribution conductors are fabricated by sequentially forming a first decoupling capacitor plate and a second decoupling capacitor plate separated by a capacitor dielectric layer on the backside of the wafer, and then selectively forming conductive power and ground TSV structures in the wafer substrate layer, the conductive power and ground TSV structures connecting the first decoupling capacitor plate and the second decoupling capacitor plate to an embedded power rail and other features formed in or on the wafer substrate layer respectively. In a selected first embodiment, one or more first TSV openings are etched through the backside wafer to expose an embedded Vdd region or a power rail / conductor feature in the wafer substrate layer, and then the one or more first TSV openings are lined and capped with a dielectric layer. After that, one or more second TSV openings are etched through the backside wafer to expose a ground region in the wafer substrate layer. Subsequently, the first TSV openings and the second TSV openings are partially filled with one or more electroplated coatings to form direct electrical contact with the first decoupling capacitor plate, and then a patterned dielectric liner layer is selectively formed in the remaining first TSV openings and second TSV openings, the patterned dielectric liner layer protecting the electroplated coatings in the second TSV openings and exposing the electroplated coatings in the first TSV openings, so that subsequent metal electroplating processes can fill the first TSV openings and the second TSV openings to form direct electrical contact between the second decoupling capacitor plate and the electroplated coatings in the first TSV openings rather than between the first decoupling capacitor plates.

[0012] In a selected second embodiment, the first TSV openings and the second TSV openings are partially filled with one or more electroplated coatings to form direct electrical contact with the first decoupling capacitor plate rather than the second decoupling capacitor plate. Subsequently, a patterned dielectric liner layer is selectively formed on the backside of the wafer and in the remaining first TSV openings and second TSV openings to expose the electroplated coatings in the first TSV openings and the second TSV openings. With the electroplated coatings exposed and the first decoupling capacitor plate and the second decoupling capacitor plate additionally protected by the patterned dielectric liner layer, a first patterned metal layer and a second patterned metal layer can then be formed to fill the first TSV openings and the second TSV openings, thereby forming direct electrical contact with the electroplated coatings in the first TSV openings and the second TSV openings respectively rather than the first decoupling capacitor plate and the second decoupling capacitor plate.

[0013] In a selected third embodiment, a first TSV opening and a second TSV opening are etched through the dorsal wafer simultaneously to expose the buried metal features in the wafer substrate layer. Subsequently, a first patterned dielectric liner layer is selectively formed in the first TSV opening and the second TSV opening to expose the buried metal features. Then, one or more electroplated cladding layers are formed, and the one or more electroplated cladding layers partially fill the first TSV opening and the second TSV opening without contacting the first decoupling capacitor plate and the second decoupling capacitor plate. Next, one or more sacrificial dielectric layers are formed to partially fill the first TSV opening and the second TSV opening at positions at least partially aligned with the first decoupling capacitor plate. With the sacrificial dielectric layer in place, a second patterned dielectric liner layer is selectively formed in the remaining first TSV opening and second TSV opening as an etch mask to protect the second decoupling capacitor plate and expose the sacrificial dielectric layer in the first TSV opening and the second TSV opening. Subsequently, one or more selective etch processes are selectively applied to remove the sacrificial dielectric layer from the first TSV opening and the second TSV opening, and only the first decoupling capacitor plate is exposed in the second TSV opening. With the electroplated cladding layer exposed in the first TSV opening and the second TSV opening, the first decoupling capacitor plate exposed in the second TSV opening, and the second decoupling capacitor plate exposed on the dorsal side of the wafer, one or more first patterned metal layers can then be formed to fill the first TSV opening to form a direct electrical contact between the electroplated cladding layer in the first TSV opening and the second decoupling capacitor plate exposed on the dorsal side of the wafer rather than between the first decoupling capacitor plates. Additionally, one or more second patterned metal layers can then be formed to fill the second TSV opening to form a direct electrical contact between the electroplated cladding layer in the second TSV opening and the first decoupling capacitor plate rather than between the second decoupling capacitor plates.

[0014] In the present disclosure, an improved integrated circuit design, structure, and manufacturing method are described for forming backside power and ground distribution conductors as part of or after the backend process, thereby solving various problems in the art. After reviewing the remainder of the present application with reference to the drawings and detailed description provided herein, various limitations and disadvantages of conventional solutions and techniques will become apparent to those skilled in the art. Various illustrative embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Although various details are set forth in the following description, it should be understood that the present invention may be practiced without these specific details, and many implementation-specific decisions may be made regarding the present invention described herein to achieve the particular goals of the device designer, such as compliance with process technology or associated design constraints, which vary from implementation to implementation. Although such development work may be complex and time-consuming, it is merely routine taskwork for those of ordinary skill in the art who benefit from the present disclosure. For example, selected aspects are depicted with reference to a simplified cross-sectional view of a semiconductor device, but not every device feature or geometry is included so as not to limit or obscure the present invention. Such descriptions and representations are commonly used by those skilled in the art to describe and convey the gist of their work to other technicians in the art. It should also be noted that throughout this detailed description, certain elements in the figures are shown for simplicity and clarity and are not necessarily drawn to scale. Additionally, the dimensions of some elements in the figures may be exaggerated relative to other elements to help enhance understanding of the embodiments of the present disclosure. Additionally, reference numerals have been repeated in the figures to denote corresponding or similar elements. Additionally, the depicted device layers shown as being deposited and / or etched are represented by simplified line drawings, but it should be understood that in reality, for example, when the described etching process is applied at different rates to different materials, or when the described deposition or growth process generates layers based on underlying materials, the actual profile or dimensions of the device layers will be non-linear.

[0015] Various illustrative embodiments of the present invention will now be described in detail with reference to Figures 1-28 In addition, although specific example materials, thicknesses, and processes are described herein, those skilled in the art will recognize that other materials, thicknesses, and processes having similar properties or characteristics may be substituted without loss of functionality. It should be noted that throughout this detailed description, certain material layers will be deposited and removed to form a semiconductor structure. In the absence of a detailed description herein of the specific procedures for processing such layers or the thicknesses of such layers, it will be expected that conventional techniques known to those skilled in the art will be used to deposit, remove, form, or otherwise process such layers to an appropriate thickness. Such details are well known and are not considered necessary to teach those skilled in the art how to make or use the present invention.

[0016] Turning now to Figure 1, shows a portion of the semiconductor structure 1 in cross-sectional form, having one or more interlayer dielectric (ILD) layers 13 and a first metal wire conductor layer M1 formed over the semiconductor substrate 10, wherein one or more integrated circuit (IC) devices or elements 12 are fabricated using front-end-of-line (FEOL) wafer processing steps. As should be appreciated, the FEOL IC devices 12 can include one or more transistors, resistors, capacitors, diodes, or other semiconductor components formed on or in the semiconductor substrate, which can be formed of any suitable semiconductor material or combination of materials, such as gallium arsenide, silicon germanium, semiconductor-on-insulator (SOI), silicon, single-crystalline silicon, etc. For example, the depicted transistors include gates formed over source / drain regions of the channel, wherein the transistors are separated from each other by isolation regions (ISO) and connected to the patterned first metal wire conductor layer M1 formed in the ILD layer 13. Additionally, the substrate 10 can include one or more Vdd regions, such as N+ regions or buried power rail structures that can be formed of any suitable conductive material (e.g., a metal layer or a conductive implant). As shown, the FEOL IC devices 12 are formed on the top or front side of the semiconductor structure 1 rather than on the wafer back side. Additionally, the depicted semiconductor substrate 10 can have a specified thickness (e.g., 30 μm) achieved by applying a wafer backgrinding process.

[0017] Figure 2 Shows the connection after sequentially forming a first decoupling capacitor plate 14 and a second decoupling capacitor plate 16 separated by a capacitor dielectric layer 15 on the wafer back side according to a selected embodiment of the present disclosure. Figure 1Processing of the semiconductor structure 2. As an initial step, the first decoupling capacitor plate 14 can be formed as a Vss plate layer of a predetermined thickness above the bottom or back side of the semiconductor substrate layer 10, for example, by depositing a conductive material (such as copper, silver, aluminum, graphene, etc.) using any suitable deposition technique such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), atmospheric pressure CVD (AP-CVD), chemical bath deposition (CBD), or any combination of the above. In other embodiments, the first decoupling capacitor plate 14 can be formed of a nickel plate layer surrounded by a blanket film of Si3N4 or other suitable dielectric. On the first decoupling capacitor plate 14, the capacitor dielectric layer 15 can be formed as a metal-insulator-metal (MIM) dielectric of a predetermined thickness on the first decoupling capacitor plate 14, for example, by depositing a high-k dielectric layer (such as TaN) or other suitable insulating material using any suitable deposition technique. On the capacitor dielectric layer 15, the second decoupling capacitor plate 16 can be formed as a Vdd plate layer of a predetermined thickness on the capacitor dielectric layer 15, for example, by depositing a conductive material (such as tantalum) using any suitable deposition technique, thereby forming a metal-insulator-metal (MIM) capacitor on the back side of the wafer.

[0018] Figure 3 Shown is the connection after applying one or more anisotropic etching processes to create one or more first through-silicon via (TSV) openings 17 through the back side wafer to expose the buried Vdd region 11 or other power rail / conductor features in the wafer substrate layer according to a selected embodiment of the present disclosure. Figure 2 Processing of the semiconductor structure 3. Although any suitable anisotropic etching process can be used, the etching process can use a patterned photoresist mask (not shown) having an opening exposing the intended etching region, followed by performing a reactive ion etching (RIE) step with a suitable etching chemistry to remove the exposed portions of the underlying Vdd plate 16, MIM dielectric layer 15, Vss plate 14, and semiconductor substrate 10. For example, a controlled photoetching process such as timed anisotropic dry etching can be used to remove a portion of the exposed portions of the underlying layers 10, 14, 15, 16 to a predetermined depth exposing the buried Vdd region 11. Alternatively, the etching process can be stopped by a silicon nitride layer (not shown), or they can enter the ILD layer 13 to connect to one of the patterned first metal wire conductor layers M1 or other middle-of-line process (MEOL) features such as contacts. Although the sidewalls of the TSV etching openings 17 are substantially vertical, it should be understood that due to etching process variations, there may be slight deviations in the sidewall profiles.

[0019] Figure 4Illustrated is the processing of the semiconductor structure 4 after lining one or more first TSV openings 17 with a dielectric liner layer 18 and then covering with a dielectric capping layer 19 in accordance with selected embodiments of the present disclosure. For example, the dielectric liner layer 18 can be formed by conformally depositing a suitable low-k dielectric layer (e.g., Si3N4) of a predetermined thickness using any suitable deposition technique. Thus, the dielectric liner layer 18 covers the backside of the wafer as well as the bottom and sidewalls of one or more first TSV openings 17. After forming the dielectric liner layer 18, a blanket dielectric TSV via capping layer 19 is formed using any suitable deposition technique to cover and seal the first TSV openings 17. For example, a tetraethyl orthosilicate (TEOS) layer can be deposited at high pressure using a PECVD process such that the dielectric TSV via capping layer 19 seals the etched TSV openings 17 by bread-loafing. Instead of the capping dielectric layer 19, the TSV vias can be filled with a liquid spin-on polymer or organic material that also coats the back surface. Figure 3 The processing of the semiconductor structure 4 is described. For example, the dielectric liner layer 18 can be formed by conformally depositing a suitable low-k dielectric layer (e.g., Si3N4) of a predetermined thickness using any suitable deposition technique. Thus, the dielectric liner layer 18 covers the backside of the wafer as well as the bottom and sidewalls of one or more first TSV openings 17. After forming the dielectric liner layer 18, a blanket dielectric TSV via capping layer 19 is formed using any suitable deposition technique to cover and seal the first TSV openings 17. For example, a tetraethyl orthosilicate (TEOS) layer can be deposited at high pressure using a PECVD process such that the dielectric TSV via capping layer 19 seals the etched TSV openings 17 by bread-loafing. Instead of the capping dielectric layer 19, the TSV vias can be filled with a liquid spin-on polymer or organic material that also coats the back surface.

[0020] Figure 5 Illustrated is the processing of the semiconductor structure 5 after applying one or more anisotropic etching processes to create one or more second TSV openings 21 through the backside wafer to expose the semiconductor substrate layer 10 in accordance with selected embodiments of the present disclosure. While any suitable anisotropic etching process can be used, the etching process can use a patterned photoresist etch mask 20 formed on the dielectric capping layer 19 to protect the wafer backside, with mask openings exposing the intended etching regions, followed by performing an RIE step with a suitable etching chemistry to remove the exposed portions of the underlying dielectric capping layer 19, dielectric liner 18, Vdd plate 16, MIM dielectric layer 15, Vss plate 14, and semiconductor substrate 10. For example, one or more second TSV openings 21 can be formed using a controlled photoetching process such as timed anisotropic dry etching, and / or a silicon nitride layer (not shown) can be used to stop the anisotropic etching, and / or into the ILD layer 13 to connect to a patterned first metal wire conductor layer M1 or another middle-of-line process (MEOL) feature such as a contact. While the sidewalls of the TSV etch openings 21 are substantially vertical, it should be understood that due to etching process variations, minor deviations in the sidewall profile may occur. Thus, the second TSV openings 21 expose the semiconductor substrate 10 that will form the TSVs 21. Figure 4 The processing of the semiconductor structure 5 is described. While any suitable anisotropic etching process can be used, the etching process can use a patterned photoresist etch mask 20 formed on the dielectric capping layer 19 to protect the wafer backside, with mask openings exposing the intended etching regions, followed by performing an RIE step with a suitable etching chemistry to remove the exposed portions of the underlying dielectric capping layer 19, dielectric liner 18, Vdd plate 16, MIM dielectric layer 15, Vss plate 14, and semiconductor substrate 10. For example, one or more second TSV openings 21 can be formed using a controlled photoetching process such as timed anisotropic dry etching, and / or a silicon nitride layer (not shown) can be used to stop the anisotropic etching, and / or into the ILD layer 13 to connect to a patterned first metal wire conductor layer M1 or another middle-of-line process (MEOL) feature such as a contact. While the sidewalls of the TSV etch openings 21 are substantially vertical, it should be understood that due to etching process variations, minor deviations in the sidewall profile may occur. Thus, the second TSV openings 21 expose the semiconductor substrate 10 that will form the TSVs 21.

[0021] Figure 6 Illustrated is the processing of the semiconductor structure after selectively removing the dielectric liner 18 from the bottom of the first TSV openings 17 using one or more selective etching processes 22 in accordance with selected embodiments of the present disclosure. Figure 5Processing of the semiconductor structure 6. Although any suitable selective etching process 22 can be used, the processing can include removing the patterned etch mask 20 and the dielectric capping layer 19 from the backside of the wafer using one or more suitable etch chemistries, and then applying an anisotropic or directional etch to remove the dielectric liner layer 18 from the horizontal surfaces (e.g., the backside of the wafer and the bottom of the first TSV opening 17), while retaining the dielectric liner layer 18 on the vertical surfaces (e.g., the sidewalls of the first TSV opening 17). Thus, the first TSV opening 23 exposes the buried Vdd region 11 that will form the power TSVp 23.

[0022] Figure 7 Shown is an attachment after partially filling the first TSV opening 21 and the second TSV opening 23 with one or more conductive TSV structures 24, 25 in accordance with a selected embodiment of the present disclosure to form a direct electrical contact with the first decoupling capacitor plate 14. Figure 6 Processing of the semiconductor structure 7. In a selected embodiment, the conductive TSV structure is formed by first depositing a conductive barrier film or liner layer 24 formed of any suitable diffusion barrier material that also allows electrodeposition (e.g., Ti, TiN, Ta, TaN, TiN, TiC, TaC, CuWP, etc.). As part of the conductive barrier film / liner layer, one or more conductive seed layers can be formed of any suitable conductive material, such as copper, copper alloy, silver, gold, tungsten, aluminum, etc. In a selected embodiment, the conductive TSV structure can be formed by blanket depositing the barrier film in the TSV openings 21, 23, then depositing a thin seed layer (e.g., copper or copper alloy, nickel, etc.) over the barrier film, and then partially filling the TSV openings 21, 23 with a metal material 25, such as by using electroplating, electroless plating, or depositing a conductive material (e.g., Cu, Co, Ni, Mn, Mg, Zn, Al, etc.). The electroplating process can be controlled to provide a bottom-up partial electroplating such that the metal material 25 is only formed on the horizontal surfaces to cover the backside of the wafer and the bottoms of the TSV openings 21, 23, and forms a direct electrical contact with the first decoupling capacitor plate 14 rather than the second decoupling capacitor plate 15.

[0023] Figure 8 Shown is an attachment after selectively removing the exposed portions of the conductive barrier / seed layer 24 from the backside of the wafer and the exposed sidewalls of the TSV openings 21, 23. Figure 7Processing of the semiconductor structure 8. Although any suitable selective removal etching process can be used, the processing can include removing the metal layer 25 from the backside of the wafer, for example, by using a chemical mechanical polishing (CMP) step, thereby exposing the conductive barrier / seeding layer 24 on the second decoupling capacitor plate 16. Alternatively, formation of the metal layer 25 on the backside of the wafer can be prevented first by forming a patterned photoresist layer to cover the backside of the wafer but not the TSV openings 21, 23 before the electroplating process for partially filling the TSV openings 21, 23, and then removing the patterned photoresist layer using one or more suitable etching and / or polishing steps to expose the conductive barrier / seeding layer 24 on the second decoupling capacitor plate 16. Subsequently, isotropic etching can be applied to remove the exposed portions of the conductive barrier / seeding layer 24 from the backside of the wafer and the sidewalls of the TSV openings 21, 23. Thus, the first TSV opening 23 retains the remaining dielectric liner layers 18A, 18B that protect the first decoupling capacitor plate 14 and the second decoupling capacitor plate 16, but the second TSV opening 21 exposes the first decoupling capacitor plate 14 and the second decoupling capacitor plate 16.

[0024] Figure 9 Shown is the connection after lining the first TSV opening 21 and the second TSV opening 23 with the conformal dielectric layer 26 according to a selected embodiment of the present disclosure. Figure 8 Processing of the semiconductor structure 9. For example, the conformal dielectric layer 26 can be formed by depositing a suitable low-k dielectric layer (e.g., Si3N4, SiO2) of a predetermined thickness using atomic layer deposition (ALD) or any other suitable deposition technique. Thus, the conformal dielectric layer 26 covers the backside of the wafer and the bottoms and sidewalls of the first TSV opening 21 and the second TSV opening 23.

[0025] Figure 10 Shown is the connection after applying the etching and / or polishing step 27 to selectively remove the conformal dielectric layer 26 from the backside of the wafer but not from the TSV openings 21, 23 according to a selected embodiment of the present disclosure. Figure 9 Processing of the semiconductor structure 10. Although any suitable selective etching / polishing process 27 can be used, the processing can include removing the conformal dielectric layer 26 from the backside of the wafer using a CMP step or a patterned mask and a selective etching process, thereby exposing the second decoupling capacitor plate 16.

[0026] Figure 11 Shown is the connection after selectively removing the conformal dielectric layer 26 from the bottom of the first TSV opening 23 using one or more selective etching processes 29 according to a selected embodiment of the present disclosure. Figure 10Processing of the semiconductor structure 11. Although any suitable selective etching process 29 can be used, the processing can include forming a patterned etch mask 28 to cover the second TSV opening 21, and then applying an anisotropic or directional etch to remove the conformal dielectric layer 26 from the bottom of the first TSV opening 23 while leaving the conformal dielectric layers 26A-C on the vertical sidewall surfaces of the first TSV opening 23. Thus, the conductive TSV structure 25 in the first TSV opening 23 is exposed.

[0027] Figure 12 Shown is the connection after filling the first TSV opening 21 and the second TSV opening 23 with one or more conductive layers to form a Vdd connection metal plate 30 in direct electrical contact with the buried Vdd region 11 and the second decoupling capacitor plate 16 according to a selected embodiment of the present disclosure. Figure 11 Processing of the semiconductor structure 12. In a selected embodiment, the Vdd connection metal plate 30 is formed by first depositing a conductive barrier film or liner layer formed of any suitable diffusion barrier material (e.g., Ti, TiN, Ta, TaN, TiN, TiC, TaC, CuWP, etc.) that also allows electrodeposition. Additionally, one or more conductive seed layers can be formed on the conductive barrier film / liner layer using any suitable conductive material (e.g., copper, copper alloy, silver, gold, tungsten, aluminum, etc.), and then the TSV openings 21, 23 are filled with a metal material using electroplating, electroless plating, or deposition of a conductive material (e.g., Cu, Co, Ni, Mn, Mg, Zn, Al, etc.). The resulting Vdd connection metal plate 30 is formed on the backside of the wafer and is in direct contact with the second decoupling capacitor plate 16 and the conductive TSV structure 25 in the TSVp opening 23 rather than with the second decoupling capacitor plate 15. As should be understood, a separate Vss connector (not shown) is separately routed through the semiconductor structure to connect to the first decoupling capacitor plate 14 and the conductive TSV structure 25 in the TSVg opening 21.

[0028] To further improve the fabrication of the separate backside ground and power connection lines, reference is now made to Figure 13 which depicts the connection after selectively removing the conformal dielectric layer 26 from the bottoms of both the first TSV opening 21 and the second TSV opening 23 using one or more selective etching processes 41 according to a selected embodiment of the present disclosure. Figure 10Partial cross-sectional view of a semiconductor structure. Although any suitable selective etching process 41 can be used, the process can include forming a patterned etch mask 40 to cover the back side of the wafer without covering the mask openings above the first TSV opening 21 and the second TSV opening 23, and then applying an anisotropic or directional etch to remove the conformal dielectric layer 26 from the bottoms of the first TSV opening 21 and the second TSV opening 23 while leaving the conformal dielectric layer 26D-F on the back side of the wafer and on the exposed vertical sidewall surfaces of the first TSV opening 21 and the second TSV opening 23. Thus, the conductive TSV structures 25 in both the first TSV opening 21 and the second TSV opening 23 are exposed.

[0029] Figure 14 Shows the connection after forming the patterned Vss metal layer 42 and Vdd metal layer 43 in the first TSV opening 21 and the second TSV opening 23 according to a selected embodiment of the present disclosure. Figure 13 Processing of the semiconductor structure 14. In a selected embodiment, the patterned metal layers 42, 43 are formed by filling the first TSV opening 21 and the second TSV opening 23 with one or more conductive layers and then applying a patterned etching process to simultaneously form the patterned Vss metal layer 42 and Vdd metal layer 43 that are in direct electrical contact with the conductive TSV structures 25 in the TSV openings 21, 23. In a selected embodiment, the patterned metal layers 42, 43 are formed by first depositing a diffusion barrier film or liner layer formed of any suitable diffusion barrier material (e.g., Ti, TiN, Ta, TaN, TiN, TiC, TaC, CuWP, etc.) that also allows for electroplating in the TSV openings 21, 23. Additionally, one or more conductive seed layers can be formed on the diffusion barrier film / liner layer using any suitable conductive material (e.g., copper, copper alloy, silver, gold, tungsten, aluminum, etc.), and then the TSV openings 21, 23 are filled with a metal material using electroplating, electroless plating, or deposition of a conductive material (e.g., Cu, Co, Ni, Mn, Mg, Zn, Al, etc.). Then, the deposited conductive layer is patterned and etched using any suitable selective etching process to form the patterned Vss metal layer 42 and Vdd metal layer 43 that are in direct contact with the first decoupling capacitor plate 14 / semiconductor substrate 10 (via the conductive TSV structure 25 in the TSVg opening 21) and the buried Vdd region 11 (via the conductive TSV structure 25 in the TSVp opening 23) on the back side of the wafer, respectively. As should be understood, a separate Vdd connector (not shown) is separately routed through the semiconductor structure to connect to the second decoupling capacitor plate 16 and the conductive TSV structure 25 in the TSVg opening 23.

[0030] To further improve the fabrication of the separate backside ground and power connection lines, reference is now made to Figure 15, which depicts a portion cross-sectional view of a semiconductor structure after applying one or more anisotropic etching processes to simultaneously create a first TSV opening 103 and a second TSV opening 104 through the backside wafer to expose the buried metal features 101, 102 in the wafer substrate layer. While any suitable anisotropic etching process can be used, the etching process can use a patterned photoresist mask (not shown) having an opening that exposes the intended etching region, followed by performing an RIE step with a suitable etching chemistry to remove the exposed portions of the underlying Vdd plate 16, MIM dielectric layer 15, Vss plate 14, and semiconductor substrate 10. For example, one or more second TSV openings 21 can be formed using a controlled optical etching process such as timed anisotropic dry etching, and / or a silicon nitride layer (not shown) can be used to stop the anisotropic etching, and / or to enter the ILD layer 13 to connect to a patterned first metal wire conductor layer M1 or to another middle-of-line process (MEOL) feature such as a contact. While the sidewalls of the TSV etching openings 103, 104 are substantially vertical, it should be understood that due to etching process variations, there may be minor deviations in the sidewall profiles. Figure 2 Although any suitable anisotropic etching process can be used, the etching process can use a patterned photoresist mask (not shown) having an opening that exposes the intended etching region, followed by performing an RIE step with a suitable etching chemistry to remove the exposed portions of the underlying Vdd plate 16, MIM dielectric layer 15, Vss plate 14, and semiconductor substrate 10. For example, one or more second TSV openings 21 can be formed using a controlled optical etching process such as timed anisotropic dry etching, and / or a silicon nitride layer (not shown) can be used to stop the anisotropic etching, and / or to enter the ILD layer 13 to connect to a patterned first metal wire conductor layer M1 or to another middle-of-line process (MEOL) feature such as a contact. While the sidewalls of the TSV etching openings 103, 104 are substantially vertical, it should be understood that due to etching process variations, there may be minor deviations in the sidewall profiles.

[0031] Figure 16 shows the subsequent processing of semiconductor structure 16 after selectively forming a first capping dielectric layer 105 on the sidewalls of the TSV openings 103, 104 according to a selected embodiment of the present disclosure. Figure 15 For example, the first capping dielectric layer 105 can be formed by conformally depositing a suitable low-k dielectric layer (e.g., Si3N4) of a predetermined thickness using any suitable deposition technique to cover the backside of the wafer as well as the bottom and sidewalls of the TSV openings 103, 104. After forming the first capping dielectric layer 105, one or more selective etching processes can be applied to remove the first capping dielectric layer 105 from the bottom of the TSV openings 103, 104. For example, anisotropic or directional etching can be applied to remove the first capping dielectric layer 105 from the horizontal surfaces (e.g., the backside of the wafer and the bottom of the TSV openings 103, 104), while retaining the first capping dielectric layer 105 on the vertical surfaces (e.g., the sidewalls of the TSV openings 103, 104). Thus, the TSV openings 103, 104 expose the buried metal features 101, 102.

[0032] Figure 17 shows the subsequent processing of a semiconductor structure according to a selected embodiment of the present disclosure after partially filling the first TSV opening 103 and the second TSV opening 104 with one or more conductive TSV structures 106, 107 to form a direct electrical contact with the first decoupling capacitor plate 14. Figure 16Processing of the semiconductor structure 17. In selected embodiments, a conductive TSV structure is formed by first depositing a diffusion barrier film / seed liner layer 106 formed of any suitable diffusion barrier material that also permits electrodeposition (e.g., Ti, TiN, Ta, TaN, TiN, TiC, TaC, CuWP, etc.). As part of the diffusion barrier film / seed liner layer 106, one or more conductive seed layers may be formed of any suitable conductive material, such as copper, copper alloy, silver, gold, tungsten, aluminum, etc. In selected embodiments, a conductive TSV structure may be formed by blanket depositing a barrier film in the TSV openings 103, 104, followed by depositing a thin seed layer (e.g., copper or copper alloy, nickel, etc.) over the barrier film, and then partially filling the TSV openings 103, 104 with a copper plating layer 107 or other suitable metallic material by, for example, using electroplating, electroless plating, or depositing a conductive material (e.g., Cu, Co, Ni, Mn, Mg, Zn, Al, etc.). The electroplating process may be controlled to provide bottom-up partial electroplating such that the copper plating layer 107 is formed only on the horizontal surfaces to cover the backside of the wafer and the bottoms of the TSV openings 103, 104, and forms a direct electrical contact with the first decoupling capacitor plate 14 rather than the second decoupling capacitor plate 15.

[0033] Figure 18 Shown is a connection after forming a sacrificial dielectric layer 108 on the backside of the wafer and at the bottoms of the first TSV opening 103 and the second TSV opening 104 according to a selected embodiment of the present disclosure. Figure 17 Processing of the semiconductor structure 18. In selected embodiments, the sacrificial dielectric layer 108 is formed by anisotropically depositing a suitable dielectric layer of a predetermined thickness (e.g., Si3N4, SiO2). Examples of such anisotropic deposition processes include, but are not limited to, low pressure CVD (LPCVD), low pressure plasma enhanced CVD (LP-PECVD), etc. Thus, the sacrificial dielectric layer 108 is not formed on the sidewalls of the TSV openings 103, 104, but is formed on the backside of the wafer and at the bottoms of the TSV openings 103, 104 to cover the copper plating layer 107 at the bottoms of the TSV openings 103, 104. Although the sacrificial dielectric layer 108 is shown deposited on the copper plating layer 107 on the backside of the wafer, it should be understood that the copper plating layer 107 on the backside of the wafer may be removed, for example, by using a CMP process or other suitable selective etching process, such that the sacrificial dielectric layer 108 is formed directly on the second decoupling capacitor plate 16. In any case, the directionally deposited sacrificial dielectric layer 108 exposes the diffusion barrier / seed layer on the exposed sidewalls of the TSV openings 103, 104.

[0034] Figure 19Shows the processing of semiconductor structure 19 after selectively removing the exposed portions of the conduction barrier / seeding layer 106 from the backside of the wafer and the exposed sidewalls of the TSV openings 103, 104 in accordance with a selected embodiment of the present disclosure. Although any suitable selective removal etching process may be used, isotropic etching with a suitable etching chemistry may be applied to remove the exposed portions of the conduction barrier / seeding layer 106 from the backside of the wafer and the sidewalls of the TSV openings 103, 104. Thus, the TSV openings 103, 104 retain the remaining dielectric liner layer 105 that protects the first decoupling capacitor plate 14 and the second decoupling capacitor plate 16. Figure 18 The processing of semiconductor structure 19 is shown. Although any suitable selective removal etching process may be used, isotropic etching with a suitable etching chemistry may be applied to remove the exposed portions of the conduction barrier / seeding layer 106 from the backside of the wafer and the sidewalls of the TSV openings 103, 104. Thus, the TSV openings 103, 104 retain the remaining dielectric liner layer 105 that protects the first decoupling capacitor plate 14 and the second decoupling capacitor plate 16.

[0035] Figure 20 Shows the processing of semiconductor structure 20 after lining the first TSV opening 103 and the second TSV opening 104 with a conformal dielectric liner layer 109 in accordance with a selected embodiment of the present disclosure. For example, the conformal dielectric liner layer 109 may be formed by depositing a suitable low-k dielectric layer (e.g., Si3N4, SiO2) of a predetermined thickness using atomic layer deposition (ALD) or any other suitable deposition technique to cover the backside of the wafer and the bottoms and sidewalls of the first TSV opening 103 and the second TSV opening 104. Figure 19 The processing of semiconductor structure 20 is shown. For example, the conformal dielectric liner layer 109 may be formed by depositing a suitable low-k dielectric layer (e.g., Si3N4, SiO2) of a predetermined thickness using atomic layer deposition (ALD) or any other suitable deposition technique to cover the backside of the wafer and the bottoms and sidewalls of the first TSV opening 103 and the second TSV opening 104.

[0036] Figure 21 Shows the processing of semiconductor structure 21 after applying an unpatterned anisotropic etching process 110 to selectively remove the conformal dielectric liner layer 109 from the backside of the wafer and the bottoms of the TSV openings 103, 104 in accordance with a selected embodiment of the present disclosure. Although any suitable selective etching process 110 may be used, the processing may include applying anisotropic or directional etching to remove the conformal dielectric liner layer 109 from the bottoms of the TSV openings 103, 104 while retaining the conformal dielectric liner layer 109 on the vertical sidewall surfaces of the TSV openings 103, 104. Thus, the sacrificial dielectric layer 108 is exposed on the backside of the wafer and within the TSV openings 103, 104. Figure 20 The processing of semiconductor structure 21 is shown. Although any suitable selective etching process 110 may be used, the processing may include applying anisotropic or directional etching to remove the conformal dielectric liner layer 109 from the bottoms of the TSV openings 103, 104 while retaining the conformal dielectric liner layer 109 on the vertical sidewall surfaces of the TSV openings 103, 104. Thus, the sacrificial dielectric layer 108 is exposed on the backside of the wafer and within the TSV openings 103, 104.

[0037] Figure 22 Shows the processing of semiconductor structure 22 after applying a patterned isotropic etching process 112 to selectively remove at least the sacrificial dielectric layer 108 from the TSV openings 103, 104 in accordance with a selected embodiment of the present disclosure. Figure 21Processing of the semiconductor structure 22. Although any suitable selective etching process 112 can be used, the processing can include forming a patterned etch mask 111 around the TSV openings 103 on the sacrificial dielectric layer 108, followed by applying an isotropic etch with a suitable etch chemistry to remove the exposed portions of the sacrificial dielectric layer 108 from the backside of the wafer and the bottoms of the TSV openings 103, 104 while retaining the copper plating layer 107 on the backside of the wafer and the bottoms of the TSV openings 103, 104. Thus, the conduction barrier film / seed liner layer 106 on the sidewalls of the TSV openings 103, 104 is exposed.

[0038] Figure 23 Shows the connection after applying a selective etching process 114 to at least selectively remove the exposed portions of the conduction barrier film / seed liner layer 106 from the TSV opening 103 according to a selected embodiment of the present disclosure. Figure 22 Processing of the semiconductor structure 23. Although any suitable selective etching process 114 can be used, the processing can include forming a patterned etch mask 113 on the copper plating layer 107 to cover the TSV opening 104. Using the patterned etch mask 113 and the remaining sacrificial dielectric layer 108 as an etch mask, an etching process with a suitable etch chemistry can be applied to remove the exposed portions of the conduction barrier film / seed liner layer 106 from the backside of the wafer and the exposed sidewalls of the TSV opening 103. Thus, the exposed conduction barrier film / seed liner layer 106 on the sidewalls of the TSV opening 103 is removed, thereby exposing at least a portion of the first capping dielectric layer 105.

[0039] Figure 24 Shows the connection after applying a selective etching process 116 to at least selectively remove the exposed first capping dielectric layer 105 on the sidewalls of the TSV opening 103 according to a selected embodiment of the present disclosure. Figure 23 Processing of the semiconductor structure 24. Although any suitable selective etching process 116 can be used, the processing can use the patterned etch mask 113 and the remaining sacrificial dielectric layer 108 as an etch mask, and at this time, an etching process with a suitable etch chemistry is applied to remove the exposed portions of the first capping dielectric layer 105 from the sidewalls of the TSV opening 103. Thus, the exposed first capping dielectric layer 105 on the sidewalls of the TSV opening 103 is removed, thereby forming an opening 117 in the TSV opening 103 that exposes at least a portion of the first decoupling capacitor plate 14.

[0040] Figure 25 Shows the connection after forming a second seed layer 118 in the TSV openings 103, 104 to make direct electrical contact with the conductive TSV structures 106, 107 according to a selected embodiment of the present disclosure. Figure 24Processing of the semiconductor structure 25. For example, the second seed layer 118 can be formed by conformally depositing one or more conductive seed layers of a predetermined thickness using any suitable conductive material (e.g., copper, copper alloy, silver, gold, tungsten, aluminum, etc.) using any suitable deposition technique.

[0041] Figure 26 Illustrated is a semiconductor structure 26 after a metal plating layer 119 is formed over the back side of the wafer and used to fill the TSV openings 103, 104 according to a selected embodiment of the present disclosure. Figure 25 Processing of the semiconductor structure 26. For example, the metal plating layer 119 can be formed by electroplating, electroless plating, or depositing a conductive material (e.g., Cu, Co, Ni, Mn, Mg, Zn, Al, etc.) of a predetermined thickness using any suitable deposition technique.

[0042] Figure 27 Illustrated is a semiconductor structure 27 after a patterned Vss metal layer 120 and a patterned Vdd metal layer 121 are formed according to a selected embodiment of the present disclosure. Figure 26 Processing of the semiconductor structure 27. For example, any suitable selective etching process can be used to pattern and etch the metal plating layer 119 to form a patterned Vss metal layer 120 and a Vdd metal layer 121 on the back side of the wafer. As formed, the patterned Vss metal layer 120 is electrically connected to the buried metal feature 101 and the first decoupling capacitor plate 14 via the conductive TSV structure 107 in the TSVg opening 103. Additionally, the patterned Vdd metal layer 121 is electrically connected to the buried metal feature 102 via the conductive TSV structure 107 in the TSVp opening 104 and is also connected to the second decoupling capacitor plate 16 via the remaining copper plating layer 107 on the back side of the wafer.

[0043] Turning now to Figure 28 , illustrated is a simplified process flow 200 for manufacturing separate back-side ground and power connection lines according to a selected embodiment of the present disclosure. Although the selected embodiments of the back-side ground and power connection manufacturing methods are described with reference to the example back-end manufacturing process, those skilled in the art should understand that the illustrated sequence of steps can be used at any suitable stage of the device manufacturing process and can be modified, reduced, or augmented in accordance with the disclosure of the present invention. Thus, it should be understood that the method of the present disclosure can be considered to perform the identified sequence of steps in the order described in Figure 28 , but these steps can also be performed in parallel, in a different order, or as combined independent operations.

[0044] The disclosed manufacturing method starts with one or more front-end-of-line (FEOL) processing steps 201 for manufacturing a wafer substrate having buried Vdd and / or Vss regions and / or power rails connected to one or more integrated circuit elements (e.g., transistors, capacitors, resistors, diodes, etc.). Generally, FEOL processing is the first part of IC manufacturing where individual components (transistors, capacitors, resistors, etc.) are patterned in the semiconductor and typically covers everything up to (but not including) the deposition of the metal interconnect layers.

[0045] At step 202, a Vss plate conductor plate layer, a MIM dielectric layer, and a Vdd plate conductor layer are sequentially formed on the back side of the wafer substrate. In an example embodiment, the Vss plate conductor plate layer may be formed as a nickel plate layer with a dielectric coating, but any suitable conductive material may be deposited to form the first decoupling capacitor plate. Additionally, the MIM dielectric layer may be formed on the Vss plate conductor plate layer by depositing a high-k dielectric material (e.g., TaN). Additionally, the Vdd plate conductor layer may be formed on the MIM dielectric layer by depositing a conductive material (e.g., Ta), but any suitable conductive material may be deposited to form the second decoupling capacitor plate.

[0046] At step 203, power and ground TSV openings may be selectively etched through the back side of the wafer substrate to contact buried Vdd and / or Vss regions or power rails formed in the semiconductor substrate. In other embodiments, power and ground TSV openings may be selectively etched through the wafer substrate to contact features in the ILD interconnect layer. As disclosed herein, the power and ground TSV openings may be formed simultaneously or sequentially using any suitable masking etch process, such as by forming a patterned photoresist layer as an etch mask and then applying one or more anisotropic etch processes to etch through the Vss plate conductor plate layer, the MIM dielectric layer, the Vdd plate conductor layer, and the back side of the wafer substrate.

[0047] At step 204, a conformal dielectric layer is selectively formed on the sidewalls (but not on the bottom) of the power TSV opening. In an example embodiment, the selective formation of the conformal dielectric layer may include an initial step of depositing a conformal dielectric layer above the back side of the wafer, followed by the application of an anisotropic etch process to selectively remove the conformal dielectric layer from the bottom (but not the sidewalls) of the power TSV opening. In a selected embodiment, the conformal dielectric layer may be formed of photoimageable polyimide, or SiOx, SiCN, SixNy, or a combination and variant thereof may be used.

[0048] At step 205, one or more conductive layers may be used to partially fill the power and ground TSV openings. In an example embodiment, one or more conductive layers may be formed by sequentially depositing a barrier liner layer, a seed layer, and an electroplated cladding layer in the power and ground TSV openings up to the level of the Vss plate conductor plate layer rather than the Vdd plate conductor plate layer in the ground TSV opening. As disclosed herein, the barrier film may use any suitable diffusion barrier layer that also allows for electrodeposition, including but not limited to TiN, TaN, TiC, TaC, CuWP, or the like or combinations thereof. Additionally, the electroplated cladding metal may include cobalt, nickel, copper, etc. Various combinations of these and slight additions of other metals such as Mn, Mg, Zn, Al etching may also be employed.

[0049] At step 206, a dielectric liner layer is selectively formed that covers the sidewalls of the power and ground TSV openings and one or more conductive layers in the ground TSV opening, but exposes one or more conductive layers in the power TSV opening. In an example embodiment, the selective formation of the dielectric liner layer may include an initial step of depositing a conformal dielectric liner layer above the backside of the wafer, followed by the application of a selective masking and / or etching process to selectively remove the conformal dielectric liner layer to protect or cover the conductive layers in the ground TSV opening while exposing the conductive layers in the power TSV opening.

[0050] At step 207, the remaining portions of the power and ground TSV openings are filled with one or more conductive layers to cover the backside of the wafer and form the Vdd plate and / or Vss plate as part of the backside power and ground distribution network. In an example embodiment, one or more conductive layers may be formed by sequentially depositing a seed layer and an electroplated cladding layer in the power and ground TSV openings to fill the power and ground TSV openings and cover the backside of the wafer. The conductive layer may be planarized on the backside of the wafer to form the Vdd plate layer. Additionally or alternatively, the conductive layer may be patterned and etched to form the Vdd plate / conductor layer and / or the Vss plate / conductor layer.

[0051] As described above, the present disclosure provides a mechanism for integrating backside power and ground distribution network connections by adding through-silicon vias through the backside, which are selectively filled with conductive layers using selective deposition and removal of a passivation layer such that the conductive TSV connectors electrically connect the buried power lines or regional power in the wafer substrate to the decoupling capacitor plates of a uniform film, full-die decoupling MIM capacitor formed on the backside of the wafer. In addition to reducing manufacturing costs and the complexity of forming power and ground connections, the disclosed backside power and ground distribution network also reduces front-side metallization congestion, resistance, capacitance, and power consumption issues for routing power and ground signals through the backside of the substrate, while also providing improved EMI shielding for the decoupling capacitor plates and TSVs.

[0052] While the described exemplary embodiments disclosed herein relate to various semiconductor and integrated circuit device structures and methods of manufacturing the same, the invention is not necessarily limited to the example embodiments that illustrate the inventive aspects of the invention applicable to a wide variety of semiconductor processes and / or devices. Accordingly, the specific embodiments disclosed above are illustrative only and should not be construed as limitations of the invention, since the invention may be modified and practiced in different but equivalent manners, which would be apparent to those skilled in the art who have benefited from the teachings herein. Accordingly, the foregoing description is not intended to limit the invention to the particular forms set forth, but on the contrary, is intended to cover such alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims, such that those skilled in the art should understand that they may make various changes, substitutions, and variations in its broadest form without departing from the spirit and scope of the invention.

[0053] Benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, these benefits, advantages, solutions to problems, and any element that may cause any benefit, advantage, or solution to occur or become more apparent should not be construed as an essential, necessary, or fundamental feature of any or all of the elements of the claims. As used herein, the term “comprises,” “comprising,” or any other variation thereof is intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Claims

1. A method, characterized in that include: providing a semiconductor wafer including a plurality of integrated circuit (IC) devices formed on a front side of a semiconductor substrate layer having integrated device connection features formed therein; forming a decoupling capacitor on the back side of the semiconductor substrate layer, the decoupling capacitor comprising a first capacitor plate, a capacitor dielectric layer, and a second capacitor plate; selectively etching a plurality of through semiconductor via (TSV) openings through the decoupling capacitor and the backside of the semiconductor substrate layer to contact the integrated device connection features; forming a first voltage supply TSV conductor in a first TSV opening of each IC device, the first voltage supply TSV conductor providing a direct electrical connection between the first capacitor plate and a first integrated device connection feature formed in the semiconductor substrate layer; forming a second voltage supply TSV conductor in a second TSV opening of each IC device, the second voltage supply TSV conductor providing a direct electrical connection between the second capacitor plate and a second integrated device connection feature formed in the semiconductor substrate layer; singulating the semiconductor wafer into a plurality of integrated circuit dies; Wherein the first voltage supply TSV conductor is not directly electrically connected to the second capacitor plate, and wherein the second voltage supply TSV conductor is not directly electrically connected to the first capacitor plate.

2. The method according to claim 1, characterized in that Selectively etching the plurality of TSV openings includes sequentially etching the first TSV opening and the second TSV opening through the decoupling capacitor and the backside of the semiconductor substrate layer to contact the integrated device connection features.

3. The method according to claim 1, characterized in that Selectively etching the plurality of TSV openings includes simultaneously etching the first TSV opening and the second TSV opening through the decoupling capacitor and the backside of the semiconductor substrate layer to contact the integrated device connection features.

4. The method according to claim 3, characterized in that Forming the first voltage supply TSV conductor includes: selectively forming a conformal dielectric layer on sidewalls but not on a bottom of the first TSV opening to expose the first integrated device connection feature; partially filling the first TSV opening with one or more first conductive layers to form at least a portion of the first voltage supply TSV conductor; selectively etching the conformal dielectric layer from a portion of the sidewall of the first TSV opening to expose the first capacitor plate; and filling the first TSV opening with one or more second conductive layers directly electrically connected to the first capacitor plate and the one or more first conductive layers, Wherein the unetched portion of the conformal dielectric layer prevents direct electrical connection between the first voltage supply TSV conductor and the second capacitor plate.

5. A method for forming a backside supply voltage distribution conductor on a semiconductor device, the backside supply voltage distribution conductor being shielded from electromagnetic interference, characterized in that The method comprises: forming a first decoupling capacitor plate and a second decoupling capacitor plate separated by a capacitor dielectric layer on a back side of the semiconductor device; and A conductive through silicon via (TSV) structure is selectively formed in the semiconductor device, comprising: a conductive first voltage supply TSV structure that electrically connects a Vdd power connection feature formed in the semiconductor device directly to the second decoupling capacitor plate instead of directly to the first decoupling capacitor plate, and A conductive second voltage supply TSV structure electrically connects a Vss ground connection feature formed in the semiconductor device directly to the first decoupling capacitor plate instead of directly to the second decoupling capacitor plate.

6. The method according to claim 5, characterized in that Selectively forming a conductive TSV structure includes: selectively etching a first TSV opening and a second TSV opening through the first decoupling capacitor plate and the second decoupling capacitor plate separated by the capacitor dielectric layer on the back side of the semiconductor device to contact the Vdd power connection feature and the Vss ground connection feature, respectively; forming the conductive first voltage supply TSV structure in the first TSV opening to provide a direct electrical connection between the first decoupling capacitor plate and the Vdd power connection feature formed in the semiconductor device; and The conductive second voltage supply TSV structure is formed in the second TSV opening to provide a direct electrical connection between the second decoupling capacitor plate and the Vss ground connection feature formed in the semiconductor device.

7. The method according to claim 6, characterized in that Forming the conductive first voltage supply TSV structure includes: selectively forming a conformal dielectric layer on sidewalls but not on a bottom of the first TSV opening to expose the Vdd power connection feature; partially filling the first TSV opening with one or more first conductive layers to form at least a portion of the conductive first voltage supply TSV structure; and filling the first TSV opening with one or more second conductive layers to form the conductive first voltage supply TSV structure, Wherein the conformal dielectric layer prevents direct electrical connection between the conductive first voltage supply TSV structure and the first decoupling capacitor plate.

8. The method according to claim 6, characterized in that Forming the conductive second voltage supply TSV structure includes: partially filling the second TSV opening with one or more first conductive layers to form at least a portion of the conductive second voltage supply TSV structure directly electrically connecting between the first decoupling capacitor plate and the Vss ground connection feature; selectively forming an insulating dielectric layer in an unfilled portion of the second TSV opening; and filling the unfilled portion of the second TSV opening with one or more second conductive layers, Wherein the insulating dielectric layer prevents direct electrical connection between the conductive second voltage supply TSV structure and the second decoupling capacitor plate.

9. The method according to claim 6, characterized in that Selectively etching first and second TSV openings includes simultaneously etching first and second TSV openings through the first and second decoupling capacitor plates separated by the capacitor dielectric layer and the back side of the semiconductor device to contact the Vdd power connection feature and the Vss ground connection feature, respectively.

10. An integrated circuit, characterized in that: include: a semiconductor substrate comprising a plurality of integrated circuit (IC) devices formed on a front side of the semiconductor substrate and first and second integrated connection features formed in or over the semiconductor substrate; a capacitor formed on the back side of the semiconductor substrate, the capacitor comprising a first capacitor plate and a second capacitor plate separated by a capacitor dielectric layer; a first conductive TSV structure formed through the backside of the semiconductor substrate to electrically connect the first integrated connection feature directly to the second capacitor plate instead of directly to the first capacitor plate; as well as A second TSV structure is formed through the backside of the semiconductor substrate to electrically connect the second integrated connection feature directly to the first capacitor plate instead of directly to the second capacitor plate.

Images