Semiconductor structure and preparation method thereof, memory device and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor structure and a preparation method thereof, a memory device and electronic equipment. The preparation method of the semiconductor structure comprises the following steps: providing a substrate; forming a first initial semiconductor layer of which the material is a doped amorphous material; then, forming a first electrode and a first semiconductor layer made of a single crystal material; then, a second initial semiconductor layer made of a doped amorphous material is formed, and the doping type of the second initial semiconductor layer is opposite to that of the first initial semiconductor layer; then, forming a second electrode and a second semiconductor layer made of a single crystal material; then, a gate structure, a third electrode, a first channel, a fourth electrode and a second channel are formed, the first electrode, the first channel, the gate structure and the third electrode form a first transistor, and the second electrode, the second channel, the gate structure and the fourth electrode form a second transistor. The semiconductor structure provided by the embodiment of the invention is simple in preparation process, small in occupied area, low in manufacturing cost and high in working performance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology. Specifically, the present application relates to a semiconductor structure, a method for manufacturing the same, a storage device, and an electronic device. Background Art

[0002] A memory is the main medium for storing data in a computer. With the development and progress of storage technology, storage devices are continuously evolving towards miniaturization, high device density, and high integration. At the same time, they also face problems and challenges brought by manufacturing and other aspects. Summary of the Invention

[0003] The present application provides a semiconductor structure, a method for manufacturing the same, a storage device, and an electronic device. The manufacturing process of the semiconductor structure is simple, it occupies a small area, has a low manufacturing cost, and high working performance.

[0004] In a first aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, including:

[0005] Providing a substrate;

[0006] Forming a first initial semiconductor layer on one side of the substrate, the material of the first initial semiconductor layer being a doped amorphous material;

[0007] Converting the first initial semiconductor layer into a first electrode and a first semiconductor layer, the first electrode being located at one end of the first semiconductor layer, and the material of the first semiconductor layer being a single crystal material;

[0008] Forming a second initial semiconductor layer on the side of the first semiconductor layer away from the substrate. The positive projection of the first electrode on the substrate and the positive projection of the first semiconductor layer on the substrate respectively overlap with the positive projection of the second initial semiconductor layer on the substrate. The first electrode and the first semiconductor layer are respectively insulated from the second initial semiconductor layer. The material of the second initial semiconductor layer is a doped amorphous material, and the doping type of the second initial semiconductor layer is opposite to that of the first initial semiconductor layer;

[0009] Converting the second initial semiconductor layer into a second electrode and a second semiconductor layer, the second electrode being located at one end of the second semiconductor layer, and the material of the second semiconductor layer being a single crystal material;

[0010] Forming a gate structure, the positive projection of the gate structure on the substrate overlapping with the positive projections of the first semiconductor layer and the second semiconductor layer on the substrate;

[0011] Form a third electrode at an end of the first semiconductor layer away from the first electrode, and the remaining first semiconductor layer forms a first channel. Form a fourth electrode at an end of the second semiconductor layer away from the second electrode, and the remaining second semiconductor layer forms a second channel. The first electrode, the first channel, the gate structure, and the third electrode form a first transistor, and the second electrode, the second channel, the gate structure, and the fourth electrode form a second transistor.

[0012] In some alternative embodiments of the present application, forming the first initial semiconductor layer into the first electrode and the first semiconductor layer includes:

[0013] Adopt a metal-induced crystallization process to form a part of the first initial semiconductor layer into the first electrode, and transform another part of the first initial semiconductor layer of amorphous material into a single-crystal material of the first semiconductor layer.

[0014] In some alternative embodiments of the present application, before forming the first initial semiconductor layer on one side of the substrate, the preparation method further includes:

[0015] Form a first barrier layer on one side of the substrate;

[0016] Forming the first initial semiconductor layer on one side of the substrate includes:

[0017] Form a first amorphous silicon thin film on a side of the first barrier layer away from the substrate;

[0018] Perform ion implantation on the first amorphous silicon thin film;

[0019] Perform a first patterning process to form the first amorphous silicon thin film into a sequentially connected first initial electrode region, a first initial channel region, and a second initial electrode region. The area of the projection of the first initial electrode region on the substrate and the area of the projection of the second initial electrode region on the substrate are respectively larger than the area of the projection of the first initial channel region on the substrate, so as to serve as the first initial semiconductor layer.

[0020] In some alternative embodiments of the present application, forming the first initial semiconductor layer into the first electrode and the first semiconductor layer includes:

[0021] Form a first covering layer on one side of the substrate. The first covering layer covers the first initial semiconductor layer. The first covering layer has a first induction hole, and the bottom of the first induction hole exposes the first initial electrode region;

[0022] Form a first induction layer on one side of the substrate. The first induction layer covers the first covering layer, the inner wall of the first induction hole, and the exposed first initial electrode region. The first induction layer is in contact with the first initial electrode region, and the material of the first induction layer includes metal;

[0023] Perform a first heat treatment to convert the amorphous silicon in the first initial electrode region into metal silicide to form the first electrode;

[0024] Perform a second heat treatment, using the metal material in the first induced layer as the induction source and the metal silicide of the first electrode as the medium, to induce the amorphous silicon in the first initial channel region and the second initial electrode region to convert into single crystal silicon and activate the implanted ions to form the first semiconductor layer.

[0025] In some optional embodiments of the present application, forming a first covering layer on one side of the substrate includes:

[0026] Deposit a silicon oxide material on one side of the substrate to form a first initial covering layer, and the first initial covering layer covers the first barrier layer and the first initial semiconductor layer;

[0027] Perform a second patterning process to form a first induced hole penetrating the first initial covering layer. The orthographic projection of the first induced hole on the substrate covers the orthographic projection of the first initial electrode region on the substrate, and the patterned first initial covering layer forms the first covering layer.

[0028] In some optional embodiments of the present application, forming a first induced layer on one side of the substrate includes:

[0029] Deposit a first silicon oxide thin film and a first nickel thin film on one side of the substrate in sequence. The first silicon oxide thin film covers the first covering layer, the inner wall of the first induced hole, and the exposed first initial electrode region. The first nickel thin film covers the side of the first silicon oxide thin film away from the substrate, and the first silicon oxide thin film and the first nickel thin film form the first induced layer;

[0030] Perform a first heat treatment, including:

[0031] Perform an annealing treatment at 400°C - 500°C for a treatment time of 1 min - 5 min, so that the amorphous silicon in the first initial electrode region reacts with the nickel material in the first induced layer to form nickel silicide to form the first electrode;

[0032] Perform a second heat treatment, including:

[0033] Perform an annealing treatment at 500°C - 600°C for a treatment time of 1 h - 24 h. The induction source is the nickel material in the first induced layer, and the medium is the nickel silicide of the first electrode.

[0034] In some optional embodiments of the present application, after performing the second heat treatment, the preparation method further includes:

[0035] Remove the remaining first nickel thin film;

[0036] Deposit a silicon oxide material on one side of the substrate to form a second barrier layer, which covers the first silicon oxide thin film and fills the first induced hole.

[0037] In some alternative embodiments of the present application, forming a second initial semiconductor layer on the side of the first semiconductor layer away from the substrate includes:

[0038] Form a second amorphous silicon thin film on the side of the second barrier layer away from the substrate;

[0039] Perform a third patterning process to form the second amorphous silicon thin film into a third initial electrode region, a second initial channel region, and a fourth initial electrode region that are sequentially connected. The orthographic projection area of the third initial electrode region on the substrate and the orthographic projection area of the fourth initial electrode region on the substrate are respectively larger than the orthographic projection area of the second initial channel region on the substrate;

[0040] Ion implant the second amorphous silicon thin film to form a second initial semiconductor layer. The ion type implanted in the second initial semiconductor layer is opposite to the ion type implanted in the first initial semiconductor layer.

[0041] In some alternative embodiments of the present application, forming the second initial semiconductor layer into a second electrode and a second semiconductor layer includes:

[0042] Form a second covering layer on one side of the substrate. The second covering layer covers the second initial semiconductor layer and the second barrier layer. The second covering layer has a second induced hole, and the bottom of the second induced hole exposes the third initial electrode region;

[0043] Form a second induced layer on one side of the substrate. The second induced layer covers the second covering layer, the inner wall of the second induced hole, and the exposed third initial electrode region. The second induced layer contacts the third initial electrode region, and the material of the second induced layer includes a metal;

[0044] Perform a third heat treatment to transform the amorphous silicon in the third initial electrode region into a metal silicide to form a second electrode;

[0045] Perform a fourth heat treatment. Using the metal material in the second induced layer as an induction source and the metal silicide of the second electrode as a medium, induce the amorphous silicon in the second initial channel region and the fourth initial electrode region to transform into single crystal silicon and activate the implanted ions to form a second semiconductor layer.

[0046] In some alternative embodiments of the present application, before forming the gate structure, the preparation method further includes:

[0047] Deposit a silicon oxide material on one side of the substrate to form a first insulating layer, which covers the second induced layer and fills the second induced hole;

[0048] Forming a gate structure includes:

[0049] Form a first groove exposing a first initial channel region and a second initial channel region, the first groove extending in a direction perpendicular to the substrate;

[0050] Form a gate dielectric layer that covers sidewalls of the first initial channel region, sidewalls of the second initial channel region, and inner walls of the first groove;

[0051] Form a gate electrode that fills the first groove, with the gate dielectric layer located between the first initial channel region and the gate electrode and between the second initial channel region and the gate electrode. The first transistor and the second transistor share a common gate electrode.

[0052] In some alternative embodiments of the present application, after forming the gate structure, before forming a third electrode at an end of the first semiconductor layer away from the first electrode, with the remaining first semiconductor layer forming a first channel, and forming a fourth electrode at an end of the second semiconductor layer away from the second electrode, with the remaining second semiconductor layer forming a second channel, the preparation method further includes:

[0053] Form a second insulating layer on one side of the substrate, the second insulating layer covering the first insulating layer, the gate dielectric layer, and the gate electrode;

[0054] Forming a third electrode at an end of the first semiconductor layer away from the first electrode, with the remaining first semiconductor layer forming a first channel, and forming a fourth electrode at an end of the second semiconductor layer away from the second electrode, with the remaining second semiconductor layer forming a second channel, includes:

[0055] Form a second groove exposing a second initial electrode region and a fourth initial electrode region, the second groove extending in a direction perpendicular to the substrate, and a positive projection of the second groove on the substrate covering a positive projection of the second initial electrode region on the substrate and covering a positive projection of the fourth initial electrode region on the substrate;

[0056] Deposit nickel material on surfaces of the exposed second initial electrode region and the fourth initial electrode region respectively, and perform rapid thermal annealing treatment to transform single-crystalline silicon in the second initial electrode region and the fourth initial electrode region into nickel silicide respectively. After the rapid thermal annealing treatment, the second initial electrode region forms the third electrode, the first initial channel region forms the first channel, the fourth initial electrode region after the rapid thermal annealing treatment forms the fourth electrode, and the second initial channel region forms the second channel.

[0057] In some alternative embodiments of the present application, after forming a third electrode at an end of the first semiconductor layer away from the first electrode, with the remaining first semiconductor layer forming a first channel, and forming a fourth electrode at an end of the second semiconductor layer away from the second electrode, with the remaining second semiconductor layer forming a second channel, the preparation method further includes:

[0058] A drain-end connection structure is formed, the drain-end connection structure fills the second groove, the drain-end connection structure is in contact with the third electrode and the fourth electrode respectively, and the first transistor and the second transistor share a drain-end connection structure.

[0059] In some alternative embodiments of the present application, after forming the drain-end connection structure, the manufacturing method further includes:

[0060] Form a via hole penetrating the second insulating layer, and the bottom of the via hole exposes the gate electrode;

[0061] Form a gate electrode connection structure, fill the via hole with the gate electrode connection structure, one end of the gate electrode connection structure is in contact with the gate electrode, and the other end is used for connection with an external device.

[0062] In some alternative embodiments of the present application, after forming the gate electrode connection structure, the manufacturing method further includes:

[0063] Form a third groove exposing the first electrode, the third groove extends in a direction perpendicular to the substrate, and the orthographic projection of the third groove on the substrate overlaps with the orthographic projection of the first electrode on the substrate;

[0064] Form a first source-end connection structure, fill the third groove with the first source-end connection structure, and the first source-end connection structure is in contact with the first electrode;

[0065] Form a fourth groove exposing the second electrode, the fourth groove extends in a direction perpendicular to the substrate, the orthographic projection of the fourth groove on the substrate overlaps with the orthographic projection of the second electrode on the substrate, and has no overlap with the orthographic projection of the third groove on the substrate;

[0066] Form a second source-end connection structure, fill the fourth groove with the second source-end connection structure, and the second source-end connection structure is in contact with the second electrode.

[0067] In a second aspect, an embodiment of the present application provides a semiconductor structure, including:

[0068] A substrate;

[0069] A first transistor disposed on one side of the substrate, the first transistor includes a first channel, a first electrode, a gate structure, and a third electrode, the material of the first channel is a single crystal material, the first electrode is located at one end of the first channel, the third electrode is located at the end of the first channel far from the first electrode, and the orthographic projection of the gate structure on the substrate overlaps with the orthographic projection of the first channel on the substrate and is insulated from the first channel;

[0070] A second transistor is disposed on a side of the first transistor away from the substrate. The second transistor includes a second channel, a second electrode, a gate structure, and a fourth electrode. The material of the second channel is a single crystal material. The second electrode is located at one end of the second channel, and the fourth electrode is located at an end of the second channel away from the second electrode. The orthographic projection of the gate structure on the substrate overlaps the orthographic projection of the second channel on the substrate and is insulated from the second channel;

[0071] The conduction type of the first transistor is opposite to that of the second transistor.

[0072] In some alternative embodiments of the present application, the first transistor is an N-type field effect transistor, and the second transistor is a P-type field effect transistor. Along the direction perpendicular to the substrate, the N-type field effect transistor and the P-type field effect transistor are stacked on the substrate in sequence;

[0073] and / or,

[0074] The first transistor is a junctionless field effect transistor, and the second transistor is a junctionless field effect transistor.

[0075] In some alternative embodiments of the present application, the gate structure extends along the direction perpendicular to the substrate, and the first transistor and the second transistor share a gate structure;

[0076] The semiconductor structure further includes a drain terminal connection structure, a gate electrode connection structure, a first source terminal connection structure, and a second source terminal connection structure;

[0077] One end of the gate electrode connection structure is connected to the gate electrode of the gate structure, and the other end is used for connection with an external device;

[0078] The drain terminal connection structure is respectively connected to the third electrode and the fourth electrode, and the first transistor and the second transistor share a drain terminal connection structure;

[0079] The first source terminal connection structure is connected to the first electrode, and its orthographic projection on the substrate has no overlap with the orthographic projection of the second electrode on the substrate; the second source terminal connection structure is connected to the second electrode;

[0080] The dimension of the first source terminal connection structure along the direction perpendicular to the substrate is greater than the dimension of the second source terminal connection structure along the direction perpendicular to the substrate, and the first source terminal connection structure and the second source terminal connection structure are in a stepped shape.

[0081] In a third aspect, an embodiment of the present application provides a storage device, including: a semiconductor structure prepared by using the preparation method of the above semiconductor structure; or, the above semiconductor structure.

[0082] In a fourth aspect, an embodiment of the present application provides an electronic device, including: the above storage device.

[0083] The beneficial technical effects brought by the technical solution provided in the embodiment of the present application include:

[0084] In the embodiment of the present application, the material of the first initial semiconductor layer is a doped amorphous material. The first initial semiconductor layer is formed into a first electrode and a first semiconductor layer. The amorphous material of the first initial semiconductor layer is transformed into a single-crystal material of the first semiconductor layer. The first electrode is located at one end of the first semiconductor layer. The orthographic projection of the gate structure on the substrate overlaps with the orthographic projection of the first semiconductor layer on the substrate. A third electrode is formed at the end of the first semiconductor layer away from the first electrode. The remaining first semiconductor layer forms a first channel. The first electrode, the first channel, the gate structure, and the third electrode form a first transistor. The material of the first channel is a single-crystal material, which has the advantages of high mobility and low impedance, can effectively reduce the resistance of the gate structure, and thus improve the working performance of the first transistor.

[0085] In the embodiment of the present application, the material of the second initial semiconductor layer is a doped amorphous material. The second initial semiconductor layer is formed into a second electrode and a second semiconductor layer. The amorphous material of the second initial semiconductor layer is transformed into a single-crystal material of the second semiconductor layer. The second electrode is located at one end of the second semiconductor layer. The orthographic projection of the gate structure on the substrate overlaps with the orthographic projection of the second semiconductor layer on the substrate. A fourth electrode is formed at the end of the second semiconductor layer away from the second electrode. The remaining second semiconductor layer forms a second channel. The second electrode, the second channel, the gate structure, and the second electrode form a second transistor. The material of the second channel is a single-crystal material, which has the advantages of high mobility and low impedance, can effectively reduce the resistance of the gate structure, and thus improve the working performance of the second transistor.

[0086] In the embodiment of the present application, the second initial semiconductor layer is located on the side of the first semiconductor layer away from the substrate. The orthographic projections of the first electrode and the second semiconductor layer on the substrate respectively overlap with the orthographic projection of the second initial semiconductor layer on the substrate, and the first electrode and the first semiconductor layer are respectively insulated from the second initial semiconductor layer, so that the formed second transistor is located on the side of the first transistor away from the substrate and is insulated from the first transistor. Along the direction perpendicular to the substrate, the first transistor and the second transistor are stacked on the substrate in sequence, so that the semiconductor structure occupies less space and area, and the integration density of the storage device can be improved. The first transistor and the second transistor are stacked in the vertical direction, which can further reduce the area occupied by the device and improve the integration degree of the storage device. At the same time, it can be formed on the same substrate by a simple method, realizing high density, high performance, multi-function and low power consumption of a single chip.

[0087] In the embodiment of the present application, the first transistor and the second transistor share a gate structure, and the on-off states of the upper and lower two transistors (i.e., the first transistor and the second transistor) with different conduction types can be simultaneously controlled by the same gate structure.

[0088] The present application provides a method for fabricating a 3D (3Dimension) stacked CFET structure. The fabricated CFET structure has an NFET (N-type field effect transistor) and a PFET (P-type field effect transistor). The PFET is vertically stacked on top of the NFET and the PFET and NFET share a common gate. The materials of the first channel and the second channel are both single crystal materials transformed from amorphous materials, having a relatively high mobility and a relatively low impedance. The fabrication process of the CFET structure in the present application is simple, the fabricated CFET structure occupies a small area, has a low manufacturing cost, and a high working performance.

[0089] Additional aspects and advantages of the present application will be given in part in the following description, and will become apparent from the following description, or will be understood through the practice of the present application. Description of the Drawings

[0090] The above and / or additional aspects and advantages of the present application will become apparent and be easily understood from the following description of the embodiments in conjunction with the drawings, where:

[0091] Figure 1 is a schematic flowchart of a method for fabricating a semiconductor structure provided by an embodiment of the present application;

[0092] Figures 2 to 30 is a schematic structural diagram of a method for fabricating a semiconductor structure provided by an embodiment of the present application at different processes.

[0093] Reference Signs:

[0094] 100 - Semiconductor structure; 10 - Substrate; 21 - First initial semiconductor layer; 22 - First amorphous silicon thin film; 23 - First initial electrode region; 24 - First initial channel region; 25 - Second initial electrode region; 31 - First electrode; 32 - First semiconductor layer; 33 - Third electrode; 34 - First channel; 41 - Second initial semiconductor layer; 42 - Second amorphous silicon thin film; 43 - Third initial electrode region; 44 - Second initial channel region; 45 - Fourth initial electrode region; 51 - Second electrode; 52 - Second semiconductor layer; 53 - Fourth electrode; 54 - Second channel; 60 - Gate structure; 61 - Gate dielectric layer; 62 - Gate electrode; 71 - First barrier layer; 72 - Second barrier layer; 73 - First insulating layer; 74 - Second insulating layer; 81 - First capping layer; 811 - First initial capping layer; 82 - First induced hole; 83 - First induced layer; 831 - First silicon oxide thin film; 832 - First nickel thin film; 91 - Second capping layer; 92 - Second induced hole; 93 - Second induced layer; 931 - Second silicon oxide thin film; 932 - Second nickel thin film; 101 - First trench; 102 - Second trench; 103 - Drain end connection structure; 104 - Via; 105 - Gate electrode connection structure; 106 - Third trench; 107 - First source end connection structure; 108 - Fourth trench; 109 - Second source end connection structure; 110 - First transistor; 120 - Second transistor. Detailed implementation manners

[0095] The embodiments of the present application will be described below with reference to the accompanying drawings in the present application. It should be understood that the implementation manners described below in conjunction with the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application, and do not constitute limitations on the technical solutions of the embodiments of the present application.

[0096] Those skilled in the art of the present technology can understand that unless specifically stated otherwise, the singular forms "a", "an", "the", and "said" used herein may also include the plural forms. It should be further understood that the term "including" used in the description of the present application means the presence of the described features, integers, steps, operations, elements, and / or components, but does not exclude the presence of other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by the art of the present technology. The term "and / or" used herein means at least one of the items defined by the term, for example, "A and / or B" can be implemented as "A", or implemented as "B", or implemented as "A and B".

[0097] To make the objectives, technical solutions, and advantages of the present application clearer, the embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0098] With the development and progress of storage technologies, storage devices are continuously evolving towards miniaturization, high device density, and high integration.

[0099] Compared with the traditional CMOS (Complementary Metal Oxide Semiconductor) structure in which transistors are arranged on a two-dimensional plane, the vertically stacked CFET (Complementary Field Effect Transistor) structure reduces the standard cell area by 50%, and is considered a solution path for CMOS scaling technology.

[0100] However, the manufacturing process of the conventional monolithic CFET structure is extremely complex, and there are process challenges such as inner sidewalls, epitaxy, and N / P isolation, which are not conducive to reducing the manufacturing cost of the CFET structure and improving the working performance of the CFET structure.

[0101] The semiconductor structure, its preparation method, storage device, and electronic device provided by this application aim to solve the above technical problems in the prior art.

[0102] The technical solution of this application and how the technical solution of this application solves the above technical problems will be described in detail below with specific embodiments. It should be noted that the following embodiments can refer to, draw on, or combine with each other. For the same terms, similar features, and similar implementation steps in different embodiments, they will not be described repeatedly.

[0103] The embodiment of this application provides a preparation method of a semiconductor structure. The schematic flow diagram of the preparation method of this semiconductor structure is as Figure 1 shown, and the schematic structural diagram of the preparation method of this semiconductor structure at different processes is as Figures 2 to 30 shown. The preparation method of this semiconductor structure includes:

[0104] S101. Provide a substrate 10. Optionally, the substrate 10 is a silicon substrate. The silicon substrate serves as the starting material and can also be the wafer of the underlying circuit.

[0105] S102. Form a first initial semiconductor layer 21 on one side of the substrate 10. The material of the first initial semiconductor layer 21 is a doped amorphous material.

[0106] S103. Make the first initial semiconductor layer 21 form a first electrode 31 and a first semiconductor layer 32. The first electrode 31 is located at one end of the first semiconductor layer 32, and the material of the first semiconductor layer 32 is a single crystal material.

[0107] S104. On the side of the first semiconductor layer 32 away from the substrate 10, form a second initial semiconductor layer 41. The positive projections of the first electrode 31 and the first semiconductor layer 32 on the substrate 10 respectively overlap with the positive projection of the second initial semiconductor layer 41 on the substrate 10. The first electrode 31 and the first semiconductor layer 32 are respectively insulated from the second initial semiconductor layer 41. The material of the second initial semiconductor layer 41 is a doped amorphous material, and the doping type of the second initial semiconductor layer 41 is opposite to the doping type of the first initial semiconductor layer 21.

[0108] S105. Make the second initial semiconductor layer 41 form a second electrode 51 and a second semiconductor layer 52. The second electrode 51 is located at one end of the second semiconductor layer 52. The material of the second semiconductor layer 52 is a single crystal material.

[0109] S106. Form a gate structure 60. The positive projection of the gate structure 60 on the substrate 10 overlaps with the positive projections of the first semiconductor layer 32 and the second semiconductor layer 52 on the substrate 10.

[0110] S107. Make the end of the first semiconductor layer 32 away from the first electrode 31 form a third electrode 33, and the remaining first semiconductor layer 32 form a first channel 34. Make the end of the second semiconductor layer 52 away from the second electrode 51 form a fourth electrode 53, and the remaining second semiconductor layer 52 form a second channel 54. The first electrode 31, the first channel 34, the gate structure 60, and the third electrode 33 form a first transistor 110. The second electrode 51, the second channel 54, the gate structure 60, and the fourth electrode 53 form a second transistor 120.

[0111] In the embodiment of the present application, the semiconductor structure 100 can be prepared by the preparation method of the semiconductor structure.

[0112] In the embodiment of the present application, the substrate 10 has a supporting effect on the first transistor 110 and the second transistor 120.

[0113] In the embodiment of the present application, the material of the first initial semiconductor layer 21 is a doped amorphous material. The first initial semiconductor layer 21 is formed into a first electrode 31 and a first semiconductor layer 32. The amorphous material of the first initial semiconductor layer 21 is transformed into a single-crystalline material of the first semiconductor layer 32. The first electrode 31 is located at one end of the first semiconductor layer 32. The orthographic projection of the gate structure 60 on the substrate 10 overlaps with the orthographic projection of the first semiconductor layer 32 on the substrate 10. A third electrode 33 is formed at the end of the first semiconductor layer 32 away from the first electrode 31, and the remaining first semiconductor layer 32 forms a first channel 34. The first electrode 31, the first channel 34, the gate structure 60, and the third electrode 33 form a first transistor 110. The material of the first channel 34 is a single-crystalline material, which has the advantages of high mobility and low impedance, can effectively reduce the resistance of the gate structure 60, and thus improve the working performance of the first transistor 110.

[0114] In the embodiment of the present application, the material of the second initial semiconductor layer 41 is a doped amorphous material. The second initial semiconductor layer 41 is formed into a second electrode 51 and a second semiconductor layer 52. The amorphous material of the second initial semiconductor layer 41 is transformed into a single-crystalline material of the second semiconductor layer 52. The second electrode 51 is located at one end of the second semiconductor layer 52. The orthographic projection of the gate structure 60 on the substrate 10 overlaps with the orthographic projection of the second semiconductor layer 52 on the substrate 10. A fourth electrode 53 is formed at the end of the second semiconductor layer 52 away from the second electrode 51, and the remaining second semiconductor layer 52 forms a second channel 54. The second electrode 51, the second channel 54, the gate structure 60, and the fourth electrode 53 form a second transistor 120. The material of the second channel 54 is a single-crystalline material, which has the advantages of high mobility and low impedance, can effectively reduce the resistance of the gate structure 60, and thus improve the working performance of the second transistor 120.

[0115] In the embodiment of the present application, the second initial semiconductor layer 41 is located on the side of the first semiconductor layer 32 away from the substrate 10. The orthographic projections of the first electrode 31 and the first semiconductor layer 32 on the substrate 10 respectively overlap with the orthographic projection of the second initial semiconductor layer 41 on the substrate 10, and the first electrode 31 and the first semiconductor layer 32 are respectively insulated from the second initial semiconductor layer 41, so that the formed second transistor 120 is located on the side of the first transistor 110 away from the substrate 10 and is insulated from the first transistor 110. Along the direction perpendicular to the substrate 10, the first transistor 110 and the second transistor 120 are stacked on the substrate 10 in sequence, so that the semiconductor structure occupies less space and area, and the integration density of the storage device can be improved. Stacking the first transistor 110 and the second transistor 120 in the vertical direction can further reduce the area occupied by the device and improve the integration degree of the storage device. At the same time, it can be formed on the same substrate 10 by a simple method, realizing high density, high performance, multi-function and low power consumption of a single chip.

[0116] In the embodiment of the present application, the first transistor 110 and the second transistor 120 share a gate structure 60. The shared gate structure 60 can be used as a signal input terminal, and the on-off states of the upper and lower two transistors with different conduction types (i.e., the first transistor 110 and the second transistor 120) can be controlled simultaneously through the same gate structure 60.

[0117] In some alternative embodiments of the present application, the first transistor 110 is an N-type field effect transistor, and the second transistor 120 is a P-type field effect transistor. Along the direction perpendicular to the substrate 10, the N-type field effect transistor and the P-type field effect transistor are stacked on the substrate 10 in sequence.

[0118] The present application provides a preparation method for a 3D (3 Dimension, three-dimensional) stacked CFET structure. The prepared CFET structure has an NFET (N-type field effect transistor) and a PFET (P-type field effect transistor). The PFET is vertically stacked on the NFET and the PFET and the NFET share a gate. The materials of the first channel 34 and the second channel 54 are both single crystal materials transformed from amorphous materials, with relatively high mobility and low impedance. Compared with the traditional CMOS structure, the preparation process of the CFET structure in the present application is simple, the occupied area of the prepared CFET structure is small, the manufacturing cost is low, and the working performance is high.

[0119] Of course, in some other alternative embodiments of the present application, according to actual needs, the first transistor 110 can be a P-type field effect transistor, and the second transistor 120 can be an N-type field effect transistor. Along the direction perpendicular to the substrate 10, the P-type field effect transistor and the N-type field effect transistor are stacked on the substrate 10 in sequence.

[0120] Optionally, in the embodiment of the present application, the first electrode 31, the first channel 34, and the third electrode 33 are arranged in sequence along a first direction parallel to the substrate 10. The second electrode 51, the second channel 54, and the fourth electrode 53 are arranged in sequence along the first direction parallel to the substrate 10.

[0121] In some alternative embodiments of the present application, as Figure 2 shown, before forming the first initial semiconductor layer 21 on one side of the substrate 10, the preparation method further includes: forming a first barrier layer 71 on one side of the substrate 10.

[0122] In some alternative embodiments of the present application, as Figures 2 to 4 shown, forming the first initial semiconductor layer 21 on one side of the substrate 10 includes:

[0123] As Figure 2As shown, a first amorphous silicon thin film 22 is formed on a side of the first barrier layer 71 away from the substrate 10. Optionally, an SiO2 (silicon dioxide) and a-Si (amorphous silicon) stack may be sequentially deposited on one side of the substrate 10, the formed SiO2 thin film serving as the first barrier layer 71 and the formed a-Si thin film serving as the first amorphous silicon thin film 22. In the embodiments of the present application, the first barrier layer 71 is used to prevent or inhibit the diffusion of impurities (such as impurities in the substrate 10) into the first amorphous silicon thin film 22. In some optional embodiments of the present application, the thickness (dimension in the direction perpendicular to the substrate 10) of the a-Si thin film is 10 nm - 30 nm.

[0124] Next, as Figure 2 shown, ion implantation is performed on the first amorphous silicon thin film 22. Optionally, N-type ion implantation is performed on the first amorphous silicon thin film 22. Optionally, the implanted ion is P (phosphorus), the energy is 20 keV (kilo-electron volts), and the implantation dose is 3×10 14 cm -2 . Optionally, the implanted ion is P 31 .

[0125] Next, as Figure 3 and Figure 4 shown, a first patterning process is performed to form the first amorphous silicon thin film 22 into a first initial electrode region 23, a first initial channel region 24, and a second initial electrode region 25 that are sequentially connected. The orthographic projection area of the first initial electrode region 23 on the substrate 10 and the orthographic projection area of the second initial electrode region 25 on the substrate 10 are respectively larger than the orthographic projection area of the first initial channel region 24 on the substrate 10, so as to serve as the first initial semiconductor layer 21.

[0126] The first initial electrode region 23, the first initial channel region 24, and the second initial electrode region 25 form the initial active layer of the first transistor 110. The implanted ion types of the first initial electrode region 23, the first initial channel region 24, and the second initial electrode region 25 are the same, so that there is no PN junction in the initial active layer of the first transistor 110, and the prepared first transistor 110 is a junctionless device. Optionally, the first initial electrode region 23, the first initial channel region 24, and the second initial electrode region 25 have uniform doping. Optionally, N-type ion implantation is performed on the first amorphous silicon thin film 22, and the prepared first transistor 110 is an NFET.

[0127] It should be noted that in the embodiments of the present application, there is no order preference for performing ion implantation and the first patterning process on the first amorphous silicon thin film 22. Ion implantation may be performed on the first amorphous silicon thin film 22 first, and then the first patterning process may be performed, or the first patterning process may be performed first, and then ion implantation may be performed on the patterned first amorphous silicon thin film 22.

[0128] Optionally, the material of the first initial semiconductor layer 21 may also be amorphous germanium.

[0129] In some alternative embodiments of the present application, forming the first initial semiconductor layer 21 into the first electrode 31 and the first semiconductor layer 32 includes:

[0130] Adopting a metal-induced crystallization process, forming a part of the first initial semiconductor layer 21 into the first electrode 31, and transforming another part of the first initial semiconductor layer 21 made of amorphous material into the first semiconductor layer 32 made of single-crystal material.

[0131] By adopting the metal-induced crystallization process, while obtaining an appropriate crystallization rate, the uniformity and stability of obtaining a large-area single-crystal material can be improved. The metal-induced crystallization technology has the advantages of simple process, enabling the crystallization of amorphous silicon thin films in a short time, high efficiency, and the prepared single-crystalline silicon thin films having higher mobility and lower impedance.

[0132] In some alternative embodiments of the present application, as Figures 6 to 10 shown, forming the first initial semiconductor layer 21 into the first electrode 31 and the first semiconductor layer 32 includes:

[0133] As Figure 6 and Figure 7 shown, forming a first covering layer 81 on one side of the substrate 10, the first covering layer 81 covering the first initial semiconductor layer 21, the first covering layer 81 having first induced holes 82, and the bottom of the first induced holes 82 exposing the first initial electrode region 23.

[0134] Next, as Figure 8 shown, forming a first inducing layer 83 on one side of the substrate 10, the first inducing layer 83 covering the first covering layer 81, the inner wall of the first induced holes 82, and the exposed first initial electrode region 23, the first inducing layer 83 contacting the first initial electrode region 23, and the material of the first inducing layer 83 including a metal.

[0135] Next, as Figure 9 shown, performing a first heat treatment to transform the amorphous silicon in the first initial electrode region 23 into a metal silicide to form the first electrode 31;

[0136] Next, as Figure 10 shown, performing a second heat treatment, using the metal material in the first inducing layer 83 as an inducing source and the metal silicide of the first electrode 31 as a medium, inducing the amorphous silicon in the first initial channel region 24 and the second initial electrode region 25 to transform into single-crystalline silicon, and activating the implanted ions to form the first semiconductor layer 32.

[0137] In the embodiment of the present application, after the first heat treatment, the amorphous silicon in the first initial electrode region 23 reacts with the metal in the first induction layer 83 to be transformed into metal silicide, forming the first electrode 31. Then, the second heat treatment is carried out. Taking the metal material in the first induction layer 83 as the induction source and the metal silicide of the first electrode 31 as the medium, the first initial channel region 24 and the second initial electrode region 25 are induced to crystallize laterally (parallel to the direction of the substrate 10), so that the amorphous silicon in the first initial channel region 24 and the second initial electrode region 25 is transformed into single crystal silicon, and the implanted ions are activated.

[0138] In some alternative embodiments of the present application, as Figures 5 to 7 shown, a first covering layer 81 is formed on one side of the substrate 10, including:

[0139] As Figure 5 shown, a silicon oxide material is deposited on one side of the substrate 10 to form a first initial covering layer 811, and the first initial covering layer 811 covers the first barrier layer 71 and the first initial semiconductor layer 21. Optionally, SiO2 is deposited on one side of the substrate 10 and planarized to form the first initial covering layer 811.

[0140] Then, as Figure 6 and Figure 7 shown, a second patterning process is carried out to form a first induction hole 82 penetrating through the first initial covering layer 811. The positive projection of the first induction hole 82 on the substrate 10 covers the positive projection of the first initial electrode region 23 on the substrate 10, and the patterned first initial covering layer 811 forms the first covering layer 81.

[0141] In the embodiment of the present application, the positive projection of the first induction hole 82 on the substrate 10 covers the positive projection of the first initial electrode region 23 on the substrate 10, that is, the dimension of the first induction hole 82 along the direction parallel to the substrate 10 is larger than the dimension of the first initial electrode region 23 along the direction parallel to the substrate 10, so that the process window for induced crystallization is wider, and the entire channel can be induced to crystallize.

[0142] In some alternative embodiments of the present application, as Figure 8 shown, a first induction layer 83 is formed on one side of the substrate 10, including:

[0143] A first silicon oxide thin film 831 and a first nickel thin film 832 are sequentially deposited on one side of the substrate 10. The first silicon oxide thin film 831 covers the first covering layer 81, the inner wall of the first induction hole 82 and the exposed first initial electrode region 23. The first nickel thin film 832 covers the side of the first silicon oxide thin film 831 away from the substrate 10. The first silicon oxide thin film 831 and the first nickel thin film 832 form the first induction layer 83.

[0144] Optionally, a 2-nm-thick SiO2 thin film and a 10-nm-thick Ni (nickel) thin film are sequentially deposited on one side of the substrate 10. The SiO2 thin film serves as the first silicon oxide thin film 831, and the Ni thin film serves as the first nickel thin film 832.

[0145] In some alternative embodiments of the present application, the metal for inducing crystallization includes, but is not limited to, one or more of nickel, chromium, cobalt, palladium, germanium, aluminum, tungsten, etc.

[0146] In some alternative embodiments of the present application, as Figure 9 shown ( Figure 9 the first nickel thin film 832 is not shown), a first heat treatment is performed, including:

[0147] Annealing is performed at 400°C - 500°C for a treatment time of 1 min - 5 min, so that the amorphous silicon in the first initial electrode region 23 reacts with the nickel material in the first induction layer 83 to form nickel silicide, thereby forming the first electrode 31. Annealing in this temperature range and time range can form the NiSi2 phase, and the NiSi2 phase has the smallest lattice mismatch with the single-crystal silicon lattice, resulting in the highest quality of induced crystallization. Optionally, rapid thermal annealing treatment can be performed to form nickel silicide NiSi2, thereby forming the first electrode 31.

[0148] During the rapid thermal annealing treatment, the nickel material in the first induction layer 83 rapidly diffuses into the first initial electrode region 23, and the nickel material forms a high-quality induction medium NiSi2 with the amorphous silicon for crystallization.

[0149] In some alternative embodiments of the present application, as Figure 10 shown ( Figure 10 the first nickel thin film 832 is not shown), a second heat treatment is performed, including:

[0150] Annealing is performed at 500°C - 600°C for a treatment time of 1 h - 24 h. The induction source is the nickel material in the first induction layer 83, and the medium is the nickel silicide of the first electrode 31. This temperature range is for low-temperature induction of amorphous silicon crystallization, which can avoid solid-phase epitaxial crystallization during the crystallization process and is beneficial to improving the crystallization quality.

[0151] Annealing is performed at 500°C - 600°C for a treatment time of 1 h - 24 h. Using the nickel material in the first induction layer 83 as the induction source and the nickel silicide of the first electrode 31 as the induction medium, the first initial channel region 24 and the second initial electrode region 25 are induced to crystallize, so that the amorphous silicon in the first initial channel region 24 and the second initial electrode region 25 crystallizes into single-crystal silicon. Since the lattice constants of NiSi2 and c-Si (single-crystal silicon) are and relatively close, the lattice mismatch is extremely small, and at the same time, the implanted ions P will be activated during the crystallization process.

[0152] In some alternative embodiments of the present application, such as Figure 11 shown ( Figure 11 in which the first nickel thin film 832 has been removed), after the second heat treatment, the preparation method further includes:

[0153] Removing the remaining first nickel thin film 832. Optionally, the remaining first nickel thin film 832 can be cleaned by acid leaching.

[0154] Next, a silicon oxide material is deposited on one side of the substrate 10 to form a second barrier layer 72, and the second barrier layer 72 covers the first silicon oxide thin film 831 and fills the first induced hole 82. Optionally, SiO2 is deposited on one side of the substrate 10 and planarized to form the second barrier layer 72.

[0155] In some alternative embodiments of the present application, such as Figures 12 to 15 shown, a second initial semiconductor layer 41 is formed on the side of the first semiconductor layer 32 away from the substrate 10, including:

[0156] Such as Figure 12 shown, a second amorphous silicon thin film 42 is formed on the side of the second barrier layer 72 away from the substrate 10. Optionally, an a-Si thin film with a thickness of 10 nm - 30 nm is deposited on the side of the second barrier layer 72 away from the substrate 10 as the second amorphous silicon thin film 42.

[0157] Next, as Figure 13 and Figure 14 shown, a third patterning process is performed to form the second amorphous silicon thin film 42 into a third initial electrode region 43, a second initial channel region 44, and a fourth initial electrode region 45 that are sequentially connected. The orthographic projection areas of the third initial electrode region 43 and the fourth initial electrode region 45 on the substrate 10 are respectively larger than the orthographic projection area of the second initial channel region 44 on the substrate 10.

[0158] Next, as Figure 15 shown, ion implantation is performed on the second amorphous silicon thin film 42 to form the second initial semiconductor layer 41, and the ion type implanted in the second initial semiconductor layer 41 is opposite to the ion type implanted in the first initial semiconductor layer 21. Optionally, P-type ion implantation is performed on the second amorphous silicon thin film 42. Optionally, the implanted ion is BF2 (boron difluoride), the energy is 30 keV, and the implantation dose is 3×10 14 cm -2 .

[0159] The third initial electrode region 43, the second initial channel region 44, and the fourth initial electrode region 45 form the initial active layer of the second transistor 120. The types of implanted ions in the third initial electrode region 43, the second initial channel region 44, and the fourth initial electrode region 45 are the same, such that there is no PN junction in the initial active layer of the second transistor 120, and the fabricated second transistor 120 is a junctionless device. Optionally, the third initial electrode region 43, the second initial channel region 44, and the fourth initial electrode region 45 have uniform doping. Optionally, P-type ion implantation is performed on the second amorphous silicon thin film 42, and the fabricated second transistor 120 is a PFET.

[0160] It should be noted that in the embodiments of the present application, there is no sequence requirement for performing ion implantation on the second amorphous silicon thin film 42 and the third patterning process. Ion implantation can be performed on the second amorphous silicon thin film 42 first and then the third patterning process, or the third patterning process can be performed first and then ion implantation on the patterned second amorphous silicon thin film 42.

[0161] Optionally, the material of the second initial semiconductor layer 41 can also be amorphous germanium.

[0162] In some alternative embodiments of the present application, forming the second initial semiconductor layer 41 into the second electrode 51 and the second semiconductor layer 52 includes:

[0163] Using a metal-induced crystallization process, a part of the second initial semiconductor layer 41 is formed into the second electrode 51, and the other part of the second initial semiconductor layer 41 in amorphous state is transformed into the second semiconductor layer 52 in single crystal material.

[0164] Using the metal-induced crystallization process can improve the uniformity and stability of obtaining large-area single crystal material while achieving an appropriate crystallization rate. The metal-induced crystallization technology has the advantages of simple process, enabling the crystallization of amorphous silicon thin film in a short time, high efficiency, and the prepared single crystal silicon thin film having higher mobility and lower impedance.

[0165] In some alternative embodiments of the present application, as Figures 16 to 20 shown, forming the second initial semiconductor layer 41 into the second electrode 51 and the second semiconductor layer 52 includes:

[0166] As Figure 16 and Figure 17 shown, a second covering layer 91 is formed on one side of the substrate 10. The second covering layer 91 covers the second initial semiconductor layer 41 and the second barrier layer 72. The second covering layer 91 has a second induced hole 92, and the bottom of the second induced hole 92 exposes the third initial electrode region 43.

[0167] Next, as Figure 18As shown, a second induction layer 93 is formed on one side of the substrate 10. The second induction layer 93 covers the second covering layer 91, the inner wall of the second induction layer 93, and the exposed third initial electrode region 43. The second induction layer 93 is in contact with the third initial electrode region 43, and the material of the second induction layer 93 includes metal.

[0168] Next, as Figure 19 shown ( Figure 19 showing the second silicon oxide thin film 931 of the second induction layer 93, and not showing the second nickel thin film 932 of the second induction layer 93), a third heat treatment is performed to transform the amorphous silicon in the third initial electrode region 43 into metal silicide to form the second electrode 51.

[0169] Next, as Figure 20 shown ( Figure 20 showing the second silicon oxide thin film 931 of the second induction layer 93, and not showing the second nickel thin film 932 of the second induction layer 93), a fourth heat treatment is performed. Using the metal material in the second induction layer 93 as the induction source and the metal silicide of the second electrode 51 as the medium, the amorphous silicon in the second initial channel region 44 and the fourth initial electrode region 45 is induced to transform into single crystal silicon, and the implanted ions are activated to form the second semiconductor layer 52.

[0170] In the embodiment of the present application, after the third heat treatment, the amorphous silicon in the third initial electrode region 43 reacts with the metal in the second induction layer 93 to transform into metal silicide, forming the second electrode 51. Then, a fourth heat treatment is performed. Using the metal material in the second induction layer 93 as the induction source and the metal silicide of the second electrode 51 as the medium, crystallization is induced laterally (parallel to the direction of the substrate 10) in the second initial channel region 44 and the fourth initial electrode region 45, so that the amorphous silicon in the second initial channel region 44 and the fourth initial electrode region 45 is transformed into single crystal silicon.

[0171] In some alternative embodiments of the present application, as Figure 16 and Figure 17 shown, a second covering layer 91 is formed on one side of the substrate 10, including:

[0172] Depositing a silicon oxide material on one side of the substrate 10 to form a second initial covering layer, and the second initial covering layer covers the second barrier layer 72 and the second initial semiconductor layer 41. Optionally, depositing SiO2 on one side of the substrate 10 and performing a planarization process to form the second initial covering layer.

[0173] Next, a fourth patterning process is performed to form a second induction hole 92 penetrating the second initial covering layer. The positive projection of the second induction hole 92 on the substrate 10 covers the positive projection of the third initial electrode region 43 on the substrate 10, and the second initial covering layer after the patterning process forms the second covering layer 91.

[0174] In the embodiments of the present application, the orthographic projection of the second induction hole 92 on the substrate 10 covers the orthographic projection of the third initial electrode region 43 on the substrate 10, that is, the dimension of the second induction hole 92 in the direction parallel to the substrate 10 is greater than the dimension of the third initial electrode region 43 in the direction parallel to the substrate 10, so that the process window for induced crystallization is relatively wide, and induced crystallization can occur throughout the channel.

[0175] In some alternative embodiments of the present application, as Figure 18 shown, a second induction layer 93 is formed on one side of the substrate 10, including:

[0176] A second silicon oxide thin film 931 and a second nickel thin film 932 are sequentially deposited on one side of the substrate 10. The second silicon oxide thin film 931 covers the second covering layer 91, the inner wall of the second induction hole 92, and the exposed third initial electrode region 43. The second nickel thin film 932 covers the side of the second silicon oxide thin film 931 away from the substrate 10. The second silicon oxide thin film 931 and the second nickel thin film 932 form the second induction layer 93.

[0177] Optionally, a 2-nm-thick SiO2 thin film and a 10-nm-thick Ni (nickel) thin film are sequentially deposited on one side of the substrate 10. The SiO2 thin film serves as the second silicon oxide thin film 931, and the Ni thin film serves as the second nickel thin film 932.

[0178] In some alternative embodiments of the present application, the metal for induced crystallization includes, but is not limited to, one or more of nickel, chromium, cobalt, palladium, germanium, aluminum, tungsten, etc.

[0179] In some alternative embodiments of the present application, as Figure 19 shown ( Figure 19 the second nickel thin film 932 of the second induction layer 93 is not shown), a third heat treatment is performed, including:

[0180] A rapid thermal annealing treatment is performed at 600 °C for a treatment time of 60 s, so that the amorphous silicon in the third initial electrode region 43 reacts with the nickel material in the second induction layer 93 to transform into nickel silicide, thereby forming the second electrode 51.

[0181] During the rapid thermal annealing treatment, the nickel material in the second induction layer 93 rapidly diffuses to the third initial electrode region 43, and the nickel material and the amorphous silicon form a high-quality induction medium NiSi2 for crystallization.

[0182] In some alternative embodiments of the present application, as Figure 20 shown ( Figure 20 the second nickel thin film 932 of the second induction layer 93 is not shown), a fourth heat treatment is performed, including:

[0183] Annealing treatment is carried out at 500°C - 600°C for 60 minutes. The inducing source is the nickel material of the second inducing layer 93, and the medium is the nickel silicide of the second electrode 51.

[0184] Annealing treatment is carried out at 500°C - 600°C for 60 minutes. Using the nickel material of the second inducing layer 93 as the inducing source and the nickel silicide of the second electrode 51 as the inducing medium, the second initial channel region 44 and the fourth initial electrode region 45 are induced to crystallize, making the amorphous silicon in the second initial channel region 44 and the fourth initial electrode region 45 crystallize into single crystal silicon. Since the lattice constants of NiSi2 and c-Si (single crystal silicon) are and relatively close, the lattice mismatch is extremely small. At the same time, the implanted ion BF2 will be activated during the crystallization process.

[0185] The CFET structure prepared in the embodiment of the present application has an NFET and a PFET. The PFET is vertically stacked on the NFET and shares a gate; both the NFET and the PFET are junctionless devices, and their source and drain electrodes and the channel have uniform doping; the channel of the CFET structure is a single crystal induced by metal silicidation-induced amorphous transformation. Compared with traditional CMOS, the preparation process of the CFET structure in the embodiment of the present application is simple, has a small area, low cost, and the preparation thermal budget is less than or equal to 600°C.

[0186] In some optional embodiments of the present application, after the fourth heat treatment, the preparation method further includes:

[0187] Removing the remaining second nickel thin film 932. Optionally, the remaining second nickel thin film 932 can be cleaned by acid leaching.

[0188] In some optional embodiments of the present application, as Figure 21 shown, before forming the gate structure 60, the preparation method further includes:

[0189] Depositing a silicon oxide material on one side of the substrate 10 to form a first insulating layer 73. The first insulating layer 73 covers the second inducing layer 93 and fills the second inducing hole 92. Optionally, SiO2 is deposited on one side of the substrate 10 and planarized to form the first insulating layer 73. The first insulating layer 73 covers the second silicon oxide thin film 931 and fills the second inducing hole 92.

[0190] In some optional embodiments of the present application, as Figures 22 to 24 shown, forming the gate structure 60 includes:

[0191] As Figure 22 and Figure 23As shown, a first groove 101 is formed to expose a first initial channel region 24 and a second initial channel region 44. The first groove 101 extends in a direction perpendicular to the substrate 10. Optionally, the dimension of the first groove 101 along a second direction parallel to the substrate 10 is greater than the dimension of the first initial channel region 24 along the second direction and greater than the dimension of the second initial channel region 44 along the second direction, so as to expose the circumferential sidewalls of the first initial channel region 24 and the second initial channel region 44. The first groove 101 penetrates through the first insulating layer 73, the second silicon oxide thin film 931, the second covering layer 91, the second barrier layer 72, the first silicon oxide thin film 831, the first covering layer 81, and extends to the first barrier layer 71.

[0192] Next, as Figure 24 shown, a gate dielectric layer 61 is formed. The gate dielectric layer 61 covers the sidewalls of the first initial channel region 24, the sidewalls of the second initial channel region 44, and the inner wall of the first groove 101. Optionally, the material of the gate dielectric layer 61 includes but is not limited to high-k materials. High-k materials generally refer to materials with a dielectric constant greater than 3.9, such as hafnium oxide (HfO2), etc. Forming the gate dielectric layer 61 with a high-k material can increase the capacitance. Optionally, the gate dielectric layer 61 is formed by depositing a high-k material.

[0193] Next, as Figure 24 shown, a gate electrode 62 is formed. The gate electrode 62 fills the first groove 101. The gate dielectric layer 61 is located between the first initial channel region 24 and the gate electrode 62 and between the second initial channel region 44 and the gate electrode 62. The first transistor 110 and the second transistor 120 share a gate electrode 62. The gate dielectric layer 61 is used to block the first initial channel region 24 and the gate electrode 62, and block the second initial channel region 44 and the gate electrode 62, so that the first initial channel region 24 is insulated from the gate electrode 62, and the second initial channel region 44 is insulated from the gate electrode 62. The gate electrode 62 and the gate dielectric layer 61 form a gate structure 60. Optionally, the material of the gate electrode 62 includes but is not limited to TiN (titanium nitride), W (tungsten).

[0194] In some alternative embodiments of the present application, as Figure 25 shown, after the gate structure 60 is formed, before forming a third electrode 33 at the end of the first semiconductor layer 32 away from the first electrode 31, with the remaining first semiconductor layer 32 forming a first channel 34, and forming a fourth electrode 53 at the end of the second semiconductor layer 52 away from the second electrode 51, with the remaining second semiconductor layer 52 forming a second channel 54, the manufacturing method further includes:

[0195] A second insulating layer 74 is formed on one side of the substrate 10. The second insulating layer 74 covers the first insulating layer 73, the gate dielectric layer 61, and the gate electrode 62. Optionally, SiO2 is deposited on one side of the substrate 10 and planarized to form the second insulating layer 74.

[0196] In some alternative embodiments of the present application, as Figures 25 to 27 shown, a third electrode 33 is formed at an end of the first semiconductor layer 32 away from the first electrode 31, and the remaining first semiconductor layer 32 forms a first channel 34. A fourth electrode 53 is formed at an end of the second semiconductor layer 52 away from the second electrode 51, and the remaining second semiconductor layer 52 forms a second channel 54, including:

[0197] As Figure 25 and Figure 26 shown, a second groove 102 is formed to expose the second initial electrode region 25 and the fourth initial electrode region 45. The second groove 102 extends in a direction perpendicular to the substrate 10, and the orthographic projection of the second groove 102 on the substrate 10 covers the orthographic projection of the second initial electrode region 25 on the substrate 10 and covers the orthographic projection of the fourth initial electrode region 45 on the substrate 10. Optionally, the second groove 102 is formed by an etching process.

[0198] Next, as Figure 27 shown, nickel materials are respectively deposited on the surfaces of the exposed second initial electrode region 25 and the fourth initial electrode region 45, and a rapid thermal annealing treatment is performed to transform the single-crystalline silicon of the second initial electrode region 25 and the fourth initial electrode region 45 into nickel silicide respectively. The second initial electrode region 25 after the rapid thermal annealing treatment forms the third electrode 33, and the first initial channel region 24 forms the first channel 34. The fourth initial electrode region 45 after the rapid thermal annealing treatment forms the fourth electrode 53, and the second initial channel region 44 forms the second channel 54.

[0199] In the embodiment of the present application, the orthographic projection of the second groove 102 on the substrate 10 covers the orthographic projection of the second initial electrode region 25 on the substrate 10 and covers the orthographic projection of the fourth initial electrode region 45 on the substrate 10, that is, the dimension of the second groove 102 in the direction parallel to the substrate 10 is greater than the dimension of the second initial electrode region 25 in the direction parallel to the substrate 10 and greater than the dimension of the fourth initial electrode region 45 in the direction parallel to the substrate 10, so that the process window of the silicided drain end is wider, which is beneficial to preparing large-area and high-quality nickel silicide to form the third electrode 33 and the fourth electrode 53.

[0200] In the embodiment of the present application, the first channel 34 of the first transistor 110 is a single-crystalline material transformed from an amorphous material induced by metal silicidation. The preparation process is simple, the first transistor 110 prepared occupies a small area, has a low manufacturing cost, and has high working performance.

[0201] In the embodiment of the present application, the second channel 54 of the second transistor 120 is a single-crystalline material transformed from an amorphous material induced by metal silicidation. The preparation process is simple, the second transistor 120 prepared occupies a small area, has a low manufacturing cost, and has high working performance.

[0202] In some alternative embodiments of the present application, such as Figure 27 shown, after forming the third electrode 33 at the end of the first semiconductor layer 32 away from the first electrode 31, and the remaining first semiconductor layer 32 forms the first channel 34, and forming the fourth electrode 53 at the end of the second semiconductor layer 52 away from the second electrode 51, and the remaining second semiconductor layer 52 forms the second channel 54, the preparation method further includes:

[0203] Forming a drain-end connection structure 103, the drain-end connection structure 103 fills the second groove 102, the drain-end connection structure 103 is in contact with the third electrode 33 and the fourth electrode 53 respectively, and the first transistor 110 and the second transistor 120 share a drain-end connection structure 103.

[0204] Optionally, materials such as TiN, W, etc. are filled in the second groove 102 to form the drain-end connection structure 103, and the drain-end connection structure 103 is in contact with the third electrode 33 and the fourth electrode 53 respectively, so as to facilitate the interconnection of the third electrode 33 of the first transistor 110 and the fourth electrode 53 of the second transistor 120. The third electrode 33 of the first transistor 110 and the fourth electrode 53 of the second transistor 120 can be connected to external devices through the drain-end connection structure 103.

[0205] In some alternative embodiments of the present application, such as Figure 28 shown, after forming the drain-end connection structure 103, the preparation method further includes:

[0206] Forming a via 104 penetrating the second insulating layer 74, and the bottom of the via 104 exposes the gate electrode 62.

[0207] Then, forming a gate electrode connection structure 105, filling the via 104 with the gate electrode connection structure 105, one end of the gate electrode connection structure 105 is in contact with the gate electrode 62, and the other end is used to connect to an external device.

[0208] The gate electrode 62 is connected to an external device through the gate electrode connection structure 105. The first transistor 110 and the second transistor 120 share the gate electrode 62, and the gate electrode connection structure 105 is provided at the shared gate electrode 62, eliminating the need to add circuit connections between the gates of each field effect transistor, avoiding the occupation of space by the connection circuits, and further improving the integration of the memory device.

[0209] In some alternative embodiments of the present application, such as Figure 29 and Figure 30 shown, after forming the gate electrode connection structure 105, the preparation method further includes:

[0210] A third groove 106 exposing the first electrode 31 is formed. The third groove 106 extends in a direction perpendicular to the substrate 10 . The orthographic projection of the third groove 106 on the substrate 10 overlaps with the orthographic projection of the first electrode 31 on the substrate 10 .

[0211] Next, a first source terminal connection structure 107 is formed. The first source terminal connection structure 107 fills the third groove 106 and contacts the first electrode 31. The first electrode 31 can be connected to an external device through the first source terminal connection structure 107.

[0212] In some optional embodiments of the present application, such as Figure 29 and Figure 30 As shown, after forming the gate electrode connection structure 105, the preparation method further includes:

[0213] A fourth groove 108 is formed to expose the second electrode 51 . The fourth groove 108 extends in a direction perpendicular to the substrate 10 . The orthographic projection of the fourth groove 108 on the substrate 10 overlaps with the orthographic projection of the second electrode 51 on the substrate 10 , and does not overlap with the orthographic projection of the third groove 106 on the substrate 10 .

[0214] Next, a second source terminal connection structure 109 is formed. The second source terminal connection structure 109 fills the fourth groove 108 and contacts the second electrode 51. The second electrode 51 can be connected to an external device through the second source terminal connection structure 109.

[0215] In the embodiment of the present application, the first electrode 31, the first channel 34 and the third electrode 33 of the first transistor 110 are located in the same layer, and the second electrode 51, the second channel 54 and the fourth electrode 53 of the second transistor 120 are located in the same layer and are located on the side of the first channel 34 away from the substrate 10. The distance between the first electrode 31 and the substrate 10 is smaller than the distance between the second electrode 51 and the substrate 10, so the depth of the third groove 106 along the direction perpendicular to the substrate 10 is greater than the depth of the fourth groove 108 along the direction perpendicular to the substrate 10, and the third groove 106 and the fourth groove 108 are staircase grooves.

[0216] Optionally, a dimension of the second electrode 51 along the second direction is smaller than a dimension of the first electrode 31 along the second direction (i.e., the first electrode 31 and the second electrode 51 form a step along a direction perpendicular to the substrate 10), so that a portion of the orthographic projection of the first electrode 31 on the substrate 10 is not covered by the orthographic projection of the second electrode 51 on the substrate 10, the orthographic projection of the third groove 106 on the substrate 10 does not overlap with the orthographic projection of the second electrode 51 on the substrate 10, and overlaps with the orthographic projection of the first electrode 31 on the substrate 10 that is not covered by the second electrode 51, the second electrode 51 avoids the third groove 106, and the first electrode 31 is exposed at the bottom of the third groove 106.

[0217] In the embodiments of the present application, the gate structure 60 shared by the first transistor 110 and the second transistor 120 can be used as a signal input terminal. The drain electrodes of the first transistor 110 and the second transistor 120 are electrically connected and can be used as a signal output terminal. The source electrodes of the first transistor 110 and the second transistor 120 can be grounded and connected to a power supply respectively, for example, to realize the function of an inverter. Two field effect transistors with different polarities are three-dimensionally stacked, and the on-off states of the upper and lower two transistors are simultaneously controlled by the same gate structure 60. The drain electrodes of the upper and lower two transistors are connected through the drain connection structure 103 to construct a three-dimensional complementary field effect transistor.

[0218] The preparation method of the semiconductor structure of the present application relates to the technical field of information materials and devices.

[0219] The preparation method of the semiconductor structure of the present application can be applied to wafer-level three-dimensional cache (3D Cache) stacking integration.

[0220] The preparation method of the semiconductor structure of the present application can be applied to the preparation of 3D stacked CFET structures.

[0221] Based on the same inventive concept, an embodiment of the present application further provides a semiconductor structure 100. The schematic structural diagram of the semiconductor structure 100 is as shown in Figure 29 and Figure 30 and includes: a substrate 10, a first transistor 110, and a second transistor 120.

[0222] The first transistor 110 is disposed on one side of the substrate 10. The first transistor 110 includes a first channel 34, a first electrode 31, a gate structure 60, and a third electrode 33. The material of the first channel 34 is a single crystal material. The first electrode 31 is located at one end of the first channel 34. The third electrode 33 is located at the end of the first channel 34 away from the first electrode 31. The orthographic projection of the gate structure 60 on the substrate 10 overlaps with the orthographic projection of the first channel 34 on the substrate 10 and is insulated from the first channel 34.

[0223] The second transistor 120 is disposed on the side of the first transistor 110 away from the substrate 10. The second transistor 120 includes a second channel 54, a second electrode 51, a gate structure 60, and a fourth electrode 53. The material of the second channel 54 is a single crystal material. The second electrode 51 is located at one end of the second channel 54. The fourth electrode 53 is located at the end of the second channel 54 away from the second electrode 51. The orthographic projection of the gate structure 60 on the substrate 10 overlaps with the orthographic projection of the second channel 54 on the substrate 10 and is insulated from the second channel 54.

[0224] The conduction type of the first transistor 110 is opposite to that of the second transistor 120.

[0225] In the embodiments of the present application, the substrate 10 supports the first transistor 110 and the second transistor 120.

[0226] In the embodiments of the present application, the first electrode 31 is located at one end of the first channel 34, the third electrode 33 is located at the end of the first channel 34 away from the first electrode 31, the orthographic projection of the gate structure 60 on the substrate 10 overlaps with the orthographic projection of the first channel 34 on the substrate 10 and is insulated from the first channel 34. The first electrode 31, the first channel 34, the gate structure 60, and the third electrode 33 form the first transistor 110. The material of the first channel 34 is a single crystal material, which has the advantages of high mobility and low impedance, can effectively reduce the resistance of the gate structure 60, and thus improve the working performance of the first transistor 110.

[0227] In the embodiments of the present application, the second electrode 51 is located at one end of the second semiconductor layer 52, the fourth electrode 53 is located at the end of the second channel 54 away from the second electrode 51, the orthographic projection of the gate structure 60 on the substrate 10 overlaps with the orthographic projection of the second channel 54 on the substrate 10 and is insulated from the second channel 54. The second electrode 51, the second channel 54, the gate structure 60, and the fourth electrode 53 form the second transistor 120. The material of the second channel 54 is a single crystal material, which has the advantages of high mobility and low impedance, can effectively reduce the resistance of the gate structure 60, and thus improve the working performance of the second transistor 120.

[0228] In the embodiments of the present application, the second transistor 120 is located on the side of the first transistor 110 away from the substrate 10. Along the direction perpendicular to the substrate 10, the first transistor 110 and the second transistor 120 are stacked on the substrate 10 in sequence, so that the semiconductor structure occupies a small space and area, and the integration density of the storage device can be improved. Stacking the first transistor 110 and the second transistor 120 vertically can further reduce the area occupied by the device and improve the integration degree of the storage device. At the same time, it can be formed on the same substrate 10 by a simple method, realizing high density, high performance, multi-function and low power consumption of a single chip.

[0229] In the embodiments of the present application, the first transistor 110 and the second transistor 120 share a gate structure 60. The shared gate structure 60 can be used as a signal input terminal, and the on-off states of the upper and lower two transistors with different conduction types can be controlled simultaneously through the same gate structure 60.

[0230] In some alternative embodiments of the present application, the first transistor 110 is an N-type field effect transistor, and the second transistor 120 is a P-type field effect transistor. Along the direction perpendicular to the substrate 10, the N-type field effect transistor and the P-type field effect transistor are stacked on the substrate 10 in sequence.

[0231] The present application provides a method for fabricating a 3D stacked CFET structure. The fabricated CFET structure has an NFET and a PFET, with the PFET vertically stacked on top of the NFET and the PFET and NFET sharing a common gate. The materials of the first channel 34 and the second channel 54 are both single-crystalline materials transformed from amorphous materials, having a relatively high mobility and a relatively low impedance. Compared with the traditional CMOS structure, the fabrication process of the CFET structure in the present application is simple, the fabricated CFET structure occupies a small area, has a low manufacturing cost, and has high working performance.

[0232] Of course, in some alternative embodiments of the present application, according to actual needs, the first transistor 110 may be a P-type field effect transistor, and the second transistor 120 may be an N-type field effect transistor. Along the direction perpendicular to the substrate 10, the P-type field effect transistor and the N-type field effect transistor are sequentially stacked on the substrate 10.

[0233] In some alternative embodiments of the present application, the first transistor 110 is a junctionless field effect transistor, and the second transistor 120 is a junctionless field effect transistor.

[0234] In some alternative embodiments of the present application, as Figure 29 and Figure 30 shown, the gate structure 60 extends along the direction perpendicular to the substrate 10, and the first transistor 110 and the second transistor 120 share a common gate structure 60.

[0235] In some alternative embodiments of the present application, as Figure 29 and Figure 30 shown, the semiconductor structure 100 further includes a drain terminal connection structure 103, a gate electrode connection structure 105, a first source terminal connection structure 107, and a second source terminal connection structure 109; one end of the gate electrode connection structure 105 is connected to the gate electrode 62 of the gate structure 60, and the other end is used for connection with an external device; the drain terminal connection structure 103 is respectively connected to the third electrode 33 and the fourth electrode 53, and the first transistor 110 and the second transistor 120 share a common drain terminal connection structure 103; the first source terminal connection structure 107 is connected to the first electrode 31, and the orthographic projection of the first source terminal connection structure 107 on the substrate 10 does not overlap with the orthographic projection of the second electrode 51 on the substrate 10; the second source terminal connection structure 109 is connected to the second electrode 51; the dimension of the first source terminal connection structure 107 along the direction perpendicular to the substrate 10 is greater than the dimension of the second source terminal connection structure 109 along the direction perpendicular to the substrate 10, and the first source terminal connection structure 107 and the second source terminal connection structure 109 are in a stepped shape.

[0236] The semiconductor structure of the present application can be applied to a 3D stacked CFET structure.

[0237] Based on the same inventive concept, an embodiment of the present application further provides a storage device, which includes: a semiconductor structure prepared by using the preparation method of the above semiconductor structure; or, the above semiconductor structure 100.

[0238] In some alternative embodiments of the present application, the storage device includes a plurality of semiconductor structures. Among the plurality of semiconductor structures, several semiconductor structures are arranged in an array along a direction parallel to the substrate 10; and / or, among the plurality of semiconductor structures, several semiconductor structures are stacked in sequence along a direction perpendicular to the substrate 10.

[0239] By this arrangement, an array structure and / or a 3D stacking structure can be formed, which can improve the storage capacity of the storage device, reduce the storage cost, improve the integration degree and storage density, and contribute to miniaturization.

[0240] It should be noted that since the storage device of the embodiment of the present application includes the semiconductor structure of the embodiment of the present application, therefore, the storage device of the embodiment of the present application also has the above beneficial effects of the semiconductor structure of the embodiment of the present application, which will not be elaborated here.

[0241] In some alternative embodiments of the present application, the storage device may be a random access memory, specifically a static random access memory or a dynamic random access memory. Of course, it may also be a flash memory storage, etc.

[0242] Based on the same inventive concept, an embodiment of the present application further provides an electronic device, which includes: the above storage device.

[0243] It should be noted that since the electronic device of the embodiment of the present application includes the storage device of the embodiment of the present application, therefore, the electronic device of the embodiment of the present application also has the above beneficial effects of the storage device of the embodiment of the present application, which will not be elaborated here.

[0244] In some alternative embodiments of the present application, the electronic device includes a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a mobile power supply, etc. Among them, the storage device may include the memory in a computer, etc., which is not limited here.

[0245] Applying the embodiments of the present application can at least achieve the following beneficial effects:

[0246] In the embodiment of the present application, the material of the first initial semiconductor layer is a doped amorphous material. The first initial semiconductor layer is formed into a first electrode and a first semiconductor layer. The amorphous material of the first initial semiconductor layer is transformed into a single crystal material of the first semiconductor layer. The first electrode is located at one end of the first semiconductor layer. The orthographic projection of the gate structure on the substrate overlaps with the orthographic projection of the first semiconductor layer on the substrate. A third electrode is formed at the end of the first semiconductor layer away from the first electrode, and the remaining first semiconductor layer forms a first channel. The first electrode, the first channel, the gate structure, and the third electrode form a first transistor. The material of the first channel is a single crystal material, which has the advantages of high mobility and low impedance, can effectively reduce the resistance of the gate structure, and thus improve the working performance of the first transistor.

[0247] In the embodiment of the present application, the material of the second initial semiconductor layer is a doped amorphous material. The second initial semiconductor layer is formed into a second electrode and a second semiconductor layer. The amorphous material of the second initial semiconductor layer is transformed into a single crystal material of the second semiconductor layer. The second electrode is located at one end of the second semiconductor layer. The orthographic projection of the gate structure on the substrate overlaps with the orthographic projection of the second semiconductor layer on the substrate. A fourth electrode is formed at the end of the second semiconductor layer away from the second electrode, and the remaining second semiconductor layer forms a second channel. The second electrode, the second channel, the gate structure, and the second electrode form a second transistor. The material of the second channel is a single crystal material, which has the advantages of high mobility and low impedance, can effectively reduce the resistance of the gate structure, and thus improve the working performance of the second transistor.

[0248] In the embodiment of the present application, the second initial semiconductor layer is located on the side of the first semiconductor layer away from the substrate. The orthographic projections of the first electrode and the second semiconductor layer on the substrate respectively overlap with the orthographic projection of the second initial semiconductor layer on the substrate, and the first electrode and the first semiconductor layer are respectively insulated from the second initial semiconductor layer, so that the formed second transistor is located on the side of the first transistor away from the substrate and is insulated from the first transistor. Along the direction perpendicular to the substrate, the first transistor and the second transistor are stacked on the substrate in sequence, so that the semiconductor structure occupies less space and area, and can improve the integration density of the storage device. Stacking the first transistor and the second transistor vertically can further reduce the area occupied by the device and improve the integration degree of the storage device. At the same time, it can be formed on the same substrate by a simple method, realizing high density, high performance, multi-function and low power consumption of a single chip.

[0249] In the embodiment of the present application, the first transistor and the second transistor share a gate structure, and the on-off states of the upper and lower two transistors with different conduction types can be simultaneously controlled by the same gate structure.

[0250] The present application provides a method for fabricating a 3D stacked CFET structure. The fabricated CFET structure has NFETs and PFETs, with the PFETs vertically stacked on top of the NFETs and the PFETs and NFETs sharing a common gate. The materials of the first channel and the second channel are both single-crystalline materials transformed from amorphous materials, having relatively high mobility and low impedance. The fabrication process of the CFET structure in the present application is simple, the fabricated CFET structure occupies a small area, has a low manufacturing cost, and high working performance.

[0251] The fabricated first transistor and second transistor are junctionless devices, with the first electrode, the first channel, and the third electrode having uniform doping, and the second electrode, the second channel, and the fourth electrode having uniform doping.

[0252] By using the metal-induced crystallization process, it is possible to obtain an appropriate crystallization rate while improving the uniformity and stability of obtaining large-area single-crystalline materials. The metal-induced crystallization technology has the advantages of simple process, enabling the crystallization of amorphous silicon thin films in a relatively short time, high efficiency, and the prepared single-crystalline silicon thin films having relatively high mobility and low impedance. The first channel of the first transistor and the second channel of the second transistor are respectively single-crystalline materials transformed from metal-silicided-induced amorphous materials, with a simple fabrication process, the fabricated semiconductor structure occupying a small area, having a low manufacturing cost, and high working performance.

[0253] Those skilled in the art of the present technology can understand that the various operations, methods, steps, measures, and solutions in the processes discussed in the present application can be alternated, changed, combined, or deleted. Further, other steps, measures, and solutions in the various operations, methods, and processes discussed in the present application can also be alternated, changed, rearranged, decomposed, combined, or deleted. Further, the steps, measures, and solutions in the prior art that are the same as those disclosed in the various operations, methods, and processes in the present application can also be alternated, changed, rearranged, decomposed, combined, or deleted.

[0254] In the description of the present application, the directions or positional relationships indicated by the words "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are the exemplary directions or positional relationships based on the drawings, which are for the convenience of describing or simplifying the embodiments of the present application, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application.

[0255] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this application, unless otherwise specified, the meaning of "a plurality" is two or more.

[0256] In the description of this application, it should be noted that unless otherwise clearly defined and limited, the terms "mounted", "connected" and "coupled" shall be construed broadly. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a direct connection or an indirect connection through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0257] In the description of this specification, specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in a suitable manner.

[0258] It should be understood that although the steps in the flowchart of the drawings are shown in sequence according to the indication of the arrows, the execution order of these steps is not limited to the order indicated by the arrows. Unless otherwise clearly stated in this document, in some implementation scenarios of the embodiments of this application, the steps in each process can be executed in other orders according to requirements. Moreover, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on the actual implementation scenario. Some or all of these sub-steps or stages may be executed at the same time or at different times. In the scenario where the execution times are different, the execution order of these sub-steps or stages can be flexibly configured according to requirements, and the embodiments of this application do not limit this.

[0259] The above are only some implementation manners of this application. It should be pointed out that for those of ordinary skill in the art, without departing from the technical concept of the solution of this application, using other similar implementation means based on the technical idea of this application also belongs to the protection scope of the embodiments of this application.

Claims

1. A method for preparing a semiconductor structure, characterized in that, Comprising: Providing a substrate; Forming a first initial semiconductor layer on one side of the substrate, the material of the first initial semiconductor layer being a doped amorphous material; Forming the first initial semiconductor layer into a first electrode and a first semiconductor layer, the first electrode being located at one end of the first semiconductor layer, the material of the first semiconductor layer being a single crystal material; Forming a second initial semiconductor layer on the side of the first semiconductor layer away from the substrate, the positive projection of the first electrode on the substrate and the positive projection of the first semiconductor layer on the substrate respectively overlap with the positive projection of the second initial semiconductor layer on the substrate, the first electrode and the first semiconductor layer are respectively insulated from the second initial semiconductor layer, the material of the second initial semiconductor layer being a doped amorphous material, and the doping type of the second initial semiconductor layer being opposite to the doping type of the first initial semiconductor layer; Forming the second initial semiconductor layer into a second electrode and a second semiconductor layer, the second electrode being located at one end of the second semiconductor layer, the material of the second semiconductor layer being a single crystal material; Forming a gate structure, the positive projection of the gate structure on the substrate overlapping with the positive projections of the first semiconductor layer and the second semiconductor layer on the substrate; Forming a third electrode at the end of the first semiconductor layer away from the first electrode, and forming a first channel with the remaining first semiconductor layer, forming a fourth electrode at the end of the second semiconductor layer away from the second electrode, and forming a second channel with the remaining second semiconductor layer, the first electrode, the first channel, the gate structure and the third electrode form a first transistor, and the second electrode, the second channel, the gate structure and the fourth electrode form a second transistor.

2. The method for preparing a semiconductor structure according to claim 1, wherein Forming the first initial semiconductor layer into a first electrode and a first semiconductor layer includes: Adopting a metal-induced crystallization process to form a part of the first initial semiconductor layer into a first electrode, and transforming another part of the first initial semiconductor layer of amorphous material into a first semiconductor layer of single crystal material.

3. The method for preparing a semiconductor structure according to claim 1 or 2, characterized in that, Before forming the first initial semiconductor layer on one side of the substrate, the preparation method further includes: Forming a first barrier layer on one side of the substrate; Forming the first initial semiconductor layer on one side of the substrate includes: Forming a first amorphous silicon thin film on the side of the first barrier layer away from the substrate; Performing ion implantation on the first amorphous silicon thin film; Performing a first patterning process to form the first amorphous silicon thin film into a first initial electrode region, a first initial channel region and a second initial electrode region connected in sequence, the positive projection area of the first initial electrode region on the substrate and the positive projection area of the second initial electrode region on the substrate are respectively larger than the positive projection area of the first initial channel region on the substrate, so as to be used as the first initial semiconductor layer.

4. The method for preparing a semiconductor structure according to claim 3, wherein Forming the first initial semiconductor layer into a first electrode and a first semiconductor layer includes: A first covering layer is formed on one side of the substrate, the first covering layer covering the first initial semiconductor layer, the first covering layer having a first induced hole, and the bottom of the first induced hole exposing the first initial electrode region; A first induced layer is formed on one side of the substrate, the first induced layer covering the first covering layer, the inner wall of the first induced hole, and the exposed first initial electrode region, the first induced layer being in contact with the first initial electrode region, and the material of the first induced layer including a metal; A first heat treatment is performed to transform the amorphous silicon in the first initial electrode region into a metal silicide to form the first electrode; A second heat treatment is performed, with the metal material in the first induced layer as the induction source and the metal silicide of the first electrode as the medium, to induce the amorphous silicon in the first initial channel region and the second initial electrode region to transform into single crystal silicon and activate the implanted ions to form the first semiconductor layer.

5. The method for preparing a semiconductor structure according to claim 4, wherein, Forming a first covering layer on one side of the substrate includes: Depositing a silicon oxide material on one side of the substrate to form a first initial covering layer, the first initial covering layer covering the first barrier layer and the first initial semiconductor layer; A second patterning process is performed to form a first induced hole penetrating through the first initial covering layer, the positive projection of the first induced hole on the substrate covering the positive projection of the first initial electrode region on the substrate, and the patterned first initial covering layer forms the first covering layer.

6. The method for preparing a semiconductor structure according to claim 4, wherein Forming a first induced layer on one side of the substrate includes: Sequentially depositing a first silicon oxide thin film and a first nickel thin film on one side of the substrate, the first silicon oxide thin film covering the first covering layer, the inner wall of the first induced hole, and the exposed first initial electrode region, the first nickel thin film covering the side of the first silicon oxide thin film away from the substrate, and the first silicon oxide thin film and the first nickel thin film form the first induced layer; Performing a first heat treatment includes: Performing an annealing treatment at 400°C - 500°C for a treatment time of 1 min - 5 min to cause the amorphous silicon in the first initial electrode region to react with the nickel material in the first induced layer to form nickel silicide to form the first electrode; Performing a second heat treatment includes: Performing an annealing treatment at 500°C - 600°C for a treatment time of 1 h - 24 h, the induction source being the nickel material in the first induced layer and the medium being the nickel silicide of the first electrode.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein After performing the second heat treatment, the preparation method further includes: Removing the remaining first nickel thin film; Depositing a silicon oxide material on one side of the substrate to form a second barrier layer, the second barrier layer covering the first silicon oxide thin film and filling the first induced hole.

8. The method for preparing a semiconductor structure according to claim 7, wherein Forming a second initial semiconductor layer on the side of the first semiconductor layer away from the substrate includes: Forming a second amorphous silicon thin film on the side of the second barrier layer away from the substrate; Perform a third patterning process to form the second amorphous silicon thin film into a third initial electrode region, a second initial channel region, and a fourth initial electrode region that are sequentially connected. The orthographic projection area of the third initial electrode region on the substrate and the orthographic projection area of the fourth initial electrode region on the substrate are respectively larger than the orthographic projection area of the second initial channel region on the substrate; Perform ion implantation on the second amorphous silicon thin film to form the second initial semiconductor layer. The ion type implanted in the second initial semiconductor layer is opposite to the ion type implanted in the first initial semiconductor layer.

9. The method for preparing a semiconductor structure according to claim 8, wherein, Form the second initial semiconductor layer into a second electrode and a second semiconductor layer, including: Form a second capping layer on one side of the substrate. The second capping layer covers the second initial semiconductor layer and the second barrier layer. The second capping layer has a second induction hole, and the bottom of the second induction hole exposes the third initial electrode region; Form a second induction layer on one side of the substrate. The second induction layer covers the second capping layer, the inner wall of the second induction hole, and the exposed third initial electrode region. The second induction layer is in contact with the third initial electrode region, and the material of the second induction layer includes metal; Perform a third heat treatment to transform the amorphous silicon in the third initial electrode region into metal silicide to form the second electrode; Perform a fourth heat treatment. Using the metal material in the second induction layer as the induction source and the metal silicide of the second electrode as the medium, induce the amorphous silicon in the second initial channel region and the fourth initial electrode region to transform into single crystal silicon and activate the implanted ions to form the second semiconductor layer.

10. The method for preparing a semiconductor structure according to claim 9, wherein, Before forming the gate structure, the preparation method further includes: Deposit a silicon oxide material on one side of the substrate to form a first insulating layer. The first insulating layer covers the second induction layer and fills the second induction hole; Form a gate structure, including: Form a first groove exposing the first initial channel region and the second initial channel region. The first groove extends in a direction perpendicular to the substrate; Form a gate dielectric layer. The gate dielectric layer covers the sidewalls of the first initial channel region, the sidewalls of the second initial channel region, and the inner wall of the first groove; Form a gate electrode. The gate electrode fills the first groove. The gate dielectric layer is located between the first initial channel region and the gate electrode and between the second initial channel region and the gate electrode. The first transistor and the second transistor share one gate electrode.

11. The method for preparing a semiconductor structure according to claim 10, wherein, Before forming the third electrode at the end of the first semiconductor layer away from the first electrode and forming the first channel with the remaining first semiconductor layer, and forming the fourth electrode at the end of the second semiconductor layer away from the second electrode and forming the second channel with the remaining second semiconductor layer, the preparation method further includes: Form a second insulating layer on one side of the substrate. The second insulating layer covers the first insulating layer, the gate dielectric layer, and the gate electrode; Forming a third electrode at an end of the first semiconductor layer away from the first electrode, and forming a first channel with the remaining first semiconductor layer; forming a fourth electrode at an end of the second semiconductor layer away from the second electrode, and forming a second channel with the remaining second semiconductor layer, including: Forming a second groove exposing the second initial electrode region and the fourth initial electrode region, the second groove extending in a direction perpendicular to the substrate, and a positive projection of the second groove on the substrate covering a positive projection of the second initial electrode region on the substrate and covering a positive projection of the fourth initial electrode region on the substrate; Depositing a nickel material on surfaces of the exposed second initial electrode region and the fourth initial electrode region respectively, and performing a rapid thermal annealing process to transform monocrystalline silicon in the second initial electrode region and the fourth initial electrode region into nickel silicide respectively. After the rapid thermal annealing process, the second initial electrode region forms a third electrode, the first initial channel region forms a first channel, the fourth initial electrode region forms a fourth electrode after the rapid thermal annealing process, and the second initial channel region forms a second channel.

12. The method for preparing a semiconductor structure according to claim 11, wherein, After forming a third electrode at an end of the first semiconductor layer away from the first electrode, and forming a first channel with the remaining first semiconductor layer; forming a fourth electrode at an end of the second semiconductor layer away from the second electrode, and forming a second channel with the remaining second semiconductor layer, the manufacturing method further includes: Forming a drain end connection structure, the drain end connection structure filling the second groove, the drain end connection structure contacting the third electrode and the fourth electrode respectively, and the first transistor and the second transistor sharing one drain end connection structure.

13. The method for preparing a semiconductor structure according to claim 12, wherein, After forming the drain end connection structure, the manufacturing method further includes: Forming a via hole penetrating the second insulating layer, a bottom of the via hole exposing the gate electrode; Forming a gate electrode connection structure, the gate electrode connection structure filling the via hole, one end of the gate electrode connection structure contacting the gate electrode, and the other end being used for connection with an external device.

14. The method for manufacturing a semiconductor structure according to claim 13, wherein, After forming the gate electrode connection structure, the manufacturing method further includes: Forming a third groove exposing the first electrode, the third groove extending in a direction perpendicular to the substrate, and a positive projection of the third groove on the substrate overlapping a positive projection of the first electrode on the substrate; Forming a first source end connection structure, the first source end connection structure filling the third groove, the first source end connection structure contacting the first electrode; Forming a fourth groove exposing the second electrode, the fourth groove extending in a direction perpendicular to the substrate, a positive projection of the fourth groove on the substrate overlapping a positive projection of the second electrode on the substrate and having no overlap with a positive projection of the third groove on the substrate; Forming a second source end connection structure, the second source end connection structure filling the fourth groove, the second source end connection structure contacting the second electrode.

15. A semiconductor structure, characterized in that, Including: A substrate; A first transistor is disposed on one side of the substrate. The first transistor includes a first channel, a first electrode, a gate structure, and a third electrode. The material of the first channel is a single crystal material. The first electrode is located at one end of the first channel, and the third electrode is located at the end of the first channel away from the first electrode. The orthographic projection of the gate structure on the substrate overlaps the orthographic projection of the first channel on the substrate and is insulated from the first channel; A second transistor is disposed on the side of the first transistor away from the substrate. The second transistor includes a second channel, a second electrode, a gate structure, and a fourth electrode. The material of the second channel is a single crystal material. The second electrode is located at one end of the second channel, and the fourth electrode is located at the end of the second channel away from the second electrode. The orthographic projection of the gate structure on the substrate overlaps the orthographic projection of the second channel on the substrate and is insulated from the second channel; The conduction type of the first transistor is opposite to that of the second transistor.

16. The semiconductor structure according to claim 15, wherein The first transistor is an N-type field-effect transistor, and the second transistor is a P-type field-effect transistor. Along the direction perpendicular to the substrate, the N-type field-effect transistor and the P-type field-effect transistor are stacked on the substrate in sequence; and / or The first transistor is a junctionless field-effect transistor, and the second transistor is a junctionless field-effect transistor.

17. The semiconductor structure according to claim 15, wherein The gate structure extends along the direction perpendicular to the substrate, and the first transistor and the second transistor share a gate structure; The semiconductor structure further includes a drain-end connection structure, a gate-electrode connection structure, a first source-end connection structure, and a second source-end connection structure; One end of the gate-electrode connection structure is connected to the gate electrode of the gate structure, and the other end is used for connection to an external device; The drain-end connection structure is respectively connected to the third electrode and the fourth electrode, and the first transistor and the second transistor share a drain-end connection structure; The first source-end connection structure is connected to the first electrode, and its orthographic projection on the substrate does not overlap the orthographic projection of the second electrode on the substrate; The second source-end connection structure is connected to the second electrode; The dimension of the first source-end connection structure along the direction perpendicular to the substrate is greater than the dimension of the second source-end connection structure along the direction perpendicular to the substrate, and the first source-end connection structure and the second source-end connection structure are in a stepped shape.

18. A storage device, characterized in that, Comprising: A semiconductor structure prepared by using the preparation method of the semiconductor structure according to any one of claims 1 to 14; Or, the semiconductor structure according to any one of claims 15 to 17.

19. An electronic device, characterized in that, Comprising: The storage device according to claim 18.

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