Method for forming semiconductor structure

Abstract

The invention provides a method for forming a semiconductor structure (100), the method comprising: forming a layer stack (110) on a substrate (102), the layer stack (110) comprising: a first sub-stack; a second sub-stack (130) on the first sub-stack (120) and comprising a plurality of sacrificial layers alternating between first and second sacrificial layers (132a, 132b) wherein adjacent first and second sacrificial layers (132a, 132b) of the second sub-stack (130) are separated by a liner (133); a third sub-stack (140) on the second sub-stack (130); forming a recess (160) in the layer stack; forming an internal spacer (162) in the recess (160); removing the at least one second sacrificial layer (132b) of the second sub-stack (130) by etching, thereby forming at least one first cavity (135); and filling the at least one first cavity (135) with a dielectric material, thereby forming at least one dielectric layer (136).

Description

Technical Field

[0001] The present disclosure relates to a method for forming a semiconductor structure. Background Art

[0002] Complementary FETs (CFETs) are currently on the scaling roadmap as one of the next-generation scaling options. A CFET includes an NFET (i.e., an N-type FET) and a PFET (i.e., a P-type FET) stacked on top of each other (or vice versa). The NFET and PFET are vertically separated by an intermediate dielectric isolation (MDI), and the bottom device can also be separated from the substrate by a bottom dielectric isolation (BDI). Summary of the Invention

[0003] An object of the present inventive concept is to provide an improved semiconductor structure and / or an improved method for manufacturing the same.

[0004] Another object is to provide a semiconductor structure and / or FET having few dislocations.

[0005] Yet another object is to provide a semiconductor structure and / or FET having a high degree of freedom in selecting layer materials.

[0006] Yet another object is to provide a method for forming a semiconductor structure having relatively less stringent etch selectivity requirements. Yet another object is to provide a stable semiconductor structure. Other objects or additional objects can be understood from the following.

[0007] According to a first aspect of the present invention, there is provided a method for forming a semiconductor structure, the method comprising:

[0008] forming a layer stack on a substrate, the layer stack comprising:

[0009] a first sub-stack comprising a first sacrificial layer and a channel layer defining the topmost layer of the first sub-stack on the first sacrificial layer, and

[0010] a second sub-stack located on the first sub-stack and comprising a plurality of sacrificial layers alternating between a first and a second sacrificial layer, wherein adjacent first and second sacrificial layers of the second sub-stack are separated by a liner layer, wherein the first sacrificial layer defines the corresponding bottommost and topmost layers of the second sub-stack, and the second sub-stack comprises at least one second sacrificial layer;

[0011] a third sub-stack located on the second sub-stack and comprising a channel layer defining the bottommost layer of the third sub-stack and a first sacrificial layer on the channel layer;

[0012] Wherein the first sacrificial layer is formed of a first sacrificial semiconductor material, the second sacrificial layer is formed of a second sacrificial semiconductor material different from the first sacrificial semiconductor material, and the liner layer is formed of a semiconductor material different from the first sacrificial semiconductor material and the second sacrificial semiconductor material;

[0013] Form source / drain trenches that expose the end faces of the layer stack;

[0014] Form trenches in the layer stack by laterally etching back the end faces of the first sacrificial layer from opposite ends of the layer stack by selective etching;

[0015] Form internal spacers in the trenches;

[0016] Remove at least one second sacrificial layer of the second sub-stack by etching, thereby forming at least one first cavity, while protecting the first sacrificial layer of the second sub-stack from the etching action by the internal spacers and the liner layer; and

[0017] Fill at least one first cavity with a dielectric material, thereby forming at least one dielectric layer.

[0018] The phrase "the first layer disposed on the second layer" with respect to any layer of the layer stack (or a layer of a sub-stack) herein means that the first layer is disposed directly above the second layer (i.e., adjacent to the second layer).

[0019] Relative spatial terms such as "topmost", "bottom", "lower", "vertical", "stacked on top of" are understood herein to represent positions or orientations within the reference frame of the semiconductor device. Specifically, these terms can be understood relative to the normal direction of the substrate on which the layer stack is formed, or equivalently relative to the bottom-up / stacking direction of the layer stack. Accordingly, terms such as "lateral" and "horizontal" should be understood as positions or orientations parallel to the substrate.

[0020] The term "thickness" should be understood as the dimension of a structure (e.g., a layer of a sub-stack) as seen along the normal to the surface underlying the structure (e.g., a layer of a sub-stack). For example, the thickness of a layer of the layer stack or the thickness of a sub-stack can refer to the thickness dimension of the layer / sub-stack as seen along the bottom-up / stacking direction of the device layer.

[0021] The semiconductor structure can be a semiconductor structure for fabricating a stack of FETs including top and bottom field-effect transistors (FETs). The stack of FETs can be a CFET, where the top FET is an NFET and the bottom FET is a PFET, or vice versa. Thus, the semiconductor structure can be a semiconductor structure suitable for conversion into a stack of FETs (e.g., a CFET).

[0022] Thus, the method is compatible with complementary FET (CFET) device fabrication. The method is also compatible with fin device fabrication. The resulting semiconductor structure can be used to produce a stack of FETs.

[0023] The layer stack may sometimes be referred to as a superlattice stack.

[0024] When referring to opposite ends of the layer stack herein, it is understood that the opposite ends may be the ends at which source / drain regions are to be formed. It is also understood that the opposite ends may be opposite sides of the gate structure.

[0025] The channel layer of the first sub-stack may be the channel layer for the bottom FET. Similarly, the channel layer of the third sub-stack may be the channel layer for the top FET. The channel layer may be a Si layer.

[0026] The first sacrificial layer may be a layer that can be replaced by a gate stack during the production of the FET stack.

[0027] The second sacrificial layer is a layer in which the second sacrificial material has been replaced by a dielectric material during the production of the FET stack. The dielectric material can then act as an electrical isolation between the bottom and top FETs. This electrical isolation between the bottom and top FETs may be referred to as an intermediate dielectric isolation.

[0028] The liner layer may be a layer that is resistant to the etchant used to etch the second sacrificial layer. The liner layer may be resistant to the etchant used to trench the first sacrificial layer. The liner layer may be thin, e.g., thinner than the first and second sacrificial layers. As described above, the first and second sacrificial layers are formed of different semiconductor materials. Thus, the etchant may have different etch rates for the first and second sacrificial layers. Thus, the first and second sacrificial layers may be selectively etched at different points during the production process. The channel layer, the liner layer, the first sacrificial layer, and the second sacrificial layer may all be made of different materials. Alternatively, the channel layer and the liner layer are formed of the same material different from the first and second sacrificial semiconductor materials. Advantageously, the channel layer and the liner layer are formed of Si, while the first and second sacrificial layers are formed of SiGe, where the first and second sacrificial layers have different Ge contents.

[0029] Layers of different materials may have a lattice mismatch. The lattice mismatch may introduce strain in the layer stack. When the strain becomes too large during the epitaxial growth process, relaxation may occur due to the formation of dislocations. Dislocations are generally disadvantageous in FETs. Compared with conventional production methods, the present invention makes it possible to avoid dislocations while providing a high degree of freedom in the selection of layer materials and less stringent etch selectivity requirements.

[0030] The term "inner spacer" herein means a dielectric layer portion formed in a groove to cover an end face of a first sacrificial layer. Forming the inner spacer can include conformally depositing an inner spacer material layer. Forming the inner spacer can include subsequently etching the inner spacer material layer such that discrete portions of the inner spacer material layer remain in each groove to form the inner spacer therein. Specifically, an isotropic etching process can be used to etch the inner spacer material to remove the inner spacer outside the groove. The isotropic etching process allows the inner spacer material layer to be etched at (at least substantially) a uniform rate. Thus, a structure covered by the inner spacer material layer can remain substantially covered by the inner spacer material layer to be separated from the etchant until the end face of the channel layer is exposed, where the etching can be stopped. The inner spacer material layer can be deposited to a thickness such that the groove is pinched off (i.e., closed).

[0031] The term "conformal deposition" herein refers to a deposition processing technique that results in a conformally grown layer or film. Conformal deposition can be achieved using an atomic layer deposition (ALD) processing technique.

[0032] Providing a liner and an inner spacer has many advantages:

[0033] Since the first sacrificial layer of the sub-stack is protected from the action of the etching by the inner spacer and the liner, it is convenient to form at least one dielectric layer. To form the at least one dielectric layer, a first cavity is formed by etching. The inner spacer and the liner ensure that the material removal by etching does not extend to portions of the semiconductor structure that do not need to be removed. For example, when etching the second sacrificial layer, the inner spacer and the liner can ensure that the first sacrificial layer is not exposed to the etchant. Since the inner spacer and the liner protect the first sacrificial layer, the requirements for selectivity to etching are relatively less stringent, and thus a greater degree of freedom is provided in the selection of the materials of the first and second sacrificial layers. Therefore, the materials of the first and second sacrificial layers can be selected to have a small lattice mismatch. The first and second sacrificial layers can also be selected to have a small lattice mismatch with respect to the liner and the channel layer. Thus, the method enables a layer stack with a reduced risk of relaxation and reduced epitaxial growth-induced defects (such as dislocations). Thus, a high-quality semiconductor structure is provided, which in turn enables improved device performance.

[0034] Liners are particularly important because they can protect the interface between the first and second sacrificial layers during the etching of the second sacrificial layer. The liner can be thin, for example thinner than the first and second sacrificial layers. Thus, the liner can protect the interface between the first and second sacrificial layers while contributing little or no strain to the layer stack.

[0035] For illustration, consider a first scenario where no liner is used. In this scenario, it may be necessary to use first and second sacrificial layers with very different sacrificial semiconductor materials. For example, SiGe layers with very different Ge contents can be used as the respective first and second sacrificial layers. Additionally, it may not be possible to arbitrarily exchange materials between the first and second sacrificial layers. For example, if the second sacrificial layer is to be removed before the first sacrificial layer, the second sacrificial layer may have to have a higher Ge content than the first sacrificial layer.

[0036] For further illustration, consider a second scenario where an internal spacer and a liner are used. In this scenario, first and second sacrificial layers with very similar sacrificial semiconductor materials can be used. For example, as the respective first and second sacrificial layers, the SiGe layers have only a small difference in Ge content. The reasons for enabling this design choice are as follows:

[0037] The first sacrificial layer can have a higher Ge content than the second sacrificial layer. It is conceivable that for a given etchant, a sacrificial layer with a relatively high Ge content is etched at a faster rate compared to a sacrificial layer with a relatively low Ge content. Thus, during subsequent etching, the etchant can etch the second sacrificial layer, which has a much lower Ge content than the first sacrificial layer. Additionally, the presence of the internal spacer and the liner can protect the remaining first sacrificial layer. Therefore, less stringent selectivity requirements are provided. It can also be envisioned that the channel layer of the layer stack can be made of Si, which is hardly etched by the given etchant. Thus, by placing the first sacrificial layer near (or even adjacent to) the channel layer, the channel layer can protect the first sacrificial layer in a manner similar to the internal spacer and the liner, which further reduces the selectivity requirements. For example, compared to a conventional structure without a liner, the difference between the high Ge content and the low Ge content is reduced. Therefore, according to the above exemplary scenarios, the present invention provides a great degree of freedom in selecting layer materials, which, compared to conventional methods, can be used to promote other strain distributions in the layer stack. For example, the present invention allows the use of SiGe layers with only a small difference in Ge content as the respective first and second sacrificial layers. It should be noted that the above scenarios are examples. The present invention is also applicable to sacrificial semiconductor materials other than SiGe. Since the selectivity requirements for the layer materials of the layer stack by the liner and the internal spacer are relatively less stringent, it becomes possible to grow a fully strained layer stack that includes two or more channels per device polarity. Conventional integration schemes may include layer materials with a large lattice mismatch therebetween, thus hindering the possibility of forming a layer stack that includes multiple channels per device polarity. The less stringent selectivity requirements enable the formation of a layer stack that includes multiple channels per device polarity. For example, a layer stack with two or more nanosheets per device polarity can be achieved. This enables further scaling of the device.

[0038] The term "device polarity" herein refers to the type of FET, e.g., p-type or n-type MOSFET, where p-type MOSFET is one polarity and n-type MOSFET is the other polarity.

[0039] Although the method can be advantageously used in combination with forming fin and CFET devices, it is contemplated that the method can also be used to form other horizontal channel FET devices (e.g., nanowire FET (NWFET) or nanosheet FET (NSHFET) as described above) that require internal spacers, which can benefit from the liner.

[0040] The term "layer stack" herein denotes a structure of layers formed sequentially on top of each other. The layer stack can in particular be fin-shaped.

[0041] The material of the channel layer can be Si 1-a Ge a , and the material of the liner can be Si 1-b Ge b , the first sacrificial semiconductor material can be Si 1-c Ge c , the second sacrificial semiconductor material can be Si 1-d Ge d , where 0 ≤ a ≤ b < d < c.

[0042] The channel layer can be formed of Si 1-a Ge a channel material. The channel material can be Si. Thus, a can be equal to 0.

[0043] The liner can be formed of Si 1-b Ge b layer material. The layer material can be Si. Thus, b can be equal to 0.

[0044] The first sacrificial layer can be formed of a first sacrificial material of Si 1-c Ge c .

[0045] The second sacrificial layer can be formed of a second sacrificial material of Si 1-d Ge d .

[0046] The first and second sacrificial materials can be selected such that c is greater than d. In other words, the Ge content of the second sacrificial material can be less than the Ge content of the first sacrificial material. The first sacrificial layer can thus be said to be formed of a first sacrificial material having a high Ge content. In other words, the layer adjacent to the channel layer can have a high Ge content. The second sacrificial layer can thus be said to be formed of a second sacrificial material having a low Ge content. The second sub-stack can thus include a plurality of sacrificial layers alternating between high and low Ge contents.

[0047] In this context, it can be noted that the terms high and low refer to the Ge content of the first and second sacrificial layers relative to each other. Thus, even if the first sacrificial layer may have a high Ge content relative to the second sacrificial layer, the Ge content may still be lower than that of the high Ge content layer in a conventional structure. More specifically, the use of an inner spacer, a liner layer, and the arrangement of the first sacrificial layer (having a high Ge content) relative to the channel layer (i.e., arranging the first sacrificial layer very close to or adjacent to the channel layer) results in the Ge content of the first sacrificial layer of the present invention being lower than that of the low Ge content layer in a conventional structure when arranged near or adjacent to the channel layer. Thus, the present invention provides reduced selectivity requirements.

[0048] Using a liner layer that separates the sacrificial layer and the inner spacer enables the removal of the second sacrificial layer, and subsequently a dielectric layer can replace the second sacrificial layer. As described above, the second sacrificial layer can be said to have a low Ge content. The first sacrificial layer can be said to have a high Ge content. It is recognized that this method can facilitate the formation of the dielectric layer by removing the second sacrificial layer having a low Ge content, and thus can provide an improved method. In addition, during the act of removing the at least one SiGe layer having a low Ge content, the liner layer and the inner spacer can protect the SiGe layer having a high Ge content.

[0049] As described above, the use of the liner layer and the inner spacer enables the first and second sacrificial layers to be selected such that the lattice mismatch between them is minimized. In other words, if the first sacrificial layer is formed of a first sacrificial material of Si 1-c Ge c and the second sacrificial layer is formed of a second sacrificial material of Si 1-d Ge d then c can be selected to be greater than d, while the difference between c and d can be relatively small. Thus, it can be recognized that this method can facilitate the use of a small difference in Ge content between the high and low Ge content sacrificial layers. Thus, a greater degree of design is provided for the semiconductor structure. In addition, the reduction in lattice mismatch between the sacrificial layers enables the superlattice growth of these layers to be carried out with a reduced risk of relaxation and a reduced amount of defects caused by epitaxial growth. Thus, a semiconductor structure having, for example, reduced leakage current can be provided. In addition, the growth of a fully strained superlattice is achieved, which in turn provides a semiconductor structure with improved device performance.

[0050] This method implies that the corresponding channel layers of the first and third sub-stacks can be located beside the corresponding first sacrificial layers (SiGe layers with a high Ge content). It is recognized that by placing the channel layer beside a SiGe layer with a high Ge content (instead of beside a SiGe layer with a low Ge content), the strain distribution of the layer stack can be different (and favorable) compared to a conventional layer stack. In other words, in such a conventional layer stack, the corresponding channel layers of the first and third sub-stacks are placed beside SiGe layers with a low Ge content. Compared to the conventional method and its associated semiconductor structure, this favorable strain distribution can promote a low risk of dislocation formation during the epitaxial growth process of the layer stack. Therefore, higher-quality FETs can be promoted, such as FETs without dislocations in the channel layer.

[0051] In this context, it can be noted that by placing the channel layer beside a SiGe layer with a high Ge content, the channel layer can be adjacent to the SiGe layer with the high Ge content.

[0052] Furthermore, the favorable strain distribution can promote a large design freedom for the semiconductor structure. For example, compared to conventional devices, other layer thicknesses of the SiGe layer can be achieved. For example, it is possible to fabricate a MDI that is thicker than a conventional structure.

[0053] During the production process of the FET stack, the SiGe layer can be used as a sacrificial layer. As described above, the SiGe layer with a low Ge content can be replaced by a dielectric material. The dielectric material (dielectric layer) can be said to form an intermediate dielectric isolation (MDI) in the final product. In the final product, the SiGe layer with a high Ge content can be replaced by a gate stack, such as a fully surrounding gate design or a triple gate design.

[0054] In this context, it can be noted that the difference in Ge content between the sacrificial layers can be selected to facilitate the selective etching of the sacrificial layers. However, it is recognized that too large a difference in Ge content can lead to the following strain distribution: this strain distribution may increase the risk of layer stack relaxation, resulting in more defects. Therefore, as described above, this method provides a favorable strain distribution while still enabling selective etching.

[0055] The first sacrificial semiconductor material can have a composition such that c can be in the range of 0.25 - 0.35.

[0056] For example, c can be less than 0.30. Generally, by having c in the range of 0.25 - 0.35, full-strain superlattice growth of the sacrificial layer can be provided. The superlattice can also be grown with a reduced risk of relaxation and a reduced amount of epitaxial growth-induced defects.

[0057] As another example, the first sacrificial material can be Si 0.75 Ge0.25 while the second sacrificial material can be Si 0.9 Ge 0.1 This relative difference in Ge content can facilitate the selective processing (e.g., selective etching) of the different sacrificial and channel layers of the layer stack, while enabling superlattice growth with a reduced risk of relaxation and a reduced amount of defects.

[0058] The thickness of the liner layer can be in the range of 1 nm to 3 nm.

[0059] As an example, the thickness of the liner layer can be 1 nm, 2 nm, or 3 nm. As another example, the thickness of the liner layer can be less than 2 nm or less than 3 nm. When removing the second sacrificial layer, this thickness of the liner layer provides sufficient protection to the first sacrificial layer of the second sub-stack while providing a thin semiconductor structure. This enables further scaling of the device. Additionally, the reduced growth thickness of the liner layer can enable a reduction in the amount of growth defects in the layer stack. The liner layer can be thin enough to prevent parasitic source and drain epitaxial growth.

[0060] Furthermore, this liner layer thickness can prevent the diffusion of atoms throughout the layer stack during processing steps such as annealing while still enabling a relatively thin semiconductor structure to be achieved.

[0061] Forming the recess can include isotropically selectively etching the end faces of the first sacrificial layer from opposite ends of the layer stack.

[0062] The isotropic etching of the end faces allows for the controlled formation of the recess. Thus, this facilitates subsequent processing steps, such as the action of forming internal spacers in the recess.

[0063] However, it is also conceivable that any suitable dry etching process or wet etching process (e.g., HCl or APM) that allows for the selective etching of the first sacrificial material can be used.

[0064] The second sub-stack can include at least two second sacrificial layers.

[0065] The method can accordingly include replacing each second sacrificial layer of the sub-stack with a corresponding dielectric layer by selectively etching the second sacrificial semiconductor material to form corresponding cavities in the second sub-stack and then filling each cavity with a dielectric material.

[0066] This means that the resulting semiconductor structure can thus include at least two dielectric layers disposed between the bottommost channel layer of the third sub-stack and the topmost channel layer of the first sub-stack. As described above, using at least two second sacrificial layers enables the formation of multiple relatively thin dielectric layers, where each of the dielectric layers can be thinner than a single thick dielectric layer unit. The smaller thickness of the second sacrificial layer can facilitate its replacement with a dielectric layer, as the second sacrificial layer can be removed more quickly, thereby reducing the exposure of the first sacrificial layer and the channel layer to the etchant. Additionally, the second sacrificial layer can have a thickness such that removing it enables the conformal deposition (e.g., by ALD) of a dielectric material that is thick enough to fill (and pinch off). A semiconductor structure can also be provided with a thick enough spacer between the first sub-stack and the third sub-stack. Moreover, the method can enable the formation of a layer stack with a reduced risk of relaxation and a reduced amount of growth defects. By including a second sub-stack with at least two second sacrificial layers (and subsequently at least two dielectric layers), the channels of the first sub-stack and the third sub-stack can be sufficiently electrically isolated from each other.

[0067] As described above, it should be noted that using a liner material and internal spacers (and the resulting less stringent selectivity requirements) can promote a large design freedom for the semiconductor structure. Since it is possible to select a sacrificial material to reduce the lattice mismatch therebetween, there is room to fabricate a thicker MDI than conventional structures while ensuring that the layer stack still does not undergo relaxation. It is also conceivable that a single (thick) MDI unit can be formed instead of multiple (thin) MDIs.

[0068] Filling the at least one first cavity with a dielectric material can be performed by atomic layer deposition ALD.

[0069] This enables the formation of a high-quality dielectric layer.

[0070] The method can further include:

[0071] Removing the first sacrificial layer of the layer stack to form a second cavity;

[0072] Forming a first gate stack extending around each channel layer of the first sub-stack;

[0073] Forming a second gate stack extending around each channel layer of the third sub-stack;

[0074] Wherein each of the first and second gate stacks extends through the second cavity.

[0075] Thus, the method can include gates for controlling the current in the top channel layer and the bottom channel layer.

[0076] The layer stack may further include a bottom second sacrificial layer disposed between the substrate and the first sub-stack, and a liner layer disposed between the bottom second sacrificial layer and the first sub-stack, and wherein the method further includes:

[0077] Removing the bottom second sacrificial layer disposed between the substrate and the first sub-stack by etching to form a bottom cavity;

[0078] Filling the bottom cavity with a dielectric material to form a bottom dielectric layer.

[0079] Thus, the method may include a bottom dielectric layer that electrically isolates the layer stack from the substrate. Accordingly, leakage current can be reduced.

[0080] The act of removing the bottom second sacrificial layer disposed between the substrate and the first sub-stack may be performed simultaneously with the act of removing each second sacrificial layer of the second sub-stack.

[0081] Accordingly, the amount of processing steps of the method can be reduced. Accordingly, an efficient method of forming a semiconductor structure is provided.

[0082] This also means that the bottom second sacrificial layer disposed between the substrate and the bottom channel layer may be formed of a second sacrificial material. In other words, the bottom second sacrificial layer may be formed of Si 1-d Ge d formed. Accordingly, the bottom second sacrificial layer can be removed simultaneously with the act of removing the second sacrificial layer of the second sub-stack by etching, for example, in a single step. When the second sacrificial layer is removed by etching, the bottom second sacrificial layer can be exposed to the same etchant and removed at the same rate. Accordingly, the bottom second sacrificial layer and the respective second sacrificial layers can be removed together. This eliminates any potential issues of grooving the remaining layer in a further separate processing step. This also makes the method more efficient. This also further facilitates any subsequent processing steps, such as the formation of a dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] The above and other objects, features and advantages of the inventive concept will be better understood from the following detailed description, which is illustrative and non-limiting, with reference to the accompanying drawings. Unless otherwise noted, the same reference numerals will be used for the same elements in the drawings.

[0084] Figure 1a -c to 12a-b illustrate the formation of a semiconductor structure applied to a method of forming a semiconductor device in cross-sectional views depicted schematically. DETAILED DESCRIPTION

[0085] Figure 1a -b depicts a semiconductor structure 100 at an initial stage of a method for forming a resulting semiconductor device, particularly a stacked transistor device such as a CFET device.

[0086] The axes X, Y, and Z represent a first direction, a second direction transverse to the first direction, and a direction perpendicular or bottom-up / stacked, respectively. Specifically, the X and Y directions can be referred to as transverse or horizontal directions because they are parallel to the main plane of the substrate 102 of the structure 100. The Z direction is parallel to the normal direction of the substrate 102.

[0087] Figure 1a -b depicts corresponding cross-sectional views of the structure 100 taken along the vertical planes B-B' (parallel to the XZ plane) and A-A' (parallel to the YZ plane). Unless otherwise specified, the cross-sectional views of the subsequent figures correspond to Figure 1a the cross-sectional views in -b.

[0088] The structure 100 includes a substrate 102 and a device layer stack 110 formed on the substrate 102. The substrate 102 can be a conventional semiconductor substrate suitable for complementary FETs. The substrate 102 can be a single-layer semiconductor substrate, such as formed from a bulk substrate such as a Si substrate, a germanium (Ge) substrate, or a silicon germanium (SiGe) substrate. However, multi-layer / composite substrates are also possible, such as a semiconductor layer epitaxially grown on a bulk substrate or a semiconductor-on-insulator (SOI) substrate, such as a Si-on-insulator substrate, a Ge-on-insulator substrate, or a SiGe-on-insulator substrate.

[0089] The device layer stack 110 includes a first sub-stack 120, a second sub-stack 130 on the first sub-stack 120, and a third sub-stack 140 on the second sub-stack 130.

[0090] For clarity of illustration, Figure 1c the first sub-stack 120 (bottom), the second sub-stack 130 (middle), and the third sub-stack 140 (top) are depicted separately.

[0091] The first sub-stack 120 includes a first sacrificial layer 122a and a channel layer 124 on the first sacrificial layer 122a. The channel layer 124 forms the top (i.e., the uppermost) layer of the first sub-stack 120. The layers 122a and 124 can be referred to as a unit of the first sub-stack 120. Although Figure 1c only one such unit (i.e., a single one) of the first sub-stack 120 is depicted, it should be understood that the first sub-stack 120 can include more than just a single unit. For example, the first sub-stack 120 can include, for example, two, three, or four, etc. units. Thus, the first sub-stack 120 can include two, three, or four, etc. first sacrificial layers 122a and channel layers 124, respectively. In the case where the first sub-stack 120 includes multiple such units, the units can be arranged coherently. For example, these units can be stacked on top of each other.

[0092] The second sub-stack 130 includes a plurality of sacrificial layers alternating between a first sacrificial layer 132a and a second sacrificial layer 132b. The adjacent first sacrificial layer 132a and second sacrificial layer 132b of the second sub-stack 130 are separated by a liner layer 133. Thus, it can be said that the liner layer 133 can be adjacent to each first sacrificial layer 132a and second sacrificial layer 132b separated by it.

[0093] Figure 1c The second sub-stack 130 is shown, which includes (in the bottom-up / stacking direction) the bottommost first sacrificial layer 132a, the liner layer 133, the second sacrificial layer 132b, the liner layer 133a, the first sacrificial layer 132a, the liner layer 133, the second sacrificial layer 132b, the liner layer 133, and the topmost first sacrificial layer 132a. Thus, the bottommost first sacrificial layer 132 is disposed on the first sub-stack 120, i.e., on the channel layer 124. Although Figure 1c only two second sacrificial layers 132b of the second sub-stack 130 are depicted, it should be understood that the second sub-stack 130 can include more than two second sacrificial layers 132b. It is also conceivable that the second sub-stack 130 can include one (i.e., a single) second sacrificial layer 132b.

[0094] The third sub-stack 140 includes a channel layer 144 and a first sacrificial layer 142a on the channel layer 144. The channel layer 144 forms the bottom layer (i.e., the bottommost layer) of the third sub-stack 140. Thus, the channel layer 144 is disposed on the second sub-stack 130, i.e., on the topmost first sacrificial layer 132a. The layers 144 and 142a can be referred to as a unit of the third sub-stack 140. Although Figure 1c only one such unit (i.e., a single) of the third sub-stack 140 is depicted, it should be understood that the third sub-stack 140 can include more than just a single unit. For example, the third sub-stack 140 can include, for example, two, three, or four such units. Thus, the third sub-stack 140 can include two, three, or four first sacrificial layers 142a and channel layers 144, respectively. In the case where the third sub-stack 140 includes a plurality of such units, the units can be arranged coherently. For example, the units can be stacked on top of each other.

[0095] The first sacrificial layers (122a, 132a, 142a) of the first to third sub-stacks 120, 130, 140 and the second sacrificial layer of the second sub-stack 130 can be formed to have a uniform or at least similar thickness. It is also conceivable that the second sacrificial layer can be formed to have a greater thickness than each first sacrificial layer (122a, 132a, 142a) of the first to third sub-stacks 120, 130, 140. The total thickness of the second sub-stack 130 can accordingly exceed the thickness of each first sacrificial layer of the first sub-stack 120 and the third sub-stack 140.

[0096] The channel layers 124 of the first and third sub-stacks 120, 140 may also have a uniform or at least similar thickness, such as a thickness different from or the same as that of the first sacrificial layer of the layer stack 110.

[0097] Each liner layer of the second sub-stack 130 may have a uniform or at least similar thickness.

[0098] For example, the channel layers of the first and third sub-stacks 120, 140 may each be formed to a thickness of 3 - 10 nm, the first sacrificial layers (122a, 132a, 142a) of the first to third sub-stacks 120, 130, 140 may each be formed to a thickness of 3 - 10 nm, the second sacrificial layer 132b may be formed to a thickness of 5 - 30 nm, and the liner layer 133 may be formed to a thickness of 1 - 3 nm. The total thickness of the second sub-stack 130 may be, for example, 20 - 50 nm.

[0099] Each first sacrificial layer (122a, 132a, 142a) of the first to third sub-stacks 120, 130, 140 is formed of the same first sacrificial material.

[0100] The second sacrificial layer 132b of the second sub-stack 130 is formed of a second sacrificial material different from the first sacrificial material. Each channel layer (124, 144) of the first and third sub-stacks 120, 140 is formed of the same channel material different from each of the first and second sacrificial materials. The liner layer 133 is formed of a semiconductor material different from the first and second semiconductor materials.

[0101] For example, the channel material may be Si 1-a Ge a , the liner material may be Si 1-b Ge b , the first sacrificial material may be Si 1-c Ge c , and the second sacrificial material may be Si 1-d Ge d , where 0 ≤ a ≤ b < d < c. For example, c may be in the range of 0.25 - 0.35. In a more specific example, the channel material is Si, and the first sacrificial material may be Si 0.75 Ge 0.25 , and the second sacrificial material may be Si 0.9 Ge 0.1 . This relative difference in Ge content can facilitate the selective processing (e.g., selective etching) of the different sacrificial layers and channel layers of the layer stack 110, while enabling superlattice growth with a reduced risk of relaxation and a reduced amount of defects.

[0102] The layers of the device layer stack 110 can each be epitaxial layers, for example, grown epitaxially using deposition techniques known per se, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). This enables high-quality material layers with favorable composition and dimensional control.

[0103] The deposited layers can be formed sequentially and then patterned to define an elongated fin-shaped layer stack extending in the X direction. The dashed line 110' schematically indicates the profile of the layer stack 110 after fin patterning and before fin slotting, as described below. Although the drawings depict only a single layer stack, it should be understood that multiple parallel fin-shaped layer stacks can be formed. Conventional fin patterning techniques can be used, such as single patterning techniques such as lithography and etching ("litho-etch") or multiple patterning techniques such as LELE (lithography-etching-lithography-etching) (litho-etch) x , self-aligned double or quadruple patterning (SADP or SAQP) multiple patterning techniques).

[0104] The layers of the layer stack 110 can each be formed as nanosheets, for example, with a width (along Y) to thickness (along Z) ratio greater than 1, such as a width in the range of 10 nm to 30 nm and a thickness in the range of 3 nm to 10 nm. The layer stack can also be patterned such that the channel layer forms a layer in the shape of a nanowire. For example, the nanowire can have a thickness similar to that of an exemplary nanosheet but a smaller width, such as 3 nm to 10 nm.

[0105] As Figure 1a shown in -b, after fin patterning, the lower part of the device layer stack 110 can be surrounded by a shallow trench isolation (STI) 104, such as SiO2.

[0106] As Figure 1a further shown in -b, a sacrificial gate structure 150 can be formed to extend across the layer stack 110. The sacrificial gate structure 150 includes a sacrificial gate body 152. The sacrificial gate body 152 can be formed by depositing a sacrificial gate body material (such as amorphous silicon) on the layer stack 110 and then patterning the sacrificial gate body 152 therein. Although the drawings depict only the sacrificial gate structure 150, it should be understood that multiple parallel sacrificial gate structures can be formed across the layer stack 110. Conventional patterning techniques can be used, such as single patterning techniques, such as lithography and etching ("litho-etch") or multiple patterning techniques, such as (lithography-etching) x , SADP or SAQP.

[0107] The sacrificial gate structure 150 further includes a first spacer or a first spacer layer 154 on opposite sides of the sacrificial gate body 152. The first spacer 154 may also be referred to as a gate spacer 154. The gate spacer 154 can be formed by conformally depositing a gate spacer material and then anisotropically (e.g., top-down) etching the gate spacer material to remove portions of the gate spacer material from the horizontally oriented surfaces of the structure 100, and leaving portions of the gate spacer material on the side surfaces of the sacrificial gate body 152 to form the gate spacer 154. The gate spacer 154 can be formed of a dielectric material, such as an oxide, nitride, or carbide deposited by ALD, such as SiN, SiC, SiCO, SiCN, or SiBCN.

[0108] As shown, the sacrificial gate structure 150 may further include a capping layer 156, formed, for example, from one or more remaining layers of hard mask material patterned from the sacrificial gate body.

[0109] After forming the sacrificial gate structure 150, the device layer stack 110 can be trenched by etching the device layer stack 110 in a top-down direction (e.g., negative Z), while using the sacrificial gate structure 150 as an etch mask. The etching can extend through each of the third, second, and first sub-stacks 140, 130, 120 such that portions of each of their layers remain under the sacrificial gate structure 150, as Figure 1a shown.

[0110] As Figure 1a shown, etching the device layer stack 110 forms trenches 103 in the layer stack 110. Corresponding trenches 103 can be formed in the layer stack 110 at opposite sides of the layer stack 110.

[0111] As will be apparent hereinafter, each of the first sacrificial layers (e.g., 122a, 132a, 142a) of the first through third sub-stacks 120, 130, 140 will undergo the same processing steps. Thus, for simplicity, these layers will generally be referred to hereinafter as the first sacrificial layer of the device layer stack 110, or the first sacrificial layer of the first sub-stack 120, the second sub-stack 130, or the third sub-stack 140. For corresponding reasons, the channel layers (124, 144) of the first and third sub-stacks 120, 140 can generally be represented hereinafter as the channel layer of the layer stack 110, or the channel layer of the first sub-stack 120 or the third sub-stack 140.

[0112] Figure 2a -b shows the processing steps for forming the inner spacer 162.

[0113] In Figure 2a-b, trenches 160 have been formed in the layer stack 110 by selectively etching the end faces of each of the first sacrificial layers of the layer stack 110 from opposite ends of the layer stack 100 (e.g., along the X direction and the negative X direction). The lateral etching can be achieved by an isotropic etching process. Any suitable dry etching process or wet etching process (e.g., HCl or APM) that allows selective etching of the first sacrificial material can be used. As Figure 2a shown, the degree of lateral etching can correspond to the thickness of the gate spacer 154. In other words, the depth of the trench 160 (e.g., along the X direction) can correspond to the thickness of the gate spacer 154 (along the X direction).

[0114] In Figure 3a , the trenches 160 have been filled with one or more conformally deposited inner spacer materials. Examples of inner spacer materials include conformally deposited dielectric materials such as oxides, nitrides, or carbides, such as SiN deposited by ALD. In one example, a single inner spacer material (e.g., SiN) can be deposited to fill the trenches 160. In another example, a first inner spacer material (e.g., SiOC) can be deposited to partially fill the trenches 160, where a second inner spacer material (e.g., SiN) can be deposited to fill the remaining space in the trenches 160 (by pinching off).

[0115] As further shown in Figure 3a , inner spacers 162 have been formed in the trenches 160 by subjecting the inner spacer material to an isotropic etching process to remove portions of the inner spacer material deposited outside the trenches 160. Any suitable isotropic etching process (wet or dry) for etching dielectric materials (e.g., SiN or SiN and SiOC) can be used. As shown, when the end faces of the channel layers of the layer stack 110 are exposed, the etching can stop, and discrete portions of the inner spacer material remain in the trenches 160 to form the inner spacers 162.

[0116] Figure 4a -b shows the process step of replacing the second sacrificial layer 132b of the second sub-stack 130 with a corresponding dielectric layer 136.

[0117] In Figure 4aIn [description], the second sacrificial layer 132b of the second sub-stack 130 has been removed by selectively etching the second sacrificial semiconductor material, thereby forming a cavity 135 in the second sub-stack 130. An isotropic etching process (wet or dry) can be used to etch the second sacrificial semiconductor material to etch back the end face of the second sacrificial layer 132b laterally from the opposite side of the layer stack 110. For example, HCl-based dry etching can be used to remove the second sacrificial layer material with a Ge content less than that of the first sacrificial material. However, other suitable etching processes (such as wet etching processes) are also known in the art and can also be used for this purpose.

[0118] In Figure 5a -b, the cavity 135 has been filled with a dielectric material, such as a nitride, such as SiN. The dielectric material can be conformally deposited (e.g., by ALD), and its thickness is sufficient to fill (and pinch off) the corresponding cavity 135. Examples of dielectric materials include SiO2, Si3N4, SiCO, SiOCN, SiON, SiCN, SiC, SiBCN, and SiBCNO.

[0119] The dielectric material has been subjected to an isotropic etching process to remove the portion of the dielectric material deposited outside the corresponding cavity 135. Any suitable isotropic etching process (wet or dry) for etching the dielectric material (such as SiN) can be used. The dielectric material remaining in the corresponding cavity 135 forms the corresponding dielectric layer 136.

[0120] As described above, although Figure 1c only two second sacrificial layers 132b of the second sub-stack 130 are depicted, it should be understood that the second sub-stack 130 can include more than two second sacrificial layers 132b. It is also conceivable that the second sub-stack 130 can include one (i.e., a single) second sacrificial layer 132b. Therefore, subsequent processing steps may involve forming at least one dielectric layer 136.

[0121] As Figure 1a shown, the layer stack 110 may further include a bottom second sacrificial layer 116. The bottom second sacrificial layer 116 can be disposed between the substrate 102 and the first sub-stack 120. A liner layer 133 can be disposed between the bottom second sacrificial layer 116 and the first sub-stack 120. The liner layer 133 can separate the bottom second sacrificial layer 116 from the first sub-stack 120. The liner layer 133 can be adjacent to the bottom second sacrificial layer 116 and the first sacrificial layer 122a of the first sub-stack 120.

[0122] The bottom second sacrificial layer 116 can be subjected to the same processing steps as the second sacrificial layer 132b of the second sub-stack 130.

[0123] In Figure 4aIn [description], the bottom second sacrificial layer 116 disposed between the substrate 102 and the bottom channel layer 112 is removed by etching, thereby forming a bottom cavity 117. An isotropic etching process (wet or dry) can be used to etch the bottom second sacrificial semiconductor material to etch back the end faces of the bottom second sacrificial layer 116 laterally from opposite sides of the layer stack 110. For example, a dry etching based on HCl can be used to remove the bottom second sacrificial layer material with a Ge content less than that of the first sacrificial material. However, other suitable etching processes (such as wet etching processes) are also known in the art and can also be used for this purpose.

[0124] In Figure 5a [description], the bottom cavity 117 has been filled with a dielectric material, such as a nitride, such as SiN. The dielectric material can be conformally deposited (e.g., by ALD) to a thickness sufficient to fill (and pinch off) the bottom cavity 117. Examples of dielectric materials include SiO2, Si3N4, SiCO, SiOCN, SiON, SiCN, SiC, SiBCN, and SiBCNO.

[0125] The dielectric material has been subjected to an isotropic etching process to remove the portion of the dielectric material deposited outside the bottom cavity 117. Any suitable isotropic etching process (wet or dry) for etching the dielectric material (such as SiN) can be used. The dielectric material remaining in the bottom cavity 117 forms a dielectric layer 118.

[0126] The bottom second sacrificial layer 116 can be formed of the same sacrificial material as the second sacrificial material. In other words, the bottom second sacrificial layer 116 can be formed of Si 1-d Ge d formed. In a more specific example, if the second sacrificial layer 132b is Si 0.9 Ge 0.1 , then the second sacrificial layer 116 can also be Si 0.9 Ge 0.1 .

[0127] The action of removing the bottom second sacrificial layer 116 can be performed simultaneously with the action of removing at least one second sacrificial layer 132b of the layer stack 110.

[0128] In Figure 6a -b, source and drain regions 164 and 166 have been respectively formed on the channel layers of the first sub-stack 120 and the third sub-stack 140. The source and drain regions 164, 166 have been formed by epitaxially growing semiconductor material on the end faces of the channel layers exposed at opposite sides of the sacrificial gate structure 150.

[0129] The source and drain regions 164 formed on the end face of the channel layer of the first sub-stack 120 may be of a first conductivity type, while the source and drain regions 166 formed on the end face of the channel layer of the third sub-stack 140 may be of a second opposite conductivity type. The first and second conductivity types may be p-type and n-type, or vice versa. Doping may be achieved by in-situ doping. When epitaxy is performed on the end face of the channel layer of the first sub-stack 120, different conductivity type source and drain regions 164 and source and drain regions 166 may be achieved by masking the end face of the channel layer of the third sub-stack 140. Masking of the end face of the channel layer of the third sub-stack 140 may be provided, for example, by forming a temporary covering spacer along the third sub-stack 140. After the epitaxy of the source and drain regions 164 is completed, the temporary covering spacer may be removed, and the source and drain regions 164 may be covered with one or more dielectric materials (e.g., ALD-deposited SiN and an interlayer dielectric such as SiO2). Then epitaxy may be performed on the end face of the channel layer of the third sub-stack 140. However, this is merely an example, and other process techniques facilitating the formation of source and drain regions 164, 166 of different conductivity types may also be used.

[0130] As shown, the source and drain regions 164, 166 may subsequently be covered by an insulating layer 170. The insulating layer 170 may be formed of an insulating material such as an oxide, e.g., SiO2, or another interlayer dielectric, and may be deposited, planarized, and grooved, for example, by chemical mechanical polishing (CMP) and / or etchback. CMP and / or etchback may continue to also remove any capping 156 of the sacrificial gate structure 150. However, it is also possible to stop CMP and / or etchback on the capping 156 and subsequently use a separate etching step to open the capping.

[0131] In Figure 7a -b, a gate trench 172 has been formed by removing the sacrificial gate body 152 between the opposing gate spacers 154. Any conventional suitable etching process (isotropic or anisotropic, wet or dry) allowing selective removal of the sacrificial gate body 152 (e.g., amorphous silicon) may be used.

[0132] In Figure 8a -b, the first sacrificial layer of the device layer stack 110 has been removed by selectively etching the first sacrificial semiconductor material from the gate trench 172. The same type of etching process as during the formation of the recess 160 may be used for this step. By removing the first sacrificial layer, the channel layer of the device layer stack 110 may be released in the sense that its upper and lower surfaces may be exposed within the gate trench 172. Thus, a second cavity 155 is formed. Since the dielectric layer 154 was surrounded by a first dielectric layer (e.g., the first dielectric layer 132a and the second dielectric layer 132b of the second sub-stack 130) before this process step, the dielectric layer 154 is also released.

[0133] Figure 9a -b to Figure 12a -b shows the process steps for forming a gate stack 180 in the gate trench 172 that surrounds the released channel layer and the dielectric layer 136.

[0134] In Figure 9a -b, a gate dielectric layer and a first gate work function metal (WFM) 174 have been conformally deposited in the gate trench 172. For clarity of illustration, the gate dielectric layer is not shown separately in the figure, but its coverage can correspond to where the layer 174 indicates. The gate dielectric layer can be formed of a conventional high-k dielectric, such as HfO2, HfSiO, LaO, AlO, or ZrO. The first WFM 174 can be formed of one or more effective WFMs (e.g., an n-type WFM such as TiAl or TiAlC and / or a p-type WFM such as TiN or TaN). The gate dielectric layer and the first WFM can be deposited by ALD.

[0135] As Figure 9b Further shown, a blocking mask 154 can then be formed in the lower portion of the gate trench 172. The blocking mask 154 can be formed to a certain thickness (e.g., along the Z direction) such that portions of the first WFM 174 that surround the channel layer of the first sub-stack 120 (e.g., portion 174a that surrounds the channel layer 124) are covered, while portions of the first WFM 174 that surround the channel layer 144 of the third sub-stack 140 (e.g., portion 174b that surrounds the channel layer 144) are exposed.

[0136] The blocking mask 154 can be formed by depositing a blocking mask material that fills the gate trench 172. The blocking mask material can be, for example, spin-on carbon or another organic spin-on material. Subsequently, the blocking mask material can be etched back (e.g., using anisotropic etching) from the top down to a target level. As shown, the target level can be positioned along the dielectric layer 136. Thus, portions of the first WFM 174 that surround the channel layer of the third sub-stack 140 can be exposed.

[0137] In Figure 10a -b, the first WFM 174 has been removed from the channel layer of the third sub-stack 140 while using the blocking mask 154 as an etch mask. Depending on the specific thickness of the blocking mask 154, at least a portion of the first WFM 174 that surrounds the dielectric layer 136 can also be removed. However, due to the blocking mask 154, the first WFM 174 that surrounds the channel layer of the first sub-stack 120 (e.g., portion 174a that surrounds the channel layer 124) can be retained.

[0138] The first WFM 174 can be removed using a suitable isotropic (wet or dry) etch, allowing for selective removal of the first WFM 174 without removing the gate dielectric. Subsequently, the blocking mask 154 can be removed from the trench 172.

[0139] In Figure 11a -b, a second gate WFM 176 has been conformally deposited in the gate trench 172. The second WFM 176 can be deposited on the gate dielectric surrounding the channel layer of the third sub-stack 140 and on the portions of the gate dielectric exposed on the liner 133 / dielectric layer 136. The second WFM 176 can thus surround the channel layer of the third sub-stack 140. As Figure 11a -b shows, the second gate WFM 176 can be further deposited on the first WFM 174 surrounding the channel layer of the first sub-stack 140.

[0140] The first WFM 174 can form the first gate stack. The second gate WFM 176 can be used for the second gate stack. Each of the first and second gate stacks can extend through the second cavity 155.

[0141] Subsequently, gate fill metal 178 (e.g., W, Al, Co, or Ru) can be deposited to fill the remaining space of the gate trench 172. The gate fill metal 178 can be deposited, for example, by CVD or PVD.

[0142] Reference numeral 180 denotes the complete gate stack, including a lower portion and an upper portion. The lower portion includes the gate dielectric layer, the first WFM 174, the second WFM 176, and the gate fill metal 178 surrounding the channel layer of the first sub-stack 110, and the upper portion includes the gate dielectric, the second WFM 176, and the gate fill metal 178 surrounding the channel layer of the third sub-stack 140.

[0143] Figure 12a -b depicts the resulting device structure 100 after gate metal is grooved to make the top surface of the gate stack 180 flush with the upper surface of the gate spacer 154.

[0144] The device structure 100 includes a bottom device that includes the channel layer of the first sub-stack 120, which extends between the source and drain regions 164 and the lower portion of the gate stack 180. The device structure 100 also includes a bottom device that includes the channel layer of the third sub-stack 140, which extends between the source and drain regions 166 and the upper portion of the gate stack 180. The dielectric layer 136 remains as an electrically passive dummy channel between the channels of the bottom and top devices and is surrounded by the gate stack 180.

[0145] Thereafter, the method can form source / drain contacts by etching contact trenches in the insulating layer 170 and depositing one or more contact metals in the trenches over the source and drain regions 164, 166. Separate contacts for the source and drain regions of the bottom device and the top device can be achieved by the following steps: depositing a first contact metal over the source and drain regions 164, 166, etching back the contact metal to a level between the source and drain regions 164 and 166 to expose the source and drain regions 166, depositing an insulating contact spacer layer over the etched-back contact metal, and subsequently depositing a second contact metal over the source and drain regions 166. Separate source and drain contacts can be applied to either or both sides of the device 100.

[0146] In the foregoing, the inventive concept has been described mainly with reference to a limited number of examples. However, as will be readily understood by those skilled in the art, other examples besides the ones disclosed above are equally possible within the scope of the inventive concept defined by the appended claims.

Claims

1. A method for forming a semiconductor structure (100), the method comprising: A layer stack (110) is formed on a substrate (102), the layer stack (110) comprising: a first sub-stack (120) comprising a first sacrificial layer (122a) and a channel layer (124a) on the first sacrificial layer (122a) defining a topmost layer of the first sub-stack (120); and a second substack (130) on the first substack (120) and comprising a plurality of sacrificial layers alternating between first and second sacrificial layers (132a, 132b), wherein adjacent first and second sacrificial layers (132a, 132b) of the second substack (130) are separated by a liner (133), wherein the first sacrificial layer (132a) defines respective bottom and top layers of the second substack (130), the second substack (130) comprising at least one second sacrificial layer (132b); A third sub-stack (140) on the second sub-stack (130) and comprising a channel layer (144) defining the bottommost layer of the third sub-stack (140) and a first sacrificial layer (142a) on the channel layer (144); wherein the first sacrificial layer (122a, 132a, 144a) is formed of a first sacrificial semiconductor material, the second sacrificial layer (132b) is formed of a second sacrificial semiconductor material different from the first sacrificial semiconductor material, and the liner (133) is formed of a semiconductor material different from the first sacrificial semiconductor material and the second sacrificial semiconductor material; forming a source / drain groove (103), wherein the source / drain groove exposes an end surface of the layer stack (110); forming a groove (160) in the layer stack (100) by selectively etching back the end surface of the first sacrificial layer (122a, 132a, 142a) in a lateral direction from opposite ends of the layer stack (110); forming an inner spacer (162) in the groove (160); removing the at least one second sacrificial layer (132b) of the second sub-stack (130) by etching to form at least one first cavity (135), while protecting the first sacrificial layer (132a) of the second sub-stack (130) from the etching by the inner spacer (162) and the liner (133); and The at least one first cavity (135) is filled with a dielectric material, thereby forming at least one dielectric layer (136).

2. The method according to claim 1, characterized in that The material of the channel layer is Si 1-a Ge a , the material of the liner is Si 1-b Ge b , the first sacrificial semiconductor material is Si 1-c Ge c , and the second sacrificial semiconductor material is Si 1- d Ge d , where 0≤a≤b<d<c.

3. The method according to claim 2, characterized in that c is in the range of 0.25-0.

35.

4. The method according to any one of the preceding claims, characterized in that The thickness of the liner (133) is in the range of 1 nm to 3 nm.

5. The method according to any one of the preceding claims, characterized in that Forming the groove (160) includes isotropically and selectively etching end surfaces of the first sacrificial layer (122a, 132a, 142a) from opposite ends of the layer stack (110).

6. The method according to any one of the preceding claims, characterized in that The second sub-stack (130) includes at least two second sacrificial layers (132b).

7. The method according to any one of the preceding claims, characterized in that Filling the at least one first cavity (135) with a dielectric material is performed by atomic layer deposition ALD.

8. The method according to any one of the preceding claims, characterized in that Also includes: removing the first sacrificial layer (122a, 132a, 144a) of the layer stack (110) to form a second cavity (155); forming a first gate stack extending around each channel layer of the first sub-stack (120); forming a second gate stack extending around each channel layer of the third sub-stack (140); Each of the first gate stack and the second gate stack extends through the second cavity (155).

9. The method according to any one of the preceding claims, characterized in that The layer stack (110) further comprises a bottom second sacrificial layer (116) arranged between the substrate (102) and the first sub-stack (120), and a liner (130) arranged between the bottom second sacrificial layer (116) and the first sub-stack (120), and wherein the method further comprises: removing a bottom second sacrificial layer (116) disposed between the substrate (102) and the first sub-stack (120) by etching, thereby forming a bottom cavity (117); The bottom cavity (117) is filled with a dielectric material, thereby forming a bottom dielectric layer (118).

10. The method according to claim 9, characterized in that The action of removing the bottom second sacrificial layer (116) disposed between the substrate (102) and the first sub-stack (120) and the action of removing each second sacrificial layer (132b) of the second sub-stack (130) are performed simultaneously.

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