Method for forming semiconductor structure

Abstract

The present invention provides a method for forming a semiconductor structure (100), the method comprising: forming a substrate (102; 202), forming a layer stack (110; 210), the layer stack comprising: a first sub-stack, a second sub-stack (130; 230) on the second sub-stack, a third sub-stack (140; 240), the second sub-stack comprising at least one second sub-stack in the first sacrificial layer (132a; a plurality of sacrificial layers alternating between the first sacrificial layer (132a) and the second sacrificial layer (132b); a recess (160; 160 ') is formed in the first sacrificial layer. 260) in the housing; removing the at least one second sacrificial layer; depositing a dielectric material in the at least one cavity; and depositing a dielectric material in the recess of the first sacrificial layer; wherein at least one of the action of depositing the dielectric material in the at least one cavity and the action of depositing the dielectric material in the recess of the first sacrificial layer is performed by a first chemical vapor deposition (CVD) method.

Description

Technical Field

[0001] The present disclosure relates to a method for forming a semiconductor structure. Background Art

[0002] Complementary FETs (CFETs) are currently on the scaling roadmap as one of the next-generation scaling options. A CFET includes an NFET (i.e., an N-type FET) and a PFET (i.e., a P-type FET) stacked on top of each other (or vice versa). The NFET and PFET are vertically separated by an intermediate dielectric isolation (MDI), and the bottom device can also be separated from the substrate by a bottom dielectric isolation (BDI). Summary of the Invention

[0003] An object of the present inventive concept is to provide an improved semiconductor structure and / or an improved method for manufacturing the same.

[0004] Another object is to provide a method for forming a semiconductor structure with relatively few processing steps.

[0005] Another object is to provide a stable semiconductor structure with improved electrical performance. Other objects or additional objects can be understood from the following.

[0006] According to a first aspect of the present invention, there is provided a method for forming a semiconductor structure, the method comprising:

[0007] Forming a layer stack on a substrate, the layer stack comprising:

[0008] A first sub-stack including a first sacrificial layer and a channel layer defining the topmost layer of the first sub-stack on the first sacrificial layer, and

[0009] A second sub-stack located on the first sub-stack and including a plurality of sacrificial layers alternating between a first and a second sacrificial layer, wherein adjacent first and second sacrificial layers of the second sub-stack are separated by a liner layer, wherein the first sacrificial layer defines the respective bottommost and topmost layers of the second sub-stack, and the second sub-stack includes at least one second sacrificial layer;

[0010] A third sub-stack located on the second sub-stack and including a channel layer defining the bottommost layer of the third sub-stack and a first sacrificial layer on the channel layer;

[0011] wherein the first sacrificial layer is formed of a first sacrificial semiconductor material, the second sacrificial layer is formed of a second sacrificial semiconductor material different from the first sacrificial semiconductor material, and the liner layer is formed of a semiconductor material different from the first semiconductor material and the second semiconductor material;

[0012] Forming source / drain grooves that expose end faces of the layer stack (110);

[0013] A groove is formed in the first sacrificial layer by laterally etching back the end face of the first sacrificial layer of the layer stack from opposite ends of the layer stack by selective etching;

[0014] The at least one second sacrificial layer of the second sub-stack is removed by selective etching to form at least one cavity, while protecting the first sacrificial layer of the second sub-stack from vertical etching by a liner layer; and

[0015] A dielectric material is deposited in the at least one cavity; and

[0016] A dielectric material is deposited in the groove of the first sacrificial layer;

[0017] Wherein at least one of the action of depositing a dielectric material in the at least one cavity and the action of depositing a dielectric material in the groove of the first sacrificial layer is performed by a first chemical vapor deposition (CVD) method, and the first CVD method includes:

[0018] Reacting an oxygen-containing silicon compound gas as a film-forming gas with the non-oxidizing hydrogen-containing gas in a state where at least the non-oxidizing hydrogen-containing gas is plasmaized to form a film of a flowable silanol compound; and

[0019] Subsequently, annealing the film of the flowable silanol compound into a first dielectric material,

[0020] Wherein the oxygen-containing silicon compound gas includes Si α O β (O-C m H n ) Γ C x H y , where m, n, and α are integers of 1 or greater; and where β, Γ, x, and y are integers of 0 or greater; and β and Γ are not both 0.

[0021] The phrase "the first layer disposed on the second layer" with respect to any layer of the layer stack (or a layer of a sub-stack) herein means that the first layer is disposed directly above the second layer (i.e., adjacent to the second layer).

[0022] Relative spatial terms such as "topmost", "bottom", "lower", "vertical", "stacked on top of... " are understood herein to represent a position or orientation within the reference frame of the semiconductor device. Specifically, these terms can be understood with respect to the normal direction of the substrate on which the layer stack is formed, or equivalently with respect to the bottom-up direction of the layer stack. Accordingly, terms such as "lateral" and "horizontal" should be understood as a position or orientation parallel to the substrate.

[0023] The term "thickness" shall be understood as the dimension of a structure (e.g., a layer of a sub-stack) as seen along the normal to the surface underlying the structure (e.g., a layer of a sub-stack). For example, the thickness of a layer of a layer stack or the thickness of a sub-stack may refer to the thickness dimension of the layer / sub-stack as seen along the bottom-up direction of the device layer.

[0024] The semiconductor structure can be a semiconductor structure for generating a stack of FETs including top and bottom field effect transistors (FETs). The stack of FETs can be a CFET, where the top FET is an NFET and the bottom FET is a PFET, or vice versa. Thus, the semiconductor structure can be a semiconductor structure suitable for conversion into a stack of FETs (e.g., a CFET).

[0025] Thus, the method is compatible with complementary FET (CFET) device fabrication. The method is also compatible with split-die device fabrication. The resulting semiconductor structure can be used to produce a stack of FETs.

[0026] A layer stack can sometimes be referred to as a superlattice stack.

[0027] When referring to the opposite ends of a layer stack herein, it can be understood that the opposite ends can be the ends where source / drain regions are to be formed.

[0028] The channel layer of the first sub-stack can be the channel layer for the bottom FET. Similarly, the channel layer of the third sub-stack can be the channel layer for the top FET. The channel layer can be a Si layer.

[0029] The first sacrificial layer can be a layer that can be replaced by a gate stack during the production of the FET stack.

[0030] The second sacrificial layer is a layer that is replaced by a dielectric material during the production of the FET stack. Then, the dielectric material can act as an electrical isolation between the bottom and top FETs. This electrical isolation between the bottom and top FETs can be referred to as intermediate dielectric isolation.

[0031] The liner layer can be a layer that is resistant to the etchant used for etching the second sacrificial layer. The liner layer can be a layer that is resistant to the etchant used for grooving the first sacrificial layer. The liner layer can be a thin layer, e.g., thinner than the first and second sacrificial layers.

[0032] As described above, the first and second sacrificial layers are formed of different semiconductor materials. Accordingly, an etchant can have different etch rates for the first and second sacrificial layers. Thus, the first and second sacrificial layers can be selectively etched at different points during the manufacturing process, or if they are etched simultaneously, they will be etched different amounts. The channel layer, the liner layer, the first sacrificial layer, and the second sacrificial layer can all be made of different materials. Alternatively, the channel layer and the liner layer are formed of the same material different from the first and second sacrificial semiconductor materials. Advantageously, the channel layer and the liner layer are formed of Si, while the first and second sacrificial layers are formed of SiGe, where the first and second sacrificial layers have different Ge contents.

[0033] The dielectric material deposited in at least one cavity can form a corresponding MDI layer.

[0034] The dielectric material can be a nitride, such as SiN. The dielectric material can be conformally deposited (e.g., by ALD) to a thickness sufficient to fill (and pinch off) the corresponding cavity. Examples of dielectric materials include SiO2, Si3N4, SiCO, SiOCN, SiON, SiCN, SiC, SiBCN, and SiBCNO.

[0035] The dielectric material deposited in the grooves of the first sacrificial layer can form an inner spacer.

[0036] The term "inner spacer" herein means a portion of a dielectric layer formed in a groove to cover the end face of the first sacrificial layer. Forming the inner spacer can include conformally depositing a layer of inner spacer material. Forming the inner spacer can include subsequently etching the inner spacer material layer such that discrete portions of the inner spacer material layer remain in each groove to form an inner spacer therein. Specifically, an isotropic etching process can be used to etch the spacer material. The isotropic etching process allows the inner spacer material layer to be etched at a uniform rate (at least substantially). Thus, the structures covered by the inner spacer material layer can remain substantially covered by the inner spacer material layer to be separated from the etchant until the channel layer end face is exposed, where the etching can be stopped. The inner spacer material layer can be deposited to a thickness such that the grooves are pinched off (i.e., closed).

[0037] The term "conformal deposition" herein refers to a deposition process that results in a conformally grown layer or film. Conformal deposition can be achieved using an atomic layer deposition (ALD) process.

[0038] In this context, it can be noted that any deposition step, such as forming a dielectric layer and an inner spacer, can alternatively be formed by a first CVD method. Any advantages of using the first CVD method compared to using a conventional method (such as ALD) will be apparent from the following.

[0039] A first CVD method is described in US20220235456A1, which is incorporated herein by reference. Specifically, the detailed description of US20220235456A1 is incorporated herein by reference.

[0040] The first CVD method may be referred to as ultra chemical vapor deposition (UCVD) or chemical vapor liquid deposition. In the following description, the term UCVD will be mainly used.

[0041] The UCVD method has many advantages:

[0042] The UCVD method can deposit materials mainly in cavities and / or trenches. Thus, a dielectric material can be mainly deposited in the cavities formed by removing the second sacrificial layer and / or in the grooves. The dielectric material deposited by the UCVD method can have a flat profile.

[0043] In this context, it can be noted that a flat profile generally means that the end faces of the dielectric material may have few or no rounded corners. The rounding of the end face corners is sometimes referred to as curvature. Providing a dielectric material with such a flat profile can reduce processing steps because separate steps such as pre-cleaning may not be required. Reducing the pre-cleaning step can enable a reduction in the erosion of the dielectric layer / sacrificial layer or any other layers in the layer stack that would normally be subject to erosion.

[0044] In addition, the UCVD method can provide a dielectric material compound with few voids, such as a void-free dielectric material, thereby providing a high-quality dielectric material.

[0045] The formation of the grooves in the first sacrificial layer and the removal of at least one second sacrificial layer are performed by etching. The liner layer is particularly important because it can protect the interface between the first and second sacrificial layers during the etching. Thus, the liner layer can be a layer resistant to the etchant used to etch, for example, the second sacrificial layer. The liner layer can be thin, for example, thinner than the first and second sacrificial layers. Thus, the liner layer can protect the interface between the first and second sacrificial layers while contributing little or no strain to the layer stack.

[0046] In this context, it can be noted that the liner layer can protect the interface between the first and second sacrificial layers, in the sense that it can prevent or at least reduce any erosion of the first and second sacrificial layers. Such erosion typically results in an undesired profile of the first and second sacrificial layers, such as curvature of the end faces, which in turn hinders the ability to form a high-quality dielectric layer in the layer stack. Thus, providing a liner layer can facilitate the formation of a high-quality dielectric layer, which in turn results in a semiconductor structure with improved electrical properties.

[0047] In this context, it can be further noted that the liner does not necessarily provide protection only for the first and second sacrificial layers. The liner can provide protection and thus reduce the erosion of the remaining layers of the layer stack, such as the channel layer.

[0048] Furthermore, the use of the liner in combination with the deposition carried out by the UVCD method can jointly promote a higher-quality dielectric layer.

[0049] Although the method can be advantageously used in combination with the formation of finfets and CFET devices, it is conceivable that the method can also be used to form other horizontal-channel FET devices that require internal spacers (such as nanowire FETs (NWFETs) or nanosheet FETs (NSHFETs) as described above), which can benefit from the liner.

[0050] The term "layer stack" herein refers to a structure of layers formed sequentially on top of each other. The layer stack can in particular be fin-shaped.

[0051] The act of depositing a dielectric material in at least one chamber can be performed by a first CVD method.

[0052] By depositing a dielectric material in at least one chamber by a first CVD method, the deposition of the dielectric material elsewhere can be reduced or completely avoided. Therefore, the cleaning steps can be reduced during the production process.

[0053] By depositing a dielectric material in at least one chamber by a first CVD method, an MDI with few or no curved profiles can be achieved. Therefore, the ends of the MDI can be flat.

[0054] The acts of depositing a dielectric material in at least one chamber and depositing a dielectric material in the grooves of the first sacrificial layer can be performed by a first chemical vapor deposition method.

[0055] Therefore, the cleaning steps can be further reduced during the production process. An MDI and internal spacers with few or no curved profiles can be achieved. Therefore, the ends of both the MDI and the internal spacers can be flat.

[0056] The acts of depositing a dielectric material in at least one chamber and depositing a dielectric material in the grooves of the first sacrificial layer can be performed simultaneously.

[0057] By simultaneously depositing a dielectric material in at least one chamber and in the grooves of the first sacrificial layer, the manufacturing process can be simplified.

[0058] In this context, it can be noted that the act of simultaneously depositing a dielectric material in at least one chamber and in the grooves means that the dielectric materials in at least one chamber and the grooves can be the same material.

[0059] The material of the channel layer can be Si 1-a Ge a , and the material of the liner layer can be Si 1-b Ge b , the first sacrificial semiconductor material can be Si 1-c Ge c , and the second sacrificial semiconductor material can be Si 1-d Ge d , where 0 ≤ a ≤ b < c < d.

[0060] The channel layer can be formed of Si 1-a Ge a channel material. The channel material can be Si. Thus, a can be equal to 0.

[0061] The liner layer can be formed of Si 1-b Ge b liner layer material. The layer material can be Si. Thus, b can be equal to 0.

[0062] The first sacrificial layer can be formed of Si 1-c Ge c first sacrificial material.

[0063] The second sacrificial layer can be formed of Si 1-d Ge d second sacrificial material.

[0064] The first and second sacrificial materials can be selected such that d is greater than c. In other words, the Ge content of the second sacrificial material can be greater than the Ge content of the first sacrificial material. Thus, the first sacrificial layer can be said to be formed of the first sacrificial material having a low Ge content. In other words, the layer adjacent to the channel layer can have a low Ge content. The second sacrificial layer can be said to be formed of the second sacrificial material having a high Ge content. Thus, the second sub-stack can include a plurality of sacrificial layers alternating between high and low Ge contents.

[0065] The first sacrificial semiconductor material can have a composition such that c is in the range of 0.1 - 0.25. The second sacrificial semiconductor material can have a composition such that d is in the range of 0.35 - 0.5.

[0066] As an example, the first sacrificial material can be Si 0.75 Ge 0.25 , while the second sacrificial material can be Si 0.5 Ge 0.5 . These relative differences in Ge content can facilitate the selective processing (e.g., selective etching) of the different sacrificial layers, liner layers, and channel layers of the layer stack.

[0067] The material of the liner layer can have a composition such that b is less than 0.05.

[0068] As an example, the liner material can be Si 0.98 Ge 0.02 . Thus, the Ge content of the liner can be sufficiently different from the Ge content of the sacrificial layer. These relative differences in Ge content can facilitate the selective processing (e.g., selective etching) of different sacrificial layers and channel layers of the layer stack, while having little or no erosion of the liner.

[0069] The dielectric material deposited by the first CVD method can include SiOC or SiOCN.

[0070] Such materials can provide sufficient electrical isolation between the channels of the first sub-stack and the channels of the third sub-stack.

[0071] The act of forming a groove in the first sacrificial layer of the layer stack:

[0072] can be performed before the act of removing the at least one second sacrificial layer of the second sub-stack; and

[0073] can be performed using a first selective etch that is selective to the materials of the channel layer and the liner but not selective to the first sacrificial semiconductor material and the second sacrificial semiconductor material.

[0074] Thus, the channel layer and the liner can be retained in the layer stack while the first and second sacrificial layers can be etched. The channel layer and the liner can be subject to little or no erosion.

[0075] The act of removing the at least one second sacrificial layer of the second sub-stack is performed using a second selective etch that is selective to the materials of the channel layer, the liner, and the first sacrificial semiconductor material but not selective to the second sacrificial semiconductor material.

[0076] Thus, the channel layer, the liner, and the first sacrificial layer can be retained in the layer stack while the second sacrificial layer can be etched. The channel layer, the liner, and the first sacrificial layer can be subject to little or no erosion.

[0077] The thickness of the liner can be in the range of 1 nm to 5 nm.

[0078] As an example, the thickness of the liner can be 1 nm, 2 nm, 3 nm, 4 nm, or 5 nm. As another example, the thickness of the liner can be less than 2 nm, 3 nm, 4 nm, or less than 5 nm. This thickness of the liner provides sufficient protection to the first sacrificial layer of the second sub-stack during the removal of the second sacrificial layer while providing a thin semiconductor structure. This enables further scaling of the device. In addition, the reduced growth thickness of the liner can enable a reduction in the amount of growth defects in the layer stack. The liner can be thin enough to prevent parasitic source and drain epitaxial growth.

[0079] In addition, such a liner thickness can prevent atoms from diffusing throughout the layer stack during processing steps such as annealing, while still enabling a relatively thin semiconductor structure to be achieved.

[0080] The recess may include isotropically selectively etching the end faces of the first sacrificial layer from opposite ends of the layer stack.

[0081] Due to the liner, even when the end faces of the first sacrificial layer are isotropically etched, rounding of the corners of the first sacrificial layer can be avoided. In other words, using the liner enables isotropic selective etching while avoiding rounding of the corners of the first sacrificial layer. The isotropic etching of the end faces allows for the controlled formation of the recess. This thus facilitates subsequent processing steps, such as the action of depositing a dielectric material in the cavity / recess.

[0082] The method may further include:

[0083] forming a sacrificial gate structure extending across the layer stack, the sacrificial gate structure including a sacrificial gate body and first spacers on opposite sides of the sacrificial gate body;

[0084] wherein the source / drain recesses are formed as follows:

[0085] etching through the device layer stack while using the sacrificial gate structure as an etch mask such that portions of the first, second, and third sub-stacks of the device layer stack are retained under the sacrificial gate structure.

[0086] Thus, the method can provide for the efficient fabrication of semiconductor structures.

[0087] The method may further include:

[0088] forming source and drain regions by epitaxially growing semiconductor material on the end faces of the channel layer exposed in the source / drain recesses. Description of the Drawings

[0089] The above and other objects, features, and advantages of the inventive concept will be better understood from the following detailed description, which is illustrative and non-limiting, with reference to the accompanying drawings. Unless otherwise noted, the same reference numerals will be used for the same elements in the drawings.

[0090] Figures 1 to 27 Schematic cross-sectional views illustrate semiconductor structure formation steps of a method applied to a semiconductor device according to some embodiments.

[0091] Figures 28 to 39 Schematic cross-sectional views illustrate semiconductor structure formation steps of a method applied to a semiconductor device according to some embodiments. Detailed Description

[0092] Figures 1 to 13 Shows an implementation of the method according to the present invention. This implementation may be referred to as Implementation A. Figures 1-2 Depicts a layer stack 110 at an initial stage of a method for forming a final semiconductor structure 100. Figures 1 to 13 Shows the formation of the semiconductor structure 100, where the finished semiconductor structure 100 is as Figures 12-13 shown. Figures 14-15 to Figures 26-27 Shows the formation of a FET stack 1000 starting from the semiconductor structure 100. The FET stack 1000 can be a CFET device.

[0093] The axes X, Y, and Z represent a first direction, a second direction transverse to the first direction, and a vertical or bottom-up direction, respectively. Specifically, the X and Y directions can be referred to as lateral or horizontal directions because they are parallel to the main plane of the substrate 102 of the structure 100. The Z direction is parallel to the normal direction of the substrate 102.

[0094] Figures 1-2 Depicts corresponding cross-sectional views of the layer stack 110 taken along a vertical plane B-B' (parallel to the XZ plane) and A-A' (parallel to the YZ plane). Unless otherwise specified, the cross-sectional views of subsequent figures correspond to Figures 1-2 the cross-sectional views in.

[0095] The layer stack 110 is disposed on a substrate 102. The substrate 102 can be a conventional semiconductor substrate suitable for complementary FETs. The substrate 102 can be a single-layer semiconductor substrate, for example, formed from a bulk substrate such as a Si substrate, a germanium (Ge) substrate, or a silicon-germanium (SiGe) substrate. However, multi-layer / composite substrates are also possible, such as a semiconductor layer epitaxially grown on a bulk substrate or a semiconductor-on-insulator (SOI) substrate, such as a Si-on-insulator substrate, a Ge-on-insulator substrate, or a SiGe-on-insulator substrate.

[0096] The device layer stack 110 includes a first sub-stack 120, a second sub-stack 130 on the first sub-stack 120, and a third sub-stack 140 on the second sub-stack 130.

[0097] For clarity of illustration, Figure 5 the first sub-stack 120 (bottom), the second sub-stack 130 (middle), and the third sub-stack 140 (top) are depicted separately.

[0098] The first sub-stack 120 includes a first sacrificial layer 122a and a channel layer 124 on the first sacrificial layer 122a. The channel layer 124 forms the top (i.e., the topmost) layer of the first sub-stack 120. The layers 122a and 124 can be referred to as a unit of the first sub-stack 120. AlthoughFigure 5 Only one such unit (i.e., single) of the first sub-stack 120 is depicted, but it should be understood that the first sub-stack 120 may include more than just a single unit. For example, the first sub-stack 120 may include, for example, two, three, or four such units. Thus, the first sub-stack 120 may include two, three, or four such first sacrificial layers 122a and channel layers 124, respectively. In the case where the first sub-stack 120 includes multiple such units, the units may be arranged coherently. For example, these units may be stacked on top of each other.

[0099] The second sub-stack 130 includes a plurality of sacrificial layers that alternate between a first sacrificial layer 132a and a second sacrificial layer 132b. Adjacent first sacrificial layer 132a and second sacrificial layer 132b of the second sub-stack 130 are separated by a liner layer 133. Thus, it can be said that the liner layer 133 may be adjacent to each first sacrificial layer 132a and second sacrificial layer 132b that it separates.

[0100] Figure 5 The second sub-stack 130 is shown, which includes (in the bottom-to-top direction) the bottommost first sacrificial layer 132a, a liner layer 133, a second sacrificial layer 132b, a liner layer 133a, a first sacrificial layer 132a, a liner layer 133, a second sacrificial layer 132b, a liner layer 133, and the topmost first sacrificial layer 132a. Thus, the bottommost first sacrificial layer 132 is disposed on the first sub-stack 120, i.e., on the topmost channel layer 124. Although Figure 5 Only two second sacrificial layers 132b of the second sub-stack 130 are depicted, but it should be understood that the second sub-stack 130 may include more than two second sacrificial layers 132b. It is also conceivable that the second sub-stack 130 may include one (i.e., single) second sacrificial layer 132b.

[0101] The third sub-stack 140 includes a channel layer 144 and a first sacrificial layer 142a on the channel layer 144. The channel layer 144 forms the bottom layer (i.e., the bottommost layer) of the third sub-stack 140. Thus, the channel layer 144 is disposed on the second sub-stack 130, i.e., on the topmost first sacrificial layer 132a. Layers 144 and 142a may be referred to as a unit of the third sub-stack 140. Although Figure 5 Only one such unit (i.e., single) of the third sub-stack 140 is depicted, but it should be understood that the third sub-stack 140 may include more than just a single unit. For example, the third sub-stack 140 may include, for example, two, three, or four such units. Thus, the third sub-stack 140 may include two, three, or four such first sacrificial layers 142a and channel layers 144, respectively. In the case where the third sub-stack 140 includes multiple such units, the units may be arranged coherently. For example, these units may be stacked on top of each other.

[0102] The first sacrificial layers (122a, 132a, 142a) of the first to third sub-stacks 120, 130, 140 and the second sacrificial layers of the first to third sub-stacks 120, 130, 140 may be formed to have a uniform or at least similar thickness. It is also conceivable that the second sacrificial layer may be formed to have a greater thickness than each of the first sacrificial layers of the first to third sub-stacks 120, 130, 140 (122a, 132a, 142a). The total thickness of the second sub-stack 130 may accordingly exceed the thickness of each of the first sacrificial layers of the first sub-stack 120 and the third sub-stack 140.

[0103] The channel layers 124 of the first and third sub-stacks 120, 140 may also have a uniform or at least similar thickness, such as a thickness different from or the same as that of the first sacrificial layer of the layer stack 110.

[0104] Each liner layer of the second sub-stack 130 may have a uniform or at least similar thickness.

[0105] For example, the channel layers of the first and third sub-stacks 120, 140 may each be formed to have a thickness of 3 - 10 nm, the first sacrificial layers (122a, 132a, 142a) of the first to third sub-stacks 120, 130, 140 may each be formed to have a thickness of 3 - 10 nm, the second sacrificial layer 132b may be formed to have a thickness of 5 - 30 nm, and the liner layer 133 may be formed to have a thickness of 1 - 5 nm. The liner layer 133 is preferably 2 - 3 nm. The total thickness of the second sub-stack 130 may be, for example, 20 - 50 nm.

[0106] Each of the first sacrificial layers (122a, 132a, 142a) of the first to third sub-stacks 120, 130, 140 is formed of the same first sacrificial material.

[0107] The second sacrificial layer 132b of the second sub-stack 130 is formed of a second sacrificial material different from the first sacrificial material. Each of the channel layers (124, 144) of the first and third sub-stacks 120, 140 is formed of the same channel material different from each of the first and second sacrificial materials. The liner layer 133 is formed of a semiconductor material different from the first and second semiconductor materials.

[0108] For example, the channel layer material may be Si 1-a Ge a , the liner layer material may be Si 1-b Ge b , the first sacrificial material may be Si 1-c Ge c , and the second sacrificial material may be Si 1-d Ge d, where 0 ≤ a ≤ b < c < d. For example, c can be in the range of 0.1 - 0.25. Additionally, d can be in the range of 0.35 - 0.5. In a more specific example, the channel material can be Si (i.e., a = 0), the liner material can be Si (i.e., b = 0), the first sacrificial material can be Si 0.75 Ge 0.25 , and the second sacrificial material can be Si 0.5 Ge 0.5 . These relative differences in Ge content facilitate selective processing (e.g., selective etching) of the different sacrificial layers, liner layer 133, and channel layer of the device layer stack 110.

[0109] Each layer of the device layer stack 110 can be an epitaxial layer, for example, grown epitaxially using deposition techniques known per se such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). This enables high-quality material layers with favorable composition and dimensional control.

[0110] The deposited layers can be formed sequentially and then patterned to define an elongated fin-shaped layer stack extending in the X direction. The dashed line 110’ schematically indicates the profile of the layer stack 110 after fin patterning and before fin slotting, as described below. Although the drawings depict only a single layer stack, it should be understood that multiple parallel fin-shaped layer stacks can be formed. Conventional fin patterning techniques can be used, such as single patterning techniques such as lithography and etching (“litho-etch”) or multiple patterning techniques such as (litho-etch) x , self-aligned double or quadruple patterning (SADP or SAQP)).

[0111] Each layer of the layer stack 110 can be formed as a nanosheet, for example, with a width (along Y) to thickness (along Z) ratio greater than 1, for example, the width is in the range of 10 nm to 30 nm and the thickness is in the range of 3 nm to 10 nm. The layer stack can also be patterned such that the channel layer forms a nanowire-shaped layer. For example, the nanowire can have a thickness similar to that of an example nanosheet but a smaller width, such as 3 nm to 10 nm.

[0112] As Figures 3-4 shown, after fin patterning, the lower part of the device layer stack 110 can be surrounded by shallow trench isolation (STI) 104 such as SiO2.

[0113] As Figures 1-2Further shown, the sacrificial gate structure 150 can be formed to extend across the layer stack 110. The sacrificial gate structure 150 includes a sacrificial gate body 152 (and gate spacers 154, discussed later). The sacrificial gate body 152 can be formed by depositing sacrificial gate body material (such as amorphous silicon) on the layer stack 110 and then patterning the sacrificial gate body 152 therein. Although the drawings depict only the sacrificial gate structure 150, it should be understood that multiple parallel sacrificial gate structures can be formed across the layer stack 110. Conventional patterning techniques can be used, such as single patterning techniques, such as lithography and etching ("litho-etch") or multiple patterning techniques, such as (lithography-etch) x , SADP or SAQP.

[0114] The sacrificial gate structure 150 is further conformally coated with gate spacer material 154a. The gate spacer material 154 can be a dielectric material, such as an oxide, nitride, or carbide deposited by ALD, such as SiN, SiC, SiCO, SiCN, SiOCN, SiON, or SiBCN.

[0115] As shown, the sacrificial gate structure 150 can also include a capping layer 156, such as formed from one or more remaining layers of hard mask material patterned from the sacrificial gate body.

[0116] Figures 3-4 Illustrates the formation of the source / drain trenches 103.

[0117] After forming the sacrificial gate structure 150, the device layer stack 110 can be trenched by etching the device layer stack 110 in a top-down direction (e.g., negative Z), while using the sacrificial gate structure 150 as an etch mask, such that portions of each of the third, second, and first sub-stacks 140, 130, 120 are retained under the sacrificial gate structure 150, as Figure 3 shown. As Figures 3-4 shown, etching the device layer stack 110 forms trenches 103 in the layer stack 110. Corresponding trenches 103 can be formed in the layer stack 110 at opposite sides of the layer stack 110. The trenches 103 can extend into the substrate 103.

[0118] After forming the source / drain trenches 103, the portions of the gate spacer material 154a remaining on the end faces of the sacrificial gate body 152 define a first spacer or first spacer layer 154 on opposite sides of the sacrificial gate body 152. The first spacer 154 can also be referred to as the gate spacer 154.

[0119] As can be clearly seen from the following, each of the first sacrificial layers (e.g., 122a, 132a, 142a) of the first to third sub-stacks 120, 130, 140 will undergo the same processing steps. Therefore, for the sake of brevity, these layers will generally be referred to hereinafter as the first sacrificial layer of the device layer stack 110, or the first sacrificial layer of the first sub-stack 120, the second sub-stack 130, or the third sub-stack 140. For corresponding reasons, the channel layers (124, 144) of the first and third sub-stacks 120, 140 can generally be represented hereinafter as the channel layers of the layer stack 110, or the channel layers of the first sub-stack 120 or the third sub-stack 140.

[0120] Figures 6-7 The formation of the groove 160 in the first sacrificial layer of the layer stack is shown. The formation of the groove 160 can be formed after the formation of the source / drain groove 103.

[0121] In Figures 6-7 , the groove 160 has been formed in the layer stack 110 by selectively etching the end faces of each of the first sacrificial layers of the layer stack 110 from the opposite ends of the layer stack 100 (e.g., along the X direction and the negative X direction). The lateral etching can be achieved by an isotropic etching process. Any suitable dry etching process or wet etching process (e.g., HCl or APM) that allows selective etching of the first sacrificial material can be used. As Figure 6 shown, the degree of lateral etching can correspond to the thickness of the gate spacer 154. In other words, the depth of the groove 160 (e.g., along the X direction) can correspond to the thickness of the gate spacer 154 (along the X direction).

[0122] The action of forming the groove 160 in the first sacrificial layers 122a, 132a, 142a can also be accompanied by the action of forming the groove 161 in the second sacrificial layer 132b. The formation of the groove 160 in the first sacrificial layers 122a, 132a, 142a can be performed simultaneously with the action of forming the groove 161 in the second sacrificial layer 132b. Alternatively, it can be envisaged that the groove 161 can be formed first in the second sacrificial layer 132b. Subsequently, the groove 160 can be formed in the first sacrificial layer.

[0123] As Figure 6As shown, the degree of lateral etching of the second sacrificial layer 132b can correspond to a thickness greater than the thickness of the gate spacer 154. In other words, the depth of the groove 160 (e.g., along the X direction) can be greater than the thicknesses of the gate spacer 154 and the groove 160 (along the X direction). The first and second sacrificial layers can have different Ge contents and can thus be removed at different rates depending on the etchant used. An etchant with a higher etching rate for materials with a relatively high Ge content can be used. Thus, it can mean that the material of the second sacrificial layer 132b has a higher Ge content.

[0124] As Figure 6 As further shown, the liner 133 can prevent the rounding of the corners of the first sacrificial layer 132a of the second sub-stack 130. Even though the second sacrificial layer 132b of the second sub-stack 130 can be etched faster than the first sacrificial layer 132a of the second sub-stack 130, due to the presence of the protective liner 133, the etchant cannot attack the first sacrificial layer 132a through the groove 161 in the second sacrificial film 132b. Thus, the first sacrificial layer 132a of the second sub-stack 130 can be attacked laterally only via the groove 160 of the second sub-stack 130.

[0125] Figures 8-9 The removal of the second sacrificial layer of the second sub-stack is shown.

[0126] In Figure 8 it, the second sacrificial layer 132b of the second sub-stack 130 has been removed by selectively etching the second sacrificial semiconductor material, thereby forming a cavity 135 in the second sub-stack 130. The removal of the second sacrificial layer can be performed before depositing a dielectric material into any cavity or groove. An isotropic etching process (wet or dry) can be used to etch the second sacrificial semiconductor material to laterally etch the end face of the second sacrificial layer 132b from the opposite side of the layer stack 110. For example, HCl-based dry etching can be used to remove the second sacrificial layer material with a Ge content less than that of the first sacrificial material. However, other suitable etching processes (e.g., wet etching processes) are also known in the art and can also be used for this purpose.

[0127] Figures 10-11 The deposition of the dielectric material in both the cavity 135 and the groove 160 is shown.

[0128] In Figures 10-11 it, the cavity 135 and the groove 160 have been filled with a dielectric material, for example, such as SiOC or SiOCN. Thus, the dielectric materials in the cavity 135 and the groove 160 can be the same. Here, the dielectric material is deposited simultaneously in both the cavity 135 and the groove 160 by UCVD. Examples of the dielectric material include SiOC or SiOCN.

[0129] As shown Figure 10 in Figure 10 , the dielectric material deposited by UCVD can preferentially fill the cavity 135 and the groove 160, and only leave a thin film of dielectric material or no dielectric material on the end face of the layer stack. Therefore, after depositing the dielectric material, the end face of the layer stack can be flat. If another deposition method is used, the end face of the layer stack may not be flat. If another deposition method is used, the surface of the dielectric material may be uneven, with protrusions on the end faces of the channel layer and the liner layer, and / or indentations in the regions of the filled cavity 135 and groove 160.

[0130] The first CVD method may include:

[0131] reacting an oxygen-containing silicon compound gas as a film-forming gas with the non-oxidizing hydrogen-containing gas in a state where at least the non-oxidizing hydrogen-containing gas is plasmaized to form a film of a flowable silanol compound; and

[0132] subsequently annealing the film of the flowable silanol compound into a first dielectric material,

[0133] wherein the oxygen-containing silicon compound gas includes Si α O β (O-C m H n ) Γ C x H y , where m, n, and α are integers of 1 or greater; and where β, Γ, x, and y are integers of 0 or greater; and β and Γ are not both 0.

[0134] The first CVD method may be referred to as ultra chemical vapor deposition (UCVD) or chemical vapor liquid deposition. In the following description, the term UCVD will be mainly used. When filling the cavity 135 and the groove 160 with a dielectric material, the UCVD method may be superior to ALD and other conventional methods. The advantages of using the UCVD method compared with conventional methods such as ALD have been discussed and will not be further elaborated for the sake of brevity.

[0135] The dielectric material has been subjected to an isotropic etching process to remove the portions of the dielectric material deposited outside the corresponding cavity 135. Any suitable isotropic etching process (wet or dry) for etching the dielectric material (such as SiOC or SiOCN) can be used. The dielectric material remaining in the corresponding groove 160 forms the corresponding dielectric layer inner spacer 162. The dielectric material remaining in the corresponding cavity 135 forms the corresponding dielectric layer 136.

[0136] As described above, although Figure 5Only two second sacrificial layers 132b of the second sub-stack 130 are depicted, but it should be understood that the second sub-stack 130 may include more than two second sacrificial layers 132b. It is also contemplated that the second sub-stack 130 may include one (i.e., a single) second sacrificial layer 132b. Thus, subsequent processing steps may involve forming at least one dielectric layer 136.

[0137] Figures 10-11 An exposed end face of the channel layer is shown.

[0138] As Figure 12 Further shown, by subjecting the dielectric material to an isotropic etching process to remove portions of the dielectric material deposited outside the grooves 160 and the cavity 135, inner spacers 162 and dielectric layers 136 are formed in the grooves 160 and the cavity 135, respectively. Any suitable isotropic etching process (wet or dry) for etching the dielectric material (such as SiOC or SiOCN) may be used. As shown, when the end faces of the channel layers of the layer stack 110 are exposed, the etching may stop, and discrete portions of the dielectric material remain in the grooves 160 and the cavity 135 to form the inner spacers 162 and the dielectric layers 136, respectively.

[0139] As Figure 3 Shown, the layer stack 110 may further include a bottom second sacrificial layer 116. The bottom second sacrificial layer 116 may be disposed between the substrate 102 and the first sub-stack 120. A liner layer 133 may be disposed between the bottom second sacrificial layer 116 and the first sub-stack 120. The liner layer 133 may separate the bottom second sacrificial layer 116 from the first sub-stack 120. The liner layer 133 may be adjacent to the bottom second sacrificial layer 116 and the first sacrificial layer 122a of the first sub-stack 120.

[0140] The bottom second sacrificial layer 116 may undergo the same processing steps as the second sacrificial layers 132b of the second sub-stack 130 (and the first sacrificial layers of the sub-stacks 120, 130, 140). Thus, for the sake of brevity, the processing steps will not be elaborated in detail.

[0141] In Figures 6 to 8 -9, the bottom second sacrificial layer 116 disposed between the substrate 102 and the bottom channel layer 112 is removed by etching, thereby forming a groove 113 and subsequently forming a bottom cavity 117.

[0142] In Figure 10 the bottom cavity 117 has been filled with a dielectric material. This dielectric material may be the same dielectric material that fills the grooves 160 and the cavity 135.

[0143] The dielectric material has been subjected to an isotropic etching process to remove portions of the dielectric material deposited outside the bottom cavity 117. Any suitable isotropic etching process (wet or dry) for etching the dielectric material (such as SiN) can be used. The dielectric material remaining in the bottom cavity 117 forms the dielectric layer 118.

[0144] In Figures 14-15 it, source and drain regions 164 and 166 have been formed on the channel layers of the first sub-stack 120 and the third sub-stack 140, respectively. The source and drain regions 164, 166 have been formed by epitaxially growing semiconductor material on the end faces of the channel layers exposed at opposite sides of the sacrificial gate structure 150. The source and drain regions 164, 166 can be formed by epitaxially growing semiconductor material on the end faces of the channel layers exposed in the source / drain recesses 103.

[0145] The source and drain regions 164 formed on the end face of the channel layer of the first sub-stack 120 can be of a first conductivity type, while the source and drain regions 166 formed on the end face of the channel layer of the third sub-stack 140 can be of a second opposite conductivity type. The first and second conductivity types can be p-type and n-type, or vice versa. Doping can be achieved by in-situ doping. When epitaxy is performed on the end face of the channel layer of the first sub-stack 120, the source and drain regions 164 of different conductivity types and the source and drain regions 166 can be achieved by masking the end face of the channel layer of the third sub-stack 140. Masking of the end face of the channel layer of the third sub-stack 140 can be provided, for example, by forming a temporary covering spacer along the third sub-stack 140. After the epitaxy of the source and drain regions 164 is completed, the temporary covering spacer can be removed, and the source and drain regions 164 can be covered with one or more dielectric materials (such as ALD-deposited SiN and an interlayer dielectric such as SiO2). Then epitaxy can be performed on the end face of the channel layer of the third sub-stack 140. However, this is merely an example, and other process techniques facilitating the formation of source and drain regions 164, 166 of different conductivity types can also be used.

[0146] As shown, the source and drain regions 164, 166 can subsequently be embedded in the insulating layer 170 or covered by the insulating layer 170. The insulating layer 170 can be formed of an insulating material such as an oxide, for example SiO2, or another interlayer dielectric, for example deposited, planarized, and grooved by chemical mechanical polishing (CMP) and / or etchback. CMP and / or etchback can continue to also remove any capping 156 of the sacrificial gate structure 150. However, it is also possible to stop CMP and / or etchback on the capping 156 and subsequently use a separate etching step to open the capping.

[0147] In Figures 16-17Therein, the gate trench 172 has been formed by removing the sacrificial gate body 152 between the opposing gate spacers 154. Any conventional suitable etching process (isotropic or anisotropic, wet or dry) that allows for the selective removal of the sacrificial gate body 152 (e.g., amorphous silicon) can be used.

[0148] In Figures 18-19 therein, the first sacrificial layer of the device layer stack 110 has been removed by selectively etching the first sacrificial semiconductor material from the gate trench 172. The same type of etching process as during the formation of the recess 160 can be used for this step. By removing the first sacrificial layer, the channel layer of the device layer stack 110 can be released in the sense that its upper and lower surfaces can be exposed within the gate trench 172. Thus, the second cavity 155 is formed. Since the dielectric layer 154 was surrounded by a first dielectric layer (e.g., the first dielectric layers 132a and 132b of the second sub-stack 130) prior to this process step, the dielectric layer 154 is also released.

[0149] Figures 20-21 To Figures 26-27 illustrates process steps for forming a gate stack 180 in the gate trench 172 that surrounds the released channel layer and the dielectric layer 136.

[0150] In Figures 20-21 therein, a gate dielectric layer and a first gate work function metal (WFM) 174 have been conformally deposited in the gate trench 172. For clarity of illustration, the gate dielectric layer is not shown separately in the figure, but its coverage can correspond to where the layer 174 indicates. The gate dielectric layer can be formed from a conventional high-k dielectric, such as HfO2, HfSiO, LaO, AlO, or ZrO. The first WFM 174 can be formed from one or more effective WFMs (e.g., an n-type WFM such as TiAl or TiAlC and / or a p-type WFM such as TiN or TaN). The gate dielectric layer and the first WFM can be deposited by ALD.

[0151] As Figure 21 further shown, a blocking mask 154 can then be formed in the lower portion of the gate trench 172. The blocking mask 154 can be formed to a certain thickness (e.g., along the Z direction) such that portions of the first WFM 174 that surround the channel layer of the first sub-stack 120 (e.g., portion 174a that surrounds the channel layer 124) are covered, while portions of the first WFM 174 that surround the channel layer 144 of the third sub-stack 140 (e.g., portion 174b that surrounds the channel layer 144) are exposed.

[0152] The blocking mask 154 can be formed by depositing a blocking mask material that fills the gate trench 172. The blocking mask material can be, for example, spin-on carbon or another organic spin-on material. Subsequently, the blocking mask material can be etched back (e.g., using anisotropic etching) from top to bottom to a target level. As shown, the target level can be positioned along the dielectric layer 136. Accordingly, portions of the first WFM 174 that surround the channel layer of the third sub-stack 140 can be exposed.

[0153] In Figures 22-23 , the first WFM 174 has been removed from the channel layer of the third sub-stack 140 while using the blocking mask 154 as an etch mask. Depending on the specific thickness of the blocking mask 154, at least a portion of the first WFM 174 that surrounds the dielectric layer 136 may also be removed. However, due to the blocking mask 154, the first WFM 174 that surrounds the channel layer of the first sub-stack 120 (e.g., portion 174a that surrounds the channel layer 124) can be retained.

[0154] The first WFM 174 can be removed using a suitable isotropic (wet or dry) etch, allowing for the selective removal of the first WFM 174 without removing the gate dielectric. Subsequently, the blocking mask 154 can be removed from the trench 172.

[0155] In Figures 24-25 , the second gate WFM 176 has been conformally deposited in the gate trench 172. The second WFM 176 can be deposited on the gate dielectric that surrounds the channel layer of the third sub-stack 140 and on the portion of the gate dielectric that is exposed on the dielectric layer 136. The second WFM 176 can thus surround the channel layer of the third sub-stack 140. As Figures 24-25 shown, the second gate WFM 176 can be further deposited on the first WFM 174 that surrounds the channel layer of the first sub-stack 140.

[0156] The first WFM 174 can form the first gate stack. The second gate WFM 176 can be used for the second gate stack. Each of the first and second gate stacks can extend through the second cavity 155.

[0157] Subsequently, a gate fill metal 178 (such as W) can be deposited to fill the remaining space in the gate trench 172. The gate fill metal 178 can be deposited, for example, by CVD or PVD.

[0158] Reference numeral 180 denotes a complete gate stack, including a lower part and an upper part. The lower part includes a gate dielectric layer, a first WFM 174, a second WFM 176, and a gate fill metal 178 that surrounds the channel layer of the first sub-stack 110, while the upper part includes a gate dielectric, a second WFM 176, and a gate fill metal 178 that surrounds the channel layer of the third sub-stack 140.

[0159] Figures 26-27 Depicted is the resulting device structure 1000 after the gate metal is grooved to make the top surface of the gate stack 180 flush with the upper surface of the gate spacer 154.

[0160] The device structure 1000 includes a bottom device that includes the channel layer of the first sub-stack 120, which extends between the source and drain regions 164 and the lower part of the gate stack 180. The device structure 1000 also includes a bottom device that includes the channel layer of the third sub-stack 140, which extends between the source and drain regions 166 and the upper part of the gate stack 180. The dielectric layer 136 remains as an electrically passive dummy channel between the channels of the bottom device and the top device and is surrounded by the gate stack 180.

[0161] Thereafter, the method can form source / drain contacts by etching contact trenches in the insulating layer 170 and depositing one or more contact metals in the trenches on the source and drain regions 164, 166. Separate contacts for the source and drain regions of the bottom device and the top device can be achieved by the following steps: depositing a first contact metal on the source and drain regions 164, 166, etching the contact metal back to a level between the source and drain regions 164 and 166 to expose the source and drain regions 166, depositing an insulating contact separation layer on the etched contact metal, and subsequently depositing a second contact metal on the source and drain regions 166. The separate source and drain contacts can be applied to one or both sides of the device 1000.

[0162] Alternative implementations of the method are also possible. For example, a cavity can be formed and a dielectric material can be deposited in the cavity before source / drain grooving.

[0163] For example, a cavity can be formed and a dielectric material can be deposited in the cavity before source / drain grooving, and the dielectric material deposited in the cavity is deposited by a method other than the first CVD method. This can be referred to as Implementation B.

[0164] As another example, a cavity can be formed and a dielectric material can be deposited in the cavity before source / drain grooving, and the dielectric material deposited in the cavity is deposited by the first CVD method. This can be referred to as Implementation C.

[0165] Figures 28 to 37 Implementation B is illustrated.

[0166] Figure 28 Depicts layer stack 210 in the initial stage of a method for forming a final semiconductor structure 200. Figures 28 to 37 Illustrates the formation of semiconductor structure 200, where the finished semiconductor structure 200 is as Figures 38-39 shown.

[0167] Layer stack 210 is similar to layer stack 110, but is shown before being coated with gate spacer material 254a. As Figure 29 shown, the second sacrificial layer 232b can then be removed to form cavity 235.

[0168] Subsequently, a dielectric material can be deposited in cavity 235 to form dielectric layer 236. The dielectric layer 236 can be deposited by a method other than the first CVD method. For example, as Figure 30 shown, the dielectric layer 236 can be the same material as the gate spacer material 254a and can be deposited simultaneously with the gate spacer material 254a. The dielectric layer 236 can be deposited by ALD, such as plasma-enhanced ALD (PEALD). The dielectric layer 236 can include Si3N4.

[0169] As seen in Figure 33 the first sub-stack 220 includes a first sacrificial layer 222a and a channel layer 224 on the first sacrificial layer 222a. The channel layer 224 forms the top (i.e., the uppermost) layer of the first sub-stack 220.

[0170] The second sub-stack 230 includes, after fin patterning, a plurality of sacrificial layers and dielectric layers alternating between a first sacrificial layer 232a and a dielectric layer 236. The adjacent first sacrificial layer 232a and second sacrificial layer 233b of the second sub-stack 230 are separated by a liner layer 233. The liner layer 233 can abut each of the first sacrificial layer 232a and second sacrificial layer 232b it separates. Thus, the bottommost first sacrificial layer 232a is disposed on the first sub-stack 220, i.e., on the topmost channel layer 224.

[0171] The third sub-stack 240 includes a channel layer 244 and a first sacrificial layer 242a on the channel layer 244. The channel layer 244 forms the bottom (i.e., the lowermost) layer of the third sub-stack 240. Thus, the channel layer 244 is disposed on the second sub-stack 230, i.e., on the topmost first sacrificial layer 232a.

[0172] Figures 31-32 Illustrates the formation of source / drain recesses 203. This can be carried out similarly to the description in connection with Figures 3-4 the description.

[0173] Figures 34-35Shows the formation of the groove 260 in the first sacrificial layer of the layer stack 210. This can be carried out similarly to the description in conjunction with Figures 6-7 , except that the second sacrificial layer is not grooved. The reason is that the second sacrificial layer has been replaced by a dielectric material.

[0174] Figures 36-37 Shows the deposition of the dielectric material in the groove 260 in the first sacrificial layer. This can be carried out similarly to the description in conjunction with Figures 10-11 , i.e., using the first CVD method. The exception is that the dielectric material is not deposited in the cavities 235 because these cavities have already been filled.

[0175] Figures 38-39 Shows the exposed end face of the channel layer. This can be carried out similarly to the description in conjunction with Figures 12-13 .

[0176] The remaining processing of S / D, gate trenches, and gate formation is similar to that described in conjunction with Figures 16-27 .

[0177] Regarding implementation C, where cavities can be formed before source / drain grooving and a dielectric material can be deposited in the cavities, and the dielectric material deposited in the cavities is deposited by the first CVD method: In this implementation, the two actions of depositing the dielectric material in the cavities and depositing the dielectric material in the grooves of the first sacrificial layer are performed by the first CVD method but at different time points. The dielectric material deposited in the grooves of the first sacrificial layer can be the same as or different from the dielectric material deposited in the cavities.

[0178] Above, the inventive concept has been described mainly with reference to a limited number of examples. However, as will be readily understood by those skilled in the art, within the scope of the inventive concept defined by the appended claims, other examples besides those disclosed above are equally possible.

Claims

1. A method for forming a semiconductor structure (100), the method comprising: On the substrate (102; 202) to form a layer stack (110; 210), the layer stack (110; 210) include: a first sub-stack (120; 220) comprising a first sacrificial layer (122a; 222a) and a topmost channel layer (124; 224) defining the first sub-stack (120; 220) on the first sacrificial layer (122a; 222a), a second sub-stack (130; 230), the second sub-stack (130; 230) being on the first sub-stack (120; 220) and comprising a plurality of sacrificial layers alternating between first sacrificial layers (132a; 232a) and second sacrificial layers (132b), wherein adjacent first sacrificial layers (132a; 232a) and second sacrificial layers (132b) of the second sub-stack (130; 230) are separated by a liner (133; 233), wherein the first sacrificial layers (132a; 232a) define respective bottommost and topmost layers of the second sub-stack (130; 230), the second sub-stack comprising at least one second sacrificial layer (132b); a third substack (140; 240) on the second substack (130; 230) and comprising a channel layer (144; 244) defining the bottommost layer of the third substack (140; 240) and a first sacrificial layer (142a; 242a) on the channel layer (144; 244); wherein the first sacrificial layer is formed of a first sacrificial semiconductor material, the second sacrificial layer is formed of a second sacrificial semiconductor material different from the first sacrificial semiconductor material, and the liner is formed of a semiconductor material different from the first semiconductor material and the second semiconductor material; forming a source / drain groove (103), wherein the source / drain groove exposes an end surface of the layer stack; forming a recess (160; 260) in the first sacrificial layer of the layer stack by selectively etching back end faces of the first sacrificial layer of the layer stack in a lateral direction from opposite ends of the layer stack; removing the at least one second sacrificial layer of the second substack by selective etching to form at least one cavity (135; 235), while protecting the first sacrificial layer of the second substack from vertical etching by the liner; and depositing a dielectric material in the at least one cavity; and depositing a dielectric material in the groove of the first sacrificial layer; At least one of the actions of depositing the dielectric material in the at least one cavity and the actions of depositing the dielectric material in the recess of the first sacrificial layer is performed by a first chemical vapor deposition method (CVD method), wherein the first CVD method comprises: In a state where at least the non-oxidizing hydrogen-containing gas is plasmatized, reacting an oxygen-containing silicon compound gas as a film-forming gas with the non-oxidizing hydrogen-containing gas to form a flowable silanol compound film; and subsequently annealing the film of flowable silanol compound into the first dielectric material, The oxygen-containing silicon compound gas includes Si α O β (OC m H n ) Γ C x H y , wherein m, n and α are integers of 1 or greater; and wherein β, Γ, x and y are integers of 0 or greater; and β and Γ are not 0 at the same time.

2. The method according to claim 1, characterized in that The act of depositing a dielectric material in the at least one cavity (135; 235) is performed by the first CVD method.

3. The method according to claim 1 or 2, characterized in that: The two actions of depositing the dielectric material in the at least one cavity (135; 235) and depositing the dielectric material in the recess (160; 260) of the first sacrificial layer are performed by the first chemical vapor deposition method.

4. The method according to claim 3, characterized in that The actions of depositing a dielectric material in the at least one cavity (135) and depositing a dielectric material in the recess (160) of the first sacrificial layer are performed simultaneously.

5. The method according to any one of the preceding claims, characterized in that The material of the channel layer is Si 1- a Ge a , the material of the liner is Si 1-b Ge b , the first sacrificial semiconductor material is Si 1-c Ge c , and the second sacrificial semiconductor material is Si 1-d Ge d , where 0≤a≤b<c<d.

6. The method according to any one of the preceding claims, characterized in that c is in the range of 0.1-0.25, and d is in the range of 0.35-0.

5.

7. The method according to any one of the preceding claims, characterized in that b is less than 0.

05.

8. The method according to any one of the preceding claims, characterized in that The dielectric material deposited by the first CVD method includes SiOC or SiOCN.

9. The method according to any one of the preceding claims, characterized in that The act of forming a recess (160) in a first sacrificial layer of the layer stack (110): is performed before the act of removing the at least one second sacrificial layer of the second sub-stack (130); as well as The etching is performed using a first selective etch that is selective to the material of the channel layer and the material of the liner layer but not selective to the first sacrificial semiconductor material and the second sacrificial semiconductor material.

10. The method according to any one of the preceding claims, characterized in that The act of removing the at least one second sacrificial layer of the second sub-stack (130; 230) is performed using a second selective etch that is selective to the material of the channel layer, the material of the liner layer and the first sacrificial semiconductor material but not selective to the second sacrificial semiconductor material.

11. The method according to any one of the preceding claims, characterized in that The thickness of the lining layer (133; 233) is in the range of 1 nm to 5 nm.

12. The method according to any one of the preceding claims, characterized in that Forming the groove (160; 260) includes isotropically selectively etching end surfaces of the first sacrificial layer from opposite ends of the layer stack (110; 210).

13. The method according to any one of the preceding claims, characterized in that The method further comprises: forming a sacrificial gate structure (150; 250) extending across the layer stack (110; 210), the sacrificial gate structure (150; 250) comprising a sacrificial gate body (152; 252) and first spacers (154; 254) on opposite sides of the sacrificial gate body (152; 252); The source / drain grooves are formed as follows: The device layer stack (110; 210) is etched through while using the sacrificial gate structure (150; 250) as an etch mask so that portions of the first substack, the second substack and the third substack of the layer stack (110; 210) are retained below the sacrificial gate structure (150; 250).

14. The method according to any one of the preceding claims, characterized in that Also includes: Source and drain regions (164; 166) are formed by epitaxially growing semiconductor material on end surfaces of the channel layer exposed in the source / drain recesses.

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