Method for preparing solar cell and solar cell

Abstract

The present invention relates to the field of photovoltaic cell technology and provides a method for preparing a solar cell and a solar cell. The method for preparing a solar cell comprises: providing a silicon substrate having a first surface, the first surface comprising a plurality of spaced-apart first regions and a second region located between two adjacent first regions; forming a silicon oxide dielectric layer on the second region; sequentially forming a tunneling oxide layer and a doped polysilicon layer on the first surface, the tunneling oxide layer covering the first region and the silicon oxide dielectric layer, and the doped polysilicon layer covering the tunneling oxide layer; and patterning the doped polysilicon layer and the tunneling oxide layer to selectively remove the doped polysilicon layer and the tunneling oxide layer on the second region. This application solves the problem of poor passivation effect in high-efficiency cells using local contact technology.

Description

Technical Field

[0001] The present invention relates to the technical field of photovoltaic cells, and in particular to a method for preparing a solar cell and a solar cell. Background Art

[0002] Currently, the solar cell industry is widely focused on and developing next-generation cell technologies. Among them, N-type silicon-based cells featuring passivated contact technology have garnered significant attention. To commercialize cells using passivated contact technology, extensive research has been conducted on the fabrication of passivated contact structures. The core of the passivated contact structure is the introduction of an ultra-thin tunneling oxide (SiO2) layer and a doped polysilicon (Poly-Si) layer on the back of the cell.

[0003] The non-metallic contact areas of solar cells are usually not covered with polysilicon. This means that the solar cell has local contacts or finger contacts. A solar cell with local contacts only forms the metal-polysilicon contact in a localized area (a finger pattern) across the entire back side, while the rest of the area remains passivated.

[0004] However, the high-efficiency batteries currently using the above-mentioned local contact technology have the problem of poor passivation effect. Summary of the Invention

[0005] The main purpose of the present invention is to provide a method for preparing a solar cell and a solar cell, so as to solve the problem of poor passivation effect of high-efficiency cells using local contact technology in the prior art.

[0006] To achieve the above-mentioned purpose, according to one aspect of the present invention, a method for preparing a solar cell is provided, which comprises: providing a silicon substrate, the silicon substrate having a first surface, the first surface comprising a plurality of spaced-apart first regions and a second region located between two adjacent first regions; forming a silicon oxide dielectric layer on the second region; sequentially forming a tunneling oxide layer and a doped polysilicon layer on the first surface, the tunneling oxide layer covering the first region and the silicon oxide dielectric layer, and the doped polysilicon layer covering the tunneling oxide layer; and patterning the doped polysilicon layer and the tunneling oxide layer to selectively remove the doped polysilicon layer and the tunneling oxide layer on the second region.

[0007] Optionally, after patterning the doped polysilicon layer and the tunnel oxide layer, the method for preparing a solar cell further includes: removing the silicon oxide dielectric layer by wet etching to expose the second region; and forming a back passivation layer on the second region.

[0008] Optionally, the step of forming the silicon-oxygen dielectric layer on the second region includes: performing a first laser treatment on the second region to cause silicon in the silicon substrate located in the second region to react with air to form the silicon-oxygen dielectric layer.

[0009] Optionally, the laser power of the first laser treatment is 5-20W.

[0010] Optionally, the linear speed of the first laser processing is 67000~73000 mm / s.

[0011] Optionally, the step of sequentially forming a tunneling oxide layer and a doped polysilicon layer on the first surface includes: forming a tunneling oxide layer on the first surface so that the tunneling oxide layer covers the first region and the silicon oxide dielectric layer; forming an intrinsic amorphous silicon layer on a side of the tunneling oxide layer facing away from the silicon substrate; performing diffusion treatment on the intrinsic amorphous silicon layer to convert the intrinsic amorphous silicon layer into a doped polysilicon layer, and forming doped silicon glass on a side of the doped polysilicon layer facing away from the tunneling oxide layer.

[0012] Optionally, the step of patterning the doped polysilicon layer and the tunnel oxide layer includes: performing a second laser treatment on the portion of the doped silicon glass located on the second region to remove the portion of the doped silicon glass located on the second region; and using wet etching to remove the portion of the doped polysilicon layer located on the second region and the portion of the tunnel oxide layer located on the second region.

[0013] Optionally, the thickness of the silicon oxide dielectric layer is 8-10 nm.

[0014] Optionally, before forming the silicon-oxygen dielectric layer on the second region, the method for preparing a solar cell further includes: polishing the first surface.

[0015] According to another aspect of the present invention, a solar cell is provided. The solar cell is prepared by any of the above-mentioned methods for preparing a solar cell.

[0016] The technical solution of the present invention is applied to provide a method for preparing a solar cell, the method comprising: providing a silicon substrate having a first surface, the first surface including a plurality of spaced-apart first regions and a second region located between two adjacent first regions; forming a silicon oxide dielectric layer on the second region; sequentially forming a tunneling oxide layer and a doped polysilicon layer on the first surface, the tunneling oxide layer covering the first region and the silicon oxide dielectric layer, and the doped polysilicon layer covering the tunneling oxide layer; and patterning the doped polysilicon layer and the tunneling oxide layer to selectively remove the doped polysilicon layer and the tunneling oxide layer on the second region. The beneficial effect of the present application is that after selectively removing the doped polysilicon layer and the tunneling oxide layer on the second region, the remaining tunneling oxide layer and the doped polysilicon layer located on the first region together constitute a passivation contact structure, and the synergistic effect of the tunneling barrier layer and the doped polysilicon significantly improves the surface passivation effect of the silicon substrate. Among them, the tunneling oxide layer enhances the charge transfer characteristics of the silicon substrate surface by reducing non-radiative recombination, improves the passivation effect of the silicon substrate surface, and effectively improves the surface loading rate; the doped polysilicon layer provides an excellent charge transfer channel, which promotes the smooth flow of carriers. It should be noted that before forming the above-mentioned tunneling oxide layer and doped polysilicon layer, the present application first forms a silicon oxide dielectric layer on the second region so that the silicon oxide dielectric layer is located between the silicon substrate and the tunneling oxide layer in the thickness direction of the silicon substrate. Thus, the above-mentioned silicon oxide dielectric layer effectively acts as a mask in the subsequent patterning process of the doped polysilicon layer and the tunneling oxide layer, effectively isolating the influence of the patterning of the doped polysilicon layer and the tunneling oxide layer on the silicon substrate, strengthening the damage resistance of the second region of the silicon substrate, maintaining the surface integrity and quality of the second region, thereby reducing non-radiative recombination on the surface of the silicon substrate and improving the passivation effect. In summary, through this application, the problem of poor passivation effect of high-efficiency batteries using local contact technology in the prior art is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which constitute part of this application, are intended to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are intended to explain the present invention and do not constitute an undue limitation of the present invention. In the accompanying drawings:

[0018] Figure 1 A schematic flow chart of a method for preparing a solar cell according to an embodiment of the present invention is shown;

[0019] Figure 2 A schematic structural diagram of performing a first laser treatment on the second region to form a silicon-oxygen dielectric layer in a method for preparing a solar cell according to an embodiment of the present invention is shown;

[0020] Figure 3 Shown in Figure 2A schematic diagram of a structure in which a tunnel oxide layer, a doped polysilicon layer and a doped silicon glass layer are formed on the basis of the structure shown;

[0021] Figure 4 Shown in Figure 3 A schematic diagram of the structure after the doped silicon glass layer is subjected to a second laser treatment based on the structure shown;

[0022] Figure 5 Shown in Figure 4 Schematic diagram of a solar cell formed after patterning the doped polysilicon layer and the tunnel oxide layer based on the structure shown;

[0023] Figure 6 Shown in Figure 5 A schematic diagram of the structure after removing the silicon oxide dielectric layer based on the structure shown;

[0024] Figure 7 A schematic structural diagram of a TOPCon battery according to an embodiment of the present invention is shown;

[0025] Figure 8 A structural schematic diagram of a BC battery according to an embodiment of the present invention is shown.

[0026] The above drawings include the following reference numerals:

[0027] 10. Silicon substrate; 101. First region; 102. Second region; 200. First laser; 20. Silicon oxide dielectric layer; 30. Tunneling oxide layer; 40. Doped polysilicon layer; 500. Second laser; 50. Doped silicon glass; 60. Passivation contact structure.

[0028] 110. First silicon substrate; 111. Emitter; 112. First tunneling oxide layer; 113. First doped polysilicon layer; 114. First passivation contact structure; 115. First front passivation layer; 116. First back passivation layer; 117. First front metal electrode; 118. First back metal electrode.

[0029] 120. Second silicon substrate; 121. Second front passivation layer; 122. Second tunneling oxide layer; 123. Second doped polysilicon layer; 124. Second passivation contact structure; 125. Third tunneling oxide layer; 126. Third doped polysilicon layer; 127. Third passivation contact structure; 128. Second back passivation layer; 129. Second back metal electrode; 130. Third back metal electrode. DETAILED DESCRIPTION

[0030] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0031] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present application belongs.

[0032] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0033] It should be noted that the terms "first," "second," and the like in the specification and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate for the embodiments of the present invention described herein. In addition, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatuses.

[0034] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being “on” another element, the element may be directly on the other element or intervening elements may be present. Furthermore, in the specification and claims, when it is described that an element is “connected to” another element, the element may be “directly connected to” the other element or “connected to” the other element through a third element.

[0035] The present application is further described in detail below with reference to specific embodiments. These embodiments should not be construed as limiting the scope of protection claimed in this application.

[0036] As described in the background art, the passivation effect of high-efficiency batteries using local contact technology in the prior art is poor.

[0037] In the current photovoltaic cell manufacturing field, especially for high-efficiency cells using local contact technology, the traditional solar cell preparation process will cause damage to the silicon substrate. Therefore, in order to solve the problem of poor passivation effect of high-efficiency cells using local contact technology, the present application proposes a method for preparing a solar cell, which comprises: providing a silicon substrate, the silicon substrate having a first surface, the first surface comprising a plurality of first regions spaced apart and a second region located between two adjacent first regions; forming a silicon oxide dielectric layer on the second region; sequentially forming a tunneling oxide layer and a doped polysilicon layer on the first surface, the tunneling oxide layer covering the first region and the silicon oxide dielectric layer, and the doped polysilicon layer covering the tunneling oxide layer; patterning the doped polysilicon layer and the tunneling oxide layer to selectively remove the doped polysilicon layer and the tunneling oxide layer on the second region.

[0038] After selectively removing the doped polysilicon layer and tunneling oxide layer from the second region, the remaining tunneling oxide layer and doped polysilicon layer from the first region together form a passivation contact structure. The synergistic effect of the tunneling barrier layer and doped polysilicon significantly enhances the surface passivation of the silicon substrate. Furthermore, the tunneling oxide layer reduces non-radiative recombination, enhancing the charge transfer characteristics on the silicon substrate surface, improving the passivation effect and effectively improving the surface loading rate. The doped polysilicon layer provides an excellent charge transfer channel, promoting the smooth flow of carriers. It should be noted that, before forming the above-mentioned tunneling oxide layer and doped polysilicon layer, the present application first forms a silicon oxide dielectric layer on the second region so that the silicon oxide dielectric layer is located between the silicon substrate and the tunneling oxide layer in the thickness direction of the silicon substrate. Thus, the above-mentioned silicon oxide dielectric layer effectively acts as a mask in the subsequent patterning process of the doped polysilicon layer and the tunneling oxide layer, effectively isolating the influence of the patterning of the doped polysilicon layer and the tunneling oxide layer on the silicon substrate, strengthening the damage resistance of the second region of the silicon substrate, maintaining the surface integrity and quality of the second region, thereby reducing the non-radiative recombination on the surface of the silicon substrate and improving the passivation effect. In summary, through the present application, the problem of poor passivation effect of high-efficiency batteries using local contact technology in the prior art is solved.

[0039] The following describes in more detail exemplary embodiments of a method for preparing a solar cell according to the present application. However, these exemplary embodiments can be implemented in a variety of different forms and should not be construed as limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of this application thorough and complete, and to fully convey the concepts of these exemplary embodiments to those skilled in the art.

[0040] Figure 1 A flow chart of a method for preparing a solar cell provided in an embodiment of the present application is provided. Figures 2 to 6This is a schematic diagram of a solar cell manufacturing process provided in an embodiment of the present application. Figure 1 As shown, the present application provides a method for preparing a solar cell, comprising:

[0041] Step S1, providing a silicon substrate 10, the silicon substrate 10 has a first surface, the first surface includes a plurality of first regions 101 spaced apart and a second region 102 located between two adjacent first regions 101, such as Figures 2 to 6 As shown;

[0042] The silicon substrate 10 may include an N-type silicon substrate or a P-type silicon substrate according to the doping type, and may include but is not limited to a single crystal silicon substrate or a polycrystalline silicon substrate according to the crystal structure. Therefore, the silicon substrate 10 may include but is not limited to any one of an N-type single crystal silicon substrate, an N-type polycrystalline silicon substrate, a P-type single crystal silicon substrate, and a P-type polycrystalline silicon substrate.

[0043] Specifically, when the silicon substrate 10 is an N-type silicon substrate, the doping elements in the N-type silicon substrate can be one or more of phosphorus, arsenic and antimony; when the silicon substrate 10 is a P-type silicon substrate, the doping elements in the P-type silicon substrate can be one or more of boron, gallium, aluminum and indium.

[0044] The first surface may be a specific surface of the silicon substrate 10. For a photovoltaic cell, the first surface may be the front surface or the back surface that receives sunlight.

[0045] The first surface may include multiple first regions 101 and one second region 102 , with the second region 102 located between two adjacent first regions 101 ; or, the first surface may include multiple first regions 101 and multiple second regions 102 , with one second region 102 located between two adjacent first regions 101 .

[0046] It is explained here that the first area 101 and the second area 102 are obtained by artificially dividing the first surface. In some embodiments, the first area 101 can also be named a contact area, and the second area 102 can also be named a non-contact area.

[0047] Step S2, forming a silicon oxide dielectric layer 20 on the second region 102, such as Figure 2 As shown;

[0048] The silicon oxide dielectric layer 20 (SiO x ) only occurs on the second region 102 rather than covering the entire surface of the silicon substrate 10.

[0049] Optionally, the formation of the silicon oxide dielectric layer 20 may include but is not limited to being achieved by laser localized oxidation or deposition process. It is understood that the localization in the laser localized oxidation is the designated area, ie, the second area 102 .

[0050] When the silicon oxide dielectric layer 20 is formed by laser localized oxidation, the silicon oxide dielectric layer 20 can be formed on the second region 102 by laser irradiation. When the silicon oxide dielectric layer 20 is formed by a deposition process, a mask covering the first region 101 and opening the second region 102 can be provided on the first surface, so that the silicon oxide dielectric layer 20 can be formed on the second region 102.

[0051] Step S3, sequentially forming a tunneling oxide layer 30 and a doped polysilicon layer 40 on the first surface, wherein the tunneling oxide layer 30 covers the first region 101 and the silicon oxide dielectric layer 20, and the doped polysilicon layer 40 covers the tunneling oxide layer 30. Figure 3 and Figure 4 As shown;

[0052] The tunnel oxide layer 30 is an ultra-thin oxide layer, and its thickness in a direction perpendicular to the first surface may be 0.5-2 nm.

[0053] The doped polysilicon layer 40 may be formed by low pressure chemical vapor deposition (LPCVD). Optionally, the doped polysilicon layer 40 has a thickness of 70-150 nm in a direction perpendicular to the first surface.

[0054] The tunneling oxide layer 30 can be formed on the first surface of the silicon substrate 10 by thermal oxidation or chemical oxidation. It acts as an insulating but permeable barrier, allowing carriers (electrons or holes) to tunnel between the polysilicon and the silicon substrate 10 while preventing the direct flow of current. This effectively isolates defects on the surface of the silicon substrate 10, thereby optimizing the surface recombination of the silicon substrate 10. It should be noted that because the silicon oxide dielectric layer 20 is pre-formed on the second region 102, the tunneling oxide layer 30 formed on the first surface not only covers the multiple first regions 101 of the first surface, but also covers the silicon oxide dielectric layer 20. As a result, the silicon oxide dielectric layer 20 serves as a protective layer between the silicon substrate 10 and the tunneling oxide layer 30.

[0055] The doped polysilicon layer 40 is formed on the tunnel oxide layer 30. As the name implies, the doped polysilicon layer 40 is doped with specific impurities (such as boron or phosphorus). For example, when the doped impurity is boron, it is P-type doping; when the doped impurity is phosphorus, it is N-type doping. Therefore, the doped polysilicon layer 40 can be divided into an N-type doped polysilicon layer and a P-type doped polysilicon layer according to the doping type. Optionally, the doping concentration of the doping impurity (such as boron or phosphorus) in the doped polysilicon layer 40 is e19~e21cm -3 .

[0056] In some optional embodiments, for the TOPCon cell, when the above-mentioned silicon substrate 10 is an N-type silicon substrate, the doped polysilicon layer 40 formed on the N-type silicon substrate 10 is an N-type doped polysilicon layer; when the above-mentioned silicon substrate 10 is a P-type silicon substrate, the doped polysilicon layer 40 formed on the P-type silicon substrate 10 is a P-type doped polysilicon layer.

[0057] Step S4, patterning the doped polysilicon layer 40 and the tunnel oxide layer 30 to selectively remove the doped polysilicon layer 40 and the tunnel oxide layer 30 on the second region 102, as shown in FIG. Figure 5 .

[0058] It is understandable that if Figure 5 As shown, the above-mentioned patterning can remove the portion of the doped polysilicon layer 40 located on the second region 102 and the portion of the tunneling oxide layer 30 located on the second region 102, and the remaining tunneling oxide layer 30 and doped polysilicon layer 40 located on the first region 101 form a passivation contact structure 60.

[0059] In some embodiments, the patterning of the doped polysilicon layer 40 and the tunnel oxide layer 30 can be performed using wet etching, and the chemical solution used in the wet etching is an alkaline chemical solution. Optionally, before the wet etching, a patterned mask can be formed on the side of the doped polysilicon layer 40 away from the tunnel oxide layer 30 using photolithography or laser technology, so that the wet etching process acts only on the area to be removed through the chemical solution (etchant).

[0060] It is emphasized here that the silicon oxide dielectric layer 20 has a high chemical stability to alkaline chemical solutions, so that in the step of patterning the doped polysilicon layer 40 and the tunneling oxide layer 30 using an alkaline chemical solution, the silicon oxide dielectric layer 20 can be used as a mask material to protect the silicon substrate 10 under the doped silicon oxide dielectric layer 20.

[0061] This also means that after the above step S4, the silicon oxide dielectric layer 20 formed in step S2 is still retained on the second region 102. Figure 5 In some optional embodiments, after patterning the doped polysilicon layer 40 and the tunnel oxide layer 30, the method for preparing a solar cell further comprises: removing the silicon oxide dielectric layer 20 by wet etching to expose the second region 102, as shown in FIG. Figure 6 As shown; a back passivation layer is formed on the second region 102.

[0062] The material of the back passivation layer can be selected from any one or more of aluminum oxide, titanium dioxide, silicon nitride and silicon oxynitride.

[0063] In the above embodiment, due to the low cost of wet etching, the ability to process in batches, and the high selectivity of the wet etching chemical solution for the silicon oxide dielectric layer 20, wet etching can be used to efficiently and cost-effectively etch the silicon oxide dielectric layer 20 without affecting the silicon substrate 10 below the silicon oxide dielectric layer 20. Furthermore, by forming a back passivation layer on the second region 102, the material of the back passivation layer can be in direct contact with the surface of the silicon substrate 10. Based on this, and owing to the material properties of the back passivation layer, the material of the back passivation layer can passivate dangling bonds on the surface of the silicon substrate 10, effectively increasing the carrier lifetime, thereby further improving the passivation effect on the surface of the silicon substrate 10.

[0064] In addition, it should be noted that the silicon oxide dielectric layer 20 is more easily etched in an acidic environment. Therefore, in the step of removing the silicon oxide dielectric layer 20 by wet etching, the chemical solution used for the wet etching can be an acidic chemical solution. In addition, because silicon exhibits high chemical stability in an acidic environment, the surface integrity of the second region 102 can be maintained while removing the silicon oxide dielectric layer 20.

[0065] In some optional embodiments, such as Figure 2 As shown, the step of forming the silicon-oxygen dielectric layer 20 on the second region 102 includes: performing a first laser treatment on the second region 102 to cause silicon in the silicon substrate 10 located in the second region 102 to react with air and form the silicon-oxygen dielectric layer 20 .

[0066] It is understood that lasers have high energy density and excellent focusing capabilities. When a laser beam is focused on a specific area and reaches a specific power, it can locally heat that specific area, initiating a chemical reaction. Therefore, during the first laser treatment of the second area 102, when the second area 102 of the silicon substrate 10 is heated by the laser light emitted by the first laser 200, the high temperature causes the silicon to chemically react with oxygen in the air, thereby forming a silicon-oxygen dielectric layer 20. Exemplarily, the silicon-oxygen dielectric layer 20 is silicon dioxide.

[0067] In addition, in order to maintain the surface integrity of the silicon substrate 10 during the first laser treatment, the energy density of the laser during the first laser treatment can be lower than the ablation threshold of the silicon substrate 10. The ablation threshold refers to the minimum laser energy density per unit area required to trigger material removal.

[0068] In the above embodiment, when the first laser treatment is performed on the second region 102, the first laser treatment can be more directly and accurately focused on the second region 102, thereby simplifying the process flow of achieving local oxidation on the basis of allowing the silicon located in the second region 102 in the silicon substrate 10 to react with the air and form the silicon oxide dielectric layer 20.

[0069] For example, the laser type in the first laser treatment process may be 355 nm ultraviolet picosecond.

[0070] Laser power and linear velocity are key parameters that directly affect the energy density applied to the silicon substrate 10. Therefore, when the energy density of the laser during the first laser treatment process is greater than the ablation threshold of the silicon substrate 10, in order to further reasonably control the energy density of the laser during the first laser treatment process, it can also be achieved by reasonably controlling the laser power and linear velocity of the first laser treatment.

[0071] Among them, laser power is a measure of the energy released by the laser beam per unit time. Furthermore, appropriate laser power can accelerate the oxidation reaction and increase the thickness of the silicon oxide dielectric layer 20 formed per unit time. Therefore, in order to help the silicon oxide dielectric layer 20 reach the ideal film thickness as a mask material in a short period of time and improve the efficiency and output of the production line, in some embodiments, the laser power of the first laser treatment can be greater than or equal to 5W. Moreover, appropriate laser power can also directly affect the quality of subsequent processes. Therefore, in order to accelerate the growth of the silicon oxide dielectric layer 20 and enhance the process controllability of the growth of the silicon oxide dielectric layer 20, so that the silicon oxide dielectric layer 20 can effectively serve as a mask material and further ensure the surface integrity of the silicon substrate 10, the laser power of the first laser treatment can be less than or equal to 20W. In summary, the laser power of the above-mentioned first laser treatment can be 5~20W.

[0072] In addition, the linear velocity is the speed at which the laser beam moves relative to the silicon substrate 10. In some embodiments, the linear velocity of the first laser treatment can be greater than or equal to 67,000 mm / s. It can be understood that the linear velocity of the first laser treatment within this range is relatively high, thereby further ensuring that the energy density of the laser during the first laser treatment can be lower than the ablation threshold of the silicon substrate 10, thereby ensuring the surface integrity of the silicon substrate 10. A linear velocity less than 73,000 mm / s can enhance the controllability of the growth of the silicon oxide dielectric layer 20, ensuring that the formed silicon oxide dielectric layer 20 is sufficiently thick and uniform, thereby allowing the silicon oxide dielectric layer 20 to effectively serve as a mask material, further ensuring the surface integrity of the silicon substrate 10. In summary, the linear velocity of the first laser treatment can be 67,000-73,000 mm / s. In some embodiments, the linear velocity of the first laser treatment can be 700,000 mm / s.

[0073] In some optional embodiments, such as Figures 2 to 5As shown, the thickness of the silicon oxide dielectric layer 20 is 8-10 nm. In the above embodiment, a silicon oxide dielectric layer 20 having a thickness greater than or equal to 8 nm can effectively block the alkaline chemical solution during the patterning of the doped polysilicon layer 40 and the tunneling oxide layer 30. A silicon oxide dielectric layer 20 having a thickness less than or equal to 10 nm can be more easily removed in the subsequent removal process (using wet etching to remove the silicon oxide dielectric layer 20 to expose the second region 102). In some embodiments, the thickness of the silicon oxide dielectric layer can be 9 nm.

[0074] In some optional embodiments, such as Figure 3 As shown, the steps of sequentially forming a tunneling oxide layer 30 and a doped polysilicon layer 40 on the first surface include: forming a tunneling oxide layer 30 on the first surface so that the tunneling oxide layer 30 covers the first region 101 and the silicon oxide dielectric layer 20; forming an intrinsic amorphous silicon layer (not shown in the figure) on a side of the tunneling oxide layer 30 facing away from the silicon substrate 10; performing a diffusion treatment on the intrinsic amorphous silicon layer to convert the intrinsic amorphous silicon layer into a doped polysilicon layer 40, and forming a doped silicon glass 50 on a side of the doped polysilicon layer 40 facing away from the tunneling oxide layer 30.

[0075] In the above embodiment, since the tunneling oxide layer 30 has been formed on the silicon substrate 10 before the intrinsic amorphous silicon layer is formed, on the one hand, the tunneling oxide layer 30 is beneficial to preventing the diffusion of doped atoms into the silicon substrate 10; on the other hand, the tunneling oxide layer 30 is beneficial to reducing the recombination of electrons and holes, thereby improving the surface passivation effect of the silicon substrate 10. Furthermore, during the diffusion treatment of the intrinsic amorphous silicon layer, the doped atoms gain energy and can combine with the amorphous silicon atoms inside the intrinsic amorphous silicon layer to convert the intrinsic amorphous silicon layer into a doped polysilicon layer 40. In addition, the oxide containing doped atoms produced during the diffusion process can also react with silicon atoms to form doped silicon glass 50. The doped silicon glass 50 can be used as a mask for the patterned doped polysilicon layer 40 and the tunneling oxide layer 30, and can protect the portion of the doped polysilicon layer 40 located on the first region 101 and the portion of the tunneling oxide layer 30 located on the first region 101 from damage, thereby reducing surface recombination of the doped polysilicon layer 40 and enhancing the passivation effect of the doped polysilicon layer 40 on the silicon substrate 10.

[0076] For example, when the doping atom is a phosphorus atom, the oxide containing the doping atom may be phosphorus pentoxide (P2O5), and the doped silica glass 50 may be phosphosilicate glass (PSG); when the doping atom is a boron atom, the oxide containing the doping atom may be boron oxide, and the doped silica glass 50 may be borosilicate glass (BSG).

[0077] In some optional embodiments, such as Figure 4 and Figure 5As shown, when a doped silicon glass 50 is formed on a side of the doped polysilicon layer 40 facing away from the tunnel oxide layer 30, in order to remove the portion of the doped polysilicon layer 40 located on the second region 102 and the portion of the tunnel oxide layer 30 located on the second region 102, the doped silicon glass 50 may be first patterned so that the doped silicon glass 50 serves as a mask for patterning the doped polysilicon layer 40 and the tunnel oxide layer 30. Furthermore, the step of patterning the doped polysilicon layer 40 and the tunnel oxide layer 30 may include: performing a second laser treatment on the portion of the doped silicon glass 50 located on the second region 102 to remove the portion of the doped silicon glass 50 located on the second region 102; and removing the portion of the doped polysilicon layer 40 located on the second region 102 and the portion of the tunnel oxide layer 30 located on the second region 102 by wet etching. It is understood that after removing the portion of the doped polysilicon layer 40 located on the second region 102 and the portion of the tunnel oxide layer 30 located on the second region 102, the remaining portion of the doped polysilicon layer 40 located on the first region 101 and the portion of the tunnel oxide layer 30 located on the first region 101 can be the passivation contact structure 60. It is understood that the laser in the second laser treatment process can be emitted by a second laser 500, and the second laser 500 and the first laser 200 can be the same or different. By using the second laser treatment to pattern the doped silicon glass 50, the process can be compatible with the first laser treatment for forming the silicon oxide dielectric layer 20, thereby simplifying the process flow, reducing equipment costs, and providing process flexibility.

[0078] In some optional embodiments, the laser power of the second laser treatment is 70-90W.

[0079] In the above embodiment, in order to ensure that the portion of the doped silicon glass 50 located on the second region 102 is completely removed and to increase the removal speed, the laser power of the second laser treatment can be set to be greater than or equal to 70 W; further, by setting the laser power of the second laser treatment to be less than or equal to 90 W, it can help to maintain the integrity of the portion of the doped silicon glass 50 other than that located on the second region 102.

[0080] For example, the laser type in the second laser treatment process may be green light femtosecond.

[0081] In some optional implementations, before forming the silicon-oxygen dielectric layer 20 on the second region 102 , the method for preparing a solar cell further includes: polishing the first surface.

[0082] In the above-described embodiment, the polishing process can significantly reduce dangling bonds on the surface of the silicon substrate 10, thereby helping to reduce surface recombination. Furthermore, after the step of removing the silicon oxide dielectric layer 20, the close contact between the back passivation layer formed on the second region 102 of the first surface and the polished surface can more effectively passivate these dangling bonds, forming a high-quality interface, thereby further reducing the surface recombination rate and effectively improving the surface passivation effect of the silicon substrate 10.

[0083] In some embodiments, when the solar cell is a tunneling oxide passivation contact (TOPCon) cell, a method for preparing a TOPCon cell is provided, the method comprising:

[0084] S100, providing a first silicon substrate, wherein the first silicon substrate has a front surface and a back surface opposite to each other, and the back surface includes a plurality of first regions and a second region located between two adjacent first regions;

[0085] S101, forming an emitter on the front surface of a first silicon substrate;

[0086] S102, performing a first laser treatment on the second region on the back side of the first silicon substrate, so that the silicon in the second region of the first silicon substrate reacts with air to form a first silicon-oxygen dielectric layer;

[0087] S103, forming a first tunneling oxide layer on the back side of the first silicon substrate, so that the first tunneling oxide layer covers the first region and the first silicon oxide dielectric layer;

[0088] S104, forming a first intrinsic amorphous silicon layer on a side of the first tunnel oxide layer facing away from the first silicon substrate;

[0089] S105, performing a diffusion process on the first intrinsic amorphous silicon layer to convert the first intrinsic amorphous silicon layer into a first doped polysilicon layer, and forming a first doped silicon glass on a side of the first doped polysilicon layer away from the first tunnel oxide layer;

[0090] S106, performing a second laser treatment on the portion of the first doped silica glass located on the second region to remove the portion of the first doped silica glass located on the second region;

[0091] S107, removing the portion of the first doped polysilicon layer located on the second region and the portion of the first tunnel oxide layer located on the second region by a first wet etching process, and the remaining portions of the first doped polysilicon layer and the first tunnel oxide layer located on the first region form a first passivation contact structure;

[0092] S108, removing the first silicon oxide dielectric layer by a second wet etching process to expose the second region;

[0093] S109, removing a portion of the first doped silicon glass layer located on the first region, and forming a first back passivation layer on a side of the first doped polysilicon layer facing away from the first silicon substrate, so that the first back passivation layer covers the first passivation contact structure and the second region on the back side of the first silicon substrate;

[0094] S110, forming a first back metal electrode on the first region, penetrating the first back passivation layer and contacting the first doped polysilicon layer;

[0095] S111, forming a first front passivation layer on a side of the emitter away from the first silicon substrate;

[0096] S112 , forming a front metal electrode on the front surface of the first silicon substrate, penetrating through the first front passivation layer and contacting the emitter.

[0097] In some other embodiments, when the solar cell is a back contact (BC) cell, a method for preparing a BC cell is provided, the method comprising:

[0098] S200, providing a second silicon substrate, wherein the second silicon substrate has a front surface and a back surface opposite to each other, wherein the back surface includes a plurality of first regions, a second region located between two adjacent first regions, and a spacing region located between adjacent first regions and second regions;

[0099] S201, forming a second front passivation layer on the front surface of the second silicon substrate;

[0100] S202, performing a first laser treatment on the second region and the spacer region on the back side of the second silicon substrate, so that silicon in the second region and the spacer region of the second silicon substrate reacts with air to form a second silicon-oxygen dielectric layer;

[0101] S203, forming a second tunneling oxide layer on the back side of the second silicon substrate, so that the second tunneling oxide layer covers the first region and the second silicon oxide dielectric layer;

[0102] S204, forming a second intrinsic amorphous silicon layer on a side of the second tunnel oxide layer facing away from the second silicon substrate;

[0103] S205, performing a diffusion process on the second intrinsic amorphous silicon layer to convert the second intrinsic amorphous silicon layer into a second doped polysilicon layer, and forming a second doped silicon glass on a side of the second doped polysilicon layer away from the second tunnel oxide layer;

[0104] S206, performing a second laser treatment on the portion of the second doped silica glass located on the second region and the spacer region to remove the portion of the second doped silica glass located on the second region and the spacer region;

[0105] S207, removing the portion of the second doped polysilicon layer located on the second region and the spacer region and the portion of the second tunneling oxide layer located on the second region and the spacer region by a first wet etching process, and forming a second passivation contact structure by the remaining portion of the second doped polysilicon layer and the second tunneling oxide layer located on the first region;

[0106] S208, removing the second silicon oxide dielectric layer by a second wet etching process to expose the second region and the spacer region;

[0107] S209, performing the first laser treatment again on the spaced region on the back side of the second silicon substrate, so that the silicon in the spaced region of the second silicon substrate reacts with air to form a third silicon-oxygen dielectric layer;

[0108] S210, forming a third tunneling oxide layer on the back side of the second silicon substrate, so that the third tunneling oxide layer covers the second region, the third silicon oxide dielectric layer, and the second passivation contact structure;

[0109] S211, forming a third intrinsic amorphous silicon layer on a side of the third tunnel oxide layer facing away from the second silicon substrate;

[0110] S212, performing a diffusion process on the third intrinsic amorphous silicon layer to convert the third intrinsic amorphous silicon layer into a third doped polysilicon layer, and forming a third doped silicon glass on a side of the third doped polysilicon layer away from the third tunnel oxide layer;

[0111] S213, performing a second laser treatment on a portion of the third doped silicon glass located on the second passivation contact structure and the spacer region to remove the portion of the third doped silicon glass located on the second passivation contact structure and the spacer region;

[0112] S214, removing the portion of the third doped polysilicon layer located on the second passivation contact structure and the spacer region and the portion of the third tunneling oxide layer located on the second passivation contact structure and the spacer region by a first wet etching process, and the remaining portions of the third doped polysilicon layer and the third tunneling oxide layer located on the second region form a third passivation contact structure;

[0113] S215, removing the third silicon oxide dielectric layer by a second wet etching process to expose the spacer region;

[0114] S216, removing a portion of the second doped silicon glass layer located on the first region, and forming a second back passivation layer on a side of the second doped polysilicon layer and the third doped polysilicon layer facing away from the second silicon substrate, so that the second back passivation layer covers the second passivation contact structure, the third passivation contact structure, and the spacing region on the back side of the second silicon substrate;

[0115] S217. Form a second back metal electrode on the first region that penetrates the second back passivation layer and contacts the second doped polysilicon layer, and form a third back metal electrode on the second region that penetrates the second back passivation layer and contacts the third doped polysilicon layer.

[0116] According to another aspect of the present application, a solar cell is provided. The solar cell is prepared using any one of the methods for preparing a solar cell.

[0117] In some embodiments, compared with the solar cells prepared in the prior art without the step of forming a silicon oxide dielectric layer on the second region, the solar cells in this scheme are improved in terms of photoelectric conversion efficiency, open circuit voltage, short circuit current, fill factor and band gap. Among them, the improvement in photoelectric conversion efficiency can satisfy 0<Δeta≤0.05%, the improvement in open circuit voltage can satisfy 0<Δvoc≤0.0004 mV, the improvement in short circuit current can satisfy 0<Δisc≤0.004 mA, and the improvement in fill factor can satisfy 0<Δff≤0.09.

[0118] Exemplarily, the solar cell is a TOPCon cell or a back contact cell.

[0119] In some embodiments, such as Figure 7 As shown, in the case where the solar cell is a TOPCon cell, the TOPCon cell may include but is not limited to a first silicon substrate 110 , an emitter 111 , a first passivation contact structure 114 , a first front passivation layer 115 , a first back passivation layer 116 , a first front metal electrode 117 and a first back metal electrode 118 . Among them, the first silicon substrate 110 has a relative front and back surface, the back surface includes a plurality of first areas arranged at intervals and a second area located between two adjacent first areas, the first passivation contact structure 114 includes a first tunneling oxide layer 112 and a first doped polysilicon layer 113 arranged in a stacked manner, the first passivation contact structure 114 is located on the above-mentioned first area, the emitter 111 is located on the front surface of the first silicon substrate 110, the first front passivation layer 115 is located on the side of the emitter 111 away from the first silicon substrate 110, the first back passivation layer 116 includes a portion covering the side of the first passivation contact structure 114 away from the first silicon substrate 110 and a portion covering the second area on the back surface of the first silicon substrate 110, the first back metal electrode 118 is located on the first area and penetrates the first back passivation layer 116 and is in contact with the first doped polysilicon layer 113, and the first front metal electrode 117 is located on the front surface of the first silicon substrate 110 and penetrates the first front passivation layer 115 and is in contact with the emitter 111.

[0120] In other embodiments, Figure 8As shown, in the case where the solar cell is a back contact cell, the back contact cell may include but is not limited to a second silicon substrate 120, a second passivation contact structure 124, a third passivation contact structure 127, a second front passivation layer 121, a second back passivation layer 128, a second back metal electrode 129 and a third back metal electrode 130. The second silicon substrate 120 has a relative front and back, the back includes a plurality of first regions arranged at intervals and a second region located between two adjacent first regions, and there is a spacing region between the adjacent first and second regions. The second passivation contact structure 124 is located on the first region, and the second passivation contact structure 124 includes a second tunneling oxide layer 122 and a second doped polysilicon layer 123 arranged in a stacked manner. The third passivation contact structure 127 is located on the second region, and the third passivation contact structure 127 includes a third tunneling oxide layer 125 and a third doped polysilicon layer 126 arranged in a stacked manner. The second front passivation layer 121 is located at the On the front side of the second silicon substrate 120, the second back passivation layer 128 includes a portion covering the second passivation contact structure 124 on the side facing away from the second silicon substrate 120, a portion of the third passivation contact structure 127 on the side facing away from the second silicon substrate 120, and a spacing area on the back side of the second silicon substrate 120 located between adjacent first and second areas. The second back metal electrode 129 is located on the first area and penetrates through the second back passivation layer 128 to contact the second doped polysilicon layer 123. The third back metal electrode 130 is located on the second area and penetrates through the second back passivation layer 128 to contact the third doped polysilicon layer 126.

[0121] From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects:

[0122] 1. Applying the technical solution of the present invention, a method for preparing a solar cell is provided, the method comprising: providing a silicon substrate having a first surface, the first surface comprising a plurality of spaced-apart first regions and a second region located between two adjacent first regions; forming a silicon oxide dielectric layer on the second region; sequentially forming a tunneling oxide layer and a doped polysilicon layer on the first surface, the tunneling oxide layer covering the first region and the silicon oxide dielectric layer, and the doped polysilicon layer covering the tunneling oxide layer; and patterning the doped polysilicon layer and the tunneling oxide layer to selectively remove the doped polysilicon layer and the tunneling oxide layer on the second region. The beneficial effect of the present application is that after selectively removing the doped polysilicon layer and the tunneling oxide layer on the second region, the remaining tunneling oxide layer and the doped polysilicon layer located on the first region together constitute a passivation contact structure, and the synergistic effect of the tunneling barrier layer and the doped polysilicon significantly improves the surface passivation effect of the silicon substrate. Among them, the tunneling oxide layer enhances the charge transfer characteristics of the silicon substrate surface by reducing non-radiative recombination, improves the passivation effect of the silicon substrate surface, and effectively improves the surface loading rate; the doped polysilicon layer provides an excellent charge transfer channel, which promotes the smooth flow of carriers. It should be noted that before forming the above-mentioned tunneling oxide layer and doped polysilicon layer, the present application first forms a silicon oxide dielectric layer on the second region so that the silicon oxide dielectric layer is located between the silicon substrate and the tunneling oxide layer in the thickness direction of the silicon substrate. Thus, the above-mentioned silicon oxide dielectric layer effectively acts as a mask in the subsequent patterning process of the doped polysilicon layer and the tunneling oxide layer, effectively isolating the influence of the patterning of the doped polysilicon layer and the tunneling oxide layer on the silicon substrate, strengthening the damage resistance of the second region of the silicon substrate, maintaining the surface integrity and quality of the second region, thereby reducing non-radiative recombination on the surface of the silicon substrate and improving the passivation effect. In summary, through this application, the problem of poor passivation effect of high-efficiency batteries using local contact technology in the prior art is solved.

[0123] 2. By applying the technical solution of the present invention, a solar cell is provided. Since the solar cell is prepared by the above-mentioned method for preparing a solar cell, compared with a traditional solar cell that is not prepared by the method for preparing a solar cell of the present application, the second region of the silicon substrate of the solar cell of the present application can have good surface integrity and quality, which improves the non-radiative recombination phenomenon on the surface of the silicon substrate of the solar cell, improves the passivation efficiency, and solves the problem of poor passivation effect of high-efficiency batteries using local contact technology in the prior art.

[0124] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A method for preparing a solar cell, characterized in that: The method for preparing the solar cell comprises: Providing a silicon substrate, wherein the silicon substrate has a first surface, the first surface including a plurality of first regions spaced apart and a second region located between two adjacent first regions; forming a silicon oxide dielectric layer on the second region; forming a tunneling oxide layer and a doped polysilicon layer on the first surface in sequence, wherein the tunneling oxide layer covers the first region and the silicon oxide dielectric layer, and the doped polysilicon layer covers the tunneling oxide layer; patterning the doped polysilicon layer and the tunnel oxide layer to selectively remove the doped polysilicon layer and the tunnel oxide layer on the second region; The step of forming a silicon oxide dielectric layer on the second region includes: The second region is subjected to a first laser treatment, so that the silicon in the second region of the silicon substrate reacts with air to form the silicon-oxygen dielectric layer.

2. The method for preparing a solar cell according to claim 1, wherein: After patterning the doped polysilicon layer and the tunnel oxide layer, the method for preparing a solar cell further includes: removing the silicon oxide dielectric layer by wet etching to expose the second region; A back passivation layer is formed on the second region.

3. The method for preparing a solar cell according to claim 1, wherein: The laser power of the first laser treatment is 5-20W.

4. The method for preparing a solar cell according to claim 1, wherein: The linear speed of the first laser treatment is 67000~73000 mm / s.

5. The method for preparing a solar cell according to claim 1, wherein: The step of sequentially forming a tunneling oxide layer and a doped polysilicon layer on the first surface comprises: forming the tunneling oxide layer on the first surface so that the tunneling oxide layer covers the first region and the silicon oxide dielectric layer; forming an intrinsic amorphous silicon layer on a side of the tunnel oxide layer facing away from the silicon substrate; The intrinsic amorphous silicon layer is subjected to diffusion treatment to transform the intrinsic amorphous silicon layer into the doped polysilicon layer, and doped silicon glass is formed on a side of the doped polysilicon layer away from the tunnel oxide layer.

6. The method for preparing a solar cell according to claim 5, wherein: The step of patterning the doped polysilicon layer and the tunnel oxide layer comprises: performing a second laser treatment on a portion of the doped silicon glass located on the second region to remove the portion of the doped silicon glass located on the second region; The portion of the doped polysilicon layer located on the second region and the portion of the tunnel oxide layer located on the second region are removed by wet etching.

7. The method for preparing a solar cell according to any one of claims 1 to 6, characterized in that: The thickness of the silicon oxide dielectric layer is 8-10 nm.

8. The method for preparing a solar cell according to any one of claims 1 to 6, characterized in that: Before forming the silicon-oxygen dielectric layer on the second region, the method for preparing the solar cell further includes: The first surface is polished.

9. A solar cell, characterized in that: The solar cell is prepared by the method for preparing a solar cell according to any one of claims 1 to 8.

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