Display substrate and display device

Abstract

A display substrate comprises a substrate, at least one first display unit located in a display island area and a plurality of second display units located in a second display area and arranged in an array. The second display area is located on at least one side of the first display area. The first display area comprises a plurality of display island areas and a plurality of light-transmitting areas which are arranged in an array mode. The first display unit comprises N first light-emitting elements and M first pixel circuits, M and N are integers larger than 1, and M is smaller than N. The at least one first pixel circuit is connected with the at least two first light-emitting elements. The second display unit comprises M second light-emitting elements and M second pixel circuits, and the M second pixel circuits are connected with the M second light-emitting elements in a one-to-one correspondence mode. The arrangement mode of the N first light-emitting elements of the first display unit is different from the arrangement mode of the M second light-emitting elements of the second display unit.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of display technologies, and particularly to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices, which have the advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, lightness, thinness, bendability, and low cost. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this application. This overview is not intended to limit the scope of protection of the claims.

[0004] Embodiments of the present application provide a display substrate and a display device.

[0005] On the one hand, an embodiment of the present application provides a display substrate, including: a substrate. The substrate includes: a first display area and a second display area located on at least one side of the first display area; the first display area includes: a plurality of display island areas and a plurality of light-transmitting areas arranged in an array. The display island area includes: at least one first display unit; the at least one first display unit includes: N first light-emitting elements and M first pixel circuits, where both M and N are integers greater than 1, and M is less than N; at least one of the M first pixel circuits in the M first pixel circuits is connected to at least two first light-emitting elements, and is configured to drive the at least two first light-emitting elements to emit light. The second display area includes: a plurality of second display units arranged in an array; at least one of the plurality of second display units includes: M second light-emitting elements and M second pixel circuits, and the M second pixel circuits are connected to the M second light-emitting elements in a one-to-one correspondence. The arrangement of the N first light-emitting elements of the at least one first display unit is different from the arrangement of the M second light-emitting elements of the at least one second display unit.

[0006] In some exemplary embodiments, in the first display area, the display island areas and the light-transmitting areas are alternately arranged and aligned in a first direction, and the display island areas and the light-transmitting areas are alternately arranged and aligned in a second direction; wherein, the first direction intersects with the second direction.

[0007] In some exemplary embodiments, the M first pixel circuits of the at least one first display unit and the M second pixel circuits of the at least one second display unit are aligned in the first direction or the second direction. Wherein, the first direction intersects with the second direction.

[0008] In some exemplary embodiments, the at least one first display unit includes: six first light-emitting elements and four first pixel circuits, and the four first pixel circuits are arranged in sequence along a first direction. The six first light-emitting elements include: two first light-emitting elements that emit a first color light, two first light-emitting elements that emit a second color light, and two first light-emitting elements that emit a third color light. The two first light-emitting elements that emit the first color light are connected to the same first pixel circuit, the two first light-emitting elements that emit the third color light are connected to the same first pixel circuit, and the two first light-emitting elements that emit the second color light are electrically connected to two first pixel circuits in a one-to-one correspondence.

[0009] In some exemplary embodiments, the six first light-emitting elements are divided into two groups of first light-emitting elements, and the two groups of first light-emitting elements are arranged in sequence along the first direction. Each group of first light-emitting elements includes: one first light-emitting element that emits a first color light, one first light-emitting element that emits a second color light, and one first light-emitting element that emits a third color light. In each group of first light-emitting elements, the first light-emitting element that emits the first color light and the first light-emitting element that emits the second color light are arranged in sequence along a second direction, and the first light-emitting element that emits the third color light is located on the same side of the first light-emitting element that emits the first color light and the first light-emitting element that emits the second color light along the first direction. The second direction intersects the first direction.

[0010] In some exemplary embodiments, the six first light-emitting elements are divided into two groups of first light-emitting elements, and the two groups of first light-emitting elements are arranged in sequence along the first direction. Each group of first light-emitting elements includes: one first light-emitting element that emits a first color light, one first light-emitting element that emits a second color light, and one first light-emitting element that emits a third color light. In each group of first light-emitting elements, the first light-emitting element that emits the first color light, the first light-emitting element that emits the second color light, and the first light-emitting element that emits the third color light are arranged in sequence along the first direction.

[0011] In some exemplary embodiments, within the first display area, the connection sequences of the first pixel circuits and the first light-emitting elements of the first display units in adjacent row display island areas are different.

[0012] In some exemplary embodiments, in the first display area, four first pixel circuits in the display island area of the f-th row may be sequentially connected to two first light-emitting elements that emit the first color light, one first light-emitting element that emits the second color light, two first light-emitting elements that emit the third color light, and another first light-emitting element that emits the second color light. Four first pixel circuits of the first display unit in the display island area of the (f - 1)-th row may be sequentially connected to two first light-emitting elements that emit the third color light, one first light-emitting element that emits the second color light, two first light-emitting elements that emit the first color light, and another first light-emitting element that emits the second color light; where f is an integer greater than 1.

[0013] In some exemplary embodiments, the at least one second display unit includes: four second light-emitting elements and four second pixel circuits; the four second pixel circuits are arranged in sequence along the first direction. The four second light-emitting elements include: one second light-emitting element that emits the first color light, two second light-emitting elements that emit the second color light, and one second light-emitting element that emits the third color light; the second light-emitting element that emits the first color light and the second light-emitting element that emits the third color light are arranged in the same row, and the two second light-emitting elements that emit the second color light are arranged in the same row; along the first direction, the second light-emitting element that emits the first color light, the second light-emitting element that emits the second color light, the second light-emitting element that emits the third color light, and the second light-emitting element that emits the second color light are arranged in sequence.

[0014] In some exemplary embodiments, the first color light is red light, the second color light is green light, and the third color light is blue light.

[0015] In some exemplary embodiments, M first pixel circuits of the first display unit in the display island area are connected to a first scan transmission segment and a second scan transmission segment that extend along the first direction; the first scan transmission segment is configured to transmit a first scan signal, and the second scan transmission segment is configured to transmit a second scan signal. The first scan transmission segments in the display island areas that are in the same row and adjacent are connected by a first scan connection segment; the second scan transmission segments in the display island areas that are in the same row and adjacent are connected by a second scan connection segment. The second scan connection segment is located on a side of the first scan connection segment away from the substrate, and at least a part of the orthographic projection of the first scan connection segment on the substrate overlaps with the orthographic projection of the second scan connection segment on the substrate.

[0016] In some exemplary embodiments, the first pixel circuit of the first display unit in the same row display island region is further connected to a first reset control line and a first initial signal line extending along the first direction. The first initial signal line is located on a side of the first reset control line away from the substrate. The first scan connection segment is located on a side of the first initial signal line away from the substrate. The orthographic projection of the first scan connection segment on the substrate at least partially overlaps with the orthographic projection of the first initial signal line on the substrate. The orthographic projection of the first initial signal line on the substrate at least partially overlaps with the orthographic projection of the first reset control line on the substrate.

[0017] In some exemplary embodiments, M first pixel circuits of the first display unit in the display island region are connected to a light emission control transmission segment extending along the first direction. The light emission control transmission segment is configured to transmit a light emission control signal. The light emission control transmission segments in the display island regions that are adjacent and in the same row are connected by a light emission control connection segment. The light emission control connection segment and the first scan connection segment are located on two sides in the second direction of the light transmission region between the adjacent display island regions. The second direction intersects with the first direction.

[0018] In some exemplary embodiments, the first pixel circuit of the first display unit in the same row display island region is further connected to a second reset control line and a second initial signal line extending along the first direction. The second initial signal line is located on a side of the second reset control line away from the substrate. The light emission control connection segment is located on a side of the second initial signal line away from the substrate. The orthographic projection of the light emission control connection segment on the substrate at least partially overlaps with the orthographic projection of the second initial signal line on the substrate. The orthographic projection of the second initial signal line on the substrate at least partially overlaps with the orthographic projection of the second reset control line on the substrate.

[0019] In some exemplary embodiments, M first pixel circuits of the first display unit in the display island region are further connected to an initial signal transmission segment extending along the first direction. The initial signal transmission segment is configured to transmit a third initial signal. The initial signal transmission segments in the display island regions that are adjacent and in the same row are connected by an initial signal connection segment. The light emission control connection segment is located on a side of the initial signal connection segment away from the substrate. The orthographic projection of the initial signal connection segment on the substrate partially overlaps with the orthographic projection of the light emission control connection segment on the substrate.

[0020] In some exemplary embodiments, a plurality of first pixel circuits in the display island area located in the k-th row and h-th column are centrosymmetric with respect to the connection point of the display island area in the k-th row and h-th column and the display island area in the (k + 1)-th row and (h + 1)-th column; where k and h are both integers greater than 0.

[0021] In some exemplary embodiments, in the first display area, the i-th row of first pixel circuits in the display island area located in the k-th row share a first reset control line with the (i - 1)-th row of first pixel circuits in the display island area located in the (k - 1)-th row, and the (i + e)-th row of first pixel circuits in the display island area located in the k-th row share a second reset control line with the (i + e + 1)-th row of first pixel circuits in the display island area located in the (k + 1)-th row, where i is an integer greater than 1 and e is an integer greater than or equal to 0.

[0022] In some exemplary embodiments, in the first display area, the i-th row of first pixel circuits in the display island area located in the k-th row share a first initial signal line with the (i - 1)-th row of first pixel circuits in the display island area located in the (k - 1)-th row, and the (i + e)-th row of first pixel circuits in the display island area located in the k-th row share a second initial signal line with the (i + e + 1)-th row of first pixel circuits in the display island area located in the (k + 1)-th row.

[0023] In some exemplary embodiments, the display island area includes two first display units, and the two first display units are arranged along a first direction or along a second direction. The first direction intersects the second direction.

[0024] On the other hand, this embodiment provides a display device, including the display substrate as described above, and a sensor located on the non-display surface side of the display substrate, and the orthographic projection of the sensor on the display substrate overlaps at least partially with the first display area of the display substrate.

[0025] On the other hand, this embodiment provides a display substrate, including: a substrate. The substrate includes: a first display area and a second display area located on at least one side of the first display area; the first display area includes: a plurality of display island areas and a plurality of light-transmitting areas arranged in an array. The display island area includes: at least one group of first pixel circuits and a plurality of first light-emitting elements, each group of first pixel circuits includes M first pixel circuits, and at least one of the M first pixel circuits is connected to at least two first light-emitting elements; M is an integer greater than 1. The second display area includes: a plurality of groups of second pixel circuits and a plurality of second light-emitting elements, each group of second pixel circuits includes M second pixel circuits, and at least one second pixel circuit is connected to at least one second light-emitting element. The number of first light-emitting elements connected to each group of first pixel circuits is greater than the number of second light-emitting elements connected to each group of second pixel circuits; the arrangement density of the second pixel circuits in the second display area is greater than or equal to the arrangement density of the first pixel circuits in the first display area. The first pixel circuits and the second pixel circuits in the same column are connected to the same data line.

[0026] In some exemplary embodiments, each group of first pixel circuits includes four first pixel circuits, and the four first pixel circuits are connected to six first light-emitting elements. The six first light-emitting elements include: two first light-emitting elements emitting a first color light, two first light-emitting elements emitting a second color light, and two first light-emitting elements emitting a third color light. Each group of second pixel circuits includes four second pixel circuits, and the four second pixel circuits are connected to four second light-emitting elements. The four second light-emitting elements include one second light-emitting element emitting a first color light, two second light-emitting elements emitting a second color light, and one second light-emitting element emitting a third color light.

[0027] In some exemplary embodiments, the arrangement manner of the six first light-emitting elements is different from the arrangement manner of the four second light-emitting elements.

[0028] In some exemplary embodiments, the arrangement density of the first pixel circuits in the first display area in the first direction is 0.4 to 0.6 times that of the second pixel circuits in the second display area in the first direction; the arrangement density of the first pixel circuits in the first display area in the second direction is 0.4 to 0.6 times that of the second pixel circuits in the second display area in the second direction.

[0029] Other features and advantages of the present application will be described in the subsequent specification, and, in part, will be obvious from the specification, or will be understood by implementing the present application. Other advantages of the present application can be realized and obtained through the solutions described in the specification and the drawings. Description of the Drawings

[0030] The accompanying drawings are used to provide an understanding of the technical solutions of the present application and form a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solutions of the present application and do not constitute a limitation on the technical solutions of the present application.

[0031] Figure 1 Schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0032] Figure 2 Equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0033] Figure 3 For Figure 2 Working timing diagram of the provided pixel circuit;

[0034] Figure 4 Partial schematic diagram of a display area according to at least one embodiment of the present disclosure;

[0035] Figure 5 Schematic diagram of the signal correspondence relationship between a first display area and a second display area according to at least one embodiment of the present disclosure;

[0036] Figure 6 Partial top view schematic diagram of a first display area according to at least one embodiment of the present disclosure;

[0037] Figure 7 For Figure 6 Schematic diagram of the first display area after forming an occlusion layer in ;

[0038] Fig. 8A For Figure 6 Schematic diagram of the first display area after forming a first semiconductor layer in ;

[0039] Figure 8B For Fig. 8A Schematic diagram of the first semiconductor layer in ;

[0040] Fig.9A For Figure 6 Schematic diagram of the first display area after forming a first conductive layer in ;

[0041] Fig. 9B For Fig.9A Schematic diagram of the first conductive layer and the first semiconductor layer in ;

[0042] Fig. 9C For Fig.9A Schematic diagram of the first conductive layer in ;

[0043] Fig. 10A For Figure 6 Schematic diagram of the first display area after forming a second conductive layer in ;

[0044] Fig. 10B For Fig. 10ASchematic diagram of the second conductive layer in;

[0045] Fig.11A is Figure 6 Schematic diagram of the first display area after forming the second semiconductor layer in;

[0046] Fig. 11B is Fig.11A Schematic diagram of the second semiconductor layer in;

[0047] Fig. 12A is Figure 6 Schematic diagram of the first display area after forming the third conductive layer in;

[0048] Fig. 12B is Fig. 12A Schematic diagram of the third conductive layer in;

[0049] Fig.13 is Figure 6 Schematic diagram of the first display area after forming the fifth insulating layer in;

[0050] Fig.14A is Figure 6 Schematic diagram of the first display area after forming the fourth conductive layer in;

[0051] Fig. 14B is Fig.14A Schematic diagram of the fourth conductive layer in;

[0052] Fig.15 is Figure 6 Schematic diagram of the first display area after forming the seventh insulating layer in;

[0053] Fig.16A is Figure 6 Schematic diagram of the first display area after forming the fifth conductive layer in;

[0054] Fig. 16B is Fig.16A Schematic diagram of the fifth conductive layer in;

[0055] Fig.17 is Figure 6 Schematic diagram of the first display area after forming the eighth insulating layer in;

[0056] Fig.18A is Figure 6 Schematic diagram of the first display area after forming the sixth conductive layer in;

[0057] Fig.18B is Fig.18A Schematic diagram of the sixth conductive layer in;

[0058] Fig.19 is Figure 6 Schematic diagram of the first display area after forming the ninth insulating layer in;

[0059] Fig. 20A is Figure 6 A schematic diagram of the first display area after forming an anode layer in

[0060] Fig. 20B is Fig. 20A A schematic diagram of the anode layer in

[0061] Fig.21 is Figure 6 A schematic diagram of the light-transmitting area in

[0062] Fig. 22 Another partial top view schematic diagram of the first display area of at least one embodiment of the present disclosure;

[0063] Fig.23 is Fig. 22 A schematic diagram of the first display area after forming an occlusion layer in

[0064] Fig.24A is Fig. 22 A schematic diagram of the first display area after forming a first semiconductor layer in

[0065] Fig. 24B is Fig.24A A schematic diagram of the first semiconductor layer in

[0066] Fig.25A is Fig. 22 A schematic diagram of the first display area after forming a first conductive layer in

[0067] Fig.25B is Fig.25A A schematic diagram of the first conductive layer in

[0068] Fig.26A is Fig. 22 A schematic diagram of the first display area after forming a second conductive layer in

[0069] Fig.26B is Fig.26A A schematic diagram of the second conductive layer in

[0070] Fig.27A is Fig. 22 A schematic diagram of the first display area after forming a second semiconductor layer in

[0071] Fig.27B is Fig.27A A schematic diagram of the second semiconductor layer in

[0072] Fig.28A is Fig. 22 A schematic diagram of the first display area after forming a third conductive layer in

[0073] Fig.28B is Fig.28A Schematic diagram of the third conductive layer in

[0074] Fig.29A is Fig. 22 Schematic diagram of the first display area after forming the fourth conductive layer in

[0075] Fig.29B is Fig.29A Schematic diagram of the fourth conductive layer in

[0076] Fig. 30A is Fig. 22 Schematic diagram of the first display area after forming the fifth conductive layer in

[0077] Fig. 30B is Fig. 30A Schematic diagram of the fifth conductive layer in

[0078] Fig.31A is Fig. 22 Schematic diagram of the first display area after forming the sixth conductive layer in

[0079] Fig.31B is Fig.31A Schematic diagram of the sixth conductive layer in

[0080] Fig.32 is Fig. 22 Schematic diagram of the first display area after forming the anode layer in

[0081] Fig.33 is Fig. 22 Schematic diagram of the light-transmitting area in

[0082] Fig.34 Another schematic diagram of the signal correspondence between the first display area and the second display area of at least one embodiment of the present disclosure;

[0083] Fig.35 Another partial schematic diagram of the display area of at least one embodiment of the present disclosure;

[0084] Fig.36 Another partial top view schematic diagram of the first display area of at least one embodiment of the present disclosure;

[0085] Fig.37A is Fig.36 Schematic diagram of the first display area after forming the anode layer in

[0086] Fig.37B is Fig.37A Schematic diagram of the anode layer in

[0087] Fig.38 Another partial schematic diagram of the display area of at least one embodiment of the present disclosure;

[0088] Fig.39 Another partial schematic diagram of the display area according to at least one embodiment of the present disclosure;

[0089] Fig.40 Schematic diagram of a display device according to at least one embodiment of the present disclosure. Detailed implementation manners

[0090] The embodiments of the present application will be described in detail below with reference to the accompanying drawings. The present application describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those of ordinary skill in the art that there can be more embodiments and implementation solutions within the scope covered by the embodiments described in the present application. Although many possible feature combinations are shown in the drawings and discussed in the embodiments, many other combination ways of the disclosed features are also possible. Unless specifically restricted, any feature or element of any embodiment can be combined with any other feature or element in any other embodiment, or can replace any other feature or element in any other embodiment.

[0091] The present application includes and contemplates combinations with features and elements known to those of ordinary skill in the art. The embodiments, features, and elements already disclosed in the present application can also be combined with any conventional features or elements to form a unique invention solution. Any feature or element of any embodiment can also be combined with features or elements from other invention solutions to form another unique invention solution. Therefore, it should be understood that any feature shown or discussed in the present application can be implemented alone or in any appropriate combination. Therefore, the embodiments are not subject to other restrictions except those made according to the appended claims and their equivalents. In addition, various modifications and changes can be made within the scope of the protection of the appended claims.

[0092] In addition, when describing representative embodiments, the specification may have presented a method or process as a specific sequence of steps. However, to the extent that the method or process does not depend on the specific sequence of the steps described herein, the method or process should not be limited to the specific sequence of steps described. As will be understood by those of ordinary skill in the art, other step sequences are also possible. Therefore, the specific sequence of steps set forth in the specification should not be construed as a limitation on the claims. In addition, the claims directed to the method or process should not be limited to performing their steps in the order written, and those skilled in the art can easily understand that these orders can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0093] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the present application.

[0094] In addition, the terms "first", "second", etc. are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", etc. may explicitly or implicitly include at least one such feature.

[0095] In the description of the present application, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise clearly defined.

[0096] In the present application, unless otherwise clearly specified and limited, the terms "mounted", "connected", "connected to", "fixed", etc. shall be understood in a broad sense. For example, "connected" may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and may be the communication inside two elements or the interaction relationship between two elements, unless otherwise clearly limited. For those of ordinary skill in the art, the meanings of the above terms in the present application can be understood according to the circumstances.

[0097] In the present application, "electrically connected" includes the case where the components are connected together through an element having a certain electrical effect. There is no particular limitation on the "element having a certain electrical effect" as long as it can transmit the electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0098] In this application, unless otherwise clearly specified and defined, the first feature being "on" or "under" the second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may mean that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "underneath" the second feature may mean that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.

[0099] In this application, a transistor refers to an element that includes at least three terminals: a gate, a drain, and a source. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this application, the channel region refers to the region where current mainly flows.

[0100] In this application, the first pole can be the drain, the second pole can be the source, or the first pole can be the source and the second pole can be the drain. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this application, the "source" and "drain" can be interchanged. Additionally, the gate can also be referred to as the control pole.

[0101] In this application, "parallel" means that the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes the state where the angle is greater than -5° and less than 5°. Additionally, "perpendicular" means that the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes the state where the angle is greater than 85° and less than 95°.

[0102] In this application, shapes such as circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined and can be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons, or approximate hexagons. There may be some small deformations caused by tolerances, such as chamfers, rounded edges, and deformations.

[0103] The "light transmittance" in this application refers to the ability of light to pass through a medium, which is the percentage of the light flux passing through a transparent or translucent body to its incident light flux.

[0104] The terms "about" and "substantially" in this application mean that the boundaries are not strictly defined and allow for situations within the process and measurement errors. In this application, "the same" can include both exactly the same and substantially the same situations, and "substantially the same" means that the numerical difference is within 10%.

[0105] In the present application, A extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, line segment or strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the present application, "A extends along direction B" means "the main part of A extends along direction B.

[0106] With the continuous development of display technology, cameras are usually installed on display devices to meet the needs of shooting or face recognition. In order to maximize the screen-to-body ratio, technologies such as bangs screen, water drop screen, and in-screen hole have appeared one after another. These technologies are to reduce the area occupied by the camera by digging holes in part of the display area and placing a camera under the hole area, thereby increasing the screen-to-body ratio. However, the above technology requires digging out part of the display area, which will cause part of the display screen to be unable to be displayed, and the screen-to-body ratio cannot be further increased. In order to avoid punching holes in the display area and make a true full screen possible while ensuring the practicality of the display substrate, the pixel circuit external method or the pixel circuit internal method is usually used in the camera area under the screen.

[0107] The external pixel circuit method refers to setting the pixel circuit connected to the light-emitting element in the under-screen camera area in the normal display area, and improving the light transmittance of the under-screen camera area by arranging the light-emitting element and the pixel circuit separately. Since there is no pixel circuit in the under-screen camera area, there is no other light-shielding layer in this area except the anode of the light-emitting element, so a higher light transmittance can be achieved. However, in this way, the pixel circuit and the light-emitting element need to be electrically connected through a conductive connecting wire. Limited by the arrangement space of the conductive connecting wire, the size (such as the aperture) of the under-screen camera area of ​​the display substrate using the external pixel circuit method is limited. Increasing the aperture of the under-screen camera area usually requires increasing the mask process of the conductive connecting wire, resulting in increased costs. Moreover, the material of the conductive connecting wire is usually a transparent conductive material, such as indium tin oxide (ITO). Due to the large square resistance of ITO, the load of the conductive connecting wire is large, which easily affects the brightness of the light-emitting element in the under-screen camera area, causing the brightness of the under-screen camera area to decrease, thereby causing poor display in the under-screen camera area, such as vertical display poor (Mura). Moreover, the use of conductive connecting wires tends to introduce more vias, which in turn reduces the aperture ratio of the under-screen camera area and is not conducive to optimizing the light transmittance of the under-screen camera area.

[0108] The method of integrating pixel circuits means that light-emitting elements and the pixel circuits connected to the light-emitting elements are arranged in the area of the under-screen camera. Compared with the method of externally arranging pixel circuits, for the method of integrating pixel circuits, the electrical connection between the pixel circuits and the light-emitting elements in the area of the under-screen camera does not require long conductive connection lines, which can avoid the display defects in the area of the under-screen camera caused by the conductive connection lines. Moreover, the method of integrating pixel circuits does not limit the size of the area of the under-screen camera and can support a large-aperture area of the under-screen camera. However, for complex pixel circuits, due to numerous wiring, it is difficult to improve the light transmittance of the area of the under-screen camera through the layout compression of the pixel circuits, resulting in the inability to meet the light transmittance requirements for functions such as under-screen photography or under-screen face recognition.

[0109] For the method of integrating pixel circuits, by deleting some of the light-emitting elements and pixel circuits in the area of the under-screen camera, the remaining light-emitting elements and pixel circuits can be not compressed, so as to meet the light transmittance requirements for under-screen functions. However, when improving the light transmittance by deleting some of the light-emitting elements and pixel circuits in the area of the under-screen camera, it is easy to affect the display effect.

[0110] This embodiment provides a display substrate and a display device, which can not only improve the light transmittance of the area of the under-screen camera, but also make up for the loss of the display effect caused by deleting some of the light-emitting elements and pixel circuits in the area of the under-screen camera.

[0111] This embodiment provides a display substrate, including: a substrate, at least one first display unit located in a display island area, and a plurality of second display units located in a second display area and arranged in an array. The substrate includes: a first display area and a second display area located on at least one side of the first display area. The first display area includes a plurality of display island areas and a plurality of light-transmitting areas arranged in an array. At least one first display unit includes: N first light-emitting elements and M first pixel circuits, both M and N are integers greater than 1, and M is less than N. At least one of the M first pixel circuits in the M first pixel circuits is connected to at least two first light-emitting elements and is configured to drive the at least two first light-emitting elements to emit light. At least one second display unit includes: M second light-emitting elements and M second pixel circuits, and the M second pixel circuits are connected to the M second light-emitting elements in a one-to-one correspondence. The arrangement manner of the N first light-emitting elements of at least one first display unit is different from the arrangement manner of the M second light-emitting elements of at least one second display unit.

[0112] In some examples, the shapes and sizes of the plurality of display island areas in the first display area may be substantially the same, and the shapes and sizes of the plurality of light-transmitting areas may be substantially the same. The light-transmitting areas can be formed by deleting the first pixel circuits and the first light-emitting elements, and the number of the first pixel circuits corresponding to the deleted light-transmitting areas may be less than or equal to the total number of the first pixel circuits included in the plurality of display island areas.

[0113] In some examples, at least one first pixel circuit in the first display unit may be connected to at least two first light-emitting elements, and at least one first pixel circuit may be connected to at least one first light-emitting element. For example, the first display unit may include four first pixel circuits, where two of the first pixel circuits may be connected to the first light-emitting elements in a one-driving-two manner, and two of the first pixel circuits may be connected to the first light-emitting elements in a one-driving-one manner. In this example, one-driving-F means that one pixel circuit is connected to F light-emitting elements, and the pixel circuit drives the F connected light-emitting elements to emit light, where F is an integer greater than or equal to 1. For example, one-driving-one means that one pixel circuit is connected to one light-emitting element and drives the connected one light-emitting element to emit light; one-driving-two means that one pixel circuit is connected to two light-emitting elements and drives the connected two light-emitting elements to emit light. However, this embodiment is not limited thereto. In other examples, the first pixel circuits in the first display unit may be connected to the first light-emitting elements in other one-driving-many manners such as one-driving-three or one-driving-four.

[0114] In some examples, the second pixel circuits in the second display unit may be connected to the second light-emitting elements in a one-driving-one manner. The arrangement density of the second pixel circuits in the second display area may be greater than or equal to the arrangement density of the first pixel circuits in the first display area. For example, the arrangement density of the first pixel circuits in the first display area in the first direction may be 0.4 to 0.6 times that of the second pixel circuits in the second display area in the first direction, such as 0.45 to 0.55, for example, it may be approximately 0.5; or, the arrangement density of the first pixel circuits in the first display area in the column direction may be 0.4 to 0.6 times that of the second pixel circuits in the second display area in the column direction, such as 0.45 to 0.55, for example, it may be approximately 0.5. By deleting some of the first pixel circuits in the first display area in this example, the light transmittance of the first display area can be improved.

[0115] In some examples, the light transmittance of the second display area may be less than the light transmittance of the first display area.

[0116] The display substrate provided in this embodiment adopts the method of integrating pixel circuits, deletes the first pixel circuits and the first light-emitting elements in the first display area to form a light-transmitting area, and sets the arrangement manner of the first light-emitting elements to be different from that of the second light-emitting elements, which can, on the basis of improving the light transmittance of the first display area, ensure the display effect of the first display area and make up for the loss of the display effect caused by deleting some of the light-emitting elements and pixel circuits in the first display area.

[0117] In some exemplary embodiments, each display island region may include a first display unit. In other examples, at least one display island region may include multiple first display units, such as two first display units. The two first display units within the display island region may be arranged along a first direction, or may be arranged along a second direction. Among them, the first direction may intersect the second direction. For example, the first direction may be perpendicular to the second direction. In some examples, the first direction may be parallel to the row direction of the display island regions arranged in an array, and the second direction may be parallel to the column direction of the display island regions arranged in an array. This embodiment does not limit this.

[0118] In some exemplary embodiments, within the first display region, multiple display island regions and multiple light-transmitting regions are alternately arranged and aligned in the first direction, and multiple display island regions and multiple light-transmitting regions are alternately arranged and aligned in the second direction. Among them, the first direction may intersect the second direction. However, this embodiment does not limit this. In other examples, in the second direction, multiple display island regions may be continuously arranged with a dislocation. The arrangement manner of the display island regions and the light-transmitting regions in the first display region in this example may be beneficial to improving the light transmittance of the first display region.

[0119] In this example, the alternate arrangement of A and B in direction C means that along direction C, A and B are arranged at intervals, that is, along direction C, they are periodically arranged in the order of AB. The aligned arrangement of A and B in direction C means that the midlines of A and B along the direction perpendicular to direction C are substantially coincident, and the extension lines of the edges of A and B may be substantially coincident. The dislocation arrangement of A and B in direction C means that the midlines of A and B along the direction perpendicular to direction C are substantially parallel and do not coincide.

[0120] In some exemplary embodiments, the M first pixel circuits of at least one first display unit and the M second pixel circuits of at least one second display unit are arranged in alignment in the first direction or the second direction. In this example, the first pixel circuits in the first display region and the second pixel circuits in the second display region may share signal traces extending along the first direction (such as including a first scan line, a second scan line, a light emission control line, etc.), and may share signal traces extending along the second direction (such as including a data line, etc.), thereby facilitating the routing arrangement.

[0121] In some exemplary embodiments, at least one first display unit may include: six first light-emitting elements and four first pixel circuits, and the four first pixel circuits are arranged in sequence along a first direction. The six first light-emitting elements include: two first light-emitting elements that emit a first color light, two first light-emitting elements that emit a second color light, and two first light-emitting elements that emit a third color light. The two first light-emitting elements that emit the first color light are connected to the same first pixel circuit, the two first light-emitting elements that emit the third color light are connected to the same first pixel circuit, and the two first light-emitting elements that emit the second color light are electrically connected to two first pixel circuits in a one-to-one correspondence. For example, the first color light is red light, the second color light is green light, and the third color light is blue light. The first light-emitting elements in the first display area of this example can adopt an RGB arrangement, which is beneficial to improving the display effect of the first display area.

[0122] In some exemplary embodiments, the six first light-emitting elements of the first display unit may be divided into two groups of first light-emitting elements, and the two groups of first light-emitting elements are arranged in sequence along the first direction. Each group of first light-emitting elements includes: one first light-emitting element that emits a first color light, one first light-emitting element that emits a second color light, and one first light-emitting element that emits a third color light. In each group of first light-emitting elements, the first light-emitting element that emits the first color light and the first light-emitting element that emits the second color light may be arranged in sequence along a second direction, and the first light-emitting element that emits the third color light may be located on the same side of the first light-emitting element that emits the first color light and the first light-emitting element that emits the second color light along the first direction. Alternatively, in each group of first light-emitting elements, the first light-emitting element that emits the first color light, the first light-emitting element that emits the second color light, and the first light-emitting element that emits the third color light may be arranged in sequence along the first direction. The arrangement of the first light-emitting elements in the first display area of this example can optimize the display effect of the first display area.

[0123] In some exemplary embodiments, at least one second display unit may include: four second light-emitting elements and four second pixel circuits; the four second pixel circuits are arranged in sequence along a first direction. The four second light-emitting elements may include: one second light-emitting element that emits first-color light, two second light-emitting elements that emit second-color light, and one second light-emitting element that emits third-color light. The second light-emitting element that emits first-color light and the second light-emitting element that emits third-color light are arranged in the same row, and the two second light-emitting elements that emit second-color light are arranged in the same row; along the first direction, the second light-emitting element that emits first-color light, the second light-emitting element that emits second-color light, the second light-emitting element that emits third-color light, and the second light-emitting element that emits second-color light may be arranged in sequence. For example, the first-color light is red light, the second-color light is green light, and the third-color light is blue light. The second display area in this example may adopt an RGBG arrangement manner, which can ensure the display effect of the second display area.

[0124] In some exemplary embodiments, within the first display area, the connection sequence of the first pixel circuits of the first display units in adjacent row display island areas to the first light-emitting elements may be different. In some examples, the four first pixel circuits of the first display unit located in the f-th row display island area may be sequentially connected to two first light-emitting elements that emit first-color light, one first light-emitting element that emits second-color light, two first light-emitting elements that emit third-color light, and another first light-emitting element that emits second-color light. The four first pixel circuits of the first display unit located in the (f - 1)-th row display island area may be sequentially connected to two first light-emitting elements that emit third-color light, one first light-emitting element that emits second-color light, two first light-emitting elements that emit first-color light, and another first light-emitting element that emits second-color light. Wherein, f is an integer greater than 1. The connection manner of the first pixel circuits and the first light-emitting elements in the display island area in this example may be beneficial to optimizing the display uniformity of the first display area.

[0125] In some exemplary embodiments, in a first display area, M first pixel circuits of first display units in a display island area are connected to a first scan transmission segment and a second scan transmission segment extending along a first direction. The first scan transmission segment is configured to transmit a first scan signal, and the second scan transmission segment is configured to transmit a second scan signal. The first scan transmission segments in adjacent display island areas in the same row can be connected through a first scan connection segment, and the second scan transmission segments in adjacent display island areas in the same row can be connected through a second scan connection segment. For example, the first scan line may include a first scan transmission segment and a first scan connection segment that are connected at intervals along the first direction, and the first scan transmission segment and the first scan connection segment are located in different film layers; the second scan line may include a second scan transmission segment and a second scan connection segment that are connected at intervals along the first direction, and the second scan transmission segment and the second scan connection segment are located in different film layers. The second scan connection segment may be located on a side of the first scan connection segment away from the substrate, and a positive projection of the first scan connection segment on the substrate and a positive projection of the second scan connection segment on the substrate may at least partially overlap. For example, the first scan transmission segment may be located in a first conductive layer, and the first scan connection segment may be located in a fourth conductive layer; the second scan transmission segment may be located in a third conductive layer, and the second scan connection segment may be located in a fifth conductive layer. In this example, the transmission traces of the first scan signal and the second scan signal are segmented and cross-layer transferred, so that the first scan connection segment and the second scan connection segment can be overlapped for wiring, which is beneficial to increasing the area of the light-transmitting area, and further improving the light transmittance of the first display area.

[0126] In some exemplary embodiments, the first pixel circuits of the first display units in the same row display island area may also be connected to a first reset control line and a first initial signal line extending along the first direction. The first initial signal line may be located on a side of the first reset control line away from the substrate. The first scan connection segment may be located on a side of the first initial signal line away from the substrate. A positive projection of the first scan connection segment on the substrate and a positive projection of the first initial signal line on the substrate may at least partially overlap, and a positive projection of the first initial signal line on the substrate and a positive projection of the first reset control line on the substrate may at least partially overlap. For example, the first initial signal line may be located in a third conductive layer, the first reset control line may be located in a first conductive layer, and the first scan connection segment may be located in a fourth conductive layer. In this example, overlapping wiring of the first reset control line, the first initial signal line, and the first scan connection segment can be beneficial to increasing the area of the light-transmitting area, thereby improving the light transmittance of the first display area.

[0127] In some exemplary embodiments, M first pixel circuits of the first display units in the display island region may be connected to a light-emitting control transmission segment extending in a first direction; the light-emitting control transmission segment may be configured to transmit a light-emitting control signal. The light-emitting control transmission segments in the display island regions that are in the same row and adjacent to each other may be connected through a light-emitting control connection segment. For example, the light-emitting control line may include a light-emitting control transmission segment and a light-emitting control connection segment that are connected at intervals in the first direction, and the light-emitting control transmission segment and the light-emitting control connection segment are located in different film layers. For instance, the light-emitting control transmission segment may be located in a first conductive layer, and the light-emitting control connection segment may be located in a fourth conductive layer. The light-emitting control connection segment and the first scan connection segment may be located on both sides in the column direction of the light-transmitting region between the adjacent display island regions. In this example, by arranging the first scan connection segment and the light-emitting control connection segment to bypass the light-transmitting region from both sides in the column direction of the light-transmitting region, the wiring space can be optimized, which is beneficial to increasing the area of the light-transmitting region, thereby improving the light transmittance of the first display region.

[0128] In some exemplary embodiments, the first pixel circuits of the first display units in the display island regions in the same row may also be connected to a second reset control line and a second initial signal line that extend in the first direction. The second initial signal line may be located on a side of the second reset control line away from the substrate; the light-emitting control connection segment may be located on a side of the second initial signal line away from the substrate. The orthographic projection of the light-emitting control connection segment on the substrate and the orthographic projection of the second initial signal line on the substrate may at least partially overlap. The orthographic projection of the second initial signal line on the substrate and the orthographic projection of the second reset control line on the substrate may at least partially overlap. For example, the second reset control line may be located in the first conductive layer, the second initial signal line may be located in the third conductive layer, and the light-emitting control connection segment may be located in the fourth conductive layer. In this example, by overlapping the wiring of the second reset control line, the second initial signal line, and the light-emitting control connection segment, it is beneficial to increasing the area of the light-transmitting region, thereby improving the light transmittance of the first display region.

[0129] In some exemplary embodiments, M first pixel circuits of a first display unit in a display island region may also be connected to an initial signal transmission segment extending in a first direction; the initial signal transmission segment may be configured to transmit a third initial signal. Initial signal transmission segments in adjacent display island regions in the same row may be connected by an initial signal connection segment. For example, the third initial signal line may include an initial signal transmission segment and an initial signal connection segment connected at intervals in the first direction, and the initial signal transmission segment and the initial signal connection segment may be located in different film layers. The light emission control connection segment may be located on a side of the initial signal connection segment away from the substrate. A positive projection of the initial signal connection segment on the substrate and a positive projection of the light emission control connection segment on the substrate may partially overlap. For example, the initial signal transmission segment may be located in a third conductive layer, the initial signal connection segment may be located in a second conductive layer, and the light emission control connection segment may be located in a fourth conductive layer. In this example, overlapping wiring of the initial signal connection segment and the light emission control connection segment may be beneficial to increasing the area of the light-transmitting region, thereby improving the light transmittance of the first display region.

[0130] In some exemplary embodiments, a plurality of first pixel circuits in a display island region located in the k-th row and h-th column and a plurality of first pixel circuits in a display island region located in the (k + 1)-th row and (h + 1)-th column may be centrosymmetric about a connection point between the display island region in the k-th row and h-th column and the display island region in the (k + 1)-th row and (h + 1)-th column. Wherein, both k and h are integers greater than 0. In this example, flipping the first pixel circuits in the display island regions of even rows or odd rows makes the first pixel circuits in adjacent row and adjacent column display island regions centrosymmetric, which may be beneficial to reducing the wiring space in the display island region, beneficial to increasing the area of the light-transmitting region, thereby improving the light transmittance of the first display region.

[0131] In some exemplary embodiments, in the first display area, the first pixel circuit of the i-th row in the k-th row display island area and the first pixel circuit of the (i-1)-th row in the (k-1)-th row display island area may share a first reset control line, and the first pixel circuit of the (i+e)-th row in the k-th row display island area and the first pixel circuit of the (i+e+1)-th row in the (k+1)-th row display island area may share a second reset control line, where i is an integer greater than 1 and e is an integer greater than or equal to 0. In some examples, one row of first pixel circuits may be provided in each row of display island areas, and the value of e may be 0; the first pixel circuit of the i-th row in the k-th row display island area and the first pixel circuit of the (i-1)-th row in the (k-1)-th row display island area may share a first reset control line, and the first pixel circuit of the i-th row in the k-th row display island area and the first pixel circuit of the (i+1)-th row in the (k+1)-th row display island area may share a second reset control line. In some other examples, each row of display island areas includes at least two rows of first pixel circuits, and the value of e may be greater than or equal to 1. For example, each row of display island areas may include two rows of first pixel circuits, and e may be 1. The first pixel circuit of the i-th row in the k-th row display island area and the first pixel circuit of the (i-1)-th row in the (k-1)-th row display island area may share a first reset control line, and the first pixel circuit of the (i+1)-th row in the k-th row display island area and the first pixel circuit of the (i+2)-th row in the (k+1)-th row display island area may share a second reset control line. By setting adjacent rows of first pixel circuits in adjacent rows of display island areas to share the first reset control line or the second reset control line, this example can help reduce the wiring space and increase the area of the light-transmitting area, thereby improving the light transmittance of the first display area.

[0132] In some exemplary embodiments, in the first display area, the first pixel circuit of the i-th row in the k-th row display island area and the first pixel circuit of the (i - 1)-th row in the (k - 1)-th row display island area may share a first initial signal line, and the first pixel circuit of the (i + e)-th row in the k-th row display island area and the first pixel circuit of the (i + e + 1)-th row in the (k + 1)-th row display island area may share a second initial signal line. In some examples, one row of first pixel circuits may be provided in each row of display island areas, and the value of e may be 0; the first pixel circuit of the i-th row in the k-th row display island area and the first pixel circuit of the (i - 1)-th row in the (k - 1)-th row display island area may share a first initial signal line, and the first pixel circuit of the i-th row in the k-th row display island area and the first pixel circuit of the (i + 1)-th row in the (k + 1)-th row display island area may share a second initial signal line. In some other examples, each row of display island areas includes at least two rows of first pixel circuits, and the value of e may be greater than or equal to 1. For example, each row of display island areas may include two rows of first pixel circuits, and e may be 1. The first pixel circuit of the i-th row in the k-th row display island area and the first pixel circuit of the (i - 1)-th row in the (k - 1)-th row display island area may share a first initial signal line, and the first pixel circuit of the (i + 1)-th row in the k-th row display island area and the first pixel circuit of the (i + 2)-th row in the (k + 1)-th row display island area may share a second initial signal line. In this example, by setting the adjacent two rows of first pixel circuits in adjacent rows of display island areas to share the first initial signal line or the second initial signal line, it is beneficial to reduce the wiring space and increase the area of the light transmission area, thereby improving the light transmittance of the first display area.

[0133] The following uses some examples to illustrate the solution of this embodiment.

[0134] Figure 1 It is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as Figure 1 shown, the display substrate may include: a display area AA and a peripheral area BB located outside the display area AA. The display area AA may at least include: a first display area A1 and a second display area A2, and the second display area A2 may at least partially surround the first display area A1. For example, the second display area A2 may surround the first display area A1 on all four sides. The peripheral area BB may surround the second display area A2 on all four sides. However, this embodiment is not limited thereto.

[0135] In some examples, as Figure 1As shown, the first display area A1 can be referred to as an under-screen camera (FDC, Full Display With Camera) area. The second display area A2 can also be referred to as a normal display area. The light transmittance of the first display area A1 can be greater than that of the second display area A2. For example, the orthographic projection of a sensor (such as a camera or other hardware) on the display substrate can be located within the first display area A1 of the display substrate. In some examples, as Figure 1 shown, the first display area A1 can be circular, and the size of the orthographic projection of the sensor on the display substrate can be less than or equal to the size of the first display area A1. In other examples, the first display area A1 can be rectangular, and the size of the orthographic projection of the sensor on the display substrate can be less than or equal to the size of the inscribed circle of the first display area A1. This embodiment does not limit this.

[0136] In some examples, as Figure 1 shown, the first display area A1 can be located at the exact middle position at the top of the display area AA. The second display area A2 can surround the first display area A1 on all sides. However, this embodiment does not limit this. For example, the first display area A1 can be located at other positions such as the upper left corner, upper right corner, lower left corner, or lower right corner of the display area AA. For example, the second display area A2 can surround at least one side of the first display area A1.

[0137] In some examples, as Figure 1 shown, the display area AA can be rectangular, such as a rounded rectangle. The first display area A1 can be circular or oval. However, this embodiment does not limit this. For example, the first display area A1 can be other shapes such as rectangular, semi-circular, or pentagonal.

[0138] In some examples, the display area AA can be provided with multiple sub-pixels. At least one sub-pixel can include a pixel circuit and a light-emitting element. The pixel circuit can be configured to drive the connected light-emitting element. For example, the pixel circuit can be configured to provide a driving current to drive the light-emitting element to emit light. The pixel circuit can include multiple transistors and at least one capacitor. For example, the pixel circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Among them, T in the above circuit structure refers to a thin-film transistor, C refers to a capacitor, the number in front of T represents the number of thin-film transistors in the circuit, and the number in front of C represents the number of capacitors in the circuit.

[0139] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, and the light-emitting element can emit red light, green light, blue light, or white light, etc. under the drive of its corresponding pixel circuit. The light-emitting color of the light-emitting element can be determined according to needs. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited thereto.

[0140] Figure 2 This is an equivalent circuit diagram of the pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit in this example is described by taking the 8T1C structure as an example. In some examples, as Figure 2 shown, the pixel circuit in this example may include eight transistors (i.e., the first transistor T1 to the eighth transistor T8) and a storage capacitor Cst. The first transistor T1 may also be referred to as the first reset transistor, the second transistor T2 may also be referred to as the threshold compensation transistor, the third transistor T3 may also be referred to as the driving transistor, the fourth transistor T4 may also be referred to as the data writing transistor, the fifth transistor T5 may also be referred to as the first light-emitting control transistor, the sixth transistor T6 may also be referred to as the second light-emitting control transistor, the seventh transistor T7 may also be referred to as the second reset transistor, and the eighth transistor T8 may also be referred to as the third reset transistor. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer provided between the anode and the cathode.

[0141] In some examples, the first transistor T1, the third transistor T3 to the eighth transistor T8 may be first-type transistors, for example, they may be P-type transistors, and the second transistor T2 may be a second-type transistor, for example, it may be an N-type transistor. However, this embodiment is not limited thereto. For example, multiple transistors of the pixel circuit may all be P-type transistors, or may all be N-type transistors.

[0142] In some examples, the first type of transistors in the pixel circuit (e.g., including the first transistor T1, the third transistor T3 to the eighth transistor T8) may employ low-temperature polycrystalline silicon thin-film transistors, and the second type of transistors in the pixel circuit (e.g., including the second transistor T2) may employ oxide thin-film transistors. The active layer of the low-temperature polycrystalline silicon thin-film transistor uses low-temperature poly-silicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin-film transistor uses oxide semiconductor (Oxide). The low-temperature polycrystalline silicon thin-film transistor has advantages such as high mobility and fast charging, and the oxide thin-film transistor has advantages such as low leakage current. Integrating the low-temperature polycrystalline silicon thin-film transistor and the oxide thin-film transistor on a display substrate to form a low-temperature polycrystalline oxide (LTPS+Oxide) display substrate can utilize the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.

[0143] In some examples, as Figure 2 shown, the pixel circuit may be electrically connected to a first scan line GL1, a second scan line GL2, a data line DL, a first power supply line PL1, a second power supply line PL2, a light emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a first reset control line RST1, and a second reset control line RST2. The first power supply line PL1 may be configured to provide a constant first voltage signal VDD to the pixel circuit, the second power supply line PL2 may be configured to provide a constant second voltage signal VSS to the pixel circuit, and the first voltage signal VDD is greater than the second voltage signal VSS. The first scan line GL1 may be configured to provide a first scan signal SCAN1 to the pixel circuit. The second scan line GL2 may be configured to provide a second scan signal SCAN2 to the pixel circuit. The data line DL may be configured to provide a data signal to the pixel circuit. The light emission control line EML may be configured to provide a light emission control signal EM to the pixel circuit. The first reset control line RST1 may be configured to provide a first reset control signal RESET1 to the pixel circuit. The second reset control line may be configured to provide a second reset control signal RESET2 to the pixel circuit.

[0144] In some examples, as Figure 2As shown, the gate of the third transistor T3 is electrically connected to the first node N1, the first pole of the third transistor T3 is electrically connected to the second node N2, and the second pole of the third transistor T3 is electrically connected to the third node N3. The gate of the fourth transistor T4 is electrically connected to the first scan line GL1, the first pole of the fourth transistor T4 is electrically connected to the data line DL, and the second pole of the fourth transistor T4 is electrically connected to the second node N2. The gate of the second transistor T2 is electrically connected to the second scan line GL2, the first pole of the second transistor T2 is electrically connected to the third node N3, and the second pole of the second transistor T2 is electrically connected to the first node N1. The gate of the fifth transistor T5 is electrically connected to the emission control line EML, the first pole of the fifth transistor T5 is electrically connected to the first power supply line PL1, and the second pole of the fifth transistor T5 is electrically connected to the second node N2. The gate of the sixth transistor T6 is electrically connected to the emission control line EML, the first pole of the sixth transistor T6 is electrically connected to the third node N3, and the second pole of the sixth transistor T6 is electrically connected to the fourth node N4. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first pole of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second pole of the first transistor T1 is electrically connected to the third node N3. The first transistor T1 can be configured to reset the third node N3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first pole of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second pole of the seventh transistor T7 is electrically connected to the fourth node N4. The seventh transistor T7 can be configured to reset the fourth node N4. The gate of the eighth transistor T8 is electrically connected to the second reset control line RST2, the first pole of the eighth transistor T8 is electrically connected to the third initial signal line INIT3, and the second pole of the eighth transistor T8 is electrically connected to the second node N2. The eighth transistor T8 can be configured to reset the second node N2. The first electrode of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode of the storage capacitor Cst is electrically connected to the first power supply line PL1.

[0145] In this example, the first node N1 is the connection point of the storage capacitor Cst, the second transistor T2, and the third transistor T3. The second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, the eighth transistor T8, and the third transistor T3. The third node N3 is the connection point of the first transistor T1, the third transistor T3, the second transistor T2, and the sixth transistor T6. The fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7, and the light-emitting element EL.

[0146] Figure 3 For Figure 2 the provided pixel circuit's operating timing diagram. The following refers to Figure 3 to Figure 2The operation process of the pixel circuit shown will be described. Among them, the first transistor T1, the third transistor T3 to the eighth transistor T8 of the pixel circuit are P-type transistors, and the second transistor T2 is an N-type transistor.

[0147] In some examples, such as Figure 2 and Figure 3 shown, during one frame display period, the operation process of the pixel circuit may at least include: a first stage S1, a second stage S2, a third stage S3, and a fourth stage S4.

[0148] The first stage S1 is called the first reset stage. The second reset control signal RESET2 provided by the second reset control line RST2 is a low-level signal, turning on the seventh transistor T7 and the eighth transistor T8; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, turning on the second transistor T2. When the eighth transistor T8 is turned on, the third initial signal provided by the third initial signal line INIT3 is provided to the second node N2. When the seventh transistor T7 is turned on, the second initial signal provided by the second initial signal line INIT2 is provided to the fourth node N4 to initialize the fourth node N4. The first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, the first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, turning off the fourth transistor T4, the first transistor T1, the fifth transistor T5, and the sixth transistor T6. The light-emitting element EL does not emit light in this stage.

[0149] The second stage S2 is called the second reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, turning on the first transistor T1; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, turning on the second transistor T2. When the first transistor T1 and the second transistor T2 are turned on, the first initial signal provided by the first initial signal line INIT1 is provided to the first node N1 to initialize the first node N1. The second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, the first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, turning off the seventh transistor T7, the eighth transistor T8, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. The light-emitting element EL does not emit light in this stage.

[0150] The third stage S3 is called the data writing stage or the threshold compensation stage. The first scan signal SCAN1 provided by the first scan line GL1 is a low-level signal, and the fourth transistor T4 is turned on; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, and the second transistor T2 is turned on. At this stage, the first electrode of the storage capacitor Cst is at a low level, and the third transistor T3 is turned on. The second transistor T2, the fourth transistor T4, and the third transistor T3 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst. The voltage of the first electrode (i.e., the first node N1) of the storage capacitor Cst is Vdata - |Vth|, where Vdata is the data voltage output by the data line DL, and Vth is the threshold voltage of the third transistor T3. The first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, the second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, so that the first transistor T1, the seventh transistor T7, the eighth transistor T8, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0151] In the fourth stage S4, the emission control signal EM provided by the emission control line EML can be switched from a high-level signal to a low-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on. The second scan signal SCAN2 provided by the second scan line GL2 is a low-level signal, so that the second transistor T2 is turned off. The first scan signal SCAN1 provided by the first scan line GL1, the first reset control signal RESET1 provided by the first reset control line RST1, and the second reset control signal RESET2 provided by the second reset control line RST2 are high-level signals, so that the fourth transistor T4, the first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned off. The first voltage signal VDD output by the first power supply line PL1 can provide a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, driving the light-emitting element EL to emit light.

[0152] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and the first pole. Since the voltage of the first node N1 is Vdata - |Vth|, the driving current of the third transistor T3 is:

[0153] I = K × (Vgs - Vth) 2 = K × [(VDD - Vdata + |Vth|) - Vth]2 = K × [VDD - Vdata] 2 ;

[0154] Wherein, I is the driving current flowing through the third transistor T3, which is also the driving current for driving the light-emitting element, K is a constant, Vgs is the voltage difference between the gate and the first pole of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power supply line PL1.

[0155] It can be seen from the above formula that the current flowing through the light-emitting element is independent of the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can better compensate for the threshold voltage of the third transistor T3. Moreover, the pixel circuit provided in this embodiment can improve the display defect caused by low frequency and improve the display effect of the light-emitting element.

[0156] In some examples, as Figure 1 shown, the first display area A1 may include: a plurality of first pixel circuits 11 and a plurality of first light-emitting elements 13; the second display area A2 may include: a plurality of second pixel circuits 12 and a plurality of second light-emitting elements 14. At least one first pixel circuit 11 may be connected to at least one first light-emitting element 13 and configured to drive the at least one connected first light-emitting element 13 to emit light. At least one second pixel circuit 12 may be connected to at least one second light-emitting element 14 and configured to drive the at least one connected second light-emitting element 14 to emit light. In this example, the pixel circuit built-in method is adopted in the first display area A1 to drive the first light-emitting element to emit light.

[0157] Figure 4 It is a partial schematic diagram of the display area of at least one embodiment of the present disclosure. Figure 4 It schematically shows the arrangement manner of a plurality of first light-emitting elements in the first display area and a plurality of second light-emitting elements in the second display area. Figure 4 Taking the eight-row and four-column display island area in the first display area as an example for illustration. The number of display island areas in the first display area is not limited in this example.

[0158] In some examples, as Figure 4 shown, the first display area A1 may include: a plurality of display island areas A11 and a plurality of light-transmitting areas A12 arranged in an array. In the first direction X (parallel to the row direction), the display island areas A11 and the light-transmitting areas A12 may be alternately arranged and aligned. In the second direction Y (parallel to the column direction), the display island areas A11 and the light-transmitting areas A12 may be alternately arranged and aligned. However, this embodiment is not limited thereto. In some other examples, the adjacent row display island areas may be arranged in a staggered manner. For example, at least one first pixel circuit in the adjacent row display island areas may be aligned.

[0159] In some examples, the shapes and sizes of multiple display island regions A11 may be substantially the same, and the shapes and sizes of multiple light-transmitting regions A12 may be substantially the same. For example, the display island region A11 may be substantially rectangular island-shaped.

[0160] In some examples, as Figure 4 shown, at least one display island region A11 may include: a first display unit 21. The first display unit 21 may include: six first light-emitting elements and four first pixel circuits. The six first light-emitting elements may include: two first light-emitting elements 13a and 13d that emit first-color light, two first light-emitting elements 13b and 13e that emit second-color light, and two first light-emitting elements 13c and 13f that emit third-color light. For example, the first-color light may be red light, the second-color light may be green light, and the third-color light may be blue light. This embodiment is not limited thereto.

[0161] In some examples, as Figure 4 shown, the six first light-emitting elements of the first display unit 21 may be divided into two groups of first light-emitting elements, and each group of first light-emitting elements may include three first light-emitting elements that emit different-color light. For example, the first group of first light-emitting elements may include: three first light-emitting elements 13a, 13b, and 13c; the second group of first light-emitting elements may include: three first light-emitting elements 13d, 13e, and 13f. The first group of first light-emitting elements and the second group of first light-emitting elements may be arranged in sequence along the first direction X. In the first group of first light-emitting elements, the first light-emitting elements 13a and 13b may be arranged in sequence along the second direction Y, and the first light-emitting element 13c may be located on the same side of the first light-emitting elements 13a and 13b in the first direction X. For example, the first light-emitting element 13a may be located on one side of the first light-emitting element 13b in the second direction Y, and the first light-emitting element 13c may be located on one side of the first light-emitting elements 13a and 13b in the first direction X. In the second group of first light-emitting elements, the first light-emitting elements 13d and 13e may be arranged in sequence along the second direction Y, and the first light-emitting element 13f may be located on the same side of the first light-emitting elements 13d and 13e in the first direction X. For example, the first light-emitting element 13d may be located on one side of the first light-emitting element 13e in the second direction Y, and the first light-emitting element 13f may be located on one side of the first light-emitting elements 13d and 13e in the first direction X. In this example, the three first light-emitting elements that emit different-color light in each group of first light-emitting elements of the first display unit 21 may adopt the Pentile RGB arrangement.

[0162] In some examples, as Figure 4As shown, the second display area A2 may include: a plurality of second display units 22 arranged in an array. At least one second display unit 22 may include: four second light-emitting elements and four second pixel circuits. The four second light-emitting elements may include: one second light-emitting element 14a that emits first-color light, two second light-emitting elements 14b and 14d that emit second-color light, and one second light-emitting element 14c that emits third-color light. The four second light-emitting elements may be electrically connected to the four second pixel circuits in a one-to-one correspondence. Each second pixel circuit may be configured to drive a corresponding second light-emitting element to emit light. Within one second display unit 22, the second light-emitting elements 14a, 14b, 14c, and 14d may be arranged in different columns in sequence along the first direction X. The second light-emitting elements 14a and 14c may be arranged in the same row, and the second light-emitting elements 14b and 14d may be arranged in the same row. Within the second display area A2, a plurality of second light-emitting elements 14a and 14c may be arranged at intervals in the same row, a plurality of second light-emitting elements 14b and 14d may be arranged at intervals in the same row, and the row where the second light-emitting elements 14a and 14c are located may be spaced apart from the row where the second light-emitting elements 14b and 14d are located along the second direction Y, so that a plurality of second light-emitting elements 14a and 14c may be arranged at intervals in the same column, and a plurality of second light-emitting elements 14b and 14d may be arranged at intervals in the same column. In this example, the plurality of second light-emitting elements in the second display area may adopt an RGBG arrangement.

[0163] Figure 5 Schematic diagram of the signal correspondence relationship between the first display area and the second display area of at least one embodiment of the present disclosure. Figure 5 Taking one first display unit in the first display area A1 and one second display unit in the second display area A2 as examples for illustration.

[0164] In some examples, such as Figure 5As shown, the four first pixel circuits of the first display unit may include: first pixel circuits 11a, 11b, 11c, and 11d arranged in sequence along the first direction X. The first pixel circuit 11a may be connected to two first light-emitting elements 13a and 13d that emit first-color light, and is configured to drive the two first light-emitting elements 13a and 13d to emit light. The first pixel circuit 11b may be connected to a first light-emitting element 13b that emits second-color light, and is configured to drive the first light-emitting element 13b to emit light. The first pixel circuit 11c may be connected to two first light-emitting elements 13c and 13f that emit third-color light, and is configured to drive the two first light-emitting elements 13c and 13f to emit light. The first pixel circuit 11d may be connected to a first light-emitting element 13e that emits second-color light, and is configured to drive the first light-emitting element 13e to emit light. In this example, both the first pixel circuits 11a and 11c are connected to the first light-emitting elements in a one-driving-two manner, and both the first pixel circuits 11b and 11d are connected to the first light-emitting elements in a one-driving-one manner.

[0165] In some examples, as Figure 5 shown, the orthographic projection of the first pixel circuit 11a on the substrate may at least partially overlap the orthographic projections of the first light-emitting elements 13a and 13b on the substrate. The orthographic projection of the first pixel circuit 11b on the substrate may at least partially overlap the orthographic projection of the first light-emitting element 13c on the substrate. The orthographic projection of the first pixel circuit 11c on the substrate may at least partially overlap the orthographic projections of the first light-emitting elements 13d and 13e on the substrate. The orthographic projection of the first pixel circuit 11d on the substrate may at least partially overlap the orthographic projection of the first light-emitting element 13f on the substrate. In this example, the orthographic projection of the first pixel circuit and the connected first light-emitting elements on the substrate may partially overlap, or may have no overlap.

[0166] In some examples, as Figure 5 shown, the four second pixel circuits of the second display unit may include: second pixel circuits 12a, 12b, 12c, and 12d arranged in sequence along the first direction X. The second pixel circuit 12a may be connected to a second light-emitting element 14a that emits first-color light, and is configured to drive the second light-emitting element 14a to emit light. The second pixel circuit 12b may be connected to a second light-emitting element 14b that emits second-color light, and is configured to drive the second light-emitting element 14b to emit light. The second pixel circuit 12c may be connected to a second light-emitting element 14c that emits third-color light, and is configured to drive the second light-emitting element 14c to emit light. The second pixel circuit 12d may be connected to a second light-emitting element 14d that emits second-color light, and is configured to drive the second light-emitting element 14d to emit light. In this example, the four second pixel circuits may all be connected to the second light-emitting elements in a one-driving-one manner.

[0167] In some examples, as Figure 5 As shown, the orthographic projection of the second pixel circuit 12a on the substrate may at least partially overlap with the orthographic projection of the second light-emitting element 14a on the substrate. The orthographic projection of the second pixel circuit 12b on the substrate may at least partially overlap with the orthographic projection of the second light-emitting element 14b on the substrate. The orthographic projection of the second pixel circuit 12c on the substrate may at least partially overlap with the orthographic projection of the second light-emitting element 14c on the substrate. The orthographic projection of the second pixel circuit 12d on the substrate may at least partially overlap with the orthographic projection of the second light-emitting element 14d on the substrate. In this example, the orthographic projection of the second pixel circuit and the connected second light-emitting element on the substrate may at least partially overlap.

[0168] In some examples, as Figure 5 shown, the four first pixel circuits of the first display unit may be arranged in alignment with the four second pixel circuits of the second display unit in the second direction Y. For example, the first pixel circuit 11a and the second pixel circuit 12a may be arranged in alignment in the second direction Y, the first pixel circuit 11b and the second pixel circuit 12b may be arranged in alignment in the second direction Y, the first pixel circuit 11c and the second pixel circuit 12c may be arranged in alignment in the second direction Y, and the first pixel circuit 11d and the second pixel circuit 12d may be arranged in alignment in the second direction Y.

[0169] In some examples, as Figure 5 shown, the first pixel circuit 11a of the first display unit and the second pixel circuit 12a of the second display unit may be located in the same column of pixel circuits and connected to the same data line extending along the second direction Y (for example, data line DL(j)). The first pixel circuit 11b of the first display unit and the second pixel circuit 12b of the second display unit may be located in the same column of pixel circuits and connected to the same data line extending along the second direction Y (for example, data line DL(j + 1)). The first pixel circuit 11c of the first display unit and the second pixel circuit 12c of the second display unit may be located in the same column of pixel circuits and connected to the same data line extending along the second direction Y (for example, data line DL(j + 2)). The first pixel circuit 11d of the first display unit and the second pixel circuit 12d of the second display unit may be located in the same column of pixel circuits and connected to the same data line extending along the second direction Y (for example, data line DL(j + 3)). Wherein, j may be a positive integer.

[0170] In some examples, as Figure 5As shown, the four first pixel circuits of the first display unit can be arranged in the same row of pixel circuits and connected to the same first scan line (such as the first scan line GL1(f)) extending along the first direction X. The four second pixel circuits of the second display unit are arranged in the same row of pixel circuits and connected to the same first scan line (such as the first scan line GL1(f + 1)) extending along the first direction X. Here, f can be a positive integer.

[0171] In some examples, as Figure 4 and Figure 5 shown, multiple second light-emitting elements in the second display area A2 can be arranged in the RGBG arrangement, and the second pixel circuit and the second light-emitting element can have a one-to-one correspondence. Multiple first light-emitting elements in the first display area A1 can be arranged in the Pentile RGB arrangement, and by reducing the number of first pixel circuits, six first light-emitting elements can be driven to emit light by four first pixel circuits. Taking one RGB unit as one first pixel unit and one RGBG unit as one second pixel unit, then two first pixel units can be set in the pixel space corresponding to one second pixel unit, so that the resolution (PPI) of the first display area is equivalent to that of the second display area. Moreover, since the display effect of the RGB arrangement with a resolution (PPI) of a can be equivalent to the display effect of the RGBG arrangement with a PPI of a * [2 ∧ (1 / 2)], therefore, in this example, on the basis of reducing the pixel circuits in the first display area to improve the light transmittance of the first display area, by setting the arrangement of the first light-emitting elements to be different from that of the second light-emitting elements, the display effect of the first display area can be optimized, thereby improving the display uniformity of the first display area and the second display area.

[0172] Figure 6 This is a partial top view schematic diagram of the first display area of at least one embodiment of the present disclosure. Figure 6 schematically shows a partial top view schematic diagram of two rows (such as the k-th row and the k + 1-th row) and two columns (such as the h-th column and the h + 1-th column) of display island areas, where k and h are both integers greater than 0. In some examples, as Figure 6 shown, the first display area can include: multiple display island areas and multiple light-transmitting areas A12. A single light-transmitting area A12 can be surrounded by two display island areas in the first direction X and surrounded by two display island areas in the second direction Y.

[0173] In some examples, in a direction perpendicular to the display substrate, the display substrate may include: a substrate, and a circuit structure layer and a light-emitting structure layer disposed on the substrate. The light-emitting structure layer may be located on a side of the circuit structure layer away from the substrate. The circuit structure layer of the first display area may include: a plurality of first pixel circuits, and the light-emitting structure layer of the first display area may include a plurality of first light-emitting elements.

[0174] In some examples, the circuit structure layer may include: an occlusion layer, a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer disposed on the substrate. A buffer layer may be disposed between the occlusion layer and the first semiconductor layer. A first insulating layer may be disposed between the first semiconductor layer and the first conductive layer, a second insulating layer may be disposed between the first conductive layer and the second conductive layer, a third insulating layer may be disposed between the second conductive layer and the second semiconductor layer, a fourth insulating layer may be disposed between the second semiconductor layer and the third conductive layer, a fifth insulating layer may be disposed between the third conductive layer and the fourth conductive layer, a sixth insulating layer and a seventh insulating layer may be disposed between the fourth conductive layer and the fifth conductive layer, an eighth insulating layer may be disposed between the fifth conductive layer and the sixth conductive layer, and a ninth insulating layer may be disposed on a side of the sixth conductive layer away from the substrate. In some examples, the buffer layer, the first insulating layer to the sixth insulating layer may be inorganic insulating layers, and the seventh insulating layer to the ninth insulating layer may be organic insulating layers. This embodiment is not limited thereto. In some other examples, the occlusion layer may be omitted. In some other examples, one insulating layer may be disposed between the fourth conductive layer and the fifth conductive layer. In some other examples, two insulating layers may be disposed on a side of the sixth conductive layer away from the substrate to improve the flatness effect of the anode layer.

[0175] In some examples, the light-emitting structure layer may include: an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode layer sequentially disposed on the circuit structure layer. The anode layer may be electrically connected to the pixel circuits of the circuit structure layer, the organic light-emitting layer may be connected to the anode layer, the cathode layer may be connected to the organic light-emitting layer, and the organic light-emitting layer may emit light of a corresponding color under the drive of the anode layer and the cathode layer.

[0176] The structure of the display substrate will be described below by way of an example of the manufacturing process of the display substrate. The "patterning process" as mentioned in the present disclosure, for metallic materials, inorganic materials or transparent conductive materials, includes processes such as coating photoresist, mask exposure, development, etching, and photoresist stripping, and for organic materials, includes processes such as coating organic materials, mask exposure, and development. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, which are not limited in the present disclosure. A "thin film" refers to a thin film made of a certain material on a substrate by using deposition, coating or other processes. If the "thin film" does not require a patterning process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" requires a patterning process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0177] The statement that "A and B are disposed in the same layer" as mentioned in the present disclosure means that A and B are formed simultaneously by the same patterning process, or the surfaces of A and B close to the substrate side are basically at the same distance from the substrate, or the surfaces of A and B close to the substrate side are in direct contact with the same film layer. The "thickness" of a film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, the statement that "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. The "shape of A" as mentioned in the present disclosure refers to the shape of the orthographic projection of A on the substrate.

[0178] Below, taking four first pixel circuits (such as including first pixel circuits 11a, 11b, 11c, and 11d) in a display island area (such as the display island area located in the k-th row and h-th column) of the first display area as an example, the film layers of the circuit structure layer will be described. In this example, the first pixel circuit is taken as the aforementioned 8T1C structure for illustration. Among them, the first pixel circuit 11a may include: a first transistor 31a, a second transistor 32a, a third transistor 33a, a fourth transistor 34a, a fifth transistor 35a, a sixth transistor 36a, a seventh transistor 37a, an eighth transistor 38a, and a storage capacitor; the first pixel circuit 11b may include: a first transistor 31b, a second transistor 32b, a third transistor 33b, a fourth transistor 34b, a fifth transistor 35b, a sixth transistor 36b, a seventh transistor 37b, an eighth transistor 38b, and a storage capacitor. The connection relationships of the eight transistors and the storage capacitor in each first pixel circuit can be referred to Figure 2 to the equivalent circuit diagram shown.

[0179] In some examples, the preparation process of the display substrate may include the following steps.

[0180] (1) Provide a substrate. In some examples, the substrate can be a rigid substrate or a flexible substrate. For example, the rigid substrate can be, but is not limited to, one or more of glass and quartz; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In some examples, the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer. The materials of the first flexible material layer and the second flexible material layer can be materials such as polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer can be materials such as silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0) to improve the water and oxygen resistance of the substrate.

[0181] (2) Form a shielding layer. In some examples, a shielding film is deposited on the substrate, and the shielding film is patterned through a patterning process to form a shielding layer disposed on the substrate. In some examples, the shielding layer can also be referred to as a bottom shielding metal (BSM).

[0182] Figure 7 For Figure 6 Schematic diagram of the first display area after forming the shielding layer in. In some examples, as Figure 7 shown, the shielding layer of the first display area may at least include: shielding blocks 300 located in the display island area. One shielding block 300 can be provided in each display island area. The shielding blocks 300 of adjacent rows in adjacent column display island areas can be an integrally connected structure. The plurality of shielding blocks 300 in the first display area can be an integrally connected structure.

[0183] In some examples, as Figure 7As shown, the shielding block 300 located in the display island area may have two first hollow portions 301, two second hollow portions 302, two third hollow portions 303, and two fourth hollow portions 304. The shielding block 300 may be substantially symmetric about the second center line O2. The two first hollow portions 301 may be substantially symmetric about the second center line O2, and a single first hollow portion 301 may be substantially symmetric about the first center line O1 or the third center line O3. The second hollow portion 302, the third hollow portion 303, and the fourth hollow portion 304 may be located on one side of the first hollow portion 301 in the opposite direction of the second direction Y, and the fourth hollow portion 304 may be located between the second hollow portion 302 and the third hollow portion 303 in the first direction X. One second hollow portion 302 and one third hollow portion 303 may be substantially symmetric about the first center line O1, and the other second hollow portion 302 and the other third hollow portion 303 may be substantially symmetric about the third center line O3. One fourth hollow portion 304 may be substantially symmetric about the first center line O1, and the other fourth hollow portion 304 may be substantially symmetric about the third center line O3. In this example, providing a light shielding block in the display island area can provide a light shielding effect for the first type of transistor of the first pixel circuit in the display island area, and by providing hollow portions in the light shielding block, it is possible to avoid the parasitic capacitance between the large-area metal and other metal film layers, which affects the display effect.

[0184] In some examples, the shielding layer may extend to the peripheral area and be electrically connected to the first power supply line in the peripheral area to access the first voltage signal, avoiding affecting other signal traces.

[0185] (3) Form the first semiconductor layer. In some examples, a buffer thin film and a first semiconductor thin film are sequentially deposited on the substrate on which the foregoing pattern is formed, and the first semiconductor thin film is patterned through a patterning process to form a buffer layer and a first semiconductor layer provided on the buffer layer. In some examples, the material of the first semiconductor layer may be amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, polythiophene, or the like.

[0186] Fig. 8A For Figure 6 is a schematic diagram of the first display area after forming the first semiconductor layer. Figure 8B For Fig. 8A is a schematic diagram of the first semiconductor layer in Fig. 8A and Figure 8BAs shown, the first semiconductor layer of the first display region may at least include: active layers of a plurality of first-type transistors of a plurality of first pixel circuits (for example, including: the first active layer 310a of the first transistor of the first pixel circuit 11a, the third active layer 330a of the third transistor, the fourth active layer 340a of the fourth transistor, the fifth active layer 350a of the fifth transistor, the sixth active layer 360a of the sixth transistor, the seventh active layer 370a of the seventh transistor, and the eighth active layer 380a of the eighth transistor; the first active layer 310b of the first transistor of the first pixel circuit 11b, the third active layer 330b of the third transistor, the fourth active layer 340b of the fourth transistor, the fifth active layer 350b of the fifth transistor, the sixth active layer 360b of the sixth transistor, the seventh active layer 370b of the seventh transistor, and the eighth active layer 380b of the eighth transistor).

[0187] In some examples, as Fig. 8A and Figure 8B shown, the first semiconductor layer patterns of the first pixel circuits 11a and 11b in the display island region may be substantially symmetric about the first midline O1, the first semiconductor layer patterns of the first pixel circuits 11b and 11c may be substantially symmetric about the second midline O2, and the first semiconductor layer patterns of the first pixel circuits 11c and 11d may be substantially symmetric about the third midline O3. The first semiconductor layer patterns of the first pixel circuits 11a and 11b and the first semiconductor layer patterns of the first pixel circuits 11c and 11d may be substantially symmetric about the second midline O2. The first semiconductor layer patterns of different display island regions may be independent of each other.

[0188] In some examples, as Fig. 8A and Figure 8B shown, the third, fourth, fifth, sixth, and seventh active layers of the four first pixel circuits in the display island region may be an integrally connected structure. Among them, the seventh active layer 370a of the first pixel circuit 11a and the seventh active layer 370b of the first pixel circuit 11b may be directly connected, the fifth active layer 350b of the first pixel circuit 11b and the fifth active layer of the first pixel circuit 11c may be directly connected, and the seventh active layer of the first pixel circuit 11c and the seventh active layer of the first pixel circuit 11d may be directly connected.

[0189] In some examples, as Fig. 8A and Figure 8BAs shown, the first semiconductor layer pattern of the first pixel circuit 11a will be described as an example. The first active layer 310a and the fourth active layer 340a of the first pixel circuit 11a may be located on one side of the third active layer 330a along the second direction Y, and the fifth active layer 350a, the sixth active layer 360a, the seventh active layer 370a, and the eighth active layer 380a may be located on the other side of the third active layer 330a along the opposite direction of the second direction Y. The first active layer 310a, the sixth active layer 360a, and the seventh active layer 370a may be aligned in the second direction Y.

[0190] In some examples, the shape of the third active layer 330a may be generally U-shaped, the shape of the fourth active layer 340a may be generally I-shaped, and the shapes of the fifth active layer 350a, the sixth active layer 360a, the seventh active layer 370a, and the eighth active layer 380a may be generally L-shaped. However, this embodiment is not limited thereto. The arrangement and shape of the first semiconductor layer pattern of the first pixel circuits 11b, 11c, and 11d are similar to those of the first semiconductor layer pattern of the first pixel circuit 11a, so they will not be described herein again.

[0191] In some examples, the active layer of each transistor may include: a first region, a second region, and a channel region located between the first region and the second region. Among them, the material of the first semiconductor layer may include, for example, polysilicon. The channel region may not be doped with impurities and has semiconductor characteristics. The first region and the second region may be doped regions on both sides of the channel region and are doped with impurities and thus have conductivity. The impurities may vary according to the type of transistor. In some examples, the doped regions of the active layer may be interpreted as the source electrode or drain electrode of the transistor. The part of the active layer between the transistors may be interpreted as a wiring doped with impurities and can be used to electrically connect the transistors. This embodiment is not limited thereto.

[0192] In some examples, as Fig. 8A shown, the orthographic projection of the shielding layer of the first display region on the substrate may partially overlap with the orthographic projection of the first semiconductor layer on the substrate. The orthographic projection of the shielding block 300 in the display island region on the substrate may cover the orthographic projections of the third active layer, the fourth active layer, the fifth active layer, the sixth active layer, the seventh active layer, and the eighth active layer of the four first pixel circuits on the substrate and partially overlap with the orthographic projection of the first active layer on the substrate. For example, the orthographic projection of the shielding block 300 on the substrate may cover the orthographic projections of the channel regions of the active layers of the first type transistors of the four first pixel circuits on the substrate. By setting the shielding layer to shield the channel regions of the active layers of the first type transistors located in the first semiconductor layer in this example, the influence of external light on the transistors of the pixel circuit can be avoided, thereby ensuring the performance of the transistors.

[0193] (4) Form a first conductive layer. In some examples, on the substrate forming the foregoing structure, a first insulating film and a first conductive film are sequentially deposited, and the first conductive film is patterned through a patterning process to form a first insulating layer and a first conductive layer disposed on the first insulating layer. In some examples, the first conductive layer may also be referred to as a first gate metal layer, and the first insulating layer may also be referred to as a first gate insulating layer.

[0194] Fig.9A is Figure 6 a schematic diagram of the first display area after forming the first conductive layer in Fig. 9B is Fig.9A a schematic diagram of the first conductive layer and the first semiconductor layer in Fig. 9C is Fig.9A a schematic diagram of the first conductive layer in 9A to 9C In some examples, as shown in

[0195] 9A to 9C , the first conductive layer of the first display area may at least include: a first scan transmission segment 251 of multiple first scan lines (such as including first scan lines GL1(k), GL1(k + 1)), a light emission control transmission segment 261 of multiple light emission control lines (such as including light emission control lines EML(k), EML(k + 1)), multiple first reset control lines (such as including first reset control lines RST1(k), RST1(k + 1), RST1(k + 2)), multiple second reset control lines (such as including second reset control lines RST2(k - 1), RST2(k), RST2(k + 1)), and first electrodes of storage capacitors of multiple first pixel circuits (such as including first electrodes 391a, 391b).

[0196] In some examples, the first reset control line RST1(k) may be located on one side of the light-transmitting region A12 in the second direction Y at the (h + 1)-th column of the k-th row. The line segment of the first reset control line RST1(k) close to the light-transmitting region A12 may be substantially in a straight line shape extending along the first direction X. The second reset control line RST2(k) may be located on the other side of the light-transmitting region A12 in the opposite direction of the second direction Y at the (h + 1)-th column of the k-th row. The line segment of the second reset control line RST2(k) close to the light-transmitting region A12 may be substantially in a straight line shape extending along the first direction X. The first scan line GL1(k) bypasses the light-transmitting region A12 from one side of the light-transmitting region A12 in the second direction Y by using the first scan connection line, and the emission control line EML(k) may bypass the light-transmitting region A12 from the other side of the light-transmitting region A12 in the opposite direction of the second direction Y by using the emission control connection line. The wiring arrangement of the first conductive layer in this example can be conducive to increasing the area of the light-transmitting region, thereby improving the light transmittance of the first display region.

[0197] In some examples, the shape of the line segment of the first reset control line RST1(k) located in the display island region where the connected first pixel circuit is located may be substantially in a broken line shape extending along the first direction X. For example, in the display island region at the h-th column of the k-th row, the overlapping region between the first reset control line RST1(k) and the first active layers of the four first pixel circuits may serve as the gates of the first transistors of the four first pixel circuits (for example, including the gate of the first transistor 31a and the gate of the first transistor 31b).

[0198] In some examples, the shape of the first scan transmission segment 251 of the first scan line GL1(k) may be substantially in a broken line shape extending along the first direction X. For example, in the display island region at the h-th column of the k-th row, the overlapping region between the first scan transmission segment 251 of the first scan line GL1(k) and the fourth active layers of the four first pixel circuits may serve as the gates of the fourth transistors of the four first pixel circuits (for example, including the gate of the fourth transistor 34a and the gate of the fourth transistor 34b).

[0199] In some examples, the shape of the emission control transmission segment 261 of the emission control line EML(k) may be substantially in a broken line shape extending along the first direction X. For example, in the display island region at the h-th column of the k-th row, the overlapping region between the emission control transmission segment 261 of the emission control line EML(k) and the fifth active layers of the four first pixel circuits may serve as the gates of the fifth transistors of the four first pixel circuits (for example, including the gates of the fifth transistors 35a and 35b), and the overlapping region between the emission control transmission segment 261 of the emission control line EML(k) and the sixth active layers of the four first pixel circuits may serve as the gates of the sixth transistors of the four first pixel circuits (for example, including the gates of the sixth transistors 36a and 36b).

[0200] In some examples, the shape of the segment of the second reset control line RST2(k) located in the display island area where the connected first pixel circuit is located may be substantially a broken line shape extending along the first direction X. For example, in the display island area of the k-th row and h-th column, the overlapping area of the second reset control line RST2(k) and the seventh active layer of the four first pixel circuits may serve as the gates of the seventh transistors of the four first pixel circuits (for example, including the gates of the seventh transistors 37a and 37b), and the overlapping area of the second reset control line RST2(k) and the eighth active layer of the four first pixel circuits may serve as the gates of the eighth transistors of the four first pixel circuits (for example, including the gates of the eighth transistors 38a and 38b).

[0201] In some examples, the first electrode 391a of the storage capacitor of the first pixel circuit 11a may simultaneously serve as the gate of the third transistor 33a, and the first electrode 391b of the storage capacitor of the first pixel circuit 11b may simultaneously serve as the gate of the third transistor 33b. The orthographic projections of the first electrodes 391a and 391b on the substrate may be substantially rectangular. This embodiment does not limit this.

[0202] (5) Form the second conductive layer. In some examples, on the substrate on which the foregoing structure is formed, a second insulating film and a second conductive film are sequentially deposited, and the second conductive film is patterned through a patterning process to form a second insulating layer and a second conductive layer provided on the second insulating layer. In some examples, the second conductive layer may also be referred to as a second gate metal layer, and the second insulating layer may also be referred to as a second gate insulating layer.

[0203] Fig. 10A For Figure 6 is a schematic diagram of the first display area after forming the second conductive layer. Fig. 10B For Fig. 10A is a schematic diagram of the second conductive layer in Fig. 10A and Fig. 10B As shown, the second conductive layer of the first display area may at least include: second scan assist transmission segments 271 of multiple second scan assist lines (for example, including second scan assist lines GL2b(k), GL2b(k)), second electrodes of storage capacitors of multiple first pixel circuits (for example, including second electrodes 392a, 392b), and initial signal connection segments 292 of multiple third initial signal lines (for example, including third initial signal lines INIT3(k - 1), INIT3(k), INIT3(k + 1)).

[0204] In some examples, the second scanning auxiliary transmission segment 271 of the second scanning auxiliary line GL2b(k) may be located in the display island area where the connected first pixel circuit is located. The shape of the second scanning auxiliary transmission segment 271 may be generally a broken line shape extending along the first direction X. For example, in the display island area of the h-th column and the k-th row, the second scanning auxiliary transmission segment 271 of the second scanning auxiliary line GL2b(k) may be located on one side of the second electrodes (such as the second electrodes 392a and 392b) of the storage capacitor of the first pixel circuit in the second direction Y.

[0205] In some examples, in the display island area, the orthographic projection of the second electrode of the storage capacitor of each first pixel circuit on the substrate may be generally a rectangular structure having a hollowed-out area. The orthographic projection of the hollowed-out area on the substrate may be generally rectangular, and the rectangle may have rounded corners or chamfers. The second electrode 392a of the storage capacitor of the first pixel circuit 11a and the second electrode 392b of the storage capacitor of the first pixel circuit 11b may be electrically connected through the first plate connection block 392-1. The second electrode 392b of the storage capacitor of the first pixel circuit 11b and the second electrode of the storage capacitor of the first pixel circuit 11c may be electrically connected through the second plate connection block 392-2. The second electrode of the storage capacitor of the first pixel circuit 11c and the second electrode of the storage capacitor of the first pixel circuit 11d may be electrically connected through another first plate connection block 392-1. One side of the second electrode 392a of the storage capacitor of the first pixel circuit 11a away from the first pixel circuit 11b may be connected to a second plate connection block 392-2. One side of the second electrode of the storage capacitor of the first pixel circuit 11d away from the first pixel circuit 11c may be electrically connected to another second plate connection block 392-2. The length of the first plate connection block 392-1 along the second direction Y may be less than the length of the second plate connection block 392-2 along the second direction Y. The second electrode of the storage capacitor may be subsequently electrically connected to the first power supply line through the second plate connection block. In this example, the second electrodes of the storage capacitors of the four first pixel circuits in the first display island area may be an integrally connected structure, which is beneficial to ensuring the uniform transmission of the first voltage signal along the first direction X.

[0206] In some examples, the initial signal connection segment 292 of the third initial signal line INIT3(k) may be located in the adjacent rows and adjacent column display island areas of the display island area where the connected first pixel circuit is located. For example, the initial signal connection segment 292 of the third initial signal line INIT3(k) connected to the first pixel circuit in the display island area of the k-th row and h-th column may be located in the display island area of the (k + 1)-th row and (h + 1)-th column, and may be located on one side of the light-transmitting area A12 of the k-th row and (h + 1)-th column in the opposite direction of the second direction Y. The shape of the initial signal connection segment 292 may be generally linear extending along the first direction X. The initial signal connection segment 292 may be configured to connect the initial signal transmission segments in adjacent display island areas formed subsequently, so as to realize the transmission of the third initial signal in the first display area along the first direction X.

[0207] (6) Form the second semiconductor layer. In some examples, on the substrate on which the foregoing pattern is formed, a third insulating film and a second semiconductor film are sequentially deposited, and the second semiconductor film is patterned through a patterning process to form a third insulating layer and a second semiconductor layer provided on the third insulating layer. In some examples, the material of the second semiconductor layer may include indium gallium zinc oxide (IGZO, Indium Gallium Zinc Oxide). In some examples, the third insulating layer may also be referred to as the third gate insulating layer.

[0208] Fig.11A For Figure 6 is a schematic diagram of the first display area after the second semiconductor layer is formed. Fig. 11B For Fig.11A is a schematic diagram of the second semiconductor layer in Fig.11A and Fig. 11B As shown, the second semiconductor layer of the first display area may at least include: active layers of second-type transistors of a plurality of first pixel circuits (for example, including: the second active layer 320a of the second transistor 32a of the first pixel circuit 11a, the second active layer 320b of the second transistor 32b of the first pixel circuit 11b).

[0209] In some examples, within the display island area, the second semiconductor layer patterns of the first pixel circuits 11a and 11b may be substantially symmetric about the first median line O1, the second semiconductor layer patterns of the first pixel circuits 11b and 11c may be substantially symmetric about the second median line O2, and the second semiconductor layer patterns of the first pixel circuits 11c and 11d may be substantially symmetric about the third median line O3. The second semiconductor layer patterns of the first pixel circuits 11a and 11b and the second semiconductor layer patterns of the first pixel circuits 11c and 11d may be substantially symmetric about the second median line O2.

[0210] In some examples, the shapes of the second active layers 320a and 320b can be generally an inverted L shape. The overlapping region between the second scan assist transmission segment 271 of the second scan assist line GL2b(k) and the second active layer 320a can serve as the bottom gate of the second transistor 32a, and the overlapping region between the second scan assist transmission segment 271 of the second scan assist line GL2b(k) and the second active layer 320b can serve as the bottom gate of the second transistor 32b.

[0211] In some examples, the orthographic projection of the second semiconductor layer on the substrate and the orthographic projection of the shielding layer on the substrate can partially overlap. The orthographic projection of the channel region of the second active layer on the substrate and the orthographic projection of the shielding layer on the substrate can have no overlap. For example, the orthographic projections of the channel regions of the second active layers 320a and 320b on the substrate can be located within the orthographic projection range of the first hollow-out region 301 on the substrate.

[0212] (7) Form a third conductive layer. In some examples, on the substrate on which the foregoing pattern is formed, a fourth insulating film and a third conductive film are sequentially deposited, and the third conductive film is patterned through a patterning process to form a fourth insulating layer and a third conductive layer disposed on the fourth insulating layer. In some examples, the third conductive layer can also be referred to as a third gate metal layer, and the fourth insulating layer can also be referred to as a fourth gate insulating layer.

[0213] Fig. 12A For Figure 6 is a schematic diagram of the first display area after forming the third conductive layer in Fig. 12B For Fig. 12A is a schematic diagram of the third conductive layer in Fig. 12A and Fig. 12B As shown in

[0214] In some examples, within the display island region, the second scan transmission segment 281 of the first initial signal line INIT1(k) and the second scan line GL2(k) may be located on one side of the storage capacitor along the second direction Y, and the initial signal transmission segments 291 of the second initial signal line INIT2(k) and the third initial signal line INIT3(k) may be located on the side of the storage capacitor opposite to the second direction Y. The first initial signal line INIT1(k) may be located on one side of the second scan transmission segment 281 of the second scan line GL2(k) along the second direction Y, the initial signal transmission segment 291 of the third initial signal line INIT3(k) and the second initial signal line INIT2(k) may be located on the side of the second scan transmission segment 281 of the second scan line GL2(k) opposite to the second direction Y, and the second initial signal line INIT2(k) may be located on the side of the initial signal transmission segment 291 of the third initial signal line INIT3(k) opposite to the second direction Y.

[0215] In some examples, the first initial signal line INIT1(k) may be located on one side of the light-transmitting region A12 at the (h + 1)-th column of the k-th row along the second direction Y. The second initial signal line INIT2(k) may be located on the side of the light-transmitting region A12 at the (h + 1)-th column of the k-th row opposite to the second direction Y. The shape of the segment of the first initial signal line INIT1(k) within the display island region where the connected first pixel circuit is located may be approximately a broken line extending along the first direction X. The shape of the segment of the first initial signal line INIT1(k) adjacent to the light-transmitting region A12 may be approximately a straight line extending along the first direction X. The shape of the segment of the second initial signal line INIT2(k) within the display island region where the connected first pixel circuit is located may be approximately a broken line extending along the first direction X. The shape of the segment of the second initial signal line INIT2(k) adjacent to the light-transmitting region A12 may be approximately a straight line extending along the first direction X. The routing arrangement of the third conductive layer in this example can help increase the area of the light-transmitting region and improve the light transmittance of the first display region.

[0216] In some examples, the orthographic projection of the first initial signal line INIT1(k) on the substrate and the orthographic projection of the first reset control line RST1(k) on the substrate may at least partially overlap. For example, the orthographic projection of the first initial signal line INIT1(k) on the substrate may include the orthographic projection of the first reset control line RST1(k) on the substrate. The orthographic projection of the second scan transmission segment 281 of the second scan line GL2(k) on the substrate and the orthographic projection of the second scan auxiliary transmission segment 271 of the second scan auxiliary line GL2b(k) on the substrate may partially overlap. The orthographic projection of the initial signal transmission segment 291 of the third initial signal line INIT3(k) on the substrate and the orthographic projection of the emission control transmission segment 261 of the emission control line EML(k) on the substrate may partially overlap. The orthographic projection of the second initial signal line INIT2(k) on the substrate and the orthographic projection of the second reset control line RST2(k) on the substrate may at least partially overlap. For example, the orthographic projection of the second initial signal line INIT2(k) on the substrate may include the orthographic projection of the second reset control line RST2(k) on the substrate. In this example, by performing a stacked design on the traces of different conductive layers (such as including the first conductive layer, the second conductive layer, and the third conductive layer), it is possible to avoid occupying too much trace space, which is beneficial to saving the wiring space, thereby improving the light transmittance of the first display area.

[0217] (8), form the fifth insulating layer. In some examples, deposit a fifth insulating thin film on the substrate on which the foregoing pattern is formed, and pattern the fifth insulating thin film through a patterning process to form the fifth insulating layer. In some examples, the fifth insulating layer may also be referred to as an interlayer insulating layer.

[0218] Fig.13 is Figure 6 a schematic diagram of the first display area after forming the fifth insulating layer in. In some examples, as Fig.13 shown, the fifth insulating layer of the first display area may be provided with a plurality of vias, for example, it may include a first type of via (such as including the first via V1 to the nineteenth via V19), a second type of via (such as including the twenty-first via V21, the twenty-second via V22, the thirty-fifth via V35, the thirty-eighth via V38), a third type of via (such as including the twenty-third via V23, the twenty-fourth via V24, the thirty-seventh via V37, the fortieth via V40), a plurality of fourth type of vias (such as including the thirty-first via V31 to the thirty-fourth via V34), and a plurality of fifth type of vias (such as including the twenty-fifth via V25 to the twenty-ninth via V29, the thirty-sixth via V36, the thirty-ninth via V39).

[0219] In some examples, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the first type of vias may be removed to expose a partial surface of the first semiconductor layer. The fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the second type of vias may be removed to expose a partial surface of the first conductive layer. The fifth insulating layer, the fourth insulating layer, and the third insulating layer within the third type of vias may be removed to expose a partial surface of the second conductive layer. The fifth insulating layer and the fourth insulating layer within the fourth type of vias may be removed to expose a partial surface of the second semiconductor layer. The fifth insulating layer within the fifth type of vias may be removed to expose a partial surface of the third conductive layer.

[0220] In some examples, the first type of vias, the second type of vias, and the third type of vias may be formed by the same patterning process, and the fourth type of vias and the fifth type of vias may be formed by the same patterning process.

[0221] (9) Form the fourth conductive layer. In some examples, deposit a fourth conductive thin film on the substrate on which the foregoing pattern is formed, and pattern the fourth conductive thin film through a patterning process to form the fourth conductive layer on the fifth insulating layer. In some examples, the fourth conductive layer may also be referred to as the first source-drain metal layer.

[0222] Fig.14A For Figure 6 is a schematic diagram of the first display area after the fourth conductive layer is formed in Fig. 14B For Fig.14A is a schematic diagram of the fourth conductive layer in Fig.14A and Fig. 14B As shown in

[0223] In some examples, the shape of the first pixel connection electrode 401 may be generally rectangular. The first pixel connection electrode 401 may be electrically connected to the fourth active layer 340a of the fourth transistor 34a of the first pixel circuit 11a through the third via V3.

[0224] In some examples, the shape of the second pixel connection electrode 402 may be generally strip-shaped extending along the second direction Y. One end of the second pixel connection electrode 402 may be electrically connected to the second active layer 320a of the second transistor 32a of the first pixel circuit 11a through the thirty-first via V31, and the other end may be electrically connected to the first electrode 391a of the storage capacitor of the first pixel circuit 11a through the twenty-first via V21. The second pixel connection electrode 402 is electrically connected to the gate of the third transistor 33a, the first electrode 391a of the storage capacitor, and the first pole of the second transistor 32a. The second pixel connection electrode 402 may serve as the first node of the first pixel circuit 11a.

[0225] In some examples, the shape of the third pixel connection electrode 403 may be generally strip-shaped extending along the second direction Y. One end of the third pixel connection electrode 403 may be electrically connected to the first active layer 310a of the first transistor 31a of the first pixel circuit 11a through the second via V2, and the other end may be electrically connected to the second active layer 320a of the second transistor 32a through the thirty-second via V32. It may also be electrically connected to the third active layer of the third transistor 33a through the sixth via V6. The third pixel connection electrode 403 may serve as the third node of the first pixel circuit 11a.

[0226] In some examples, the shape of the fourth pixel connection electrode 404 may be generally broken-line-shaped extending along the second direction Y. The fourth pixel connection electrode 404 may be electrically connected to the fourth active layer 340a of the fourth transistor 34a of the first pixel circuit 11a through the fourth via V4, and may also be electrically connected to the eighth active layer 380a of the eighth transistor 38a through the eighth via V8.

[0227] In some examples, the shape of the fifth pixel connection electrode 405 may be generally strip-shaped extending along the second direction Y. The fifth pixel connection electrode 405 may be electrically connected to the fifth active layer 350a of the fifth transistor 35a of the first pixel circuit 11a through the fifth via V5, and may also be electrically connected to the second plate connection block 392-2 connected to the second electrode 392a of the storage capacitor of the first pixel circuit 11a through the twenty-third via V23, so as to be electrically connected to the second electrode 392a of the storage capacitor of the first pixel circuit 11a.

[0228] In some examples, the shape of the sixth pixel connection electrode 406 may be generally rectangular. The sixth pixel connection electrode 406 may be electrically connected to the sixth active layer 360a of the sixth transistor 36a of the first pixel circuit 11a through the seventh via V7.

[0229] In some examples, the shape of the seventh pixel connection electrode 407 can be generally L-shaped. The seventh pixel connection electrode 407 can be electrically connected to the eighth active layer 380a of the eighth transistor 38a of the first pixel circuit 11a through the ninth via V9, and can also be electrically connected to the initial signal transmission section 291 of the third initial signal line INIT3(k) through the twenty-sixth via V26.

[0230] In some examples, the shape of the eighth pixel connection electrode 408 can be generally a strip extending along the second direction Y. The eighth pixel connection electrode 408 can be electrically connected to the seventh active layer 370a of the seventh transistor 37a of the first pixel circuit 11a through the tenth via V10, and can also be electrically connected to the second initial signal line INIT2(k) through the twenty-seventh via V27.

[0231] In some examples, the shape of the ninth pixel connection electrode 409 can be generally an 8-shaped lying flat. One end of the ninth pixel connection electrode 409 can be electrically connected to the first active layer 310a of the first transistor 31a of the first pixel circuit 11a through the first via V1, and the other end can be electrically connected to the first initial signal line INIT1(k) through the twenty-fifth via V25.

[0232] In some examples, the shape of the tenth pixel connection electrode 410 can be generally an 8-shaped lying flat. One end of the tenth pixel connection electrode 410 can be electrically connected to the first active layer 310b of the first transistor 31b of the first pixel circuit 11b through the eleventh via V11, and the other end can be electrically connected to the first initial signal line INIT1(k) through the twenty-eighth via V28.

[0233] In some examples, the shape of the eleventh pixel connection electrode 411 can be generally rectangular. The eleventh pixel connection electrode 411 can be electrically connected to the fourth active layer 340b of the fourth transistor 34b of the first pixel circuit 11b through the thirteenth via V13.

[0234] In some examples, the shape of the twelfth pixel connection electrode 412 can be generally a strip extending along the second direction Y. One end of the twelfth pixel connection electrode 412 can be electrically connected to the second active layer 320b of the second transistor 32b of the first pixel circuit 11b through the thirty-third via V31, and the other end can be electrically connected to the first electrode 391b of the storage capacitor of the first pixel circuit 11b through the twenty-second via V22. The twelfth pixel connection electrode 412 is electrically connected to the gate of the third transistor 33b, the first electrode 391b of the storage capacitor, and the first pole of the second transistor 32b. The twelfth pixel connection electrode 412 can serve as the first node of the first pixel circuit 11b.

[0235] In some examples, the shape of the thirteenth pixel connection electrode 413 may be generally strip-shaped extending along the second direction Y. One end of the thirteenth pixel connection electrode 413 may be electrically connected to the first active layer 310b of the first transistor 31b of the first pixel circuit 11b through the twelfth via V12, and the other end may be electrically connected to the second active layer 320b of the second transistor 32b through the thirty-fourth via V34, and may also be electrically connected to the third active layer 330b of the third transistor 33b through the sixteenth via V16. The thirteenth pixel connection electrode 413 may serve as the third node of the first pixel circuit 11b.

[0236] In some examples, the shape of the fourteenth pixel connection electrode 414 may be generally polygonal line-shaped extending along the second direction Y. The fourteenth pixel connection electrode 414 may be electrically connected to the fourth active layer 340b of the fourth transistor 34b of the first pixel circuit 11b through the fourteenth via V14, and may also be electrically connected to the eighth active layer 380b of the eighth transistor 38b through the eighteenth via V18.

[0237] In some examples, the shape of the fifteenth pixel connection electrode 415 may be generally strip-shaped extending along the second direction Y. The fifteenth pixel connection electrode 415 may be electrically connected to the fifth active layer 350b of the fifth transistor 35b of the first pixel circuit 11b through the fifteenth via V15, and may also be electrically connected to the second plate connection block 392-2 to which the second electrode 392b of the storage capacitor of the first pixel circuit 11b is connected through the twenty-fourth via V24, so as to be electrically connected to the second electrode 392b of the storage capacitor of the first pixel circuit 11b.

[0238] In some examples, the shape of the sixteenth pixel connection electrode 416 may be generally rectangular. The sixteenth pixel connection electrode 416 may be electrically connected to the sixth active layer 360b of the sixth transistor 36b of the first pixel circuit 11b through the seventeenth via V17.

[0239] In some examples, the shape of the seventeenth pixel connection electrode 417 may be generally L-shaped. The seventeenth pixel connection electrode 417 may be electrically connected to the eighth active layer 380b of the eighth transistor 38b of the first pixel circuit 11b through the nineteenth via V19, and may also be electrically connected to the initial signal transmission segment 291 of the third initial signal line INIT3(k) through the twenty-ninth via V29.

[0240] In some examples, within the display island region, the first pixel circuits 11a and 11b may be substantially symmetric about the second median line O2, the first pixel circuits 11c and 11d may be substantially symmetric about the third median line O3, and the first pixel circuits 11a and 11b, the first pixel circuits 11c and 11d may be substantially symmetric about the first median line O1.

[0241] In some examples, the shape of the first routing transfer electrode 283 can be approximately L-shaped. The first routing transfer electrode 283 can be connected to the second scan assist transmission segment 271 of the second scan assist line GL2b(k) through the thirty-seventh via V37, and can also be connected to the second scan transmission segment 281 of the second scan line GL2(k) through the thirty-sixth via V36.

[0242] In some examples, the shape of the second routing transfer electrode 293 can be approximately rectangular. The second routing transfer electrode 293 can be connected to the initial signal transmission segment 291 located in the third conductive layer through the thirty-ninth via V39, and can also be connected to the initial signal connection segment 292 located in the second conductive layer through the fortieth via V40. In this example, both ends of the initial signal connection segment 292 can be respectively connected to the initial signal transmission segments 291 in the same row and in two adjacent display island regions through the second routing transfer electrode 293, so as to realize the transmission of the third initial signal in the first direction X.

[0243] In some examples, the shape of the first scan connection segment 252 of the first scan line GL1(k) can be approximately a broken line shape extending in the first direction X. The first scan connection segment 252 of the first scan line GL1(k) can be located on one side of the light-transmitting region A12 in the (h + 1)-th column of the k-th row along the second direction Y. The first scan connection segment 252 can be located, for example, in the display island region in the (h + 1)-th column of the (k - 1)-th row. The orthographic projection of the first scan connection segment 252 on the substrate can partially overlap with the orthographic projections of the first reset control line RST1(k) and the first initial signal line INIT1(k) on the substrate. One end of the first scan connection segment 252 can be connected to the first scan transmission segment 251 located in the first conductive layer in the display island region in the h-th column of the k-th row through the thirty-fifth via V35, and the other end can be connected to the first scan transmission segment in the display island region in the (h + 1)-th column of the k-th row. The first scan connection segment 252 can connect the first scan transmission segments in two adjacent display island regions along the first direction X, so as to realize the transmission of the first scan signal in the first direction X.

[0244] In some examples, the shape of the light-emitting control connection segment 262 of the light-emitting control line EML(k) can be substantially a broken line shape extending along the first direction X. The light-emitting control connection segment 262 of the light-emitting control line EML(k) can be located on one side of the light-transmitting region A12 in the (h + 1)-th column of the k-th row along the opposite direction of the second direction Y. For example, the light-emitting control connection segment 262 can be located in the display island region in the (h + 1)-th column of the (k + 1)-th row. The orthographic projection of the light-emitting control connection segment 262 on the substrate can partially overlap with the orthographic projections of the second reset control line RST2(k), the second initial signal line INIT2(k), and the initial signal connection segment 292 on the substrate. One end of the light-emitting control connection segment 262 can be connected to the light-emitting control transmission segment 261 located in the display island region in the h-th column of the k-th row and in the first conductive layer through the thirty-eighth via V38, and the other end can be connected to the light-emitting control transmission segment in the display island region in the (h + 1)-th column of the k-th row. The light-emitting control connection segment 262 can connect the light-emitting control transmission segments in two adjacent display island regions along the first direction X, so as to realize the transmission of the light-emitting control signal along the first direction X.

[0245] (10) Form the sixth insulating layer and the seventh insulating layer. In some examples, deposit a sixth insulating thin film on the substrate on which the foregoing pattern is formed, then coat a seventh insulating thin film, and pattern the seventh insulating thin film and the sixth insulating thin film respectively through a patterning process to form the sixth insulating layer and the seventh insulating layer. In some examples, the sixth insulating layer can also be called a passivation layer, and the seventh insulating layer can also be called a first planarization layer.

[0246] Fig.15 is Figure 6 a schematic diagram of the first display region after the seventh insulating layer is formed in. In some examples, as Fig.15 shown, the seventh insulating layer of the first display region can be provided with a plurality of vias, for example, can include: the forty-first via V41 to the forty-seventh via V47. The seventh insulating layer and the sixth insulating layer in the forty-first via V41 to the forty-seventh via V47 can be removed to expose a partial surface of the fourth conductive layer.

[0247] (11) Form the fifth conductive layer. In some examples, deposit a fifth conductive thin film on the substrate on which the foregoing pattern is formed, and pattern the fifth conductive thin film through a patterning process to form the fifth conductive layer on the seventh insulating layer. In some examples, the fifth conductive layer can also be called a second source-drain metal layer.

[0248] Fig.16A is Figure 6 a schematic diagram of the first display region after the fifth conductive layer is formed in. Fig. 16B is Fig.16A a schematic diagram of the fifth conductive layer in. In some examples, as Fig.16A and Fig. 16BAs shown, the fifth conductive layer of the first display area may at least include: multiple data lines (for example, including data lines DL(j-1), DL(j), DL(j+1), DL(j+2), DL(j+3), DL(j+4), DL(j+5), DL(j+6), DL(j+7), DL(j+8)), multiple first anode connection electrodes (for example, first anode connection electrodes 422a, 422b, 422c, and 422d), multiple first power connection electrodes (for example, first power connection electrodes 423a, 423b, and 423c), multiple first shielding electrodes (for example, first shielding electrodes 421a and 421b), and second scan connection segments 282 of multiple second scan lines (for example, second scan lines GL2(k), GL2(k+1)). Among them, j is an integer greater than 0.

[0249] In some examples, the multiple data lines may be substantially in a zigzag shape extending along the second direction Y. The four first pixel circuits in each display island area may be electrically connected to the four data lines in a one-to-one correspondence. The data line DL(j) may be electrically connected to the first pixel connection electrode 401 through the forty-first via V41, and thus electrically connected to the fourth transistor of the first pixel circuit 11a. The data line DL(j+1) may be electrically connected to the eleventh pixel connection electrode 411 through the forty-fifth via V45, and thus electrically connected to the fourth transistor of the first pixel circuit 11b. The data line DL(j+2) may be electrically connected to the fourth transistor of the first pixel circuit 11c. The data line DL(j+3) may be electrically connected to the fourth transistor of the first pixel circuit 11d.

[0250] In some examples, the four data lines electrically connected to the four first pixel circuits in the display island area may be divided into two groups to bypass the light-transmitting area A12 adjacent to the display island area in the second direction Y. For example, the data line DL(j) connected to the first pixel circuit 11a and the data line DL(j+1) connected to the first pixel circuit 11b may bypass the light-transmitting area A12 located in the h-th column from one side in the opposite direction of the first direction X, and the data line DL(j+2) connected to the first pixel circuit 11c and the data line DL(j+3) connected to the first pixel circuit 11d may bypass the light-transmitting area A12 located in the h-th column from one side in the first direction X. In this example, by setting the data lines to bend and bypass the light-transmitting area, it is beneficial to reduce the occupied space of the wiring, thereby improving the light transmittance of the first display area.

[0251] In some examples, the shapes of the first anode connection electrodes 422a, 422b, 422c, and 422d may be substantially rectangular. The first anode connection electrodes 422a and 422b may be located between the data lines DL(j) and DL(j+1), and the first anode connection electrodes 422c and 422d may be located between the data lines DL(j+2) and DL(j+3).

[0252] In some examples, the first anode connection electrode 422a can be electrically connected to the sixth pixel connection electrode 406 through the forty-third via V43, so as to be electrically connected to the sixth transistor of the first pixel circuit 11a. The first anode connection electrode 422b can be electrically connected to the sixteenth pixel connection electrode 416 through the forty-sixth via V46, so as to be electrically connected to the sixth transistor of the first pixel circuit 11b. The first anode connection electrode 422c can be electrically connected to the sixth transistor of the first pixel circuit 11c. The first anode connection electrode 422d can be electrically connected to the sixth transistor of the first pixel circuit 11d.

[0253] In some examples, the shapes of the first power connection electrodes 423a, 423b, and 423c can be generally rectangular. The first power connection electrode 423a can be located between the data lines DL(j) and DL(j - 1), the first power connection electrode 423b can be located between the data lines DL(j + 1) and DL(j + 2), and the first power connection electrode 423c can be located between the data lines DL(j + 3) and DL(j + 4).

[0254] In some examples, the first power connection electrode 423a can be electrically connected to the fifth pixel connection electrode 405 through the forty-second via V42, so as to be electrically connected to the fifth transistor and the storage capacitor of the first pixel circuit 11a. The second power connection electrode 423b can be electrically connected to the fifteenth pixel connection electrode 415 through the forty-fourth via V44, so as to be electrically connected to the fifth transistors and the storage capacitors of the first pixel circuits 11b and 11c. The third power connection electrode 423c can be electrically connected to the fifth transistor and the storage capacitor of the first pixel circuit 11d.

[0255] In some examples, the shapes of the first shielding electrodes 421a and 421b can be generally n-shaped. The first shielding electrode 421a can be located between the data lines DL(j) and DL(j + 1), and the first shielding electrode 421b can be located between the data lines DL(j + 2) and DL(j + 3). The orthographic projection of the first shielding electrode 421a on the substrate can cover the orthographic projections of the second pixel connection electrode 402 and the twelfth pixel connection electrode 412 on the substrate, and can achieve the shielding of the first nodes of the first pixel circuit 11a and the first pixel circuit 11b, so as to shield the influence of the remaining signals on the first nodes of the first pixel circuit 11a and 11b. The second shielding electrode 421b can achieve the shielding of the first nodes of the first pixel circuit 11c and the first pixel circuit 11d, so as to shield the influence of the remaining signals on the first nodes of the first pixel circuit 11c and 11d.

[0256] In some examples, the shape of the second scanning connection segment 282 of the second scanning line GL2(k) can be substantially a broken line shape extending along the first direction X. The second scanning connection segment 282 of the second scanning line GL2(k) can be located on one side of the light-transmitting region A12 at the (h + 1)-th column in the k-th row along the second direction Y. For example, the second scanning connection segment 282 can be located in the display island region at the (h + 1)-th column in the (k - 1)-th row. The orthographic projection of the second scanning connection segment 282 on the substrate can partially overlap with the orthographic projections of the first scanning connection segment 252, the first reset control line RST1(k), and the first initial signal line INIT1(k) on the substrate. One end of the second scanning connection segment 282 can be connected to the first routing transfer electrode 283 in the display island region at the h-th column in the k-th row through the forty-seventh via V47 to achieve connection with the second scanning transmission segment 281 and the second scanning auxiliary transmission segment 271 in the display island region at the h-th column in the k-th row. The other end of the second scanning connection segment 282 can be connected to the second scanning transmission segment 281 and the second scanning auxiliary transmission segment 271 in the display island region at the (h + 1)-th column in the k-th row. The second scanning connection segment 282 can connect the second scanning transmission segments in two adjacent display island regions along the first direction X, and can also connect the second scanning auxiliary transmission segments in two adjacent display island regions along the first direction X, thereby realizing the transmission of the second scanning signal along the first direction X.

[0257] (12), Form the eighth insulating layer. In some examples, the eighth insulating layer is coated on the substrate on which the foregoing pattern is formed, and the eighth insulating layer is patterned through a patterning process to form the eighth insulating layer. In some examples, the eighth insulating layer can also be referred to as the second planarization layer.

[0258] Fig.17 For Figure 6 Schematic diagram of the first display region after forming the eighth insulating layer. In some examples, as Fig.17 shown, the eighth insulating layer of the first display region can be provided with a plurality of vias, for example, it can include the fifty-first via V51 to the fifty-ninth via V59. The eighth insulating layer within the fifty-first via V51 to the fifty-ninth via V59 can be removed to expose a part of the surface of the fifth conductive layer.

[0259] (13), Form the sixth conductive layer. In some examples, a sixth conductive thin film is deposited on the substrate on which the foregoing pattern is formed, and the sixth conductive thin film is patterned through a patterning process to form the sixth conductive layer on the eighth insulating layer. In some examples, the sixth conductive layer can also be referred to as the third source-drain metal layer.

[0260] Fig.18A For Figure 6 Schematic diagram of the first display region after forming the sixth conductive layer. Fig.18B For Fig.18A Schematic diagram of the sixth conductive layer in Fig.18A and Fig.18B As shown in Fig.18B , the sixth conductive layer in the first display area may at least include: a plurality of second anode connection electrodes (such as second anode connection electrodes 432a, 432b, 432c, and 432d), a plurality of first voltage transmission lines (such as first voltage transmission lines 451a and 451b), a plurality of power connection bars 452, and a plurality of second power connection electrodes (such as second power connection electrodes 453a, 453b, and 453c).

[0261] In some examples, the shapes of the first voltage transmission lines 451a and 451b may be zigzag-shaped extending along the second direction Y. The first voltage transmission lines 451a and 451b may be arranged at intervals along the first direction X. The first voltage transmission line 451a may be electrically connected to the first power connection electrode 423a through the fifty-third via V53, and the first voltage transmission line 451b may be electrically connected to the first power connection electrode 423c through the fifty-fifth via V55. The first voltage transmission lines 451a and 451b may access a first voltage signal. For example, the first voltage transmission lines 451a and 451b may extend to the peripheral area and be electrically connected to the first power supply line in the peripheral area to access the first voltage signal.

[0262] In some examples, the shape of the power connection bar 452 may be generally linear extending along the first direction X. The power connection bar 452 may connect two adjacent first voltage transmission lines 451a and 451b. The power connection bar 452 in a single display island area may be connected to three second power connection electrodes 453a, 453b, and 453c. The shapes of the second power connection electrodes 453a, 453b, and 453c may be generally linear extending along the second direction Y. The second power connection electrode 453a may be connected to the first shielding electrode 421a through the fifty-first via V51, the second power connection electrode 453b may be connected to the second anode connection electrode 432b through the fifty-fourth via V54, and the second power connection electrode 453c may be connected to the second shielding electrode 421b through the fifty-second via V52. The power connection bar 452, the first voltage transmission lines 451a and 451b, and the plurality of second power connection electrodes 453a, 453b, and 453c may be an integrally connected structure, so as to form a mesh connection structure for transmitting the first voltage signal in the first display area to ensure the uniformity of the transmission of the first voltage signal.

[0263] In some examples, the second anode connection electrode 432a can be located between the first voltage transmission line 451a and the second power supply connection electrode 453a, the second anode connection electrode 432b can be located between the second power supply connection electrodes 453a and 453b, the second anode connection electrode 432c can be located between the second power supply connection electrodes 453b and 453c, and the second anode connection electrode 432d can be located between the second power supply connection electrode 453c and the first voltage transmission line 451b.

[0264] In some examples, the shapes of the second anode connection electrodes 432a, 432b, 432c, and 432d can be generally strip-shaped extending along the second direction Y. The second anode connection electrode 432a can be electrically connected to the first anode connection electrode 422a through the fifty-sixth via V56. The second anode connection electrode 432b can be electrically connected to the first anode connection electrode 422b through the fifty-seventh via V57. The second anode connection electrode 432c can be electrically connected to the first anode connection electrode 422c through the fifty-eighth via V58. The second anode connection electrode 432d can be electrically connected to the first anode connection electrode 422d through the fifty-ninth via V59.

[0265] In this example, the fifth conductive layer and the sixth conductive layer are provided to arrange the data lines and the first voltage transmission lines, which can prevent the conductive layers close to the anode layer from having too many traces arranged thereon and affecting the flatness of the anode layer. Moreover, by arranging the first voltage transmission lines on the sixth conductive layer and the data lines on the fifth conductive layer, the distance between the data lines and the anode layer can be increased, avoiding the influence of the signals transmitted by the data lines on the anode layer.

[0266] (14) Form the ninth insulating layer. In some examples, the ninth insulating layer is coated on the substrate on which the foregoing pattern is formed, and the ninth insulating layer is patterned through a patterning process to form the ninth insulating layer. In some examples, the ninth insulating layer can also be referred to as the third planarization layer.

[0267] Fig.19 For Figure 6 is a schematic diagram of the first display area after the ninth insulating layer is formed. In some examples, as Fig.19 shown, the ninth insulating layer in the first display area can be provided with a plurality of vias, for example, it can include the sixty-first via V61 to the sixty-fourth via V64. The ninth insulating layer within the sixty-first via V61 to the sixty-fourth via V64 can be removed to expose a part of the surface of the sixth conductive layer.

[0268] So far, the circuit structure layer can be fabricated. The film layer structure of the circuit structure layer in the second display area is similar to that in the first display area, so it will not be elaborated here. Among them, the first scan line, the second scan line, the second scan auxiliary line, the light emission control line, and the third initial signal line in the second display area may not adopt a segmented transfer design.

[0269] (15) Form the light-emitting structure layer. In some examples, an anode thin film is deposited on the substrate on which the aforementioned pattern is formed, and the anode thin film is patterned through a patterning process to form an anode layer.

[0270] Fig. 20A is Figure 6 a schematic diagram of the first display area after forming the anode layer in Fig. 20B is Fig. 20A a schematic diagram of the anode layer in Fig. 20A and Fig. 20B shown, the anode layer in the first display area may at least include: anodes of multiple first light-emitting elements (for example, including the anode 131a of the first light-emitting element 13a, the anode 131b of the first light-emitting element 13b, the anode 131c of the first light-emitting element 13c, the anode 131d of the first light-emitting element 13d, the anode 131e of the first light-emitting element 13e, the anode 131f of the first light-emitting element 13f), multiple anode connection blocks (for example, including anode connection blocks 132a, 132b, 132c, and 132d), and multiple anode connection bars (for example, including the first anode connection bar 133 and the second anode connection bar 134).

[0271] In some examples, the shapes of the anodes 131a, 131b, 131c, 131d, 131e, and 131f may be generally rectangular. The anode 131a may be located on one side of the anode 131b in the second direction Y. The anode 131c may be located on one side of the anodes 131a and 131b in the first direction X. The anode 131d may be located on one side of the anode 131e in the second direction Y. The anode 131f may be located on one side of the anodes 131d and 131e in the first direction X.

[0272] In some examples, the shape of the anode connection block 132a can be approximately hexagonal. The anode 131a and the anode connection block 132a can be an integrally connected structure. The anode connection block 132a can be electrically connected to the second anode connection electrode 432a through the sixty-first via V61 to achieve electrical connection with the first pixel circuit 11a. The shapes of the anode connection blocks 132b, 132c, and 132d can be approximately V-shaped. The anode 131b and the anode connection block 132b can be an integrally connected structure. The anode connection block 132b can be electrically connected to the second anode connection electrode 432b through the sixty-second via V62 to achieve electrical connection with the first pixel circuit 11b. The anode 131c and the anode connection block 132c can be an integrally connected structure. The anode connection block 132c can be electrically connected to the second anode connection electrode 432c through the sixty-third via V63 to achieve electrical connection with the first pixel circuit 11c. The anode 131e and the anode connection block 132d can be an integrally connected structure. The anode connection block 132d can be electrically connected to the second anode connection electrode 432d through the sixty-fourth via V64 to achieve electrical connection with the first pixel circuit 11d.

[0273] In some examples, the shape of the first anode connection bar 133 can be approximately a broken line shape extending along the first direction X. The two ends of the first anode connection bar 133 can be respectively connected to the anodes 131a and 131d. The first anode connection bar 133 can be located on one side of the anode 131c in the second direction Y. The first anode connection bar 133, the anodes 131a and 131d, and the anode connection block 132a can be an integrally connected structure.

[0274] In some examples, the shape of the second anode connection bar 134 can be approximately a straight line shape extending along the first direction X. The two ends of the second anode connection bar 134 can be respectively connected to the anodes 131c and 131f. The second anode connection bar 134 can be located in the middle of the anodes 131d and 131e. The second anode connection bar 134, the anodes 131c and 131f, and the anode connection block 132c can be an integrally connected structure.

[0275] In some examples, on the substrate on which the foregoing pattern is formed, a pixel definition film is coated, and a pixel definition layer is formed through a mask, exposure, and development process. As Figure 6As shown, the pixel definition layer of the first display area may form a plurality of first pixel openings (for example, including first pixel openings 130a, 130b, 130c, and 130d). The shapes of the plurality of first pixel openings may be generally rectangular. The sizes of the first pixel opening 130a of the first light-emitting element 13a and the first pixel opening 130d of the first light-emitting element 13d may be substantially the same, the sizes of the first pixel opening 130c of the first light-emitting element 13c and the first pixel opening 130f of the first light-emitting element 13f may be substantially the same, and the sizes of the first pixel opening 130b of the first light-emitting element 13b and the first pixel opening 130e of the first light-emitting element 13e may be substantially the same. The first pixel opening 130c of the first light-emitting element 13c may be larger than the first pixel opening 130a of the first light-emitting element 13a and may be larger than the first pixel opening 130b of the first light-emitting element 13b.

[0276] In some examples, the light-emitting area of the light-emitting element may be the part of the light-emitting element located in the pixel opening of the pixel definition layer. For example, the area of the light-emitting area of the first light-emitting element 13a may be greater than or equal to the area of the light-emitting area of the first light-emitting element 13b, and the area of the light-emitting area of the first light-emitting element 13c may be greater than the area of the light-emitting area of the first light-emitting element 13a and greater than the area of the light-emitting area of the first light-emitting element 13b.

[0277] In some examples, an organic light-emitting layer is formed within the previously formed pixel opening, and the organic light-emitting layer is connected to the anode layer. Subsequently, a cathode thin film is deposited, and the cathode thin film is patterned through a patterning process to form a cathode layer, and the cathode layer may be connected to the organic light-emitting layer.

[0278] Fig.21 For Figure 6 Schematic diagram of the light-transmitting area in Fig.21 As shown, the light-transmitting area A12 may include: a first area A121 and a second area A122. The orthographic projections of the first area A121 and the second area A122 on the substrate may have no overlap. The light-transmitting area A12 as a whole may be generally oval, and the shapes of the plurality of light-transmitting areas A12 are substantially the same, all being generally wider at the top and narrower at the bottom. The first area A121 may be an irregular shape, and the second area A122 may be located at the edge position of the first area A121. The cathode layer within the first area A121 may be removed, and the cathode layer within the second area A122 may be retained.

[0279] In some examples, as Fig.21As shown, the maximum length L11 of the light-transmitting region A12 along the second direction Y can be from 30 micrometers to 40 micrometers, for example, it can be approximately 35 micrometers. The maximum length L12 of the first region A121 of the light-transmitting region A12 along the first direction X can be from 70 micrometers to 90 micrometers, for example, it can be approximately 81 micrometers. The minimum length L13 of the side of the lower part of the first region A121 extending along the second direction Y in the first direction X can be from 65 micrometers to 82 micrometers, for example, it can be approximately 74 micrometers.

[0280] In some examples, after preparing the light-emitting structure layer, a packaging structure layer can be formed on the cathode. In some examples, the packaging structure layer can include a stacked first packaging layer, second packaging layer, and third packaging layer. The first packaging layer and the third packaging layer can be made of inorganic materials, and the second packaging layer can be made of organic materials. The second packaging layer can be disposed between the first packaging layer and the third packaging layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer. In some possible implementation manners, the display substrate can further include other film layers, such as a touch control structure layer, a color filter layer, etc., which are not limited in this embodiment.

[0281] In some examples, the light-blocking layer, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb). It can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON). It can be a single layer, multi-layer, or composite layer. The seventh insulating layer, the eighth insulating layer, and the ninth insulating layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. However, this embodiment is not limited thereto.

[0282] The structure of the display substrate and its manufacturing process in this embodiment are merely an exemplary illustration. In some exemplary implementation manners, the corresponding structure can be changed according to actual needs, and the patterning process can be increased or decreased. The manufacturing process of this exemplary embodiment can be realized by using currently mature manufacturing equipment, can be well compatible with the existing manufacturing process, has a simple process implementation, is easy to implement, has a high production efficiency, a low production cost, and a high yield.

[0283] In the display substrate of this example, compared with the second display area, a light-transmitting area and a display island area are formed by deleting the first pixel circuit and the first light-emitting element in the first display area. The first pixel circuit and the first light-emitting element in the display island area are set in a combination of one-drive-one and one-drive-many, and the arrangement of the first light-emitting elements in the display island area is set to be different from the arrangement of the second light-emitting elements in the second display area, which can optimize the display effect of the first display area on the basis of improving the light transmittance of the first display area.

[0284] In some examples, the first scan signal in the first display area can be transmitted through the first scan line formed by the cross-layer connection of the first scan transmission segment and the first scan connection segment, and the second scan signal can be transmitted through the second scan line formed by the cross-layer connection of the second scan transmission segment and the second scan connection segment. The first scan connection segment and the second scan connection segment can be located in different film layers and overlap in wiring, which is beneficial to saving wiring space and thus beneficial to increasing the area of the light-transmitting area. In some examples, the first scan connection segment, the second scan connection segment, the first reset control line, and the first initial signal line can be located in different film layers and overlap in wiring, which is beneficial to saving wiring space.

[0285] In some examples, the light-emitting control signal in the first display area can be transmitted through the light-emitting control line formed by the cross-layer connection of the light-emitting control transmission segment and the light-emitting control connection segment. The light-emitting control connection segment, the first scan connection segment, and the second scan connection segment can bypass the light-transmitting area from both sides along the second direction, which is beneficial to rational wiring. In some examples, the light-emitting control connection segment, the second reset control line, and the second initial signal line can be located in different film layers and overlap in wiring, which is beneficial to saving wiring space and thus beneficial to increasing the area of the light-transmitting area.

[0286] In some examples, the third initial signal in the first display area can be transmitted through the third initial signal line formed by the cross-layer connection of the initial signal transmission segment and the initial signal connection segment. The initial signal connection segment and the light-emitting control connection segment can be located in different film layers and overlap in wiring, which is beneficial to saving wiring space.

[0287] Fig. 22 This is another partial top view schematic diagram of the first display area of at least one embodiment of the present disclosure. Fig. 22 The partial top view schematic diagram shows two rows (for example, the k-th row and the k + 1-th row) and two columns (for example, the h-th column and the h + 1-th column) of the display island area, where both k and h are integers greater than 0. In some examples, such as Fig. 22As shown, the first display area may include: a plurality of display island areas and a plurality of light-transmitting areas A12. A single light-transmitting area A12 is surrounded by two display island areas in the first direction X and by two display island areas in the second direction Y. The number of film layers and the stacking order of the circuit structure layer of the display substrate in this example are similar to those of the foregoing embodiments. Hereinafter, the film layer structures of the display island area in the k-th row and the h-th column and the display island area in the (k + 1)-th row and the (h + 1)-th column will be taken as an example for description.

[0288] In some examples, the value of k may be 2d, where d is an integer greater than 0. The k-th row may be an odd row, and the (k + 1)-th row and the (k - 1)-th row may be even rows. In some other examples, the value of k may be 2d - 1, where d is an integer greater than 0. The k-th row may be an even row, and the (k + 1)-th row and the (k - 1)-th row may be odd rows. In this example, an odd row means a row with an odd row number; an even row means a row with an even row number.

[0289] Fig.23 is Fig. 22 a schematic diagram of the first display area after forming the shielding layer. In some examples, as Fig.23 shown, the shielding layer of the first display area may at least include: a plurality of shielding blocks (for example, including the shielding block 300a located in the display island area in the k-th row and the h-th column and the shielding block 300b located in the display island area in the (k + 1)-th row and the (h + 1)-th column). One shielding block 300a may be provided for each display island area in the k-th row, and one shielding block 300b may be provided for each display island area in the (k + 1)-th row. The shielding block 300a and the connected shielding block 300b may be centrosymmetric about the connection point between the two. The shielding blocks 300a and 300b of the adjacent row display island areas in the adjacent column display island areas may be an integrally connected structure. The plurality of shielding blocks 300a and 300b in the first display area may be an integrally connected structure. Regarding the shape of the shielding block, reference may be made to the description of the foregoing embodiments, so it will not be elaborated here.

[0290] Fig.24A is Fig. 22 a schematic diagram of the first display area after forming the first semiconductor layer. Fig. 24B is Fig.24A a schematic diagram of the first semiconductor layer in Fig.24A and Fig. 24B shown, the first semiconductor layer of the first display area may at least include: the active layers of a plurality of first-type transistors of a plurality of first pixel circuits. The first semiconductor layer patterns of the four first pixel circuits in the display island area in the k-th row and the h-th column and the first semiconductor layer patterns of the four first pixel circuits in the display island area in the (k + 1)-th row and the (h + 1)-th column may be centrosymmetric about the connection point between the two. Regarding the description of the first semiconductor layer pattern in each display island area, reference may be made to the description of the foregoing embodiments, so it will not be elaborated here.

[0291] Fig.25A is Fig. 22 A schematic diagram of a first display area after forming a first conductive layer in Fig.25B is Fig.25A A schematic diagram of the first conductive layer in . In some examples, as Fig.25A and Fig.25B shown, the first conductive layer of the first display area may at least include: a plurality of first scan lines (for example, including first scan lines GL1(k - 1), GL1(k), GL1(k + 1), GL1(k + 2)), a plurality of light emission control lines (for example, including light emission control lines EML(k), EML(k + 1)), a plurality of first reset control lines (for example, including first reset control lines RST1(k), RST1(k + 2)), a plurality of second reset control lines (for example, including second reset control lines RST2(k), RST2(k + 2)), and first electrodes of storage capacitors of a plurality of first pixel circuits (for example, including first electrodes 391a, 391b).

[0292] In some examples, the first scan line GL1(k), the first reset control line RST1(k), and the first scan line GL1(k - 1) may be sequentially arranged along the second direction Y, and the first electrode of the storage capacitor of the first pixel circuit in the k-th row display island area is on one side of the second direction Y. The light emission control line EML(k), the second reset control line RST2(k), and the light emission control line EML(k + 1) may be sequentially arranged along the second direction Y, and the first electrode of the storage capacitor of the first pixel circuit in the k-th row display island area is on the opposite side of the second direction Y, and is on one side of the first electrode of the storage capacitor of the first pixel circuit in the (k + 1)-th row display island area in the second direction Y.

[0293] In some examples, the first scan line GL1(k) may be located on one side of the k-th row light-transmitting area A12 in the second direction Y, and the light emission control line EML(k) may be located on the opposite side of the k-th row light-transmitting area A12 in the second direction Y. The first scan line GL1(k) and the light emission control line EML(k) may bypass the light-transmitting area A12 from opposite sides of the k-th row light-transmitting area A12 in the second direction Y.

[0294] In some examples, the first pixel circuits in each display island area are arranged in the same row. The first pixel circuit in the k-th row display island area (e.g., the first pixel circuit in the i-th row) and the first pixel circuit in the (k - 1)-th row display island area (e.g., the first pixel circuit in the (i - 1)-th row) can share the first reset control line RST1(k). The first pixel circuit in the (k + 1)-th row display island area (e.g., the first pixel circuit in the (i + 1)-th row) and the first pixel circuit in the k-th row display island area (e.g., the first pixel circuit in the i-th row) can share the second reset control line RST2(k). In this example, by flipping the first pixel circuits in the even-row display island areas upside down, the first pixel circuits in the even-row display island areas can share the first reset control line or the second reset control line with the first pixel circuits in the adjacent odd-row display island areas, so as to save the routing layout space.

[0295] Fig.26A For Fig. 22 Schematic diagram of the first display area after forming the second conductive layer. Fig.26B For Fig.26A Schematic diagram of the second conductive layer in. In some examples, as Fig.26A And Fig.26B Shown, the second conductive layer of the first display area can at least include: the second scan auxiliary transmission segments 271 of multiple second scan auxiliary lines, and the second electrodes of the storage capacitors of multiple first pixel circuits (e.g., including second electrodes 392a, 392b). The second electrodes of the storage capacitors of the four first pixel circuits in a single display island area can be an interconnected integral structure. In the display island area at the k-th row and h-th column, the second scan auxiliary transmission segment 271 can be located on one side of the second electrode of the storage capacitor of the first pixel circuit in the second direction Y; in the display island area at the (k + 1)-th row and (h + 1)-th column, the second scan auxiliary transmission segment 271 can be located on the opposite side of the second electrode of the storage capacitor of the first pixel circuit in the second direction Y.

[0296] Fig.27A For Fig. 22 Schematic diagram of the first display area after forming the second semiconductor layer. Fig.27B For Fig.27A Schematic diagram of the second semiconductor layer in. In some examples, as Fig.27A And Fig.27B Shown, the second semiconductor layer of the first display area can at least include: the active layers of the second type transistors of multiple first pixel circuits. The second semiconductor layer pattern in the display island area at the k-th row and h-th column and the second semiconductor layer pattern in the display island area at the (k + 1)-th row and (h + 1)-th column can be centrosymmetric about the connection point of the two display island areas.

[0297] Fig.28A For Fig. 22 Schematic diagram of the first display area after forming the third conductive layer. Fig.28B Schematic diagram of the third conductive layer in Fig.28A . In some examples, as shown in Fig.28A and Fig.28B , the third conductive layer in the first display area may at least include: the second scan transmission segment 281 of multiple second scan lines (such as including second scan lines GL2(k), GL2(k + 1)), multiple first initial signal lines (such as including first initial signal lines INIT1(k), INIT1(k + 1)), multiple second initial signal lines (such as including second initial signal line INIT2(k)), and multiple third initial signal lines (such as including third initial signal lines INIT3(k), INIT3(k + 1)).

[0298] In some examples, the first pixel circuits in each display island area are arranged in the same row. The first pixel circuit (such as the first pixel circuit in the i-th row) in the k-th row display island area and the first pixel circuit (such as the first pixel circuit in the (i - 1)-th row) in the (k - 1)-th row display island area may share the first initial signal line INIT1(k). The first pixel circuit (such as the first pixel circuit in the (i + 1)-th row) in the (k + 1)-th row display island area and the first pixel circuit (such as the first pixel circuit in the i-th row) in the k-th row display island area may share the second initial signal line INIT2(k). The first pixel circuit (such as the first pixel circuit in the (i + 1)-th row) in the (k + 1)-th row display island area and the first pixel circuit (such as the first pixel circuit in the (i + 2)-th row) in the (k + 2)-th row display island area may share the first initial signal line INIT1(k + 1). In this example, by flipping the first pixel circuits in the even-row display island areas up and down, the first pixel circuits in the even-row display island areas can share the first initial signal line or the second initial signal line with the first pixel circuits in the adjacent odd-row display island areas, so as to save the routing layout space.

[0299] Fig.29A Schematic diagram of the first display area after forming the fourth conductive layer in Fig. 22 . Fig.29B Schematic diagram of the fourth conductive layer in Fig.29A . In some examples, as shown in Fig.29A and Fig.29BAs shown, the fourth conductive layer in the first display area may at least include: a plurality of pixel connection electrodes (for example, including the first pixel connection electrode 401 to the seventeenth pixel connection electrode 417), and a plurality of trace transfer electrodes (for example, including the first trace transfer electrode 283). The shape of the first trace transfer electrode 283 may be generally L-shaped. The first trace transfer electrode 283 may be connected to the second scan assist transmission segment 271 of the second scan assist line GL2b(k) and the second scan transmission segment 281 of the second scan line GL2(k). The fourth conductive layer pattern in the display island area of the k-th row and h-th column and the fourth conductive layer pattern in the display island area of the (k + 1)-th row and (h + 1)-th column may be centrosymmetric about the connection point of the two display island areas.

[0300] Fig. 30A For Fig. 22 Schematic diagram of the first display area after forming the fifth conductive layer in Fig. 30B For Fig. 30A Schematic diagram of the fifth conductive layer in Fig. 30A And Fig. 30B As shown, the fifth conductive layer in the first display area may at least include: a plurality of data lines (for example, including data lines DL(j - 1), DL(j), DL(j + 1), DL(j + 2), DL(j + 3), DL(j + 4), DL(j + 5), DL(j + 6), DL(j + 7), DL(j + 8)), a plurality of first anode connection electrodes (for example, first anode connection electrodes 422a, 422b, 422c, 422d, 422e, 422f, 422g, and 422h), a plurality of first power connection electrodes (for example, first power connection electrodes 423a, 423b, and 423c), a plurality of first shielding electrodes (for example, first shielding electrodes 421a and 421b), and the second scan connection segments 282 of a plurality of second scan lines. The fifth conductive layer pattern in the display island area of the k-th row and h-th column and the fifth conductive layer pattern in the display island area of the (k + 1)-th row and (h + 1)-th column may be centrosymmetric about the connection point of the two display island areas. The first anode connection electrode 422e is connected to the first first pixel circuit in the display island area of the (k + 1)-th row and (h + 1)-th column, the first anode connection electrode 422f is connected to the second first pixel circuit in the display island area of the (k + 1)-th row and (h + 1)-th column, the first anode connection electrode 422g is connected to the third first pixel circuit in the display island area of the (k + 1)-th row and (h + 1)-th column, and the first anode connection electrode 422h is connected to the fourth first pixel circuit in the display island area of the (k + 1)-th row and (h + 1)-th column.

[0301] Fig.31A For Fig. 22 Schematic diagram of the first display area after forming the sixth conductive layer in Fig.31B For Fig.31A Schematic diagram of the sixth conductive layer in Fig.31A and Fig.31B As shown in Fig.31B , the sixth conductive layer in the first display area may at least include: a plurality of second anode connection electrodes (such as including second anode connection electrodes 432a, 432b, 432c, 432d, 432e, 432f, 432g, and 432h), a plurality of first voltage transmission lines (such as including first voltage transmission lines 451a and 451b), a plurality of power connection bars 452, and a plurality of second power connection electrodes (such as including second power connection electrodes 453a, 453b, and 453c). The shapes of the second anode connection electrodes 432e, 432f, 432g, and 432h may be substantially strip-shaped extending along the second direction Y. The second anode connection electrode 432e may be connected to the first anode connection electrode 422e, the second anode connection electrode 432f may be connected to the first anode connection electrode 422f, the second anode connection electrode 432g may be connected to the first anode connection electrode 422g, and the second anode connection electrode 432h may be connected to the first anode connection electrode 422h.

[0302] Fig.32 is Fig. 22 a schematic diagram of the first display area after forming the anode layer in [reference]. In some examples, as Fig.32 shown, the anode layer in the first display area may at least include: anodes of a plurality of first light-emitting elements (such as including an anode 131a of the first light-emitting element 13a, an anode 131b of the first light-emitting element 13b, an anode 131c of the first light-emitting element 13c, an anode 131d of the first light-emitting element 13d, an anode 131e of the first light-emitting element 13e, an anode 131f of the first light-emitting element 13f), a plurality of anode connection blocks (such as including anode connection blocks 132a, 132b, 132c, and 132d), and a plurality of anode connection bars (such as including a first anode connection bar 133 and a second anode connection bar 134). The anode layer patterns in the display island area of the k-th row and h-th column are substantially the same as the anode layer patterns in the display island area of the (k + 1)-th row and (h + 1)-th column. The anodes of two first light-emitting elements emitting the first color light in the display island area of the (k + 1)-th row may be connected to the first first pixel circuit through the second anode connection electrode 432e and the first anode connection electrode 422e, the anode of a first light-emitting element emitting the second color light may be connected to the second first pixel circuit through the second anode connection electrode 432f and the first anode connection electrode 422f, the anodes of two first light-emitting elements emitting the third color light may be connected to the third first pixel circuit through the second anode connection electrode 432g and the first anode connection electrode 422g, and the anode of another first light-emitting element emitting the second color light may be connected to the fourth first pixel circuit through the second anode connection electrode 432h and the first anode connection electrode 422h. The patterning of the anode layer in this example is similar to the anode layer pattern of the foregoing embodiment, so it will not be described in detail here.

[0303] Fig.33 is Fig. 22 a schematic diagram of the light-transmitting region in []. In some examples, the light-transmitting region A12 in the (h + 1)-th column of the k-th row and the light-transmitting region A12 in the h-th column of the (k + 1)-th row can be centrosymmetric with respect to the connection point of the display island region in the h-th column of the k-th row and the display island region in the (h + 1)-th column of the (k + 1)-th row. The light-transmitting region A12 can generally be approximately elliptical. For example, the light-transmitting region A12 in the h-th column of the (k + 1)-th row can be shaped like a narrow top and a wide bottom. The light-transmitting region A12 can include: a first region A121 and a second region A122. The orthographic projections of the first region A121 and the second region A122 on the substrate can have no overlap. The first region A121 can be an irregular shape, and the second region A122 can be located at the edge position of the first region A121. The cathode layer in the first region A121 can be removed, and the cathode layer in the second region A122 can be retained.

[0304] In some examples, as Fig.33 shown, the maximum length L21 of the light-transmitting region A12 along the second direction Y can be 34 micrometers to 42 micrometers, for example, it can be about 38 micrometers. The maximum length L22 of the first region A121 of the light-transmitting region A12 along the first direction X can be 75 micrometers to 95 micrometers, for example, it can be about 85 micrometers; the minimum length L23 of the side of the first region A121 of the light-transmitting region A12 extending along the second direction Y in the first direction X can be 65 micrometers to 81 micrometers, for example, it can be about 73 micrometers.

[0305] Compared with the foregoing embodiments, in this example, the display substrate flips the first pixel circuits in the display island regions of even rows (or odd rows) up and down, so that the first pixel circuits in adjacent rows and adjacent columns can be centrosymmetric, and the first pixel circuits in adjacent rows can share the first reset control line and the first initial signal line, or can share the second reset control line and the second initial signal line, which is beneficial to saving the wiring space in the display island region and increasing the area of the light-transmitting region, thereby improving the light transmittance of the first display region. For the remaining descriptions of the display substrate in this embodiment, reference can be made to the descriptions of the foregoing embodiments, so they will not be repeated here.

[0306] Fig.34 is another schematic diagram of the signal correspondence relationship between the first display region and the second display region of at least one embodiment of the present disclosure. Figure 5 [] shows an example of a first display unit in the display island region of the h-th column of the f-th row and a first display unit in the display island region of the (h + 1)-th column of the (f - 1)-th row in the first display region A1, where f is an integer.

[0307] In some examples, as Fig.34As shown, the four first pixel circuits 11a, 11b, 11c, and 11d in the island area shown in the h-th column of the f-th row can be arranged in sequence along the first direction X. The first pixel circuit 11a can be connected to two first light-emitting elements 13a and 13d that emit first-color light. The first pixel circuit 11b can be connected to a first light-emitting element 13b that emits second-color light. The first pixel circuit 11c can be connected to two first light-emitting elements 13c and 13f that emit third-color light. The first pixel circuit 11d can be connected to another first light-emitting element 13e that emits second-color light.

[0308] In some examples, as Fig.34 As shown, the four first pixel circuits 11a, 11b, 11c, and 11d in the island area shown in the (h + 1)-th column of the f-th row can be arranged in sequence along the first direction X. The first pixel circuit 11a can be connected to two first light-emitting elements 13c and 13f that emit third-color light. The first pixel circuit 11b can be connected to a first light-emitting element 13b that emits second-color light. The first pixel circuit 11c can be connected to two first light-emitting elements 13a and 13d that emit first-color light. The first pixel circuit 11d can be connected to another first light-emitting element 13e that emits second-color light.

[0309] In this example, the connection order of the first pixel circuits and the first light-emitting elements in the island area shown in adjacent rows is different. For example, in the f-th row, the first first pixel circuit in the island area is connected to two first light-emitting elements that emit first-color light, and the third first pixel circuit is connected to two first light-emitting elements that emit third-color light. The four first pixel circuits correspond to RGBG in sequence; in the (f - 1)-th row, the first first pixel circuit in the island area is connected to two first light-emitting elements that emit third-color light, and the third first pixel circuit is connected to two first light-emitting elements that emit first-color light. The four first pixel circuits correspond to BGRG in sequence.

[0310] In this example, by setting the connection order of the first pixel circuits and the first light-emitting elements in the island area shown in adjacent rows to be different, it is beneficial to improve the display uniformity of the first display area and enhance the display effect of the first display area. For the remaining descriptions of the display substrate in this example, reference can be made to the descriptions of the foregoing embodiments, so they will not be elaborated here.

[0311] Fig.35 It is another partial schematic diagram of the display area of at least one embodiment of the present disclosure. Fig.35 It schematically shows the arrangement manners of multiple first light-emitting elements in the first display area A1 and multiple second light-emitting elements in the second display area A2. Fig.35 Taking the eight-row and four-column display island area of the first display area A1 as an example for illustration. The number of display island areas in the first display area in this example is not limited.

[0312] In some examples, such as Fig.35 shown, the first display area A1 may include: a plurality of display island areas A11 and a plurality of light-transmitting areas A12 arranged in an array. The display island area A11 may include a first display unit 21, and the first display unit 21 may include: six first light-emitting elements and four first pixel circuits. The six first light-emitting elements may include: two first light-emitting elements 13a and 13d that emit first-color light, two first light-emitting elements 13b and 13e that emit second-color light, and two first light-emitting elements 13c and 13f that emit third-color light. For example, the first-color light may be red light, the second-color light may be green light, and the third-color light may be blue light.

[0313] In some examples, the six first light-emitting elements of the first display unit 21 may be divided into two groups of first light-emitting elements, and each group of first light-emitting elements may include three first light-emitting elements that emit different-color light. For example, the first group of first light-emitting elements may include: three first light-emitting elements 13a, 13b, and 13c; the second group of first light-emitting elements may include: three first light-emitting elements 13d, 13e, and 13f. The first group of first light-emitting elements and the second group of first light-emitting elements may be arranged in sequence along the first direction X. In the first group of first light-emitting elements, the first light-emitting elements 13a, 13b, and 13c may be arranged in sequence along the first direction X. In the second group of first light-emitting elements, the first light-emitting elements 13d, 13e, and 13f may be arranged in sequence along the first direction X. In this example, the three first light-emitting elements that emit different-color light in each group of first light-emitting elements of the first display unit 21 may adopt the Real RGB arrangement. The arrangement of the plurality of second light-emitting elements in the second display area A2 may refer to the description of the foregoing embodiments, so it will not be elaborated here.

[0314] Fig.36 It is a partial top view schematic diagram of the first display area of at least one embodiment of the present disclosure. Fig.37A is Fig.36 a schematic diagram of the first display area after forming the anode layer in Fig.37B is Fig.37A a schematic diagram of the anode layer in Fig.36 schematically shows a partial top view schematic diagram of two rows (for example, the k-th row and the k + 1-th row) and two columns (for example, the h-th column and the h + 1-th column) of display island areas. The circuit structure layer of the first display area in this example may be as Fig. 22 shown in the embodiment, so it will not be elaborated here. In some other examples, the circuit structure layer of the first display area in this example may be as Figure 6 shown in the embodiment. This embodiment does not limit this.

[0315] In some examples, such as Figures 36 to 37BAs shown, the anode layer of the first display area may at least include: anodes of a plurality of first light-emitting elements (for example, including the anode 131a of the first light-emitting element 13a, the anode 131b of the first light-emitting element 13b, the anode 131c of the first light-emitting element 13c, the anode 131d of the first light-emitting element 13d, the anode 131e of the first light-emitting element 13e, the anode 131f of the first light-emitting element 13f), a plurality of anode connection blocks (for example, including anode connection blocks 132a, 132b, 132c, and 132d), and a plurality of anode connection bars (for example, including a first anode connection bar 133 and a second anode connection bar 134).

[0316] In some examples, the shapes of the anodes 131a, 131b, 131c, 131d, 131e, and 131f may be generally rectangular. The anodes 131a, 131b, 131c, 131d, 131e, and 131f may be arranged in sequence along the first direction X.

[0317] In some examples, the shape of the anode connection block 132a may be generally hexagonal. The anode 131a and the anode connection block 132a may be an integrally connected structure. The anode connection block 132a may be connected to the first first pixel circuit. The shape of the anode connection block 132b may be generally diagonal. The anode 131b and the anode connection block 132b may be an integrally connected structure. The anode connection block 132b may be connected to the second first pixel circuit. The shape of the anode connection block 132c may be generally V-shaped. The anode 131c and the anode connection block 132c may be an integrally connected structure. The anode connection block 132c may be connected to the third first pixel circuit. The shape of the anode connection block 132d may be generally diagonal. The anode 131e and the anode connection block 132d may be an integrally connected structure. The anode connection block 132d may be connected to the fourth first pixel circuit.

[0318] In some examples, the shape of the first anode connection bar 133 may be generally a broken line shape extending along the first direction X. The two ends of the first anode connection bar 133 may be respectively connected to the anodes 131a and 131d. The first anode connection bar 133 may be located on one side of the anodes 131b and 131c in the second direction Y. The first anode connection bar 133, the anodes 131a and 131d, and the anode connection block 132a may be an integrally connected structure.

[0319] In some examples, the shape of the second anode connection bar 134 can be generally a broken line shape extending along the first direction X. The two ends of the second anode connection bar 134 can be respectively connected to the anode 131f and the anode connection block 132c. The second anode connection bar 134 can be located on one side of the anodes 131d and 131e in the opposite direction of the second direction Y. The second anode connection bar 134, the anodes 131c and 131f, and the anode connection block 132c can be an integrally connected structure.

[0320] In the display substrate of this example, by setting the first light-emitting elements in the display island area to adopt the Real RGB arrangement method, the display effect of the first display area can be optimized.

[0321] Fig.38 It is another partial schematic diagram of the display area of at least one embodiment of the present disclosure. Fig.38 The arrangement of multiple first light-emitting elements in the first display area A1 and multiple second light-emitting elements in the second display area A2 is schematically shown. Fig.38 Taking the four-row and four-column display island area of the first display area A1 as an example for illustration. The number of display island areas in the first display area is not limited in this example.

[0322] In some examples, as Fig.38 shown, the first display area A1 may include: a plurality of display island areas A11 and a plurality of light-transmitting areas A12 arranged in an array. The plurality of display island areas A11 and the plurality of light-transmitting areas A12 may be arranged at intervals along the first direction X and the second direction Y. The display island area A11 may include two first display units 21a and 21b. The two first display units 21a and 21b may be arranged in sequence along the second direction Y. Each first display unit may include six first light-emitting elements and four first pixel circuits. The display island area in this example may be generally in the shape of a square island. The setting method of the first light-emitting elements and the first pixel circuits in each first display unit may refer to the description of the foregoing embodiments, so it will not be elaborated here. In other examples, each display island area may be provided with three or more first display units arranged in sequence along the second direction Y.

[0323] Fig.39 It is another partial schematic diagram of the display area of at least one embodiment of the present disclosure. Fig.39 The arrangement of multiple first light-emitting elements in the first display area A1 and multiple second light-emitting elements in the second display area A2 is schematically shown. Fig.39 Taking the four-row and four-column display island area of the first display area A1 as an example for illustration. The number of display island areas in the first display area is not limited in this example.

[0324] In some examples, as Fig.39As shown, the first display area A1 may include: a plurality of display island areas A11 and a plurality of light-transmitting areas A12 arranged in an array. The plurality of display island areas A11 and the plurality of light-transmitting areas A12 may be arranged at intervals along the first direction X and the second direction Y. The display island area A11 may include two first display units 21a and 21b. The two first display units 21a and 21b may be arranged in sequence along the first direction X. Each first display unit may include six first light-emitting elements and four first pixel circuits. The display island area in this example may be generally rectangular island-shaped. The setting manner of the first light-emitting elements and the first pixel circuits in each first display unit may refer to the description of the foregoing embodiments, so it will not be elaborated herein. In other examples, each display island area may be provided with three or more first display units arranged in sequence along the first direction X

[0325] In other examples, at least one first pixel circuit in at least one first display unit may be connected to three or four first light-emitting elements to drive the three or four first light-emitting elements to emit light. In other examples, two groups of first light-emitting elements in at least one first display unit may adopt different arrangement manners. For example, one group of first light-emitting elements adopts the Pentile RGB arrangement manner, and the other group of first light-emitting elements adopts the Real RGB arrangement manner. In other examples, the first light-emitting elements in at least one first display unit may adopt the Pentile RGB arrangement manner, and the first light-emitting elements in at least one first display unit may adopt the Real RGB arrangement manner. This embodiment does not limit this

[0326] This embodiment provides a display substrate, including: a substrate. The substrate includes: a first display area and a second display area located on at least one side of the first display area. The first display area includes: a plurality of display island areas and a plurality of light-transmitting areas arranged in an array. The display island area includes: at least one group of first pixel circuits and a plurality of first light-emitting elements. Each group of first pixel circuits includes M first pixel circuits, and at least one of the M first pixel circuits is connected to at least two first light-emitting elements; M is an integer greater than 1. The second display area includes: multiple groups of second pixel circuits and a plurality of second light-emitting elements. Each group of second pixel circuits includes M second pixel circuits, and at least one second pixel circuit is connected to at least one second light-emitting element. The number of first light-emitting elements connected by each group of first pixel circuits is greater than the number of second light-emitting elements connected by each group of second pixel circuits; the arrangement density of the second pixel circuits in the second display area is greater than or equal to the arrangement density of the first pixel circuits in the first display area. The first pixel circuits and the second pixel circuits in the same column are connected to the same data line

[0327] The display substrate provided in this embodiment adopts the method of integrating pixel circuits, deletes the first pixel circuits and the first light-emitting elements in the first display area to form a light-transmitting area, and sets the driving relationship of the first pixel circuits to the first light-emitting elements to be different from the driving relationship of the second pixel circuits to the second light-emitting elements. On the basis of improving the light transmittance of the first display area, the display effect of the first display area can be ensured, and the loss of the display effect caused by deleting some light-emitting elements and pixel circuits in the first display area can be compensated for.

[0328] In some exemplary embodiments, each group of the first pixel circuits includes four first pixel circuits, and the four first pixel circuits are connected to six first light-emitting elements. The six first light-emitting elements include: two first light-emitting elements that emit the first color light, two first light-emitting elements that emit the second color light, and two first light-emitting elements that emit the third color light. Each group of the second pixel circuits includes four second pixel circuits, and the four second pixel circuits are connected to four second light-emitting elements. The four second light-emitting elements include one second light-emitting element that emits the first color light, two second light-emitting elements that emit the second color light, and one second light-emitting element that emits the third color light.

[0329] In some exemplary embodiments, the arrangement manner of the six first light-emitting elements is different from the arrangement manner of the four second light-emitting elements.

[0330] In some exemplary embodiments, the arrangement density of the first pixel circuits in the first display area in the first direction is 0.4 to 0.6, such as 0.45 to 0.55, for example, it can be about 0.5, of the arrangement density of the second pixel circuits in the second display area in the first direction; the arrangement density of the first pixel circuits in the first display area in the second direction is 0.4 to 0.6, such as 0.45 to 0.55, for example, it can be about 0.5, of the arrangement density of the second pixel circuits in the second display area in the second direction.

[0331] For the relevant description of the display substrate of this embodiment, reference can be made to the description of the foregoing embodiments, so it will not be elaborated here.

[0332] Fig.40 It is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As Fig.40 shown, this embodiment provides a display device, including: a display substrate 91 and a sensor 92 located on the light-emitting side of the light-emitting structure layer away from the display substrate 91. The sensor 92 can be located on the non-display surface side of the display substrate 91. The orthographic projection of the sensor 92 on the display substrate 91 can at least partially overlap with the first display area A1. For example, the orthographic projection of the sensor 92 on the display substrate 91 can be located within the range of the first display area A1.

[0333] In some examples, the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be a product with an image display function (including static images or dynamic images, where the dynamic images may be videos). For example, the display device may be any one of the following: a monitor, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a painting screen, a personal digital assistant (PDA), a digital camera, a portable video camera, a viewfinder, a navigator, a vehicle, a large-area wall, an information query device (such as a business query device in departments such as e-government, banks, hospitals, and power), a monitor, etc. Additionally, the display device may also be a microdisplay, or any one of the products such as a VR device or an AR device containing a microdisplay.

[0334] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", or "some examples" means that the features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the described features, structures, materials, or characteristics may be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0335] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A display substrate, characterized in that, Comprising: A substrate, comprising: a first display area and a second display area located on at least one side of the first display area; the first display area comprising: a plurality of display island areas and a plurality of light-transmitting areas arranged in an array; The display island area comprises: at least one first display unit; the at least one first display unit comprises: N first light-emitting elements and M first pixel circuits, both M and N being integers greater than 1, and M being less than N; at least one of the M first pixel circuits is connected to at least two first light-emitting elements and is configured to drive the at least two first light-emitting elements to emit light; The second display area comprises: a plurality of second display units arranged in an array; at least one of the plurality of second display units comprises: M second light-emitting elements and M second pixel circuits, the M second pixel circuits being connected to the M second light-emitting elements in a one-to-one correspondence; The arrangement of the N first light-emitting elements of the at least one first display unit is different from the arrangement of the M second light-emitting elements of the at least one second display unit.

2. The display substrate according to claim 1, wherein Within the first display area, the display island areas and the light-transmitting areas are alternately arranged and aligned in a first direction, and the display island areas and the light-transmitting areas are alternately arranged and aligned in a second direction, wherein the first direction intersects the second direction.

3. The display substrate according to claim 1, wherein The M first pixel circuits of the at least one first display unit and the M second pixel circuits of the at least one second display unit are aligned in the first direction or the second direction, wherein the first direction intersects the second direction.

4. The display substrate according to claim 1, wherein The at least one first display unit comprises: six first light-emitting elements and four first pixel circuits, the four first pixel circuits being arranged in sequence along the first direction; the six first light-emitting elements comprise: two first light-emitting elements emitting a first color light, two first light-emitting elements emitting a second color light, and two first light-emitting elements emitting a third color light; the two first light-emitting elements emitting the first color light are connected to the same first pixel circuit, the two first light-emitting elements emitting the third color light are connected to the same first pixel circuit, and the two first light-emitting elements emitting the second color light are connected to the two first pixel circuits in a one-to-one correspondence.

5. The display substrate according to claim 4, characterized in that, The six first light-emitting elements are divided into two groups of first light-emitting elements, the two groups of first light-emitting elements being arranged in sequence along the first direction, each group of first light-emitting elements comprising: a first light-emitting element emitting a first color light, a first light-emitting element emitting a second color light, and a first light-emitting element emitting a third color light; within each group of first light-emitting elements, the first light-emitting element emitting the first color light and the first light-emitting element emitting the second color light are arranged in sequence along the second direction, and the first light-emitting element emitting the third color light is located on the same side of the first light-emitting element emitting the first color light and the first light-emitting element emitting the second color light along the first direction; the second direction intersects the first direction.

6. The display substrate according to claim 4, wherein The six first light-emitting elements are divided into two groups of first light-emitting elements, and the two groups of first light-emitting elements are arranged in sequence along the first direction. Each group of first light-emitting elements includes: a first light-emitting element that emits first-color light, a first light-emitting element that emits second-color light, and a first light-emitting element that emits third-color light; in each group of first light-emitting elements, the first light-emitting element that emits first-color light, the first light-emitting element that emits second-color light, and the first light-emitting element that emits third-color light are arranged in sequence along the first direction.

7. The display substrate according to claim 4, wherein In the first display area, the connection sequences of the first pixel circuits of the first display units in adjacent row display islands are different.

8. The display substrate according to claim 7, wherein In the first display area, the four first pixel circuits in the f-th row display island area can be sequentially connected to two first light-emitting elements that emit first-color light, a first light-emitting element that emits second-color light, two first light-emitting elements that emit third-color light, and another first light-emitting element that emits second-color light; The four first pixel circuits of the first display units in the (f - 1)-th row display island area can be sequentially connected to two first light-emitting elements that emit third-color light, a first light-emitting element that emits second-color light, two first light-emitting elements that emit first-color light, and another first light-emitting element that emits second-color light; where f is an integer greater than 1.

9. The display substrate according to claim 4, wherein The at least one second display unit includes: four second light-emitting elements and four second pixel circuits; the four second pixel circuits are arranged in sequence along the first direction; The four second light-emitting elements include: a second light-emitting element that emits first-color light, two second light-emitting elements that emit second-color light, and a second light-emitting element that emits third-color light; the second light-emitting element that emits first-color light, the second light-emitting elements that emit second-color light, the second light-emitting element that emits third-color light, and the second light-emitting element that emits second-color light are arranged in sequence along the first direction; the second light-emitting element that emits first-color light and the second light-emitting element that emits third-color light are arranged in the same row, and the two second light-emitting elements that emit second-color light are arranged in the same row.

10. The display substrate according to any one of claims 4 to 9, characterized in that, The first-color light is red light, the second-color light is green light, and the third-color light is blue light.

11. The display substrate according to claim 1, wherein, The M first pixel circuits of the first display units in the display island area are connected to a first scan transmission segment and a second scan transmission segment that extend along the first direction; the first scan transmission segment is configured to transmit a first scan signal, and the second scan transmission segment is configured to transmit a second scan signal; The first scan transmission segments in adjacent display island areas in the same row are connected through a first scan connection segment; the second scan transmission segments in adjacent display island areas in the same row are connected through a second scan connection segment; the second scan connection segment is located on a side of the first scan connection segment away from the substrate, and at least a part of the orthographic projection of the first scan connection segment on the substrate overlaps with the orthographic projection of the second scan connection segment on the substrate.

12. The display substrate according to claim 11, wherein, The first pixel circuit of the first display unit in the display island located in the same row is also connected to a first reset control line and a first initial signal line extending along the first direction, and the first initial signal line is located on a side of the first reset control line away from the substrate; the first scan connection segment is located on a side of the first initial signal line away from the substrate; The orthographic projection of the first scan connection segment on the substrate at least partially overlaps with the orthographic projection of the first initial signal line on the substrate; The orthographic projection of the first initial signal line on the substrate at least partially overlaps with the orthographic projection of the first reset control line on the substrate.

13. The display substrate according to claim 11, wherein M first pixel circuits of the first display unit in the display island are connected to a light emission control transmission segment extending along the first direction; the light emission control transmission segment is configured to transmit a light emission control signal; the light emission control transmission segments in the display islands located in the same row and adjacent to each other are connected through a light emission control connection segment; the light emission control connection segment and the first scan connection segment are located on two sides in the second direction of the light transmission region between the adjacent display islands, and the second direction intersects with the first direction.

14. The display substrate according to claim 13, wherein The first pixel circuit of the first display unit in the display island located in the same row is also connected to a second reset control line and a second initial signal line extending along the first direction, and the second initial signal line is located on a side of the second reset control line away from the substrate; the light emission control connection segment is located on a side of the second initial signal line away from the substrate; The orthographic projection of the light emission control connection segment on the substrate at least partially overlaps with the orthographic projection of the second initial signal line on the substrate; the orthographic projection of the second initial signal line on the substrate at least partially overlaps with the orthographic projection of the second reset control line on the substrate.

15. The display substrate according to claim 13, characterized in that, M first pixel circuits of the first display unit in the display island are also connected to an initial signal transmission segment extending along the first direction; the initial signal transmission segment is configured to transmit a third initial signal; The initial signal transmission segments in the display islands located in the same row and adjacent to each other are connected through an initial signal connection segment; the light emission control connection segment is located on a side of the initial signal connection segment away from the substrate; the orthographic projection of the initial signal connection segment on the substrate partially overlaps with the orthographic projection of the light emission control connection segment on the substrate.

16. The display substrate according to claim 1, wherein The multiple first pixel circuits in the display island located in the k-th row and h-th column are centrosymmetric with respect to the connection point of the display island in the k-th row and h-th column and the display island in the (k + 1)-th row and (h + 1)-th column with the multiple first pixel circuits in the display island located in the (k + 1)-th row and (h + 1)-th column; where k and h are both integers greater than 0.

17. The display substrate according to claim 16, wherein In the first display area, the first pixel circuits of the i-th row in the display island located in the k-th row share a first reset control line with the first pixel circuits of the (i - 1)-th row in the display island located in the (k - 1)-th row, and the first pixel circuits of the (i + e)-th row in the display island located in the k-th row share a second reset control line with the first pixel circuits of the (i + e + 1)-th row in the display island located in the (k + 1)-th row, where i is an integer greater than 1 and e is an integer greater than or equal to 0.

18. The display substrate according to claim 17, wherein In the first display area, the i-th row of the first pixel circuits in the k-th row display island area shares a first initial signal line with the (i - 1)-th row of the first pixel circuits in the (k - 1)-th row display island area, and the (i + e)-th row of the first pixel circuits in the k-th row display island area shares a second initial signal line with the (i + e + 1)-th row of the first pixel circuits in the (k + 1)-th row display island area.

19. The display substrate according to claim 1, wherein The display island area includes two first display units, and the two first display units are arranged along a first direction or a second direction; the first direction intersects with the second direction.

20. A display device, characterized in that, It includes a display substrate according to any one of claims 1 to 19, and a sensor located on one side of the non-display surface of the display substrate, and the orthographic projection of the sensor on the display substrate at least partially overlaps with the first display area of the display substrate.

21. A display substrate, characterized in that, It includes: A substrate, including: a first display area and a second display area located on at least one side of the first display area; the first display area includes: a plurality of display island areas and a plurality of light-transmitting areas arranged in an array. The display island area includes: at least one group of first pixel circuits and a plurality of first light-emitting elements, and each group of first pixel circuits includes M first pixel circuits, and at least one of the M first pixel circuits is connected to at least two first light-emitting elements; M is an integer greater than 1. The second display area includes: multiple groups of second pixel circuits and a plurality of second light-emitting elements, and each group of second pixel circuits includes M second pixel circuits, and at least one second pixel circuit is connected to at least one second light-emitting element. The number of first light-emitting elements connected to each group of first pixel circuits is greater than the number of second light-emitting elements connected to each group of second pixel circuits; the arrangement density of the second pixel circuits in the second display area is greater than or equal to the arrangement density of the first pixel circuits in the first display area. The first pixel circuits and the second pixel circuits in the same column are connected to the same data line.

22. The display substrate according to claim 21, wherein, Each group of first pixel circuits includes four first pixel circuits, and the four first pixel circuits are connected to six first light-emitting elements, and the six first light-emitting elements include: two first light-emitting elements emitting a first color light, two first light-emitting elements emitting a second color light, and two first light-emitting elements emitting a third color light. Each group of second pixel circuits includes four second pixel circuits, and the four second pixel circuits are connected to four second light-emitting elements, and the four second light-emitting elements include one second light-emitting element emitting a first color light, two second light-emitting elements emitting a second color light, and one second light-emitting element emitting a third color light.

23. The display substrate according to claim 22, wherein The arrangement manner of the six first light-emitting elements is different from the arrangement manner of the four second light-emitting elements.

24. The display substrate according to claim 21, wherein The arrangement density of the first pixel circuits in the first display area in the first direction is 0.4 to 0.6 times that of the second pixel circuits in the second display area in the first direction; the arrangement density of the first pixel circuits in the first display area in the second direction is 0.4 to 0.6 times that of the second pixel circuits in the second display area in the second direction; the first direction intersects with the second direction.

Images