Display panel and display device

Abstract

The invention provides a display panel and a display device, relates to the technical field of display, and is used for reducing the load of a signal line and solving the problems of signal delay and attenuation. The display panel comprises a plurality of circuit rows arranged in the first direction, each circuit row comprises circuit areas and spacer areas which are alternately arranged in the second direction, each circuit area comprises a pixel circuit, and the first direction intersects with the second direction; the first signal line extends in the second direction and is electrically connected with the pixel circuit, the first signal line comprises a first line segment located in the circuit area and a second line segment at least located in the interval area, and the width of at least part of the second line segment in the first direction is larger than that of at least part of the first line segment in the first direction.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0002] A display panel includes pixels, and each pixel includes a pixel circuit and a light-emitting element. The pixel circuit is configured to output a driving current to the light-emitting element to drive the light-emitting element to emit light.

[0003] However, in the existing display panel, the signal lines for providing signals to the pixel circuits have a problem of large load, and thus it is easy to cause display defects such as signal delay and attenuation. Summary of the Invention

[0004] Embodiments of the present invention provide a display panel and a display device, which are used to reduce the load of signal lines and improve the problems of signal delay and attenuation.

[0005] In a first aspect, an embodiment of the present invention provides a display panel, including: A plurality of circuit rows arranged along a first direction, where each circuit row includes a circuit region and a spacer region alternately arranged along a second direction, the circuit region includes a pixel circuit, and the first direction intersects the second direction; A first signal line extending along the second direction and electrically connected to the pixel circuit, the first signal line includes a first segment located in the circuit region and at least a second segment located in the spacer region, wherein at least a part of the second segment has a width greater than at least a part of the first segment in the first direction.

[0006] In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a display device, including the above display panel.

[0007] The technical solutions provided by the embodiments of the present invention have the following beneficial effects: In the related art, the horizontal signal lines electrically connected to the pixel circuits usually adopt an equal line width design, that is, the line width of the same horizontal signal line is the same at different positions.

[0008] However, in the embodiments of the present invention, at least part of the horizontal signal lines are designed with a widened width: the display panel includes a first signal line extending horizontally, the first signal line includes a first segment located in the circuit region and at least a second segment located in the spacer region, and in the embodiments of the present invention, the second segment is designed with a widened width, so that the line width of the second segment is greater than that of the first segment. In this way, the second segment can be used to reduce the routing resistance of the first signal line, reduce the load of the first signal line, and further improve the display defects caused by signal delay and attenuation in the first signal line.

[0009] In addition, the wiring in the circuit area is complex. If the line segment of the first signal line located in the circuit area is widened, the widened line width may affect the layout of other same-layer traces or the layout of some vias, resulting in difficult layout design. However, the wiring in the spacer area is simple. In the embodiment of the present invention, the line segment of the first signal line located in the spacer area is selected to be widened, which can effectively avoid the above problems and reduce the difficulty of layout design. Brief Description of the Drawings

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those skilled in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0011] Figure 1 A schematic structural diagram of a display panel provided by an embodiment of the present invention; Figure 2 A schematic structural diagram of a first signal line provided by an embodiment of the present invention; Figure 3 Another schematic structural diagram of a first signal line provided by an embodiment of the present invention; Figure 4 Another schematic structural diagram of a first signal line provided by an embodiment of the present invention; Figure 5 A schematic structural diagram of a transistor provided by an embodiment of the present invention; Figure 6 Is Figure 5 A cross-sectional view along the A1-A2 direction; Figure 7 Another schematic structural diagram of a transistor provided by an embodiment of the present invention; Figure 8 Is Figure 7 A cross-sectional view along the B1-B2 direction; Figure 9 A schematic film layer structure diagram of a display panel provided by an embodiment of the present invention; Figure 10 Another schematic structural diagram of a display panel provided by an embodiment of the present invention; Figure 11 Another schematic structural diagram of a first signal line provided by an embodiment of the present invention; Figure 12 Another schematic film layer structure diagram of a display panel provided by an embodiment of the present invention; Figure 13 Another schematic structural diagram of a first signal line provided by an embodiment of the present invention; Figure 14 Another structural schematic diagram of the first signal line provided by the embodiment of the present invention; Figure 15 Another schematic diagram of the film layer structure of the display panel provided by the embodiment of the present invention; Figure 16 Another structural schematic diagram of the first signal line provided by the embodiment of the present invention; Figure 17 Another structural schematic diagram of the first signal line provided by the embodiment of the present invention; Figure 18 Another structural schematic diagram of the first signal line provided by the embodiment of the present invention; Figure 19 Another structural schematic diagram of the first signal line provided by the embodiment of the present invention; Figure 20 Another structural schematic diagram of the first signal line provided by the embodiment of the present invention; Figure 21 Another schematic diagram of the film layer structure of the display panel provided by the embodiment of the present invention; Figure 22 Another schematic diagram of the film layer structure of the display panel provided by the embodiment of the present invention; Figure 23 Another schematic diagram of the film layer structure of the display panel provided by the embodiment of the present invention; Figure 24 Another schematic diagram of the film layer structure of the display panel provided by the embodiment of the present invention; Figure 25 Another structural schematic diagram of the display panel provided by the embodiment of the present invention; Figure 26 Another structural schematic diagram of the display panel provided by the embodiment of the present invention; Figure 27 Another structural schematic diagram of the display panel provided by the embodiment of the present invention; Figure 28 Another structural schematic diagram of the display panel provided by the embodiment of the present invention; Figure 29 Another structural schematic diagram of the display panel provided by the embodiment of the present invention; Figure 30 is Figure 29 A structural schematic diagram of the corresponding first signal line; Figure 31 Another structural schematic diagram of the display panel provided by the embodiment of the present invention; Figure 32 A circuit structural schematic diagram of the pixel circuit provided by the embodiment of the present invention; Figure 33 A schematic diagram of a film layer structure of a pixel circuit provided by an embodiment of the present invention; Figure 34 Another schematic diagram of a film layer structure of a display panel provided by an embodiment of the present invention; Figure 35 A schematic diagram of a structure of a display device provided by an embodiment of the present invention; Figure 36 Another schematic diagram of a structure of a display device provided by an embodiment of the present invention. Detailed implementation manners

[0012] In order to better understand the technical solutions of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0013] It should be clear that the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0014] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "the" and "said" used in the embodiments of the present invention and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0015] It should be understood that the term " / and" used herein is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " herein generally represents an "or" relationship between the associated objects before and after.

[0016] The embodiments of the present invention provide a display panel, which may be a light emitting diode (LED) display panel, an organic light emitting diode (OLED) display panel, etc. For example, it is a micro LED display panel.

[0017] As Figure 1 shown, Figure 1 A schematic diagram of a structure of a display panel provided by an embodiment of the present invention. The display panel includes a plurality of circuit rows 1 arranged along a first direction x. The circuit rows 1 include circuit regions 2 and spacer regions 3 arranged alternately along a second direction y. The first direction x intersects the second direction y. Among them, the circuit region 2 includes a pixel circuit 4.

[0018] The display panel further includes a first signal line 5, which extends along the second direction y and is electrically connected to the pixel circuit 4. The first signal line 5 includes a first line segment 6 and a second line segment 7. Among them, the first line segment 6 is located in the circuit region 2, and the second line segment 7 is at least located in the spacer region 3. And at least part of the second line segment 7 has a width greater than that of at least part of the first line segment 6 in the first direction x.

[0019] In the related art, the horizontal signal lines electrically connected to the pixel circuit usually adopt an equal line width design, that is, the line widths of the same horizontal signal line at different positions are the same.

[0020] In the embodiment of the present invention, at least part of the horizontal signal lines are widened: the display panel includes a first signal line 5 extending horizontally. The first signal line 5 includes a first line segment 6 located in the circuit region 2 and a second line segment 7 at least located in the spacer region 3. In the embodiment of the present invention, the second line segment 7 is widened, so that the line width of the second line segment 7 is greater than that of the first line segment 6. In this way, the second line segment 7 can be used to reduce the routing resistance of the first signal line 5, reduce the load of the first signal line 5, and further improve the display defect problem caused by signal delay and attenuation in the first signal line 5.

[0021] In addition, the wiring in the circuit region 2 is complex. If the line segment of the first signal line 5 located in the circuit region 2 is widened, the widened line width may affect the arrangement of other same-layer wirings or the arrangement of some vias, resulting in difficult layout design. However, the wiring in the spacer region 3 is simple. In the embodiment of the present invention, the line segment of the first signal line 5 located in the spacer region 3 is selected to be widened, which can effectively avoid the above problems and reduce the layout design difficulty.

[0022] In a feasible implementation manner, in combination with Figure 32 , the pixel circuit 4 includes a plurality of transistors 8.

[0023] As Figures 2 to 4 shown, Figure 2 is a schematic structural diagram of a first signal line provided by an embodiment of the present invention, Figure 3 is another schematic structural diagram of a first signal line provided by an embodiment of the present invention, Figure 4 is still another schematic structural diagram of a first signal line provided by an embodiment of the present invention. In at least part of the first signal line 5, the first line segment 6 includes a connected first sub-line segment 9 and a second sub-line segment 10. Among them, the first sub-line segment 9 is reused as the gate of the transistor 8, and the channel length direction corresponding to the reused gate of the first sub-line segment 9 is the first direction x. In this part of the first signal line 5, the width of the second line segment 7 in the first direction x is greater than the width of the first sub-line segment 9 in the first direction x.

[0024] Regarding the structure of transistor 8, as Figures 5 to 8 shown, Figure 5 FIG. Figure 6 is a schematic structural diagram of a transistor provided by an embodiment of the present invention, Figure 6 and is Figure 5 a cross-sectional view along the A1-A2 direction, Figure 7 FIG. Figure 8 is another schematic structural diagram of a transistor provided by an embodiment of the present invention, Figure 8 and is Figure 7 a cross-sectional view along the B1-B2 direction. Transistor 8 includes an active layer cl and a gate g. The active layer cl includes a channel c, a first doped region dr1, and a second doped region dr2.

[0025] Wherein, in a direction perpendicular to the plane of the display panel, the gate g coincides with the channel c.

[0026] At least one of the first doped region dr1 and the second doped region dr2 is connected to the connection lead 11. Refer to Figure 5 and Figure 6 , the connection lead 11 may be disposed in a different layer from the active layer cl, or refer to Figure 7 and Figure 8 , the connection lead 11 may also be disposed in the same layer as the active layer cl. Wherein, the channel length of transistor 8 is the distance between the first doped region dr1 and the second doped region dr2. The channel length of transistor 8 is the first direction x, which means that the arrangement direction of the first doped region dr1 and the second doped region dr2 of transistor 8 is the first direction x.

[0027] In addition, the pixel circuit 4 may include a single-gate transistor and a double-gate transistor. For example, Figure 5 the transistor 8 shown in Figure 6 is a single-gate transistor, and the two transistors 8 shown in

[0028] constitute a double-gate transistor. The two transistors 8 in the double-gate transistor are connected in series, and the gates of the two transistors 8 are electrically connected.

[0029] Next, the first sub-segment 9 in the first signal line 5 will be explained for the single-gate transistor and the double-gate transistor. Figure 2 Refer to

[0030] Refer to Figure 3, in a structure, the transistor 8 includes a second sub-transistor 8-2 and a third sub-transistor 8-3. The second sub-transistor 8-2 and the third sub-transistor 8-3 form a double-gate transistor, and the channel length directions of both the second sub-transistor 8-2 and the third sub-transistor 8-3 are the first direction x. In at least one first signal line 5, part of the first sub-segments 9 in the first segment 6 are multiplexed as the gate of the second sub-transistor 8-2, and part of the first sub-segments 9 are multiplexed as the gate of the third sub-transistor 8-3.

[0031] See Figure 4 , in a structure, the transistor 8 includes a fourth sub-transistor 8-4 and a fifth sub-transistor 8-5. The fourth sub-transistor 8-4 and the fifth sub-transistor 8-5 form a double-gate transistor. Among them, the channel length direction of the fourth sub-transistor 8-4 is the first direction x, and the channel length direction of the fifth sub-transistor 8-5 is the second direction y. In at least one first signal line 5, at least part of the first sub-segments 9 in the first segment 6 are multiplexed as the gate of the fourth sub-transistor 8-4. It should be noted that in this structure, the gate of the fifth sub-transistor 8-5 protrudes from the first segment 6 along the first direction x, and this gate does not belong to the first segment 6.

[0032] Next, taking a film layer structure of the pixel circuit 4 as an example, the first signal line 5 will be further described.

[0033] Combined with Figures 32 to 34 , as Figure 9 shown, Figure 9 is a schematic diagram of a film layer structure of a display panel provided by an embodiment of the present invention. The pixel circuit 4 includes a second gate reset transistor M9, a second data writing transistor M10, a second threshold compensation transistor M11, and an anode reset transistor M12. In subsequent embodiments, the connection relationship of these transistors 8 will be described.

[0034] Among them, the second data writing transistor M10 and the anode reset transistor M12 are the first sub-transistors 8-1.

[0035] The second gate reset transistor M9 is a double-gate transistor. The second gate reset transistor M9 includes a first sub-reset transistor M9-1 and a second sub-reset transistor M9-2 connected in series. Among them, the first sub-reset transistor M9-1 is the second sub-transistor 8-2, and the second sub-reset transistor M9-2 is the third sub-transistor 8-3.

[0036] The second threshold compensation transistor M11 is a double-gate transistor. The second threshold compensation transistor M11 includes a first sub-compensation transistor M11-1 and a second sub-compensation transistor M11-2 connected in series. Among them, the first sub-compensation transistor M11-1 is the fifth sub-transistor 8-5, and the second sub-compensation transistor M11-2 is the fourth sub-transistor 8-4.

[0037] The first signal line 5 includes a second reset scan line PAM-S1. Part of the first sub-segments 9 in the second reset scan line PAM-S1 are multiplexed as the gates of the first sub-reset transistors M9-1, and part of the first sub-segments 9 are multiplexed as the gates of the second sub-reset transistors M9-2. Moreover, the width of the second segment 7 in the first signal line 5 in the first direction x is greater than the width of the first sub-segments 9 in the first direction x.

[0038] The first signal line 5 includes a second compensation scan line PAM-S2. Part of the first sub-segments 9 in the second compensation scan line PAM-S2 are multiplexed as the gates of the second sub-compensation transistors M11-2, part of the first sub-segments 9 are multiplexed as the gates of the second data writing transistors M10, and part of the first sub-segments 9 are multiplexed as the gates of the anode reset transistors M12. Moreover, the width of the second segment 7 in the second compensation scan line PAM-S2 in the first direction x is greater than the width of the first sub-segments 9 in the first direction x.

[0039] In the above structure, at least part of the first signal lines 5 in the display panel are scan lines for providing gate signals to the transistors 8. These first signal lines 5 are used to control the on and off of the transistors 8, and their signal quality has a greater impact on the stability of the pixel circuit 4. Therefore, after the load of this part of the first signal lines 5 is reduced, the display effect can be improved more significantly.

[0040] Moreover, in the embodiments of the present invention, the first sub-segments 9 used for multiplexing the transistor gates in these first signal lines 5 are not widened, and the width of the first sub-segments 9 still follows the design requirements of the channel width-to-length ratio of the corresponding transistors 8. Therefore, while reducing the load of these first signal lines 5, the device size of the transistors 8 connected thereto is not affected.

[0041] Further, referring again to Figures 2 to 4 , in the first segment 6, the width of the second sub-segments 10 in the first direction x is equal to the width of the first sub-segments 9 in the first direction x.

[0042] That is, in the embodiments of the present invention, the width of this part of the first signal lines 5 located in the circuit region 2 is not widened, and only the segments in the spacer region 3 are widened. This not only avoids affecting the original wiring and via arrangement in the pixel circuit 4, but also avoids increasing the parasitic capacitance between the first signal lines 5 and the pixel circuit 4.

[0043] In a feasible embodiment, as Figure 10 shown, Figure 10Another structural schematic diagram of the display panel provided by the embodiment of the present invention. The display panel further includes a second signal line 12, and the second signal line 12 extends along the first direction x and is located in the spacer region 3.

[0044] Wherein, at least a part of the second signal line 12 is electrically connected to the pixel circuit 4. For example, referring to Figures 32 to 34 , the second signal line 12 may include at least one of a first data line PWM-Data, a second data line PWM-Data, a first reset line PWM-REF, a second reset line PAM-REF, an anode reset line PAM-INIT, a first power supply line PWM-vdd, and a second power supply line PAM-vdd.

[0045] In at least a part of the first signal line 5, the connection point A between the second segment 7 and the first segment 6 is located in the spacer region 3, and the distance a1 between the connection point A and the adjacent pixel circuit 4 is less than the distance a2 between the connection point and the adjacent second signal line 12.

[0046] Wherein, the connection point A between the first segment 6 and the second segment 7 can be understood as the position where the line width of the first signal line 5 starts to change in the spacer region 3. For example, referring to Figure 11 and Figure 14 , the connection point A is the connection position of the first side 13 of the first segment 6 and the third side 15 of the second segment 7.

[0047] The distance a1 between the connection point A and the pixel circuit 4 can be understood as the distance between the second segment 7 and the closest trace in the pixel circuit 4. For example, referring to Figure 21 and Figure 22 , the distance a1 is the distance between the second segment 7 and the first trace 27.

[0048] The distance a2 between the connection point A and the adjacent second signal line 12 can be understood as the distance between the first segment 6 and the closest second signal line 12.

[0049] When widening the first signal line 5, making the widening position closer to the pixel circuit 4 can make the widened segment have a greater length, and the widened segment plays a greater role in reducing the load of the first signal line 5.

[0050] In a feasible implementation manner, as Figure 11 shown, Figure 11 Another structural schematic diagram of the first signal line provided by the embodiment of the present invention. The first segment 6 includes a first side 13 and a second side 14 opposite to each other in the first direction x, and the second segment 7 includes a third side 15 and a fourth side 16 opposite to each other in the first direction x and both extending along the second direction y.

[0051] The first signal line 5 includes a first type of first signal line 17. In the first type of first signal line 17, the distance b1 between the extension line of the third side 15 and the first side 13 is less than the distance b2 between the extension line of the fourth side 16 and the second side 14.

[0052] In the above setting method, the second line segment 7 in the first type of first signal line 17 has different widening degrees on both sides. While reducing the load of the first type of first signal line 17, it can make the widened line segment more flexibly match the wiring conditions of other traces on both sides of the first type of first signal line 17. For example, when the first type of first signal line 17 is very close to other traces on one side, the second line segment 7 can be widened to a small extent or not widened on that side, so as to ensure that there is enough distance between the second line segment 7 and the adjacent trace on that side and avoid large coupling.

[0053] In a feasible implementation manner, referring again to Figure 11 , the display panel further includes a third signal line 18 and a fourth signal line 19.

[0054] The third signal line 18 extends along the second direction y and is adjacent to the first type of first signal line 17 on one side of the first side 13. That is, the third signal line 18 is the horizontal signal line closest to the first type of first signal line 17 on one side of the first side 13, and there is no other horizontal signal line between the third signal line 18 and the first type of first signal line 17.

[0055] The fourth signal line 19 extends along the second direction y and is adjacent to the first type of first signal line 17 on one side of the second side 14. That is, the fourth signal line 19 is adjacent to the first type of first signal line 17 on one side of the second side 14 means that the fourth signal line 19 is the horizontal signal line closest to the first type of first signal line 17 on one side of the second side 14, and there is no other horizontal signal line between the fourth signal line 19 and the first type of first signal line 17.

[0056] Wherein, the distance between the third signal line 18 and the first side 13 is less than the distance between the fourth signal line 19 and the second side 14.

[0057] When the first type of first signal line 17 is closer to the adjacent horizontal signal line on one side of the first side 13, making the second line segment 7 in the first type of first signal line 17 widened to a small extent or not widened on that side can avoid the increase of the parasitic capacitance between the second line segment 7 and the third signal line 18.

[0058] It should be noted that the third signal line 18 and / or the fourth signal line 19 can also be the first signal line 5, that is, the third signal line 18 and / or the fourth signal line 19 can also adopt the widening design provided by the embodiments of the present invention.

[0059] In a feasible implementation, referring again to Figure 11 , the display panel further includes a third signal line 18. The third signal line 18 extends along the second direction y and is adjacent to the first type of first signal lines 17 on one side of the first side 13. That is, the third signal line 18 is the horizontal signal line closest to the first type of first signal lines 17 on one side of the first side 13, and there are no other horizontal signal lines between the third signal line 18 and the first type of first signal lines 17.

[0060] Wherein, the third signal line 18 and the first type of first signal lines 17 are arranged on different layers.

[0061] In the layout design of the display panel, when two adjacent horizontal signal lines are on different layers, since there is no need to consider the problem of short circuit between them, the distance between these two horizontal signal lines is usually set relatively small. When the first type of first signal lines 17 and the third signal line 18 adjacent to them on one side of the first side 13 are on different layers, the second segment 7 in the first type of first signal lines 17 can be widened to a small extent or not widened on this side, so as to avoid the increase of the parasitic capacitance between the second segment 7 and the third signal line 18.

[0062] Next, taking a film layer structure of the pixel circuit 4 as an example, the first type of first signal lines 17 will be schematically described.

[0063] As Figure 12 shown, Figure 12 is another schematic diagram of the film layer structure of the display panel provided by the embodiment of the present invention. The first type of first signal lines 17 includes a second reset scan line PAM-S1, and the third signal line 18 includes a second reset line PAM-REF. The second reset scan line PAM-S1 is adjacent to the second reset line PAM-REF on one side of the first side 13, and the second reset line PAM-REF and the second reset scan line PAM-S1 are arranged on different layers.

[0064] In the second reset scan line PAM-S1, the second segment 7 is widened to a small extent or not widened on the side close to the second reset line PAM-REF, and is widened to a large extent on the side far from the second reset line PAM-REF, so as to avoid increasing the parasitic capacitance between the second reset scan line PAM-S1 and the second reset line PAM-REF.

[0065] In a feasible implementation, as Figure 13 shown, Figure 13 is another schematic diagram of the first signal line provided by the embodiment of the present invention. In the first type of first signal lines 17, the extension line of the third side 15 coincides with the first side 13.

[0066] This setting method widens the second segment 7 of the first type of first signal line 17 unilaterally. At this time, the distance between the second segment 7 and the third signal line 18 is the same as the distance between the first segment 6 and the third signal line 18, and it will not cause an increase in the coupling between the first type of first signal line 17 and the third signal line 18.

[0067] In a feasible implementation, as Figure 14 shown, Figure 14 is another structural schematic diagram of the first signal line provided by the embodiment of the present invention. The first segment 6 includes a first side 13 and a second side 14 opposite to each other in the first direction x. The second segment 7 includes a third side 15 and a fourth side 16 opposite to each other in the first direction x and both extending along the second direction y.

[0068] The first signal line 5 includes a second type of first signal line 20. In the second type of first signal line 20, the distance b3 between the extension line of the third side 15 and the first side 13 is equal to the distance b4 between the extension line of the fourth side 16 and the second side 14.

[0069] The second segment 7 of the second type of first signal line 20 is widened equally on both sides. This structure is more suitable for the case where the first signal line 5 is far from other wirings on both sides. Widening the second segment 7 equally on both sides facilitates achieving a larger widening ratio for the second segment 7, which helps to reduce the load of the second type of first signal line 20 to a greater extent.

[0070] Next, taking a film layer structure of the pixel circuit 4 as an example, the second type of first signal line 20 will be schematically described.

[0071] As Figure 15 shown, Figure 15 is another film layer structure schematic diagram of the display panel provided by the embodiment of the present invention. The second type of first signal line 20 includes a second compensation scan line PAM-S2. In the second compensation scan line PAM-S2, the second segment 7 is widened equally on both sides, and the second compensation scan line PAM-S2 can have a lower load. Since the second compensation scan line PAM-S2 is used to provide gate signals to the first sub-compensation transistor M11-1, the second sub-compensation transistor M11-2, the second data writing transistor M10, and the anode reset transistor M12, and the number of transistors 8 it drives is relatively large, the lower its load, the smaller the delay and attenuation of the second compensation scan signal.

[0072] In a feasible implementation, as Figure 16 shown, Figure 16 is another structural schematic diagram of the first signal line provided by the embodiment of the present invention. The first signal line 5 includes a third type of first signal line 21 and a fourth type of first signal line 22.

[0073] Among them, the line width of the first segment 6 in the third type of first signal line 21 is d1, the line width of the second segment 7 is d2, the line width of the first segment 6 in the fourth type of first signal line 22 is d3, and the line width of the second segment 7 is d4. .

[0074] In the display panel, the number of transistors 8 driven by different first signal lines 5 can be different, and the distance between different first signal lines 5 and their adjacent traces can also be different. In the above setting method, different design is carried out on the widening ratio of the second segment 7 in at least two first signal lines 5, so that the widening degree of the second segment 7 in different first signal lines 5 can better adapt to its own situation.

[0075] For example, the pixel circuit 4 includes a plurality of transistors 8, and the third type of first signal line 21 is used to provide signals to the gates of the transistors 8, that is, the third type of first signal line 21 is a scan line.

[0076] Among various signal lines electrically connected to the pixel circuit 4, the scan line is used to control the on or off of the transistor 8, and the influence of the delay and attenuation of the scan signal on the display is more obvious. Therefore, setting the third type of first signal line 21 as the scan line, the wider second segment 7 in the third type of first signal line 21 can have a greater improvement effect on the delay and attenuation of the signal.

[0077] For the fourth type of first signal line 22, the fourth type of first signal line 22 can be a constant voltage signal line, or it can also be a scan line. For example, the third type of first signal line 21 includes a second compensation scan line PAM-S2, and the fourth type of first signal line 22 includes a second reset scan line PAM-S1. Compared with the second reset scan line PAM-S1, the second compensation scan line PAM-S2 drives more transistors 8, and is used to control the charging and threshold compensation of the second driving transistor M8. Therefore, the influence degree of the second compensation scan signal on the operation of the pixel circuit 4 will be greater. Setting the second compensation scan line PAM-S2 as the third type of first signal line 21 can have a greater improvement effect on the delay and attenuation of the second compensation scan signal.

[0078] In a feasible implementation manner, as Figure 17 shown, Figure 17 is another structural schematic diagram of the first signal line provided by the embodiment of the present invention. In at least part of the first signal lines 5, the second segment 7 includes a third sub-segment 23 and a fourth sub-segment 24, and the third sub-segment 23 is connected between the first segment 6 and the fourth sub-segment 24.

[0079] Wherein, along the direction of the first line segment 6 pointing to the fourth sub-line segment 24, the width of the third sub-line segment 23 increases in the first direction x, and the maximum width of the third sub-line segment 23 in the first direction x is equal to the width of the fourth sub-line segment 24 in the first direction x.

[0080] The gradual change in the width of the third sub-line segment 23 can provide a buffer with a gradual change in width when the width of the first signal line 5 changes. Especially when the widening ratio of the second line segment 7 is large, a smooth change in line width and load can be achieved.

[0081] Furthermore, as Figures 18 to 20 shown, Figure 18 Another structural schematic diagram of the first signal line provided by the embodiment of the present invention. Figure 19 Another structural schematic diagram of the first signal line provided by the embodiment of the present invention. Figure 20 Another structural schematic diagram of the first signal line provided by the embodiment of the present invention. The lengths of the third sub-line segments 23 of at least part of the first signal line 5 in the second direction y are different. And / or, the third sub-line segment 23 includes a fifth side 25, and there is a first included angle α between the extending direction of the fifth side 25 and the second direction y. The first included angles α corresponding to the third sub-line segments 23 of at least part of the first signal line 5 are different.

[0082] The above settings can make the design of the third sub-line segments 23 in different first signal lines 5 more flexible. For example, when the widths of the first line segments 6 in the first direction x of two types of first signal lines 5 are the same, but the widths of the second line segments 7 in the first direction x are different, the third sub-line segments 23 in the two can be Figure 18 as shown, with the same length in the second direction y but different corresponding first included angles α, or can also be Figure 19 as shown, with different lengths in the second direction y but the same corresponding first included angle α, or can also be Figure 20 as shown, with different lengths in the second direction y and different corresponding first included angles α.

[0083] In a feasible implementation manner, as Figure 21 and Figure 22 shown, Figure 21 Another schematic diagram of the film layer structure of the display panel provided by the embodiment of the present invention. Figure 22 Another schematic diagram of the film layer structure of the display panel provided by the embodiment of the present invention. The pixel circuit 4 includes a first pixel circuit 26, the first pixel circuit 26 is adjacent to the spacer 3, and the first pixel circuit 26 includes at least one first trace 27.

[0084] In at least a part of the first signal line 5, in a direction perpendicular to the plane of the display panel, the first segment 6 overlaps with the first trace 27, and the positive projection of the second segment 7 on the plane of the display panel is adjacent to the positive projection of the first trace 27 on the plane of the display panel. Moreover, the distance between the second segment 7 and the first trace 27 on the plane of the display panel is greater than or equal to 1 μm. Further, this distance can be greater than or equal to 1.5 μm.

[0085] It should be noted that the positive projection of the second segment 7 on the plane of the display panel being adjacent to the positive projection of the first trace 27 on the plane of the display panel means that there is no other longitudinal trace's positive projection on the plane of the display panel between their positive projections. In other words, the first trace 27 can be understood as the longitudinal trace closest to the second segment 7 in the first pixel circuit 26.

[0086] In addition, as Figure 23 shown, Figure 23 FIG. is a schematic diagram of another film layer structure of the display panel provided by the embodiment of the present invention. The display panel may further include a shielding metal 32. The film layer where the shielding metal 32 is located is on the side closer to the substrate than the film layer where the transistor 8 is located. The shielding metal 32 overlaps with the channel of the transistor 8 and is used to prevent external ambient light from irradiating on the channel and affecting the device characteristics of the transistor 8. When the positive projection of the shielding metal 32 on the plane of the display panel is included between the positive projections of the second segment 7 and the first trace 27 on the plane of the display panel, this does not belong to the case where there is a positive projection of a longitudinal trace between the positive projections of the second segment 7 and the first trace 27.

[0087] When widening the design of the first signal line 5, making the positive projection of the widening position at least 1 μm away from the positive projection of the first trace 27 can reserve sufficient space for the position deviation between the first trace 27 and the first signal line 5. For example, even if the positions of the first trace 27 and / or the first signal line 5 shift, it can be avoided that the second segment 7 is too close to the first trace 27 or the two overlap, thereby avoiding an increase in the coupling between the second segment 7 and the first trace 27. Or when the first trace 27 is the active layer of a certain transistor 8, it can be prevented that the second segment 7 overlaps with the first trace 27 and changes the aspect ratio of the transistor 8.

[0088] Further, referring again to Figure 22 , the first pixel circuit 26 includes a first transistor 28. The first trace 27 includes a first type of first trace 29, and the first type of first trace 29 is the active layer of the first transistor 28.

[0089] In at least a part of the first signal line 5, a part of the first segment 6 is multiplexed as the gate of the first transistor 28, and the orthogonal projection of the second segment 7 on the plane of the display panel is adjacent to the orthogonal projection of the first type of first trace 29 on the plane of the display panel, and the distance k1 between the orthogonal projection of the second segment 7 on the plane of the display panel and the orthogonal projection of the first type of first trace 29 on the plane of the display panel is greater than or equal to 1 μm.

[0090] For example, the first transistor 28 is an anode reset transistor M12, and the first type of first trace 29 is the active layer M12 of the anode reset transistor 8. The first signal line 5 includes a second compensation scan line PAM-S2. In the second compensation scan line PAM-S2, a part of the first segment 6 is multiplexed as the gate of the anode reset transistor M12, and the distance between the orthogonal projection of the second segment 7 on the plane of the display panel and the orthogonal projection of the active layer of the anode reset transistor M12 on the plane of the display panel is k1.

[0091] When the first type of first trace 29 is the active layer of the first transistor 28, the orthogonal projection of the active layer is spaced more than 1 μm from the orthogonal projection of the second segment 7, leaving enough margin for the trace offset caused by process errors, and preventing the second segment 7 from overlapping with the active layer and affecting the channel width-to-length ratio of the first transistor 28.

[0092] And / or, referring again to Figure 22 the first pixel circuit 26 includes a second transistor 30. The first trace 27 includes a second type of first trace 31, and the second type of first trace 31 is electrically connected to the second transistor 30.

[0093] In at least a part of the first signal line 5, in the direction perpendicular to the plane of the display panel, the first segment 6 overlaps with the second type of first trace 31, the orthogonal projection of the second segment 7 on the plane of the display panel is adjacent to the orthogonal projection of the second type of first trace 31 on the plane of the display panel, and the distance k2 between the orthogonal projection of the second segment 7 on the plane of the display panel and the orthogonal projection of the second type of first trace 31 on the plane of the display panel is greater than or equal to 1 μm.

[0094] Wherein, the second transistor 30 and the above-mentioned first transistor 28 can be the same transistor 8 or different transistors 8.

[0095] For example, referring to Figure 22, the second transistor 30 is also the anode reset transistor M12, and the first trace 31 of the second type is the connection line between the anode reset transistor M12 and the anode reset line PAM-INIT. The first signal line 5 includes the second reset scan line PAM-S1. In the second reset scan line PAM-S1, the positive projection of the first segment 6 on the plane of the display panel and the positive projection of the connection line between the anode reset transistor M12 and the anode reset line PAM-INIT on the plane of the display panel overlap, and the distance between the positive projection of the second segment 7 on the plane of the display panel and the positive projection of the connection line on the plane of the display panel is k2.

[0096] When the first trace 31 of the second type is the connection line between the second transistor 30 and other structures, the positive projection of the connection line is spaced more than 1 μm from the positive projection of the second segment 7, leaving sufficient margin for the trace offset caused by process errors, and preventing the second segment 7 from being too close to or overlapping with the connection line, thereby increasing their coupling.

[0097] In a feasible implementation manner, as Figure 24 shown, Figure 24 is another schematic diagram of the film layer structure of the display panel provided by the embodiment of the present invention. The widths of the second segments 7 in at least part of the first signal lines 5 in the first direction x are different, and the distances between the positive projections of the second segments 7 on the plane of the display panel and the positive projections of the first traces 27 on the plane of the display panel are also different.

[0098] For example, referring to Figure 24 , the first signal line 5 includes the second reset scan line PAM-S1 and the second compensation scan line PAM-S2. The width of the second segment 7 in the second compensation scan line PAM-S2 in the first direction x is greater than the width of the second segment 7 in the second reset scan line PAM-S1 in the first direction x, and the distance between the positive projection of the second segment 7 in the second compensation scan line PAM-S2 on the plane of the display panel and the positive projection of the first trace 29 of the first type on the plane of the display panel is greater than the distance between the positive projection of the second segment 7 in the second reset scan line PAM-S1 on the plane of the display panel and the positive projection of the first trace 31 of the second type on the plane of the display panel.

[0099] The second compensation scan line PAM-S2 is used to control the charging and threshold compensation of the second driving transistor M8. The quality of the second compensation scan signal has a greater impact on the pixel circuit 4. Therefore, the widening ratio of the second segment 7 in the second compensation scan line PAM-S2 can be set larger. At the same time, in the second compensation scan line PAM-S2, the first trace 28 adjacent to the second segment 7 is the active layer M12 of the anode reset transistor 8. The width of the second segment 7 is relatively large. If the active layer M12 of the anode reset transistor 8 overlaps with the second segment 7 due to the offset of the trace position, the channel width-to-length ratio of the anode reset transistor 8 will change significantly. Therefore, the distance between the orthographic projection of the second segment 7 in the second compensation scan line PAM-S2 and the orthographic projection of the first type of first trace 29 can also be set larger to avoid this problem.

[0100] Furthermore, there is a positive correlation between the width of the second segment 7 in the first direction x and the distance between the orthographic projection of the second segment 7 in the plane of the display panel and the orthographic projection of the first trace 27 in the plane of the display panel. That is, for different first signal lines 5, the larger the width of the second segment 7 in the first direction x in the first signal line 5, the larger the distance between the orthographic projection of the second segment 7 and the orthographic projection of the first trace 27.

[0101] In a feasible implementation manner, as Figure 25 shown, Figure 25 FIG. is another schematic structural diagram of the display panel provided by the embodiment of the present invention. The display panel further includes a second signal line 12, and the second signal line 12 extends along the first direction x and is located in the spacer region 3.

[0102] At least a part of the second segment 7 in the first signal line 5 includes a first hollow 33, and in the direction perpendicular to the plane of the display panel, the first hollow 33 overlaps with the second signal line 12. And / or, at least a part of the second signal line 12 includes a second hollow 34, and in the direction perpendicular to the plane of the display panel, the second hollow 34 overlaps with the second segment 7.

[0103] When the first signal line 5 extends horizontally, it will inevitably overlap with the vertically extending second signal line 12. In the embodiment of the present invention, by providing the first hollow 33 on at least a part of the second segment 7 of the first signal line 5 and / or providing the second hollow 34 on at least a part of the second signal line 12, the overlapping area between the first signal line 5 and the second signal line 12 in the spacer region 3 can be reduced, thereby reducing the coupling between the two and reducing signal interference.

[0104] In a feasible implementation manner, referring again to Figure 25 , the second signal line 12 includes a first type of second signal line 35 and a second type of second signal line 36.

[0105] Among them, the first type of second signal line 35 is used to transmit a variable voltage signal, and the variable voltage signal refers to a signal whose voltage will change, such as a data signal, etc. The second type of second signal line 36 is used to transmit a constant voltage signal, and the constant voltage signal refers to a signal whose voltage will not change, such as a power supply signal, a reset signal, etc.

[0106] In the direction perpendicular to the plane of the display panel, the first hollow 33 overlaps with the first type of second signal line 35, and the second type of second signal line 36 includes a second hollow 34.

[0107] Generally, the second type of second signal line 36 for transmitting a constant voltage signal in the spacer 3 will have a larger line width. With the above structure, on the one hand, the first hollow 33 in the first signal line 5 overlaps with the first type of second signal line 35, and the first hollow 33 can be used to reduce the coupling between the first signal line 5 and the first type of second signal line 35. In this way, the first type of second signal line 35 does not need to be provided with a second hollow 34, avoiding affecting the trace resistance of the first type of second signal line 35 itself; on the other hand, the second hollow 34 is provided in the second type of second signal line 36, and the second hollow 34 can be used to reduce the coupling between the first signal line 5 and the second type of second signal line 36. In this way, the first signal line 5 does not need to be provided with a first hollow 33 at the overlapping position with the second type of second signal line 36, avoiding excessive number of hollows in the first signal line 5 and affecting its own resistance.

[0108] In a feasible implementation manner, as Figure 26 shown, Figure 26 is another schematic structural diagram of the display panel provided by the embodiment of the present invention. The second signal line 12 includes a first type of second signal line 35 and a second type of second signal line 36.

[0109] Among them, the first type of second signal line 35 is used to transmit a variable voltage signal, and the variable voltage signal refers to a signal whose voltage will change, such as a data signal, etc. The second type of second signal line 36 is used to transmit a constant voltage signal, and the constant voltage signal refers to a signal whose voltage will not change, such as a power supply signal, a reset signal, etc.

[0110] The first hollow 33 includes a first sub - hollow 37 and a second sub - hollow 38, and the area of the first sub - hollow 37 is larger than the area of the second sub - hollow 38. In the direction perpendicular to the plane of the display panel, the first sub - hollow 37 overlaps with the first type of second signal line 35, and the second sub - hollow 38 overlaps with the second type of second signal line 36.

[0111] Compared with a constant voltage signal, a variable voltage signal is more likely to cause signal instability due to reasons such as coupling. Therefore, when a hollow is provided on the second segment 7 of the first signal line 5, some large-area hollows can be designed to overlap with the first type of second signal lines 35, so as to reduce the coupling between the first signal line 5 and the first type of second signal lines 35 to a greater extent, thereby reducing the signal interference between the two and improving the stability of the variable voltage signal on the first type of second signal lines 35.

[0112] Further, referring to Figure 25 and Figure 26 , the first type of second signal lines 35 includes data lines for providing data voltages to the pixel circuits 4. For example, in combination with Figures 32 to 34 , when the pixel circuit 4 includes a pulse width modulation module PWM and a pulse amplitude modulation module PAM, the first type of second signal lines 35 may include a first data line PWM-Data electrically connected to the pulse width modulation module PWM, and a second data line PAM-Data electrically connected to the pulse amplitude modulation module PAM.

[0113] The second type of second signal lines 36 includes power lines for providing power voltages to the pixel circuits 4, and / or includes reset lines for providing reset voltages to the pixel circuits 4. For example, in combination with Figures 32 to 34 , when the pixel circuit 4 includes a pulse width modulation module PWM and a pulse amplitude modulation module PAM, the second type of second signal lines 36 may include at least one of a first reset line PWM-REF and a first power line PWM-vdd electrically connected to the pulse width modulation module PWM, and / or includes at least one of a second reset line PAM-REF, an anode reset line PAM-INIT, and a second power line PAM-vdd electrically connected to the pulse amplitude modulation module PAM.

[0114] In a feasible implementation manner, as shown in Figure 27 , Figure 27 is another structural schematic diagram of the display panel provided by the embodiment of the present invention. The display panel further includes a second signal line 12, and the second signal line 12 extends along the first direction x and is located in the spacer region 3.

[0115] In at least part of the first signal line 5, the second segment 7 includes a fifth sub-segment 39 and a sixth sub-segment 40. In the direction perpendicular to the plane of the display panel, the fifth sub-segment 39 does not overlap with the second signal line 12, the sixth sub-segment 40 overlaps with the second signal line 12, and the width of the fifth sub-segment 39 in the first direction x is greater than the width of the sixth sub-segment 40 in the first direction x.

[0116] In this structure, the second line segment 7 includes a fifth sub-line segment 39 and a sixth sub-line segment 40 with different widths. By making the fifth sub-line segment 39 with a larger width not overlap with the second signal line 12, it is possible to avoid a large coupling between the second line segment 7 and the second signal line 12 while reducing the load of the first signal line 5 to a greater extent using the fifth sub-line segment 39.

[0117] In a feasible implementation, referring to Figures 28 to 30 , the first signal line 5 includes a fifth type of first signal line 41. In the fifth type of first signal line 41, at least part of the second line segment 7 has different widths in the first direction x, so as to reduce the load to different extents using the second line segment 7 with different widths at different positions, in order to better adapt to the signal attenuation conditions of the fifth type of first signal line 41 at different positions, etc.

[0118] In a feasible implementation, as Figure 28 shown, Figure 28 is another structural schematic diagram of the display panel provided by the embodiment of the present invention. The display panel further includes a first shift register 43. A first connection line 44 is connected between the fifth type of first signal line 41 and the first shift register 43, and a first via 45 is provided between the fifth type of first signal line 41 and the first connection line 44.

[0119] The second line segment 7 in the fifth type of first signal line 41 includes a first type of second line segment 46 and a second type of second line segment 47. Among them, the distance between the second type of second line segment 47 and the first via 45 is greater than the distance between the first type of second line segment 46 and the first via 45, and the width of the second type of second line segment 47 in the first direction x is greater than the width of the first type of second line segment 46 in the first direction x.

[0120] In the implementation of the present invention, the first shift register 43 can be located in the display area. The first shift register 43 includes a plurality of cascaded first shift units 48, and the first shift unit 48 is electrically connected to the fifth type of first signal line 41 through the first connection line 44. The first shift unit 48 can be arranged between adjacent circuit rows 1, so as to avoid occupying the border space and enable the display panel to achieve a borderless design.

[0121] In the fifth type of first signal line 41, for the second type of second line segment 47 that is far from the first via 45, since the signal transmitted by the first shift unit 48 has a longer transmission distance, the delay and attenuation of the signal during transmission will be greater. By making the second type of second line segment 47 have a larger line width, the problem of larger delay and attenuation caused by the longer signal transmission distance at this position can be weakened using the larger line width, which helps to optimize the signal consistency at different positions in the fifth type of first signal line 41.

[0122] In a feasible implementation manner, referring back to Figures 28 to 30 , in the first signal line 41 of the fifth type, at least three consecutively arranged second line segments 7 have a gradually changing width in the first direction x, so as to achieve a smooth change in the load of the first signal line 41 of the fifth type in different regions.

[0123] In a feasible implementation manner, as Figure 29 and Figure 30 shown, Figure 29 is another structural schematic diagram of the display panel provided by the embodiment of the present invention, Figure 30 is Figure 29 a structural schematic diagram of the corresponding first signal line 5. The display panel has a first central axis 49 extending in the first direction x, and the display panel includes two first display areas 50 located on opposite sides of the first central axis 49.

[0124] The display panel includes a first shift register 43, and the first shift register 43 includes a plurality of cascaded first shift units 48. The first shift units 48 are located between adjacent circuit rows 1. The first signal line 41 of the fifth type is electrically connected to two first shift registers 43, and the two first shift registers 43 are respectively located in the two first display areas 50.

[0125] For the convenience of distinction, Figure 29 and Figure 30 the two first shift registers 43 are respectively identified by reference numerals 43-1 and 43-2 in the figures.

[0126] Among them, referring to Figure 30 , the first signal line 41 of the fifth type includes two first parts 51. The two first parts 51 are respectively located in the two first display areas 50. The first part 51 includes a first sub-part 52 and a second sub-part 53. The second sub-part 53 is connected between the first sub-part 52 and the other first part 51.

[0127] The second line segment 7 in the first sub-part 52 includes a second line segment 54 of the third type and a second line segment 55 of the fourth type. Among them, the distance between the second line segment 54 of the third type and the first central axis 49 is greater than the distance between the second line segment 55 of the fourth type and the first central axis 49, and the width of the second line segment 54 of the third type in the first direction x is greater than the width of the second line segment 55 of the fourth type in the first direction x. The second line segment 7 in the second sub-part 53 includes a second line segment 56 of the fifth type and a second line segment 57 of the sixth type. The distance between the second line segment 56 of the fifth type and the first central axis 49 is greater than the distance between the second line segment 57 of the sixth type and the first central axis 49, and the width of the second line segment 56 of the fifth type in the first direction x is less than the width of the second line segment 57 of the sixth type in the first direction x. More specifically, in the first display area 50, a first connection line 44 is connected between the first shift unit 48 and the first signal line 5, and the first connection line 44 is connected to the first signal line 5 through a first via 45. The first sub - part 52 and the second sub - part 53 can be divided in the first part 51 according to the position where the first via 45 is located. That is, the first sub - part 52 is located on the side of the first via 45 away from the first central axis 49, and the second sub - part 53 is located on the side of the first via 45 close to the first central axis 49.

[0128] In the first sub - part 52, along the direction pointing to the first central axis 49, the widths of a plurality of second line segments 7 in the first direction x can be set to decrease; in the second sub - part 53, along the direction pointing to the first central axis 49, the widths of a plurality of second line segments 7 in the first direction x can be set to increase.

[0129] In this structure, two first shift registers 43 drive the first signal line 5 bilaterally. When a first shift register 43 is respectively arranged in two first display areas 50, according to the connection position of the first shift register 43 and the first part 51 of the first signal line 5, a more refined width change design can be carried out for the second line segments 7 at different positions of the first part 51, so that the second line segments 7 at positions with a longer signal transmission distance have a larger width, which helps to optimize the signal uniformity of the first signal line 5 at different positions.

[0130] In a feasible implementation manner, as Figure 31 shown, Figure 31 FIG. is another schematic structural diagram of the display panel provided by the embodiment of the present invention. The display panel further includes a first shift register 43. The first shift register 43 includes a plurality of cascaded first shift units 48, and the first shift units 48 are located between adjacent circuit rows 1.

[0131] The first signal line 5 includes a fifth - type first signal line 41, and the fifth - type first signal line 41 is electrically connected to the first shift unit 48. Among them, the fifth - type first signal line 41 includes a first sub - signal line 58 and a second sub - signal line 59. The distance between the first sub - signal line 58 and the first shift unit 48 connected thereto in the first direction x is greater than the distance between the second sub - signal line 59 and the first shift unit 48 connected thereto in the first direction x, and the width of the second line segment 7 in the first sub - signal line 58 in the first direction x is greater than the width of the second line segment 7 in the second sub - signal line 59 in the first direction x.

[0132] In a borderless display panel, the pixel circuit 4 at the edge position usually adopts an inward - shrinking design. For example, refer to Figure 30, the display panel includes a first sub-region 60 arranged along the first direction x and two second sub-regions 61. The two second sub-regions 61 are located on opposite sides of the first sub-region 60. Among them, the distance between adjacent circuit rows 1 in the second sub-region 61 is less than the distance between adjacent circuit rows 1 in the first sub-region 60. When the first shift unit 48 is located between adjacent circuit rows 1, generally it is arranged on one side of the circuit row 1 in the first sub-region 60. In this structure, the above-mentioned first sub-signal line 58 at least includes the fifth type of first signal line 41 in the second sub-region 61, and the second sub-signal line 59 at least includes the fifth type of first signal line 41 in the first sub-region 60.

[0133] For the electrically connected first shift unit 48 and the first sub-signal line 58, the signal output by the first shift unit 48 needs to be transmitted over a relatively long distance to reach the first sub-signal line 58. For this reason, the embodiments of the present invention propose that the width of the second line segment 7 in the first sub-signal line 58 can be set larger, so as to use the larger line width to weaken the problem of larger delay and attenuation of the first sub-signal line 58 caused by the relatively long signal transmission distance, and thus contribute to improving the signal consistency in the first sub-signal line 58 and the second sub-signal line 59.

[0134] Furthermore, referring again to Figure 31 , a first connection line 44 is connected between the fifth type of first signal line 41 and the first shift unit 48. Among them, the line width of the first connection line 44 connected to the first sub-signal line 58 is greater than the line width of the first connection line 44 connected to the second sub-signal line 59, so as to further improve the signal delay and attenuation problems of the first sub-signal line 58 by using the first connection line 44.

[0135] In a feasible implementation manner, the pixel circuit 4 includes a plurality of transistors 8, and at least part of the first signal line 5 is used to provide signals to the gates of the transistors 8, that is, the first signal line 5 includes a scan line. The scan line is used to drive the conduction and cut-off of the transistor 8, and its signal quality has a greater impact on the operation of the pixel circuit 4. Therefore, after widening the scan line to improve the delay and attenuation of the scan signal, the display effect can be better improved.

[0136] In a feasible implementation manner, as Figure 32 and Figure 33 shown, Figure 32 is a schematic circuit structure diagram of a pixel circuit provided by an embodiment of the present invention, Figure 33 is a schematic film layer structure diagram of a pixel circuit provided by an embodiment of the present invention. The pixel circuit 4 includes a pulse width modulation module PWM and a pulse amplitude modulation module PAM. Among them, the pulse width modulation module PWM realizes different brightness displays by controlling the light emission time, and the pulse amplitude modulation module PAM realizes different brightness displays by controlling the magnitude of the light emission current.

[0137] This kind of pixel circuit 4 is more suitable for borderless tiled display screens. In such display screens, the PPI of the display panel is small, and this kind of pixel circuit 4 can enable the light-emitting element to maintain a high luminous efficiency. However, the structure of this kind of pixel circuit 4 is complex. Affected by factors such as parasitic capacitance, the signal lines connected thereto usually have a large load. By adopting the technical solution of widening the design of the first signal line 5 provided by the embodiments of the present invention, the problem of large signal line load can be effectively overcome.

[0138] Among them, the pulse width modulation module PWM includes: The first driving transistor M1.

[0139] The first gate reset transistor M2, which is electrically connected between the first reset line PWM-REF and the gate of the first driving transistor M1.

[0140] In one case, the first gate reset transistor M2 is a double-gate transistor, including a third sub-reset transistor M2-1 and a fourth sub-reset transistor M2-2 connected in series. The gates of the third sub-reset transistor M2-1 and the fourth sub-reset transistor M2-2 are electrically connected. The first pole of the third sub-reset transistor M2-1 is electrically connected to the first reset line PAWM-REF, and the second pole of the fourth sub-reset transistor M2-2 is electrically connected to the gate of the first driving transistor M1.

[0141] The first data writing transistor M3, which is electrically connected between the first data line PWM-Data and the first pole of the first driving transistor M1.

[0142] The first threshold compensation transistor M4, which is electrically connected between the second pole and the gate of the first driving transistor M1.

[0143] In one case, the first threshold compensation transistor M4 is a double-gate transistor, including a third sub-compensation transistor M4-1 and a fourth sub-compensation transistor M4-2 connected in series. The gates of the third sub-compensation transistor M4-1 and the second sub-compensation transistor M4-2 are electrically connected. The first pole of the third sub-compensation transistor M4-1 is electrically connected to the second pole of the first driving transistor M1, and the second pole of the fourth sub-compensation transistor M4-2 is electrically connected to the gate of the first driving transistor M1.

[0144] The first capacitor C1, which is electrically connected between the sweep line SWEEP and the gate of the first driving transistor M1.

[0145] The control transistor M5, the first pole of the control transistor M5 is electrically connected to the ground wire GND, and the second pole is electrically connected to the gate of the first driving transistor M1 through the first capacitor C1.

[0146] The first light-emitting control transistor M6 is electrically connected between the first power supply line PWM-vdd and the first pole of the first driving transistor M1.

[0147] The second light-emitting control transistor M7 is electrically connected between the second pole of the first driving transistor M1 and the pulse amplitude modulation module PAM.

[0148] The pulse amplitude modulation module PAM includes: The second driving transistor M8, the gate of the second driving transistor M8 is electrically connected to the second pole of the second light-emitting control transistor M7.

[0149] The second gate reset transistor M9 is electrically connected between the second reset line PAM-REF and the gate of the second driving transistor M8.

[0150] In one case, the second gate reset transistor M9 is a dual-gate transistor, including a series-connected first sub-reset transistor M9-1 and a second sub-reset transistor M9-2. The gates of the first sub-reset transistor M9-1 and the second sub-reset transistor M9-2 are electrically connected. The first pole of the first sub-reset transistor M9-1 is electrically connected to the second reset line PAM-REF, and the second pole of the second sub-reset transistor M9-2 is electrically connected to the gate of the second driving transistor M8.

[0151] The second data writing transistor M10 is electrically connected between the second data line PAM-Data and the first pole of the second driving transistor M8.

[0152] The second compensation transistor M11 is electrically connected between the second pole of the second driving transistor M8 and the gate of the second driving transistor M8.

[0153] In one case, the second compensation transistor M11 is a dual-gate transistor, including a series-connected first sub-compensation transistor M11-1 and a second sub-compensation transistor M11-2. The gates of the first sub-compensation transistor M11-1 and the second sub-compensation transistor M11-2 are electrically connected. The first pole of the second sub-compensation transistor M11-2 is electrically connected to the second pole of the second driving transistor M8, and the second pole of the first sub-compensation transistor M11-1 is electrically connected to the gate of the second driving transistor M8.

[0154] The anode reset transistor M12 is electrically connected between the anode reset line PAM-INIT and the light-emitting element D.

[0155] The third light-emitting control transistor M13 is electrically connected between the second power supply line PAM-vdd and the first pole of the second driving transistor M8.

[0156] The fourth light-emitting control transistor M14 is electrically connected between the second pole of the second driving transistor M8 and the light-emitting element D.

[0157] A second capacitor C2 is electrically connected between a second power supply line PAM-vdd and the gate of a second driving transistor M8.

[0158] In an embodiment of the present invention, as Figure 34 shown, Figure 34 FIG. is a schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention. The first signal line 5 may include: A first reset scan line PWM-S1 that provides a signal to the gate of a first gate reset transistor M2 to improve the delay and attenuation of the first reset scan signal, etc.

[0159] And / or, a first compensation scan line PWM-S2 that provides a signal to the gates of a first threshold compensation transistor M4, a first data writing transistor M3, and a control transistor M5 to improve the delay and attenuation of the first compensation scan signal, etc.

[0160] And / or, a first light emission control scan line PWM-EM that provides a signal to the gates of a first light emission control transistor M6 and a second light emission control transistor M7 to reduce the relatively small load of the first light emission control scan line PWM-EM and improve the delay and attenuation of the first light emission control scan signal, etc.

[0161] And / or, a second reset scan line PAM-S1 that provides a signal to the gate of a second gate reset transistor M9 to improve the delay and attenuation of the second reset scan signal, etc.

[0162] And / or, a second compensation scan line PAM-S2 that provides a signal to the gates of a second data writing transistor M10, a second threshold compensation transistor M11, and an anode reset transistor M12 to improve the delay and attenuation of the second compensation scan signal, etc.

[0163] And / or, a second light emission control scan line PAM-EM that provides a signal to the gates of a third light emission control transistor M13 and a fourth light emission control transistor M14 to improve the delay and attenuation of the second light emission control scan signal, etc.

[0164] Among them, the first reset scan line PWM-S1 and the first compensation scan line PWM-S2 are respectively used to control the gate reset, charging, and threshold compensation of the first driving transistor M3, and the second reset scan line PAM-S1 and the second compensation scan line PAM-S2 are respectively used to control the gate reset, charging, and threshold compensation of the second driving transistor M8. The influence of these four scan lines on the performance of the pixel circuit 4 is greater, and correspondingly, the influence on the display effect is greater.

[0165] Therefore, in the embodiments of the present invention, the first signal line 5 may include at least one or more of a first reset scan line PWM-S1, a first compensation scan line PWM-S2, a second reset scan line PAM-S1, and a second compensation scan line PAM-S2.

[0166] In a feasible implementation manner, referring to Figures 32 to 34 , the pixel circuit 4 includes a pulse width modulation module PWM, and the pulse width modulation module PWM includes a first driving transistor M1 and a first capacitor C1.

[0167] Among them, the first signal line 5 includes a sweep line SWEEP, and the sweep line SWEEP is electrically connected to the gate of the first driving transistor M1 through the first capacitor C1.

[0168] The sweep signal can help to more accurately determine the luminous time duty ratio of each pixel and present accurate dark part details. Making the first signal line 5 include the sweep line SWEEP can improve the delay and attenuation of the sweep signal, etc., and thus also helps to optimize the display effect.

[0169] In addition, it should be noted that the circuit structure of the pixel circuit 4 shown in the drawings of the embodiments of the present invention and the arrangement manner of the transistors 8 in the layout of the pixel circuit 4 shown are only illustrative. In other alternative embodiments of the present invention, the pixel circuit 4 may also adopt other circuit structures, or the transistors 8 in the layout may also adopt other arrangement manners.

[0170] Based on the same inventive concept, the embodiments of the present invention also provide a display device, as Figure 35 and Figure 36 shown, Figure 35 is a schematic structural diagram of the display device provided by the embodiments of the present invention, Figure 36 is another schematic structural diagram of the display device provided by the embodiments of the present invention, and the display device includes the above-mentioned display panel 100.

[0171] It should be noted that, Figure 35 and Figure 36 The display devices shown are only illustrative. In the embodiments of the present invention, the display device may be Figure 35 the mobile phones, computers and other electronic devices shown, or may also be Figure 36 the spliced display screen including at least two display panels 100 shown.

[0172] The above are only the preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

[0173] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: include: A plurality of circuit rows arranged along a first direction, the circuit rows comprising circuit areas and spacing areas alternately arranged along a second direction, the circuit areas comprising pixel circuits, the first direction intersecting the second direction; A first signal line extends along the second direction and is electrically connected to the pixel circuit, the first signal line includes a first line segment located in the circuit area and a second line segment located at least in the spacing area, wherein the width of at least part of the second line segments in the first direction is greater than the width of at least part of the first line segments in the first direction.

2. The display panel according to claim 1, characterized in that: The pixel circuit includes a plurality of transistors; In at least part of the first signal line, the first line segment includes a first sub-line segment and a second sub-line segment that are connected, wherein the first sub-line segment is reused as the gate of the transistor, and the channel length direction corresponding to the gate reused by the first sub-line segment is the first direction, and the width of the second line segment in the first direction is greater than the width of the first sub-line segment in the first direction.

3. The display panel according to claim 2, characterized in that: The width of the second sub-line segment in the first direction is equal to the width of the first sub-line segment in the first direction.

4. The display panel according to claim 1, characterized in that: The display panel further includes a second signal line, which extends along the first direction and is located in the spacing area; In at least part of the first signal line, the junction of the second line segment and the first line segment is located in the spacing area, and the distance between the junction and the adjacent pixel circuit is smaller than the distance between the junction and the adjacent second signal line.

5. The display panel according to claim 1, characterized in that: The first line segment includes a first side and a second side opposite to each other in the first direction, and the second line segment includes a third side and a fourth side opposite to each other in the first direction and both extending along the second direction; The first signal lines include first-type first signal lines, in which a distance between an extension line of the third side and the first side is smaller than a distance between an extension line of the fourth side and the second side.

6. The display panel according to claim 5, characterized in that: The display panel further includes a third signal line and a fourth signal line; Among them, the third signal line extends along the second direction and is adjacent to the first type of first signal line on one side of the first edge, the fourth signal line extends along the second direction and is adjacent to the first type of first signal line on one side of the second edge, and the distance between the third signal line and the first edge is smaller than the distance between the fourth signal line and the second edge.

7. The display panel according to claim 5, characterized in that: The display panel further includes a third signal line extending along the second direction and adjacent to the first-type first signal line on one side of the first side, and the third signal line and the first-type first signal line are arranged in different layers.

8. The display panel according to claim 5, characterized in that: In the first-type first signal line, an extension line of the third side coincides with the first side.

9. The display panel according to claim 1, characterized in that: The first line segment includes a first side and a second side opposite to each other in the first direction, and the second line segment includes a third side and a fourth side opposite to each other in the first direction and both extending along the second direction; The first signal lines include second-type first signal lines, in which a distance between an extension line of the third side and the first side is equal to a distance between an extension line of the fourth side and the second side.

10. The display panel according to claim 1, characterized in that: The first signal line includes a third-category first signal line and a fourth-category first signal line; Among them, the line width of the first line segment in the third type of first signal line is d1, and the line width of the second line segment is d2; the line width of the first line segment in the fourth type of first signal line is d3, and the line width of the second line segment is d4. 。 11. The display panel according to claim 10, characterized in that: The pixel circuit includes a plurality of transistors, and the third-type first signal line is used to provide signals to gates of the transistors.

12. The display panel according to claim 1, characterized in that: In at least part of the first signal line, the second line segment includes a third sub-line segment and a fourth sub-line segment, and the third sub-line segment is connected between the first line segment and the fourth sub-line segment, wherein along the direction from the first line segment to the fourth sub-line segment, the width of the third sub-line segment in the first direction increases, and the maximum width of the third sub-line segment in the first direction is equal to the width of the fourth sub-line segment in the first direction.

13. The display panel according to claim 12, characterized in that: The lengths of the third sub-line segments in at least some of the first signal lines in the second direction are different; And / or, the third sub-line segment includes a fifth side, an extension direction of the fifth side has a first angle with the second direction, and the first angle corresponding to the third sub-line segments in at least some of the first signal lines is different.

14. The display panel according to claim 1, characterized in that: The pixel circuit includes a first pixel circuit, the first pixel circuit is adjacent to the spacer, and the first pixel circuit includes at least one first wiring; In at least part of the first signal line, in a direction perpendicular to the plane where the display panel is located, the first line segment overlaps with the first routing line, the orthographic projection of the second line segment on the plane where the display panel is located is adjacent to the orthographic projection of the first routing line on the plane where the display panel is located, and the distance between the orthographic projection of the second line segment on the plane where the display panel is located and the orthographic projection of the first routing line on the plane where the display panel is located is greater than or equal to 1 μm.

15. The display panel according to claim 14, characterized in that: The first pixel circuit includes a first transistor, the first wiring includes a first type of first wiring, and the first type of first wiring is an active layer of the first transistor; In at least part of the first signal lines, part of the first line segment is reused as the gate of the first transistor, the orthographic projection of the second line segment on the plane where the display panel is located is adjacent to the orthographic projection of the first type of first routing line on the plane where the display panel is located, and the distance between the orthographic projection of the second line segment on the plane where the display panel is located and the orthographic projection of the first type of first routing line on the plane where the display panel is located is greater than or equal to 1 μm.

16. The display panel according to claim 14, characterized in that: The first pixel circuit includes a second transistor, the first wiring includes a second type of first wiring, and the second type of first wiring is electrically connected to the second transistor; In at least part of the first signal lines, in a direction perpendicular to the plane where the display panel is located, the first line segment overlaps with the second-type first routing line, the orthographic projection of the second line segment on the plane where the display panel is located is adjacent to the orthographic projection of the second-type first routing line on the plane where the display panel is located, and the distance between the orthographic projection of the second line segment on the plane where the display panel is located and the orthographic projection of the second-type first routing line on the plane where the display panel is located is greater than or equal to 1 μm.

17. The display panel according to claim 14, characterized in that: The second line segments in at least some of the first signal lines have different widths in the first direction, and the distances between the orthographic projections of the second line segments on the plane where the display panel is located and the orthographic projections of the first lines on the plane where the display panel is located are also different.

18. The display panel according to claim 17, characterized in that: There is a positive correlation between the width of the second line segment in the first direction and the distance between the orthographic projection of the second line segment on the plane where the display panel is located and the orthographic projection of the first line on the plane where the display panel is located.

19. The display panel according to claim 1, characterized in that: The display panel further includes a second signal line, which extends along the first direction and is located in the spacing area; The second line segment in at least part of the first signal line includes a first hollowing out, and the first hollowing out overlaps with the second signal line in a direction perpendicular to the plane where the display panel is located; and / or, at least part of the second signal line includes a second hollowing out, and the second hollowing out overlaps with the second line segment in a direction perpendicular to the plane where the display panel is located.

20. The display panel according to claim 19, characterized in that: The second signal lines include a first type of second signal line for transmitting a variable voltage signal and a second type of second signal line for transmitting a constant voltage signal; Wherein, in a direction perpendicular to the plane where the display panel is located, the first hollowing overlaps with the first-type second signal line, and the second-type second signal line includes the second hollowing.

21. The display panel according to claim 19, characterized in that: The second signal lines include a first type of second signal line for transmitting a variable voltage signal and a second type of second signal line for transmitting a constant voltage signal; Among them, the first hollow includes a first sub-hollow and a second sub-hollow, the area of ​​the first sub-hollow is larger than the area of ​​the second sub-hollow, and in a direction perpendicular to the plane where the display panel is located, the first sub-hollow overlaps with the first type of second signal line, and the second sub-hollow overlaps with the second type of second signal line.

22. The display panel according to claim 20 or 21, characterized in that: The first type of second signal line includes a data line for providing a data voltage to the pixel circuit; The second signal line of the second type includes a power line for providing a power voltage to the pixel circuit, and / or includes a reset line for providing a reset voltage to the pixel circuit.

23. The display panel according to claim 1, characterized in that: The display panel further includes a second signal line, which extends along the first direction and is located in the spacing area; In at least part of the first signal line, the second line segment includes a fifth sub-line segment and a sixth sub-line segment, in a direction perpendicular to the plane where the display panel is located, the fifth sub-line segment does not overlap with the second signal line, the sixth sub-line segment overlaps with the second signal line, and the width of the fifth sub-line segment in the first direction is greater than the width of the sixth sub-line segment in the first direction.

24. The display panel according to claim 1, characterized in that: The first signal lines include first signal lines of a fifth type, in which at least some of the second line segments have different widths in the first direction.

25. The display panel according to claim 24, characterized in that: A first connecting line is connected between the fifth type first signal line and the first shift register, and a first via hole is provided between the fifth type first signal line and the first connecting line; In the fifth category first signal line, the second line segment includes a first category second line segment and a second category second line segment, the distance between the second category second line segment and the first via is greater than the distance between the first category second line segment and the first via, and the width of the second category second line segment in the first direction is greater than the width of the first category second line segment in the first direction.

26. The display panel according to claim 24, characterized in that: In the fifth type of first signal lines, at least three consecutively arranged second line segments have gradually changing widths in the first direction.

27. The display panel according to claim 24, characterized in that: The display panel has a first central axis extending along a first direction, and the display panel includes two first display areas located on opposite sides of the first central axis; The display panel comprises a first shift register, the first shift register comprises a plurality of first shift units connected in cascade, and the first shift units are located between adjacent circuit rows; The fifth type of first signal line is electrically connected to two first shift registers, and the two first shift registers are respectively located in two first display areas; Wherein, the fifth type of first signal line includes two first parts, two of the two first parts are respectively located in two first display areas, the first part includes a first sub-part and a second sub-part, and the second sub-part is connected between the first sub-part and another first part; The second line segments in the first subsection include a third type of second line segments and a fourth type of second line segments, the distance between the third type of second line segments and the first central axis is greater than the distance between the fourth type of second line segments and the first central axis, and the width of the third type of second line segments in the first direction is greater than the width of the fourth type of second line segments in the first direction; The second line segments in the second sub-section include a fifth type of second line segment and a sixth type of second line segment, the distance between the fifth type of second line segment and the first central axis is greater than the distance between the sixth type of second line segment and the first central axis, and the width of the fifth type of second line segment in the first direction is less than the width of the sixth type of second line segment in the first direction.

28. The display panel according to claim 1, characterized in that: The display panel further comprises a first shift register, the first shift register comprises a plurality of first shift units connected in cascade, and the first shift units are located between adjacent circuit rows; The first signal line comprises a fifth type of first signal line, and the fifth type of first signal line is electrically connected to the first shift unit; Among them, the fifth category first signal line includes a first sub-signal line and a second sub-signal line, the distance between the first sub-signal line and the first shift unit connected to it in the first direction is greater than the distance between the second sub-signal line and the first shift unit connected to it in the first direction, and the width of the second line segment in the first sub-signal line in the first direction is greater than the width of the second line segment in the second sub-signal line in the first direction.

29. The display panel according to claim 28, characterized in that: A first connection line is connected between the fifth-category first signal line and the first shift unit, wherein a line width of the first connection line connected to the first sub-signal line is greater than a line width of the first connection line connected to the second sub-signal line.

30. The display panel according to claim 1, characterized in that: The pixel circuit includes a plurality of transistors, and at least part of the first signal lines are used to provide signals to gates of the transistors.

31. The display panel according to claim 1, characterized in that: The pixel circuit includes a pulse width modulation module and a pulse amplitude modulation module; The pulse width modulation module includes a first driving transistor, a first gate reset transistor, a first threshold compensation transistor, a first light emission control transistor and a second light emission control transistor; wherein the first gate reset transistor is electrically connected between a first reset line and a gate of the first driving transistor, the first threshold compensation transistor is electrically connected between a second electrode of the first driving transistor and the gate of the first driving transistor, the first light emission control transistor is electrically connected between a first power line and a first electrode of the first driving transistor, and the second light emission control transistor is electrically connected between the second electrode of the first driving transistor and the pulse amplitude modulation module; The pulse amplitude modulation module includes a second driving transistor, a second gate reset transistor, a second threshold compensation transistor, a third light emission control transistor and a fourth light emission control transistor; wherein the second gate reset transistor is electrically connected between a second reset line and a gate of the second driving transistor, the second threshold compensation transistor is electrically connected between a second electrode of the second driving transistor and a gate of the first driving transistor, the third light emission control transistor is electrically connected between a second power line and a first electrode of the second driving transistor, and the second light emission control transistor is electrically connected between a second electrode of the second driving transistor and a light emitting element; Wherein, the first signal line includes: a first reset scan line providing a signal to a gate of the first gate reset transistor; and / or, a first compensation scan line providing a signal to a gate of the first threshold compensation transistor; and / or, a first light emission control scan line providing a signal to a gate of the first light emission control transistor and a gate of the second light emission control transistor; and / or, a second reset scan line providing a signal to the gate of the second gate reset transistor; and / or, a second compensation scan line providing a signal to a gate of the second threshold compensation transistor; and / or, a second light emission control scan line that provides a signal to a gate of the third light emission control transistor and a gate of the fourth light emission control transistor.

32. The display panel according to claim 1, characterized in that: The pixel circuit includes a pulse width modulation module, and the pulse width modulation module includes a first driving transistor and a first capacitor; The first signal line includes a frequency sweep line, and the frequency sweep line is electrically connected to the gate of the first driving transistor through the first capacitor.

33. A display device, characterized in that: Comprising a display panel as described in any one of claims 1 to 32.

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