Display panel

Abstract

The invention relates to a display panel. The first conductive layer is arranged on one side of the substrate, the first conductive layer comprises a plurality of first power supply signal lines arranged along a first direction, the first power supply signal lines extend along a second direction, and the first direction and the second direction are crossed; the light-emitting layer is arranged on the side, away from the substrate, of the first conductive layer, the light-emitting layer comprises a plurality of light-emitting parts arranged in the first direction and the second direction, and the light-emitting parts arranged in the second direction are located on the sides, away from the substrate, of the corresponding first power signal lines; the first power signal line comprises a first line segment, the light-emitting part comprises a bottom surface close to one side of the first power signal line, and the orthographic projection of the first line segment on the substrate is located in the orthographic projection of the bottom surface of the light-emitting part on the substrate. The ratio of the orthographic projection area of the first line segment on the substrate to the orthographic projection area of the bottom surface of the light-emitting part on the substrate is greater than or equal to 0.5; the film thickness uniformity of the light-emitting part can be improved, and the light-emitting effect and the light-emitting efficiency of the display panel can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a display panel. Background Art

[0002] As a new type of self-emitting display panel, an Organic Light-Emitting Diode (OLED) display panel is ultra-clear, thin, flexible, and highly designable. At the same time, it uses organic semiconductors for light emission, and has a wide range of material choices, making it easy to achieve full-color display within the visible light range. Especially for the top-emitting OLED display panel, due to its advantages such as a large aperture ratio, it is increasingly widely used in various fields.

[0003] Specifically, the OLED display panel includes a planarization layer disposed on a thin-film transistor device layer, an anode layer disposed on the planarization layer, a pixel definition layer disposed on the anode layer, and a light-emitting layer disposed on the pixel definition layer; wherein, the anode layer includes a plurality of anodes, the pixel definition layer includes a plurality of pixel openings corresponding one-to-one to the plurality of anodes, and the light-emitting layer includes light-emitting portions disposed on the anodes corresponding to each pixel opening.

[0004] However, due to the distribution of devices and traces in the thin-film transistor layer, the film surface within the pixel opening is uneven, which in turn affects the light-emitting effect and light-emitting efficiency of the light-emitting portions formed within the pixel opening. Summary of the Invention

[0005] An embodiment of the present application provides a display panel. By increasing the coverage range of the first segment in the first power signal line, the film thickness uniformity of the light-emitting portion is improved, and the light-emitting effect and light-emitting efficiency of the display panel are enhanced.

[0006] To achieve the above object, according to a first aspect of the present application, there is provided a display panel, which includes:

[0007] A substrate

[0008] A first conductive layer disposed on one side of the substrate. The first conductive layer includes a plurality of first power signal lines arranged along a first direction, and the first power signal lines extend along a second direction, where the first direction and the second direction intersect;

[0009] A light-emitting layer disposed on a side of the first conductive layer away from the substrate. The light-emitting layer includes a plurality of light-emitting portions arranged along the first direction and the second direction, and a plurality of the light-emitting portions arranged along the second direction are located on a side of the corresponding first power signal line away from the substrate;

[0010] Among them, the first power supply signal line includes a first line segment, the light-emitting part includes a bottom surface on one side close to the first power supply signal line, the orthographic projection of the first line segment on the substrate is located within the orthographic projection of the bottom surface of the light-emitting part on the substrate, and the ratio of the orthographic projection area of the first line segment on the substrate to the orthographic projection area of the bottom surface of the light-emitting part on the substrate is greater than or equal to 0.5.

[0011] In an embodiment of the present application, the display panel further includes a plurality of pixel driving circuits corresponding to the plurality of light-emitting parts, and the pixel driving circuit includes a switching transistor, a driving transistor, and a first capacitor connected between the switching transistor and the driving transistor;

[0012] The switching transistor partially overlaps with the first line segment along the thickness direction of the display panel, the driving transistor partially overlaps with the first line segment along the thickness direction of the display panel, and the first capacitor partially overlaps with the first line segment along the thickness direction of the display panel.

[0013] In an embodiment of the present application, the switching transistor includes a switching active part and a switching gate, and the driving transistor includes a driving active part and a driving gate;

[0014] The switching active part partially overlaps with the first line segment along the thickness direction of the display panel, the switching gate partially overlaps with the first line segment along the thickness direction of the display panel, the driving active part partially overlaps with the first line segment along the thickness direction of the display panel, and the driving gate partially overlaps with the first line segment along the thickness direction of the display panel.

[0015] In an embodiment of the present application, the display panel further includes:

[0016] A first gate layer, disposed between the substrate and the first conductive layer, and the first gate layer includes a first electrode plate of the first capacitor;

[0017] A second gate layer, disposed between the first gate layer and the first conductive layer, and the second gate layer includes a second electrode plate of the first capacitor, and the second electrode plate is disposed opposite to the first electrode plate;

[0018] A second conductive layer, disposed between the second gate layer and the first conductive layer, and the second conductive layer includes a second power supply signal line extending along the first direction and a node connection line connecting the switching active part and the second electrode plate;

[0019] Among them, the second power signal line is connected to the first power signal line through a first via hole, the node connection line is connected to the second electrode plate through a second via hole, the first via hole and the second via hole are located on opposite sides of the first line segment, and the first line segment is located between the first via hole and the second via hole and has a width in the first direction greater than or equal to the width of other positions of the first line segment in the first direction.

[0020] In an embodiment of the present application, the switching transistor and the first capacitor are connected to a first node, and the pixel driving circuit further includes a second capacitor connected to the first node, and the second capacitor is located between the first capacitor and the switching transistor;

[0021] The second capacitor is electrically connected to the first power signal line, and the second capacitor partially overlaps with the first line segment in the thickness direction of the display panel.

[0022] In an embodiment of the present application, the first line segment includes overlapping sub-parts arranged continuously in the second direction, the overlapping sub-parts partially overlap with the first capacitor in the thickness direction of the display panel, the overlapping sub-parts partially overlap with the second capacitor in the thickness direction of the display panel, and the overlapping sub-parts have the same width in the first direction at each place.

[0023] In an embodiment of the present application, the first line segment and the first capacitor have a first overlapping part in the thickness direction of the display panel, and the ratio of the orthographic projection area of the first overlapping part on the substrate to the orthographic projection area of the first capacitor on the substrate is greater than or equal to 0.5 and less than or equal to 0.8;

[0024] The first line segment and the second capacitor have a second overlapping part in the thickness direction of the display panel, and the ratio of the orthographic projection area of the second overlapping part on the substrate to the orthographic projection area of the second capacitor on the substrate is greater than or equal to 0.4 and less than or equal to 0.5.

[0025] In an embodiment of the present application, the first capacitor and the driving transistor are connected to a second node, and the pixel driving circuit further includes a first reset transistor connected to the second node, the first reset transistor is located on the side of the driving transistor away from the switching transistor, and the first reset transistor partially overlaps with the first line segment in the thickness direction of the display panel.

[0026] In an embodiment of the present application, the first reset transistor includes a first reset active portion and a first reset gate. The first reset active portion overlaps with the first line segment in the thickness direction of the display panel, and the first reset gate overlaps with the first line segment in the thickness direction of the display panel.

[0027] In an embodiment of the present application, the pixel driving circuit further includes a compensation transistor. The compensation transistor is connected between the second node and the third node, the driving transistor is connected to the third node, the compensation transistor is located on a side of the driving transistor away from the switching transistor, the compensation transistor is disposed adjacent to the first reset transistor along the first direction, and the compensation transistor overlaps with the first line segment in the thickness direction of the display panel.

[0028] In an embodiment of the present application, the pixel driving circuit further includes a first light-emitting control transistor connected between the third node and the fourth node. The display panel further includes a light-emitting device connected to the fourth node. The light-emitting device includes the light-emitting portion. The first light-emitting control transistor is located on a side of the compensation transistor away from the driving transistor, and the first light-emitting control transistor overlaps with the first line segment in the thickness direction of the display panel.

[0029] In an embodiment of the present application, the first light-emitting control transistor includes a first light-emitting control active portion and a first light-emitting control gate. The first light-emitting control active portion does not overlap with the first line segment in the thickness direction of the display panel, and the first light-emitting control gate overlaps with the first line segment in the thickness direction of the display panel.

[0030] In an embodiment of the present application, the pixel driving circuit further includes a second light-emitting control transistor connected to the fifth node. The driving transistor is connected to the fifth node. The second light-emitting control transistor is located on a side of the first reset transistor away from the driving transistor, and the second light-emitting control transistor overlaps with the first line segment in the thickness direction of the display panel.

[0031] In an embodiment of the present application, the second light-emitting control transistor includes a second light-emitting control active portion and a second light-emitting control gate. The second light-emitting control active portion overlaps with the first line segment in the thickness direction of the display panel, and the second light-emitting control gate overlaps with the first line segment in the thickness direction of the display panel.

[0032] In an embodiment of the present application, the pixel driving circuit further includes a second reset transistor connected to the fourth node and a third reset transistor connected to the fifth node. The second reset transistor and the first line segment do not overlap partially in the thickness direction of the display panel, and the third reset transistor and the first line segment do not overlap partially in the thickness direction of the display panel.

[0033] In an embodiment of the present application, the pixel driving circuit further includes a fourth reset transistor connected to the switching transistor and the first capacitor. The fourth reset transistor is disposed adjacent to the switching transistor along the first direction. The fourth reset transistor includes a fourth reset active portion and a fourth reset gate. The fourth reset active portion and the first line segment overlap partially in the thickness direction of the display panel, and the fourth reset gate and the first line segment overlap partially in the thickness direction of the display panel.

[0034] In an embodiment of the present application, the pixel driving circuit further includes a compensation transistor. The compensation transistor includes a compensation active portion and a compensation gate disposed near the edge of the bottom surface of the light emitting portion. The compensation active portion and the first line segment overlap partially in the thickness direction of the display panel, and the compensation gate and the first line segment overlap partially in the thickness direction of the display panel.

[0035] In an embodiment of the present application, the first conductive layer further includes an anode connection portion;

[0036] The display panel further includes:

[0037] An anode layer disposed on a side of the first conductive layer away from the substrate. The anode layer includes a plurality of anodes corresponding to the plurality of pixel driving circuits. The anodes are connected to the pixel driving circuits through the anode connection portions;

[0038] Wherein, the anode connection portion and the first line segment do not overlap in the first direction, and the anode connection portion and the first line segment overlap partially in the second direction.

[0039] In an embodiment of the present application, the first line segment includes a first side and a second side disposed opposite to each other along the first direction. In the first line segment of at least a part of the first power signal line, both the first side and the second side are parallel to the second direction;

[0040] The ratio of the width of the first line segment in the first direction to the width of the bottom surface of the light emitting portion in the first direction is greater than or equal to 0.5 and less than or equal to 1.

[0041] In an embodiment of the present application, the first power supply signal line further includes a second line segment connected to the first line segment along the second direction, and the second line segment does not overlap with the bottom surface of the light-emitting portion in the thickness direction of the display panel, and the width of the second line segment along the first direction is smaller than the width of the first line segment along the first direction.

[0042] The present application provides a display panel. By increasing the ratio of the area of the first line segment in the first power supply signal line to the area of the bottom surface of the light-emitting portion, the coverage range of the first line segment in the area corresponding to the bottom surface of the light-emitting portion can be increased, the film layer flatness at the position where the light-emitting portion is located can be improved, and thus the film thickness uniformity of the light-emitting portion can be effectively improved, and the light-emitting effect and light-emitting efficiency of the display panel can be improved.

[0043] Other features and advantages of the present application will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative efforts.

[0045] In order to more fully understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, where the same reference numerals represent the same parts in the following description.

[0046] Figure 1 FIG. is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present application;

[0047] Figure 2 FIG. is a schematic structural diagram of a pixel driving circuit of a display panel provided by an embodiment of the present application;

[0048] Figure 3 FIG. is a schematic plan view of a display panel provided by an embodiment of the present application;

[0049] Figure 4 FIG. is a schematic diagram of a film stack of a sub-pixel in a display panel provided by an embodiment of the present application;

[0050] Figure 5 FIG. provided by an embodiment of the present application Figure 4 is a structural diagram of a semiconductor layer therein;

[0051] Figure 6 FIG. provided by an embodiment of the present application Figure 4 is a structural diagram of a first gate layer therein;

[0052] Figure 7 Stacked diagram of the semiconductor layer and the first gate layer provided by an embodiment of the present application Figure 4 ;

[0053] Figure 8 Structural diagram of the second gate layer provided by an embodiment of the present application Figure 4 ;

[0054] Figure 9 Stacked diagram of the semiconductor, the first gate layer, and the second gate layer provided by an embodiment of the present application Figure 4 ;

[0055] Figure 10 Structural diagram of the first conductive layer provided by an embodiment of the present application Figure 4 ;

[0056] Figure 11 Stacked diagram of the semiconductor, the first gate layer, the second gate layer, and the first conductive layer provided by an embodiment of the present application Figure 4 ;

[0057] Figure 12 Structural diagram of the second conductive layer provided by an embodiment of the present application Figure 4 ;

[0058] Figure 13 Stacked diagram of the semiconductor, the first gate layer, the second gate layer, the first conductive layer, and the second conductive layer provided by an embodiment of the present application Figure 4 ;

[0059] Figure 14 Structural diagram of the anode layer provided by an embodiment of the present application Figure 4 ;

[0060] Figure 15 Planar structure schematic diagram of the first pixel definition layer and the second pixel definition layer provided by an embodiment of the present application Figure 2 ;

[0061] Explanation of reference numerals:

[0062] AA, display area; NA, non-display area; PX, sub-pixel; PD, pixel driving circuit; EL, light-emitting device

[0063] 10. Substrate; 11. Gate driving circuit; 12. Bonding terminal; 13. Light-emitting layer; 100. Light-emitting part; 1001. Bottom surface; 20. Semiconductor layer; 21. First reset signal auxiliary line; 30. First gate layer; 40. Second gate layer; 41. First jumper wire; 42. Plate connection wire; 50. Second conductive layer; 51. Second jumper wire; 52. Third jumper wire; 53. Node connection wire; 54. Fourth jumper wire; 55. Fifth jumper wire; 56. Sixth jumper wire; 57. Seventh jumper wire; 58. Eighth jumper wire; 59. Ninth jumper wire; 510. Tenth jumper wire; 511. Eleventh jumper wire; 512. Twelfth jumper wire; 60. First conductive layer; 61. First power supply signal line; 611. First line segment; 6111. Overlapping sub-part; 612. Second line segment; 62. Second reset signal auxiliary line; 63. Functional trace; 64. Anode connection part; 70. Anode layer; 71. Anode; 81. First gate insulating layer; 82. Second gate insulating layer; 83. Interlayer dielectric layer; 84. First planarization layer; 85. Second planarization layer; 86. Pixel definition layer; 861. First pixel definition layer; 862. Second pixel definition layer; 860. Pixel opening;

[0064] T1. Switching transistor; T2. Driving transistor; T3. Compensation transistor; T4. First reset transistor; T5. Second reset transistor; T6. Third reset transistor; T7. Fourth reset transistor; T8. First light-emitting control transistor; T9. Second light-emitting control transistor; C1. First capacitor; C2. Second capacitor; C3. Third capacitor; C4. Fourth capacitor; C5. Fifth capacitor; C6. Sixth capacitor; SCAN1. First control signal line; SCAN2. Second control signal line; SCAN3. Third control signal line; SCAN4. Fourth control signal line; EM1. First light-emitting control signal line; EM2. Second light-emitting control signal line; DATA. Data signal line; DATA1. First data signal line; DATA2. Second data signal line; DATA3. Third data signal line; VI1. First reset signal line; VI2. Second reset signal line; VI3. Third reset signal line; VI4. Fourth reset signal line; VDD. Second power supply signal line; VSS. Third power supply signal line; N1. First node; N2. Second node; N3. Third node; N4. Fourth node; N5. Fifth node;

[0065] C11. First plate; C12. Second plate; C21. Third plate; C22. Fourth plate; C31. Fifth plate; C41. Sixth plate; C51. Seventh plate; C61. Eighth plate;

[0066] T1A, switching active part; T2A, driving active part; T3A, compensating active part; T4A, first reset active part; T5A, second reset active part; T6A, third reset active part; T7A, fourth reset active part; T8A, first light-emitting control active part; T9A, second light-emitting control active part;

[0067] T1G, switching gate; T2G, driving gate; T3G, compensating gate; T4G, first reset gate; T5G, second reset gate; T6G, third reset gate; T7G, fourth reset gate; T8G, first light-emitting control gate; T9G, second light-emitting control gate;

[0068] T1D, switching drain; T2D, driving drain; T3D, compensating drain; T4D, first reset drain; T5D, second reset drain; T6D, third reset drain; T7D, fourth reset drain; T8D, first light-emitting control drain; T9D, second light-emitting control drain;

[0069] T1S, switching source; T2S, driving source; T3S, compensating source; T4S, first reset source; T5S, second reset source; T6S, third reset source; T7S, fourth reset source; T8S, first light-emitting control source; T9S, second light-emitting control source. Detailed implementation manner

[0070] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present application.

[0071] An embodiment of the present application provides a display panel, and the display panel includes a substrate 10, a first conductive layer 60, and a light-emitting layer 13; the first conductive layer 60 is disposed on one side of the substrate 10, the first conductive layer 60 includes a plurality of first power signal lines 61 arranged along a first direction X, the first power signal lines 61 extend along a second direction Y, and the first direction X and the second direction Y intersect; the light-emitting layer 13 is disposed on the side of the first conductive layer 60 away from the substrate 10, the light-emitting layer 13 includes a plurality of light-emitting parts 100 arranged along the first direction X and the second direction Y, and a plurality of the light-emitting parts 100 arranged along the second direction Y are located on the side of a corresponding one of the first power signal lines 61 away from the substrate 10.

[0072] Among them, the first power supply signal line 61 includes a first line segment 611, the light-emitting part 100 includes a bottom surface 1001 on a side close to the first power supply signal line 61, a positive projection of the first line segment 611 on the substrate 10 is located within a positive projection of the bottom surface 1001 of the light-emitting part 100 on the substrate 10, and a ratio of a positive projection area of the first line segment 611 on the substrate 10 to a positive projection area of the bottom surface 1001 of the light-emitting part 100 on the substrate 10 is greater than or equal to 0.5.

[0073] In the implementation and application process, in the embodiment of the present application, by increasing a ratio of an area of the first line segment 611 in the first power supply signal line 61 to an area of a bottom surface of the light-emitting part, a coverage range of the first line segment 611 in a region corresponding to the bottom surface 1001 of the light-emitting part 100 can be increased, flatness of a film layer at a position where the light-emitting part 100 is located is improved, and thus film thickness uniformity of the light-emitting part 100 can be effectively improved, and a light-emitting effect and a light-emitting efficiency of the display panel are improved.

[0074] Specifically, please refer to Figure 2 and Figure 3 , the display panel may include a display area AA and a non-display area NA adjacent to the display area AA, the non-display area NA may be disposed around the display area AA, and the non-display area NA may be a border area of the display panel.

[0075] In some embodiments, the display panel further includes a plurality of sub-pixels PX disposed in the display area AA and configured to implement a display function of the display panel, and a gate driving circuit 11 disposed in the non-display area NA, wherein the gate driving circuit 11 is configured to input a control signal to the sub-pixels PX in the display area AA.

[0076] In some embodiments, a pixel driving circuit PD is disposed in each sub-pixel PX, and the gate driving circuit 11 is configured to input a gate control signal to a transistor in the pixel driving circuit PD.

[0077] In some embodiments, a bonding terminal 12 is disposed on a lower side of the display area AA, and the display panel further includes a data signal line DATA extending into the display area AA and connected to the pixel driving circuit PD; the bonding terminal 12 may be connected to an external circuit, and the bonding terminal 12 transmits a signal input by the external circuit to the data signal line DATA, so as to drive the display panel to display a picture. For example, the bonding terminal 12 may be bonded and connected to a chip or a chip-on-film, etc., for providing a power supply and a driving signal, etc., for the display panel.

[0078] In some embodiments, the gate driving circuit 11 is disposed in the non-display area NA, and the gate driving circuit 11 can be disposed on both sides of the display area AA; the gate driving circuit 11 may include a plurality of cascaded gate driving units, and the structure of the gate driving unit is not specifically limited in this application.

[0079] In some embodiments, a plurality of the pixel driving circuits PD may be arranged in an array in the display area AA, and the pixel driving circuits PD may be pixel driving circuits PD such as 7T1C, 7T2C, 8T1C, 8T2C, 8T3C, 8T4C, 9T2C, 9T6C, etc. In the following embodiments, the 9T6C pixel driving circuit PD is taken as an example for illustration.

[0080] Please refer to Figure 2 , the pixel driving circuit PD includes a switching transistor T1, a driving transistor T2, a compensating transistor T3, a first reset transistor T4, a second reset transistor T5, a third reset transistor T6, a fourth reset transistor T7, a first light-emitting control transistor T8, a second light-emitting control transistor T9, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4, and the display panel further includes a light-emitting device EL connected to the pixel driving circuit PD.

[0081] Furthermore, the display panel further includes a plurality of signal lines, and the plurality of signal lines are used to connect the pixel driving circuit PD and transmit signals to the pixel driving circuit PD; in some embodiments, the signal lines include a first control signal line SCAN1, a second control signal line SCAN2, a third control signal line SCAN3, a fourth control signal line SCAN4, a first light-emitting control signal line EM1, a second light-emitting control signal line EM2, a data signal line DATA, a first reset signal line VI1, a second reset signal line VI2, a third reset signal line VI3, a fourth reset signal line VI4, a first power supply signal line 61, a second power supply signal line VDD, and a third power supply signal line VSS.

[0082] Wherein, the drain of the switching transistor T1 is connected to the data signal line DATA to receive a data signal Data, the source of the switching transistor T1 is connected to a first node N1, and the gate of the switching transistor T1 is connected to the first control signal line SCAN1 to receive a first control signal Scan1.

[0083] The drain of the driving transistor T2 is connected to a fifth node N5, the source of the driving transistor T2 is connected to a third node N3, and the gate of the driving transistor T2 is connected to a second node N2.

[0084] The drain of the compensation transistor T3 is connected to the second node N2, the source of the compensation transistor T3 is connected to the third node N3, and the gate of the compensation transistor T3 is connected to the second control signal line SCAN2 to receive the second control signal Scan2.

[0085] The drain of the first reset transistor T4 is connected to the first reset signal line VI1 to receive the first reset signal Vi1, the source of the first reset transistor T4 is connected to the second node N2, and the gate of the first reset transistor T4 is connected to the third control signal line SCAN3 to receive the third control signal Scan3.

[0086] The drain of the second reset transistor T5 is connected to the second reset signal line VI2 to receive the second reset signal Vi2, the source of the second reset transistor T5 is connected to the fourth node N4, and the gate of the second reset transistor T5 is connected to the fourth control signal line SCAN4 to receive the fourth control signal Scan4.

[0087] The drain of the third reset transistor T6 is connected to the third reset signal line VI3 to receive the third reset signal Vi3, the source of the third reset transistor T6 is connected to the fifth node N5, and the gate of the third reset transistor T6 is connected to the fourth control signal line SCAN4 to receive the fourth control signal Scan4.

[0088] The drain of the fourth reset transistor T7 is connected to the fourth reset signal line VI4 to receive the fourth reset signal Vi4, the source of the fourth reset transistor T7 is connected to the first node N1, and the gate of the fourth reset transistor T7 is connected to the second control signal line SCAN2 to receive the second control signal Scan2.

[0089] The drain of the first light-emitting control transistor T8 is connected to the third node N3, the source of the first light-emitting control transistor T8 is connected to the fourth node N4, and the gate of the first light-emitting control transistor T8 is connected to the first light-emitting control signal line EM1 to receive the first light-emitting control signal Em1.

[0090] The drain of the second light-emitting control transistor T9 is connected to the first power supply signal line 61 to receive the first power supply signal Vdd, the source of the second light-emitting control transistor T9 is connected to the fifth node N5, and the gate of the second light-emitting control transistor T9 is connected to the second light-emitting control signal to receive the second light-emitting control signal Em2.

[0091] The display panel further includes a light-emitting device EL connected to the pixel driving circuit PD. One end of the light-emitting device EL is connected to the fourth node N4, and the other end of the light-emitting device EL is connected to the third power supply signal line VSS to receive the third power supply signal Vss.

[0092] One plate of the first capacitor C1 is connected to the first node N1, and the other plate of the first capacitor C1 is connected to the second node N2; one plate of the second capacitor C2 is connected to the first node N1, and the other plate of the second capacitor C2 is connected to the second power supply signal line VDD; the third capacitor C3 and the fourth capacitor C4 are connected in series between the active part of the switching transistor T1 and the active part of the fourth reset transistor T7; one plate of the fifth capacitor C5 is connected to the active part of the first reset transistor T4, and the other plate of the fifth capacitor C5 is connected to the second power supply signal line VDD; one plate of the sixth capacitor C6 is connected to the active part of the compensation transistor T3, and the other plate of the sixth capacitor C6 is connected to the second power supply signal line VDD.

[0093] It should be noted that in the embodiment of the present application, the first capacitor C1 can couple a signal to the second node N2, that is, to the gate of the driving transistor T2; and the first capacitor C1 and the second capacitor C2 can stabilize the potentials of the first node N1 and the second node N2, reducing the probability of signal instability and signal flicker; the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, and the sixth capacitor C6 are respectively used to prevent the switching transistor T1, the fourth reset transistor T7, the first reset transistor T4, and the compensation transistor T3 from leaking electricity, and can also reduce the probability of signal flicker.

[0094] For the switching transistors T1 in different sub-pixels PX, the data signal lines DATA connected thereto are different. Only one of them is taken as an example for illustration in the present application.

[0095] In this embodiment, the first power supply signal line 61 and the second power supply signal line VDD are used to provide a constant high level to the pixel driving circuit PD, and the first power supply signal line 61 and the second power supply signal line VDD can be connected. The third power supply signal line VSS is used to provide a constant low level to the pixel driving circuit PD.

[0096] In this embodiment, the switching transistor T1, the driving transistor T2, the compensating transistor T3, the first reset transistor T4, the second reset transistor T5, the third reset transistor T6, the fourth reset transistor T7, the first light-emitting control transistor T8, and the second light-emitting control transistor T9 are each independently selected from one of a P-type transistor and an N-type transistor; in this application, the switching transistor T1, the driving transistor T2, the compensating transistor T3, the first reset transistor T4, the second reset transistor T5, the third reset transistor T6, the fourth reset transistor T7, the first light-emitting control transistor T8, and the second light-emitting control transistor T9 are all P-type transistors as an example for description.

[0097] In this embodiment, the source electrode is only the output terminal of this application, and the drain electrode is only the input terminal of this application, and they only have a difference in naming.

[0098] Next, for the Figure 1 structure, the film layer structure of the pixel circuit of this application will be described.

[0099] The display area AA and the non-display area NA of the display panel may be provided with a substrate 10 and an array driving layer provided on the substrate 10; within the display area AA, the display panel may further include a pixel definition layer 86 provided on the array driving layer and a light-emitting portion 100 provided on the pixel definition layer 86. Next, the film layer structure within the display area AA will be mainly described.

[0100] In some embodiments, the substrate 10 supports each layer provided on the substrate 10. When the display panel is a bottom-emitting light-emitting display device or a double-sided emitting light-emitting display device, a transparent substrate may be used. When the display panel is a top-emitting light-emitting display device, a semi-transparent or opaque substrate and a transparent substrate may be used.

[0101] In this embodiment, the substrate 10 is used to support each film layer provided on the substrate 10, and the substrate 10 may be made of an insulating material such as glass, quartz, or polymer resin. The substrate 10 may be a rigid substrate or a flexible substrate that can be bent, folded, curled, etc. Examples of flexible materials for the flexible substrate include polyimide (PI), but are not limited to polyimide (PI).

[0102] In this embodiment, the substrate 10 may include a first flexible substrate, a first barrier layer, a second flexible substrate, and a second barrier layer that are stacked. The first flexible substrate and the second flexible substrate may be formed of the same material such as polyimide, and the first barrier layer and the second barrier layer may be formed of an inorganic material including at least one of SiOx and SiNx, for example.

[0103] Please refer to Figure 1 wherein the array driving layer may include a plurality of thin film transistors, and the thin film transistors may be of an etch stop type, a back channel etch type, or may be classified into a bottom gate thin film transistor, a top gate thin film transistor, etc. according to the positions of the gate and the active portion, or may be classified into an N-type thin film transistor and a P-type thin film transistor according to the performance of the thin film transistor; among them, Figure 1 the thin film transistors in Figure 2 do not represent the structure diagrams of any of the transistors in

[0104] Please refer to Figure 1 wherein the array driving layer may include a semiconductor layer 20 disposed on the substrate 10, a first gate insulating layer 81 disposed on the semiconductor layer 20, a first gate layer 30 disposed on the first gate insulating layer 81, a second gate insulating layer 82 disposed on the first gate layer 30, a second gate layer 40 disposed on the second gate insulating layer 82, an interlayer dielectric layer 83 disposed on the second gate layer 40, a second conductive layer 50 disposed on the interlayer dielectric layer 83, a first planarization layer 84 disposed on the second conductive layer 50, a first conductive layer 60 disposed on the first planarization layer 84, a second planarization layer 85 disposed on the first conductive layer 60, a light emitting device EL and a pixel defining layer 86 disposed on the second planarization layer 85.

[0105] In some embodiments, the material of the semiconductor layer 20 may be a silicon semiconductor. For example, the material of the semiconductor layer 20 in the present application may be low temperature polycrystalline silicon.

[0106] In some embodiments, the first gate insulating layer 81, the second gate insulating layer 82, and the interlayer dielectric layer 83 are respectively disposed on the corresponding metal layer or semiconductor layer 20 and are separated by different layers of the metal layer or semiconductor layer 20; and the materials of the first gate insulating layer 81, the second gate insulating layer 82, and the interlayer dielectric layer 83 may be inorganic substances combined with silicon and oxygen or organic materials having flatness.

[0107] In some embodiments, the first gate layer 30 and the second gate layer 40 are respectively disposed on the corresponding insulating layer, and the materials of the first gate layer 30 and the second gate layer 40 may be copper, molybdenum, or a molybdenum-titanium alloy, etc.

[0108] In some embodiments, the materials of the second conductive layer 50 and the first conductive layer 60 may be copper, molybdenum, a molybdenum-titanium alloy, or a three-layer metal such as titanium-aluminum-titanium, etc.

[0109] In some embodiments, the first flat layer 84 and the second flat layer 85 are laid in a whole layer to ensure the flatness of the film layer of the array driving layer. The materials of the first flat layer 84 and the second flat layer 85 can be inorganic substances composed of a combination of silicon oxynitride or organic materials with flatness.

[0110] It should be noted that the pixel defining layer 86 is disposed on the flat layer and is provided with a plurality of pixel openings 860. The light-emitting device EL may include an anode 71, a light-emitting part 100, and a cathode which are stacked. The anode 71 is located within the pixel opening 860. The light-emitting part 100 is disposed within the pixel opening 860 and on the anode 71. The cathode is located on the light-emitting part 100.

[0111] It can be understood that each thin-film transistor and signal line in the pixel driving circuit PD can be located in the array driving layer. For example, the active part of each thin-film transistor can be located in the semiconductor layer 20, and other electrodes of each thin-film transistor or connected signal lines can be located in the first gate layer 30, the second gate layer 40, the second conductive layer 50, or the first conductive layer 60.

[0112] In the embodiments of the present application, the first power supply signal line 61 is used to transmit a constant voltage high level, and has a large thickness and width. The first power supply signal line 61 is located below the light-emitting part 100. Therefore, the first power supply signal line 61 has a greater impact on the flatness of the film layer at the position where the light-emitting part 100 is located. Thus, in the embodiments of the present application, the first power supply signal line 61 includes a first line segment 611. The light-emitting part 100 includes a bottom surface 1001 on one side close to the first power supply signal line 61. The orthographic projection of the first line segment 611 on the substrate 10 is located within the orthographic projection of the bottom surface 1001 of the light-emitting part 100 on the substrate 10. The ratio of the orthographic projection area of the first line segment 611 on the substrate 10 to the orthographic projection area of the bottom surface 1001 of the light-emitting part 100 on the substrate 10 is greater than or equal to 0.5. For example, the area ratio of the first line segment 611 can be increased by increasing the line width of the first line segment 611. Specifically, the ratio of the width of the first line segment 611 in the first direction X to the width of the bottom surface 1001 of the light-emitting part 100 in the first direction X is greater than or equal to 0.5 and less than or equal to 1. Thus, in the embodiments of the present application, by increasing the area, width, and coverage range of the first line segment 611, the flatness of the film layer at the position where the light-emitting part 100 is located can be improved, the film thickness uniformity and yield of the light-emitting part 100 can be improved, and further the light-emitting effect and light-emitting efficiency of the display panel can be improved.

[0113] It should be noted that the bottom surface 1001 of the light-emitting portion 100 is the surface of the light-emitting portion 100 close to the substrate 10.

[0114] Continuing from the above, in the embodiment of the present application, by increasing the coverage of the first line segment 611 in the first power signal line 61, it can overlap with multiple thin film transistor portions in the pixel driving circuit PD, so as to further improve the flatness of the film layer at the position corresponding to the first line segment 611, and improve the thickness uniformity and light-emitting efficiency of the light-emitting portion 100.

[0115] Please refer to Figure 4 , the display panel may include a plurality of pixel driving circuits PD arranged along the first direction X and the second direction Y, and the first direction and the second direction intersect; in some embodiments, the first direction X and the second direction Y are perpendicular to each other.

[0116] Among them, the display panel includes a plurality of repeating units, and Figure 4 as shown is one of the repeating units. Each repeating unit includes three pixel driving circuits PD arranged along the first direction X and three data signal lines DATA connected to the three pixel driving circuits PD in the repeating unit.

[0117] In the following embodiments, taking the structure of each film layer in the pixel driving circuit PD in one repeating unit as an example, the technical solution of the present application will be described.

[0118] Please refer to Figure 5 , the semiconductor layer 20 includes the switching active portion T1A of the switching transistor T1, the driving active portion T2A of the driving transistor T2, the compensation active portion T3A of the compensation transistor T3, the first reset active portion T4A of the first reset transistor T4, the second reset active portion T5A of the second reset transistor T5, the third reset active portion T6A of the third reset transistor T6, the fourth reset active portion T7A of the fourth reset transistor T7, the first light-emitting control active portion T8A of the first light-emitting control transistor T8, the second light-emitting control active portion T9A of the second light-emitting control transistor T9, and the first reset signal auxiliary line 21.

[0119] Among them, the switching active portion T1A is connected to the fourth reset active portion T7A and is spaced apart from other active portions; the first reset signal auxiliary line 21 extends along the first direction X and connects the fourth reset active portions T7A in a plurality of pixel driving circuits PD arranged along the first direction X together.

[0120] Among them, the switching active part T1A is in an n shape, and one end of the switching active part T1A is used to connect to the data signal line DATA, and the other end of the switching active part T1A is connected to the fourth reset active part T7A; the fourth reset active part T7A is in an n shape, one end of the fourth reset active part T7A is connected to the switching active part T1A, and the other end of the fourth reset active part T7A is connected to the first reset signal auxiliary line 21; the switching active part T1A and the fourth reset active part T7A are connected at the first node N1.

[0121] The driving active part T2A, the compensating active part T3A, the first reset active part T4A, the second reset active part T5A, the third reset active part T6A, the first light-emitting control active part T8A, and the second light-emitting control active part T9A are connected, and the third reset active parts T6A in a plurality of the pixel driving circuits PD arranged along the first direction X are connected together.

[0122] Among them, the driving active part T2A is in an n shape, one end of the driving active part T2A is connected to the third node N3, and the other end of the driving active part T2A is connected to the fifth node N5; one end of the compensating active part T3A is connected to the second node N2, and the other end of the compensating active part T3A is connected to the third node N3; one end of the first reset active part T4A is connected to the second node N2, and the other end of the first reset active part T4A is for signal input; one end of the first light-emitting control active part T8A is connected to the third node N3, and the other end of the first light-emitting control active part T8A is connected to the fourth node N4; one end of the second reset active part T5A is connected to the fourth node N4, and the other end of the second reset active part T5A is for signal input; one end of the second light-emitting control active part T9A is connected to the fifth node N5, and the other end of the second light-emitting control active part T9A is for signal input; one end of the third reset active part T6A is connected to the fifth node N5, and the other end of the third reset active part T6A is for signal input.

[0123] Further, the compensating active part T3A, the first reset active part T4A, the second reset active part T5A, the third reset active part T6A, the first light-emitting control active part T8A, and the second light-emitting control active part T9A are all located on a side of the driving active part T2A away from the switching active part T1A; still further, the first light-emitting control active part T8A is located on a side of the compensating active part T3A away from the driving active part T2A, and the second light-emitting control active part T9A is located on a side of the first reset active part T4A away from the driving active part T2A.

[0124] In some embodiments, the switching active part T1A and the fourth reset active part T7A are adjacent and connected along the first direction X, and the first reset active part T4A and the compensation active part T3A are adjacent and connected along the first direction X.

[0125] In some embodiments, in the same pixel driving circuit PD, the first light-emitting control active part T8A is located on a side of the driving active part T2A away from the switching active part T1A and extends along the second direction Y.

[0126] Please refer to Figure 6 and Figure 7 , the first gate layer 30 is disposed on a side of the semiconductor layer 20 away from the substrate 10, and the first gate layer 30 includes gates of each transistor in the pixel driving circuit PD.

[0127] Specifically, the first gate layer 30 includes a switching gate T1G of the switching transistor T1, a driving gate T2G of the driving transistor T2, a compensation gate T3G of the compensation transistor T3, a first reset gate T4G of the first reset transistor T4, a second reset gate T5G of the second reset transistor T5, a third reset gate T6G of the third reset transistor T6, a fourth reset gate T7G of the fourth reset transistor T7, a first light-emitting control gate T8G of the first light-emitting control transistor T8, a second light-emitting control gate T9G of the second light-emitting control transistor T9, a first electrode plate C11 of the first capacitor C1, and a third electrode plate C21 of the second capacitor C2.

[0128] Among them, the first electrode plate C11 of the first capacitor C1 is multiplexed as the driving gate T2G.

[0129] Please combine Figure 5 , Figure 6 and Figure 7 , there are two overlapping positions between the switching gate T1G and the switching active part T1A, so that the switching transistor T1 can form a double-gate structure; there are two overlapping positions between the fourth reset gate T7G and the fourth reset active part T7A, so that the fourth reset transistor T7 can form a double-gate structure; there are two overlapping positions between the compensation gate T3G and the compensation active part T3A, which can make the compensation transistor T3 form a double-gate structure; there are two overlapping positions between the first reset transistor T4 and the first reset active part T4A, so that the first reset transistor T4 can form a double-gate structure; it can be understood that the thin-film transistors with the above double-gate structure can effectively reduce the leakage current and improve the electrical properties of the thin-film transistors.

[0130] In addition, the driving gate T2G is disposed on a side of the driving active portion T2A away from the substrate 10, and the driving gate T2G overlaps with the driving active portion T2A. The second reset gate T5G overlaps with the second reset active portion T5A, the third reset gate T6G overlaps with the third reset active portion T6A, the first light-emitting control gate T8G overlaps with the first light-emitting control active portion T8A, and the second light-emitting control gate T9G overlaps with the second light-emitting control active portion T9A.

[0131] It should be noted that the fourth control signal line SCAN4 extends along the first direction X and simultaneously overlaps with the second reset active portion T5A and the third reset active portion T6A to be multiplexed as the second reset gate T5G and the third reset gate T6G.

[0132] In some embodiments, the widths of the portions where the second reset active portion T5A overlaps with the second reset gate T5G, the third reset active portion T6A overlaps with the third reset gate T6A, the first light-emitting control active portion T8A overlaps with the first light-emitting control gate T8G, and the second light-emitting control active portion T9A overlaps with the second light-emitting control gate T9G are all increased, and are all greater than the widths of the active portions of other thin film transistors in the pixel driving circuit PD. For example, the portions where the switching active portion T1A overlaps with the switching gate T1G, the driving active portion T2A overlaps with the driving gate T2G, the compensating active portion T3A overlaps with the compensating gate T3G, the first reset active portion T4A overlaps with the first reset gate T4G, and the fourth reset active portion T7A overlaps with the fourth reset gate T7G.

[0133] Furthermore, the relatively other end of the switching active portion T1A away from the first node N1 can be multiplexed as the switching drain T1D, and the end of the switching active portion T1A close to the first node N1 can be multiplexed as the switching source T1S; the relatively other end of the fourth reset active portion T7A away from the first node N1 can be multiplexed as the fourth reset drain T7D, and the end of the fourth reset active portion T7A close to the first node N1 can be multiplexed as the fourth reset source T7S.

[0134] One end of the driving active part T2A close to the fifth node N5 can be multiplexed as the driving drain T2D, and one end of the driving active part T2A close to the third node N3 can be multiplexed as the driving source T2S; one end of the compensation active part T3A close to the second node N2 can be multiplexed as the compensation drain T3D, and one end of the compensation active part T3A close to the third node N3 can be multiplexed as the compensation source T3S; one end of the first reset active part T4A close to the second node N2 can be multiplexed as the first reset source T4S, and the other end of the first reset active part T4A away from the second node N2 can be multiplexed as the first reset drain T4D; one end of the first light-emitting control active part T8A close to the third node N3 can be multiplexed as the ground first light-emitting control drain T8D, and one end of the first light-emitting control active part T8A close to the fourth node N4 can be multiplexed as the first light-emitting control source T8S; one end of the second reset active part T5A close to the fourth node N4 can be multiplexed as the second reset drain T5D, and the other end of the second reset active part T5A away from the fourth node N4 can be multiplexed as the second reset source T5S; one end of the second light-emitting control active part T9A close to the fifth node N5 can be multiplexed as the second light-emitting control source T9S, and the other end of the second light-emitting control active part T9A away from the fifth node N5 can be multiplexed as the second light-emitting control drain T9D; one end of the third reset active part T6A close to the fifth node N5 can be multiplexed as the third reset source T6S, and the other end of the third reset active part T6A away from the fifth node N5 can be multiplexed as the third reset drain T6D.

[0135] Please refer to Figure 8 and Figure 9 , the second gate layer 40 is disposed on a side of the first gate layer 30 away from the semiconductor layer 20, and the second gate layer 40 includes a plurality of signal lines and capacitor plates.

[0136] Specifically, the second gate layer 40 includes a second plate C12 of the first capacitor C1, a fourth plate C22 of the second capacitor C2, a fifth plate C31, a sixth plate C41, a seventh plate C51, and an eighth plate C61, a first reset signal line VI1, a third reset signal line VI3, a first light-emitting control signal line EM1, a second light-emitting control signal line EM2, and a first jumper wire 41; and the fifth plate C31 and the sixth plate C41 are both connected to the third reset signal line VI3, and the seventh plate C51 and the eighth plate C61 are both connected to the fourth plate C22.

[0137] Among them, the first electrode plate C11 and the second electrode plate C12 are oppositely arranged to form the first capacitor C1, the fourth electrode plate C22 and the third electrode plate C21 are oppositely arranged to form the second capacitor C2, the fifth electrode plate C31 and the switch active part T1A are oppositely arranged to form the third capacitor C3, the sixth electrode plate C41 and the fourth reset active part T7A are oppositely arranged to form the fourth capacitor C4, the seventh electrode plate C51 and the first reset active part T4A are oppositely arranged to form the fifth capacitor C5, and the eighth electrode plate C61 and the compensation active part T3A are oppositely arranged to form the sixth capacitor C6.

[0138] The first light emission control signal line EM1 is used for electrically connecting to the first light emission control gate T8G to transmit signals, the second light emission control signal line EM2 is used for electrically connecting to the second light emission control gate T9G to transmit signals, the first reset signal line VI1 is used for electrically connecting to the first reset drain T4D, and the third reset signal line VI3 is used for electrically connecting to the third reset drain T6D; the specific connection relationship can be seen in the subsequent embodiments.

[0139] Please refer to Figure 10 and Figure 11 , the second conductive layer 50 is disposed on a side of the second gate layer 40 away from the first gate layer 30, and the second conductive layer 50 includes the first control signal line SCAN1, the second control signal line SCAN2, the third control signal line SCAN3, the second reset signal line VI2, the fourth reset signal line VI4, the second power supply signal line VDD, the second jumper wire 51, the third jumper wire 52, the node connection wire 53, the fourth jumper wire 54, the fifth jumper wire 55, the sixth jumper wire 56, the seventh jumper wire 57, the eighth jumper wire 58, the ninth jumper wire 59, the tenth jumper wire 510, the eleventh jumper wire 511, and the twelfth jumper wire 512.

[0140] Among them, please combine Figure 6 , Figure 10 and Figure 11 , the second power supply signal line VDD extends along the first direction X and is connected to the fourth electrode plate C22.

[0141] The switch gate T1G is connected to the first control signal line SCAN1, and the switch active part T1A is connected to the second jumper wire 51.

[0142] The fourth reset gate T7G is connected to the second control signal line SCAN2, and the fourth reset active part T7A is connected to the first reset signal auxiliary line 21.

[0143] The third jumper wire 52 is connected to the fourth reset active part T7A and the first reset signal auxiliary wire 21;

[0144] One end of the node connection wire 53 is connected to the first node N1, and the other end of the node connection wire 53 is connected to the third electrode plate C21 and the second electrode plate C12; the fourth jumper wire 54 is connected between the second node N2 and the first electrode plate C11; the fifth jumper wire 55 is connected between the second light-emitting control signal line EM2 and the second light-emitting control gate T9G; the sixth jumper wire 56 is connected between the first reset signal line VI1 and the first reset active part T4A; the seventh jumper wire 57 is connected to the second light-emitting control active part T9A; the eighth jumper wire 58 is connected between the first light-emitting control signal line EM1 and the first light-emitting control gate T8G; the ninth jumper wire 59 is connected to the fourth node N4; the eleventh jumper wire 510 is connected between the third reset active part T6A and the first jumper wire 41, and the third jumper wire 52 is connected to Figure 11 the third reset signal line VI3 in another repeating unit in the lower middle part; the eleventh jumper wire 511 and the twelfth jumper wire 512 are both connected between the second reset active part T5A and the second reset signal line VI2. For example, one repeating unit contains three pixel driving circuits PD, and in some of the pixel driving circuits PD, the eleventh jumper wire 511 is used to connect between the second reset active part T5A and the second reset signal line VI2, and in another part of the pixel driving circuits PD, the twelfth jumper wire 512 is used to connect between the second reset active part T5A and the second reset signal line VI2.

[0145] Please refer to Figure 12 and Figure 13 As shown in, the first conductive layer 60 includes a data signal line DATA extending along the second direction Y, a first power supply signal line 61 extending along the second direction Y, a second reset signal auxiliary line 62 extending along the second direction Y, a functional trace 63 extending along the second direction Y, and an anode connection part 64.

[0146] The data signal line DATA is connected to the second jumper wire 51, and further, the data signal line DATA is connected to the switch active part T1A through the second jumper wire 51.

[0147] In some embodiments, the fourth control signal line SCAN4 reduces its width near the fifth jumper wire 64 to avoid the connection control arrangement of the subsequent jumper wire 64 and the anode 71. Moreover, the width of the fourth control signal line SCAN4 near the fifth jumper wire 64 is less than the width of the second reset gate T5G and also less than the width of the third reset gate T6G.

[0148] In some embodiments, the first conductive layer 60 includes a plurality of the data signal lines DATA arranged along the first direction X and a plurality of the first power signal lines 61 arranged along the first direction, and one of the first power signal lines 61 is located between two adjacent data signal lines DATA.

[0149] In some embodiments, please refer to Figure 8 and Figure 13 , both the seventh electrode plate C51 and the eighth electrode plate C61 are connected to the fourth electrode plate C22. Among them, there are electrode plate connection lines 42 extending along the second direction Y between the seventh electrode plate 51 and the fourth electrode plate C22 and between the eighth electrode plate 61 and the fourth electrode plate C22. And the electrode plate connection lines 42 and the data signal lines DATA do not overlap at least partially in the thickness direction of the display panel, so as to reduce the coupling capacitance generated between the seventh electrode plate C51, the eighth electrode plate C61, the fourth electrode plate C22 and the data signal lines DATA, reduce signal interference, and improve the signal stability of the pixel driving circuit PD.

[0150] In some embodiments, in a repeating unit, the data signal lines DATA may include a first data signal line DATA1, a second data signal line DATA2 and a third data signal line DATA3, and the first data signal line DATA1, the second data signal line DATA2 and the third data signal line DATA3 are respectively connected to one pixel driving circuit PD. For example, the light emitting device EL corresponding to the pixel driving circuit PD connected by the first data signal line DATA1 emits red light, the light emitting device EL corresponding to the pixel driving circuit PD connected by the second data signal line DATA2 emits green light, and the light emitting device EL corresponding to the pixel driving circuit PD connected by the third data signal line DATA3 emits blue light.

[0151] The second reset signal auxiliary line 62 is connected to the third patch cord 52. Further, the second reset signal auxiliary line 62 is connected to the fourth reset active part T7A and the first reset signal auxiliary line 21 through the third patch cord 52. The first reset signal auxiliary lines 21 extending along the first direction X in the plurality of pixel driving circuits PD are connected to the second reset signal auxiliary lines 62 extending along the second direction Y to form a network, which can reduce the impedance while realizing signal transmission.

[0152] The first power supply signal line 61 is connected to the second power supply signal line VDD, which can also be used to transmit a high-level potential. The second power supply signal lines VDD extending along the first direction X in the plurality of pixel driving circuits PD are connected to the first power supply signal lines 61 extending along the second direction Y to form a network, which can reduce the impedance while realizing signal transmission.

[0153] In some embodiments, the first power supply signal line 61 is further connected to the seventh patch cord 57 and is connected to the second light-emitting control active part T9A through the seventh patch cord 57.

[0154] Among them, the first power supply signal line 61 is used to transmit a constant-voltage high level, and has a large thickness and width. The first power supply signal line 61 is located below the light-emitting part 100. Therefore, the first power supply signal line 61 has a great influence on the film layer flatness of the position where the light-emitting part 100 is located. Thus, in the embodiments of the present application, the first power supply signal line 61 includes a first line segment 611. The light-emitting part 100 includes a bottom surface 1001 on one side close to the first power supply signal line 61. The orthographic projection of the first line segment 611 on the substrate 10 is located within the orthographic projection of the bottom surface 1001 of the light-emitting part 100 on the substrate 10. The ratio of the orthographic projection area of the first line segment 611 on the substrate 10 to the orthographic projection area of the bottom surface 1001 of the light-emitting part 100 on the substrate 10 is greater than or equal to 0.5. Further, in the embodiments of the present application, by increasing the area and coverage range of the first line segment 611, the film layer flatness of the position where the light-emitting part 100 is located can be improved, the film thickness uniformity and yield of the light-emitting part 100 can be improved, and thus the light-emitting effect and light-emitting efficiency of the display panel can be improved.

[0155] In some embodiments, the ratio of the orthographic projection area of the first line segment 611 on the substrate 10 to the orthographic projection area of the bottom surface 1001 of the light-emitting portion 100 on the substrate 10 is less than or equal to 1, or the ratio of the orthographic projection area of the first line segment 611 on the substrate 10 to the orthographic projection area of the bottom surface 1001 of the light-emitting portion 100 on the substrate 10 is less than or equal to 0.8; for example, the ratio of the orthographic projection area of the first line segment 611 on the substrate 10 to the orthographic projection area of the bottom surface 1001 of the light-emitting portion 100 on the substrate 10 may be 0.5, 0.6, 0.7, 0.8, 0.9, or 1.

[0156] In some embodiments, the ratio of the width of the first line segment 611 in the first direction X to the width of the bottom surface 1001 of the light-emitting portion 100 in the first direction X is greater than or equal to 0.5 and less than or equal to 1; it should be noted that in the related art, the line width of the power signal line usually accounts for less than 0.2 of the width of the light-emitting pixel, and the thickness of the power signal is usually relatively large, which will have a greater impact on the flatness of the film layer at the position of the light-emitting pixel; thus, in the embodiments of the present application, by increasing the width and coverage range of the first line segment 611, the flatness of the film layer at the position of the light-emitting portion 100 can be improved, the film thickness uniformity and yield of the light-emitting portion 100 can be improved, and thus the light-emitting effect and light-emitting efficiency of the display panel can be improved.

[0157] In some embodiments, the ratio of the width of the first line segment 611 in the first direction X to the width of the bottom surface 1001 of the light-emitting portion 100 in the first direction X is 0.5, 0.6, 0.7, 0.8, 0.9, or 1; further preferably, the ratio of the width of the first line segment 611 in the first direction X to the width of the bottom surface 1001 of the light-emitting portion 100 in the first direction X is greater than or equal to 0.5 and less than or equal to 0.8.

[0158] In some embodiments, the ratio of the width of the first line segment 611 in the first direction X to the width of the bottom surface 1001 of the light-emitting portion 100 in the first direction X is greater than or equal to 0.5 and less than or equal to 1.

[0159] In some embodiments, the second power supply signal line VDD is connected to the first power supply signal line 61 through a first via, the node connection line 53 is connected to the second electrode plate C12 through a second via, the first via and the second via are located on opposite sides of the first line segment 611, and the width of the first line segment 611 in the first direction X between the first via and the second via is greater than or equal to the width of the first line segment 611 at other positions in the first direction; that is, the portion of the first line segment 611 between the first via and the second via can be regarded as the portion of the first line segment 611 on the side away from the substrate 10 of the first via and the second via, and the portion between the first via and the second via. In the embodiments of the present application, by maintaining the line width uniformity of the first line segment 611 everywhere, the film layer flatness at the corresponding position of the first line segment 611 can be improved.

[0160] In some embodiments, the first line segment 611 includes overlapping sub-portions 6111 continuously arranged in the second direction Y. The overlapping sub-portions 6111 partially overlap with the first capacitor C1 in the thickness direction of the display panel, the overlapping sub-portions 6111 partially overlap with the second capacitor C2 in the thickness direction of the display panel, and the width of the overlapping sub-portions 6111 in the first direction X is equal everywhere; to effectively increase the overlapping area between the first line segment 611 and the bottom surface 1001 of the light-emitting portion 100; wherein, the overlapping sub-portions 6111 can be regarded as the portions of the first line segment 611 that overlap with the first capacitor C1 and the second capacitor C2, and the portion between the first capacitor C1 and the second capacitor C2; similarly, by maintaining the line width uniformity of the first line segment 611 everywhere, the film layer flatness at the corresponding position of the first line segment 611 can be improved.

[0161] Further, in some embodiments, the first line segment 611 and the first capacitor C1 have a first overlapping portion in the thickness direction of the display panel. The ratio of the orthographic projection area of the first overlapping portion on the substrate 10 to the orthographic projection area of the first capacitor C1 on the substrate is greater than or equal to 0.5 and less than or equal to 0.8; to effectively increase the overlapping area between the first line segment 611 and the bottom surface 1001 of the light-emitting portion 100.

[0162] The first line segment 611 and the second capacitor C2 have a second overlapping portion in the thickness direction of the display panel. The ratio of the area of the positive projection of the second overlapping portion on the substrate 10 to the area of the positive projection of the second capacitor C2 on the substrate 10 is greater than or equal to 0.4 and less than or equal to 0.5, so as to effectively increase the overlapping area between the first line segment 611 and the bottom surface 1001 of the light-emitting portion 100.

[0163] In some embodiments, the first power signal line 61 further includes a second line segment 612 connected to the first line segment 611 along the second direction Y. The second line segment 612 does not overlap with the bottom surface 1001 of the light-emitting portion 100 in the thickness direction of the display panel, and the width of the second line segment 612 along the first direction X is less than the width of the first line segment 611 along the first direction X.

[0164] In some embodiments, one end of the anode connection portion 64 is connected to the ninth jumper wire 59, and the other end of the anode connection portion 64 is used to connect to the anode 71.

[0165] The functional trace 63 extends along the second direction Y, and one functional trace 63 can be provided in each repeating unit.

[0166] In some embodiments, the functional trace 63 can extend into the non-display area NA and be connected to a constant low-level signal located in the non-display area NA to form an auxiliary cathode line, reducing the resistance of the cathode in the display panel.

[0167] In some embodiments, the functional trace 63 can be used to connect at least one of the first reset signal line VI1, the second reset signal line VI2, and the third reset signal line VI3 extending along the first direction X to form a mesh trace structure, reducing the trace resistance.

[0168] Please refer to Figure 14 , the anode layer 70 is disposed on a side of the second flat layer 85 away from the first flat layer 84. The anode layer 70 includes a plurality of anodes 71 corresponding to the plurality of pixel driving circuits PD, and the anodes 71 are connected to the anode connection portions 64, that is, the anodes 71 are connected to the pixel driving circuits PD through the anode connection portions 64, and specifically can be connected to the first light-emitting control active portion T8A.

[0169] In some embodiments, the anode connection portion 64 does not overlap with the first line segment 611 along the first direction X, and the anode connection portion 64 partially overlaps with the first line segment 611 along the second direction Y; that is, the anode connection portion 64 is located between the first line segments 611 corresponding to two adjacent pixel driving circuits PD along the second direction Y, rather than between two adjacent pixel driving circuits PD along the first direction X. Furthermore, the connection vias between the anode connection portion 64 and the pixel driving circuit PD will not affect the line width of the first line segment 611 along the first direction X, and the film layer flatness at the position where the light emitting portion 100 is located can be further improved.

[0170] Please refer to Figure 15 , the pixel defining layer 86 is disposed on a side of the anode layer 70 away from the first conductive layer 60. A plurality of pixel openings 860 are formed in the pixel defining layer 86, and a partial surface of the corresponding anode 71 is exposed through each pixel opening 860.

[0171] In some embodiments, the pixel defining layer 86 may include a first pixel defining layer 861 and a second pixel defining layer 862. Wherein, the first pixel defining layer 861 may extend along the first direction X, the second pixel defining layer 862 may extend along the second direction Y, and the first pixel defining layer 861 and the second pixel defining layer 862 intersect to enclose the pixel openings 860.

[0172] The light emitting layer 13 is disposed on the pixel defining layer 86. The light emitting layer 13 includes a plurality of light emitting portions 100. The plurality of light emitting portions 100 are disposed corresponding to the plurality of pixel openings 860. One light emitting portion 100 is disposed in the corresponding pixel opening 860 and is located on a side of the anode 71 away from the substrate 10.

[0173] In some embodiments, the cathode covers the pixel defining layer 86 and the plurality of light emitting portions 100, and the stacked anode 71, the light emitting portion 100, and the cathode may form the light emitting device EL.

[0174] In some embodiments, in the same pixel driving circuit PD, the first capacitor C1 and the driving transistor T2 partially overlap along the thickness direction of the display panel. The second capacitor C2 is located between the first capacitor C1 and the switching transistor T1, and the second capacitor is located between the driving transistor T2 and the switching transistor T1.

[0175] Continuing from the above, for the pixel driving circuit PD described in the above embodiments, at least some of the thin film transistors partially overlap with the first line segment 611 in the first direction X to further increase the coverage range of the first line segment 611.

[0176] In some embodiments, the switching transistor T1 partially overlaps with the first line segment 611 in the thickness direction of the display panel, the driving transistor T2 partially overlaps with the first line segment 611 in the thickness direction of the display panel, and the first capacitor C1 partially overlaps with the first line segment 611 in the thickness direction of the display panel.

[0177] Among them, in the switching transistor T1, the switching active part T1A partially overlaps with the first line segment 611 in the thickness direction of the display panel, the switching gate T1G partially overlaps with the first line segment 611 in the thickness direction of the display panel, the driving active part T2A partially overlaps with the first line segment 611 in the thickness direction of the display panel, the driving gate T1G partially overlaps with the first line segment 611 in the thickness direction of the display panel, and both the first electrode plate C11 and the second electrode plate C12 in the first capacitor C1 partially overlap with the first line segment 611 in the thickness direction of the display panel.

[0178] Among them, the switching transistor T1 is disposed near the edge of the pixel driving circuit PD, and the first line segment 611 partially overlaps with the switching transistor T1 in the thickness direction of the display panel, which can effectively increase the coverage range of the first power supply signal line 61.

[0179] In some embodiments, the second capacitor C2 is electrically connected to the first power supply signal line 61, and the second capacitor C2 partially overlaps with the first line segment 611 in the thickness direction of the display panel.

[0180] Among them, both the third electrode plate C21 and the fourth electrode plate C22 in the second capacitor C2 partially overlap with the first line segment 611 in the thickness direction of the display panel.

[0181] In some embodiments, the first reset transistor T4 is located on the side of the driving transistor T2 away from the switching transistor T1, and the first reset transistor T4 partially overlaps with the first line segment 611 in the thickness direction of the display panel.

[0182] Among them, in the first reset transistor T4, the first reset active part T4A and the first line segment 611 partially overlap in the thickness direction of the display panel, and the first reset gate T4G and the first line segment 611 partially overlap in the thickness direction of the display panel.

[0183] In some embodiments, the compensation transistor T3 is located on a side of the driving transistor T2 away from the switching transistor T1. The compensation transistor T3 and the first reset transistor T4 are arranged adjacent to each other along the first direction X. The compensation transistor T3 and the first line segment 611 partially overlap in the thickness direction of the display panel.

[0184] Among them, in the compensation transistor T3, the compensation active part T3A and the first line segment 611 partially overlap in the thickness direction of the display panel, and the compensation gate T3G and the first line segment 611 partially overlap in the thickness direction of the display panel.

[0185] It should be noted that the compensation gate T3G and the compensation active part T3A are arranged close to the edge of the bottom surface 1001 of the light emitting part 100. In the embodiments of the present application, the first line segment 611 is arranged to partially overlap with the compensation gate T3G and the compensation active part T3A, so as to effectively increase the coverage range of the first line segment 611 and improve the flatness of the film layer where the light emitting part 100 is located.

[0186] In some embodiments, the first light emission control transistor T8 is located on a side of the compensation transistor T3 away from the driving transistor T2, and the first light emission control transistor T8 and the first line segment 611 partially overlap in the thickness direction of the display panel.

[0187] Among them, in the first light emission control transistor T8, the first light emission control active part T8A and the first line segment 611 do not partially overlap in the thickness direction of the display panel, and the first light emission control gate T8G and the first line segment 611 partially overlap in the thickness direction of the display panel.

[0188] In some embodiments, the second light emission control transistor T9 is located on a side of the first reset transistor T4 away from the driving transistor T2, and the second light emission control transistor T9 and the first line segment 611 partially overlap in the thickness direction of the display panel.

[0189] Among them, in the second light-emitting control transistor T9, the second light-emitting control active part T9A and the first line segment 611 partially overlap in the thickness direction of the display panel, and the second light-emitting control gate T9G and the first line segment 611 partially overlap in the thickness direction of the display panel.

[0190] In some embodiments, the second reset transistor T5 and the first line segment 611 do not partially overlap in the thickness direction of the display panel, and the third reset transistor T6 and the first line segment 611 do not partially overlap in the thickness direction of the display panel.

[0191] Among them, in the second reset transistor T5, the second reset active part T5A and the second reset gate T5G do not overlap with the first line segment 611 in the thickness direction of the display panel; in the third reset transistor T6, the third reset active part T6A and the third reset gate T6G do not overlap with the first line segment 611 in the thickness direction of the display panel.

[0192] In some embodiments, the fourth reset transistor T7 is disposed adjacent to the switching transistor T1 along the first direction X, and the fourth reset transistor T7 and the first line segment 611 partially overlap in the thickness direction of the display panel.

[0193] Among them, in the fourth reset transistor T7, the fourth reset active part T7A and the first line segment 611 partially overlap in the thickness direction of the display panel, and the fourth reset gate T7G and the first line segment 611 partially overlap in the thickness direction of the display panel.

[0194] It should be noted that the fourth reset transistor T7 is disposed near the edge of the pixel driving circuit PD, and the first line segment 611 and the fourth reset transistor T7 partially overlap in the thickness direction of the display panel, which can effectively increase the coverage of the first power signal line 61.

[0195] Furthermore, in some embodiments, please refer to Figure 12, the first line segment 611 includes a first side 6111 and a second side 6112 that are oppositely arranged along the first direction X. In at least a part of the first line segment 611 of the first power signal line 61, both the first side 6111 and the second side 6112 are parallel to the second direction Y. For example, in the first power signal line 61 adjacent to the first data signal line DATA1, the first side 6111 of the first line segment 611 is parallel to the second direction Y, and a part of the second side 6112 is parallel to the second direction Y; in the first power signal line 61 adjacent to the second data signal line DATA2, the first side 6111 of the first line segment 611 is parallel to the second direction Y, and the second side 6112 is parallel to the second direction Y; in the first power signal line 61 adjacent to the third data signal line DATA3, the first side 6111 of the first line segment 611 is parallel to the second direction Y, and the second side 6112 is parallel to the second direction Y.

[0196] In summary, in the embodiment of the present application, by increasing the ratio of the area of the first line segment 611 in the first power signal line 61 to the area of the bottom surface of the light-emitting part, the coverage range of the first line segment 611 in the area corresponding to the bottom surface 1001 of the light-emitting part 100 can be increased, the film layer flatness at the position where the light-emitting part 100 is located can be improved, and thus the film thickness uniformity of the light-emitting part 100 can be effectively improved, and the light-emitting effect and light-emitting efficiency of the display panel can be improved.

[0197] According to the above object of the present application, the embodiment of the present application further provides a display device, and the display device includes the display panel.

[0198] It can be understood that since the display device has the same display panel as in the above embodiment, therefore, the display device has the same beneficial effects as the display panel, and will not be elaborated here.

[0199] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality" means two or more, unless otherwise specifically defined.

[0200] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0201] The embodiments, implementation manners and related technical features of the present application can be combined and replaced with each other without conflict.

[0202] The above are only the preferred embodiments of the present application, and do not impose any formal restrictions on the present application. However, any simple modifications, equivalent changes and decorations made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: include: substrate A first conductive layer is disposed on one side of the substrate, the first conductive layer comprises a plurality of first power signal lines arranged along a first direction, the first power signal lines extend along a second direction, and the first direction and the second direction intersect; a light-emitting layer, disposed on a side of the first conductive layer away from the substrate, the light-emitting layer comprising a plurality of light-emitting portions arranged along the first direction and the second direction, the plurality of light-emitting portions arranged along the second direction being located on a side of the corresponding first power signal line away from the substrate; Among them, the first power signal line includes a first line segment, the light-emitting portion includes a bottom surface close to the first power signal line, the orthographic projection of the first line segment on the substrate is located within the orthographic projection of the bottom surface of the light-emitting portion on the substrate, and the ratio of the orthographic projection area of ​​the first line segment on the substrate to the orthographic projection area of ​​the bottom surface of the light-emitting portion on the substrate is greater than or equal to 0.

5.

2. The display panel according to claim 1, characterized in that: The display panel further includes a plurality of pixel driving circuits arranged corresponding to the plurality of light-emitting portions, the pixel driving circuit including a switching transistor, a driving transistor, and a first capacitor connected between the switching transistor and the driving transistor; The switch transistor partially overlaps with the first line segment along the thickness direction of the display panel, the drive transistor partially overlaps with the first line segment along the thickness direction of the display panel, and the first capacitor partially overlaps with the first line segment along the thickness direction of the display panel.

3. The display panel according to claim 2, characterized in that: The switch transistor includes a switch active portion and a switch gate, and the drive transistor includes a drive active portion and a drive gate; The switch active portion partially overlaps with the first line segment along the thickness direction of the display panel, the switch gate partially overlaps with the first line segment along the thickness direction of the display panel, the driving active portion partially overlaps with the first line segment along the thickness direction of the display panel, and the driving gate partially overlaps with the first line segment along the thickness direction of the display panel.

4. The display panel according to claim 2, characterized in that: The display panel further includes: A first gate layer, disposed between the substrate and the first conductive layer, the first gate layer comprising a first plate of the first capacitor; A second gate layer, disposed between the first gate layer and the first conductive layer, the second gate layer comprising a second electrode plate of the first capacitor, the second electrode plate being disposed opposite to the first electrode plate; a second conductive layer, disposed between the second gate layer and the first conductive layer, the second conductive layer comprising a second power signal line extending along the first direction and a node connection line connected between the switch active portion and the second electrode plate; Among them, the second power signal line is connected to the first power signal line through a first via, the node connection line is connected to the second electrode plate through a second via, the first via and the second via are located on opposite sides of the first line segment, and the first line segment is located between the first via and the second via and the width along the first direction is greater than or equal to the width of other positions of the first line segment along the first direction.

5. The display panel according to claim 2, characterized in that: The switch transistor and the first capacitor are connected to a first node, the pixel driving circuit further comprises a second capacitor connected to the first node, and the second capacitor is located between the first capacitor and the switch transistor; The second capacitor is electrically connected to the first power signal line, and the second capacitor partially overlaps with the first line segment along a thickness direction of the display panel.

6. The display panel according to claim 5, characterized in that: The first line segment includes an overlapping sub-portion continuously arranged along the second direction, the overlapping sub-portion partially overlaps with the first capacitor along the thickness direction of the display panel, the overlapping sub-portion partially overlaps with the second capacitor along the thickness direction of the display panel, and the overlapping sub-portion has the same width at each location along the first direction.

7. The display panel according to claim 5, characterized in that: The first line segment and the first capacitor have a first overlapping portion along the thickness direction of the display panel, and a ratio of an orthographic projection area of ​​the first overlapping portion on the substrate to an orthographic projection area of ​​the first capacitor on the substrate is greater than or equal to 0.5 and less than or equal to 0.8; The first line segment and the second capacitor have a second overlapping portion along the thickness direction of the display panel, and a ratio of an orthographic projection area of ​​the second overlapping portion on the substrate to an orthographic projection area of ​​the second capacitor on the substrate is greater than or equal to 0.4 and less than or equal to 0.

5.

8. The display panel according to claim 2, characterized in that: The first capacitor and the driving transistor are connected to a second node, and the pixel driving circuit also includes a first reset transistor connected to the second node. The first reset transistor is located on a side of the driving transistor away from the switching transistor, and the first reset transistor partially overlaps with the first line segment along the thickness direction of the display panel.

9. The display panel according to claim 8, characterized in that: The first reset transistor includes a first reset active portion and a first reset gate, the first reset active portion partially overlaps with the first line segment along the thickness direction of the display panel, and the first reset gate partially overlaps with the first line segment along the thickness direction of the display panel.

10. The display panel according to claim 8, characterized in that: The pixel driving circuit also includes a compensation transistor, which is connected between the second node and a third node, and the driving transistor is connected to the third node. The compensation transistor is located on a side of the driving transistor away from the switching transistor, and the compensation transistor is adjacent to the first reset transistor along the first direction. The compensation transistor partially overlaps with the first line segment along the thickness direction of the display panel.

11. The display panel according to claim 10, characterized in that: The pixel driving circuit also includes a first light emitting control transistor connected between the third node and the fourth node, the display panel also includes a light emitting device connected to the fourth node, the light emitting device includes the light emitting portion, the first light emitting control transistor is located on a side of the compensation transistor away from the driving transistor, and the first light emitting control transistor partially overlaps with the first line segment along the thickness direction of the display panel.

12. The display panel according to claim 11, characterized in that: The first light emitting control transistor includes a first light emitting control active portion and a first light emitting control gate, the first light emitting control active portion partially does not overlap with the first line segment along the thickness direction of the display panel, and the first light emitting control gate partially overlaps with the first line segment along the thickness direction of the display panel.

13. The display panel according to claim 11, characterized in that: The pixel driving circuit also includes a second light-emitting control transistor connected to a fifth node, the driving transistor is connected to the fifth node, the second light-emitting control transistor is located on a side of the first reset transistor away from the driving transistor, and the second light-emitting control transistor partially overlaps with the first line segment along the thickness direction of the display panel.

14. The display panel according to claim 13, characterized in that: The second light emitting control transistor includes a second light emitting control active portion and a second light emitting control gate, the second light emitting control active portion partially overlaps with the first line segment along the thickness direction of the display panel, and the second light emitting control gate partially overlaps with the first line segment along the thickness direction of the display panel.

15. The display panel according to claim 13, characterized in that: The pixel driving circuit also includes a second reset transistor connected to the fourth node and a third reset transistor connected to the fifth node, the second reset transistor and the first line segment do not overlap partially along the thickness direction of the display panel, and the third reset transistor and the first line segment do not overlap partially along the thickness direction of the display panel.

16. The display panel according to claim 2, characterized in that: The pixel driving circuit also includes a fourth reset transistor connected to the switching transistor and the first capacitor, the fourth reset transistor is arranged adjacent to the switching transistor along the first direction, the fourth reset transistor includes a fourth reset active portion and a fourth reset gate, the fourth reset active portion partially overlaps with the first line segment along the thickness direction of the display panel, and the fourth reset gate partially overlaps with the first line segment along the thickness direction of the display panel.

17. The display panel according to claim 2, characterized in that: The pixel driving circuit also includes a compensation transistor, which includes a compensation active portion and a compensation gate arranged near the edge of the bottom surface of the light-emitting portion, the compensation active portion partially overlaps with the first line segment along the thickness direction of the display panel, and the compensation gate partially overlaps with the first line segment along the thickness direction of the display panel.

18. The display panel according to claim 2, characterized in that: The first conductive layer also includes an anode connection portion; The display panel further includes: an anode layer, arranged on a side of the first conductive layer away from the substrate, the anode layer comprising a plurality of anodes arranged corresponding to the plurality of pixel driving circuits, the anodes being connected to the pixel driving circuits via the anode connecting portion; The anode connecting portion does not overlap with the first line segment along the first direction, and the anode connecting portion partially overlaps with the first line segment along the second direction.

19. The display panel according to any one of claims 1 to 18, characterized in that: The first line segment includes a first side edge and a second side edge that are oppositely arranged along the first direction, and in at least part of the first line segment of the first power signal line, the first side edge and the second side edge are both parallel to the second direction; A ratio of a width of the first line segment along the first direction to a width of the bottom surface of the light-emitting portion along the first direction is greater than or equal to 0.5 and less than or equal to 1.

20. The display panel according to any one of claims 1 to 18, characterized in that: The first power signal line also includes a second line segment connected to the first line segment along the second direction, the second line segment does not overlap with the bottom surface of the light-emitting portion along the thickness direction of the display panel, and the width of the second line segment along the first direction is smaller than the width of the first line segment along the first direction.

Images