Display substrate, driving method thereof and display device

Abstract

The invention discloses a display substrate, a driving method of the display substrate and a display device. The display substrate comprises a substrate, K rows of sub-pixels arranged on the substrate and multiple signal lines extending in the row direction (X). The number of the same kind of signal lines is multiple, the multiple same kind of signal lines are arranged at intervals in the column direction (Y), and each row of sub-pixels is electrically connected with one signal line in the same kind of signal lines; on a plane parallel to the display substrate, the row direction (X) and the column direction (Y) intersect; each signal line is arranged to be electrically connected with at least two rows of sub-pixels, and in the at least one kind of signal lines, the number of the same kind of signal lines is a positive integer smaller than K.

Description

Display substrate, driving method thereof, and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a driving method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, embodiments of the present disclosure provide a display substrate comprising a substrate, K rows of sub-pixels disposed on the substrate, and a plurality of signal lines extending along a row direction; a plurality of signal lines of the same type are arranged in a column direction, and each row of sub-pixels is electrically connected to one of the signal lines of the same type; in a plane parallel to the display substrate, the row direction intersects the column direction;

[0006] At least some of the at least one signal line, each signal line is configured to be electrically connected to at least two rows of sub-pixels, and the number of the same signal lines in the at least one signal line is a positive integer less than K.

[0007] In an exemplary embodiment, each signal line of at least some of the at least one signal line is electrically connected to two adjacent rows of sub-pixels.

[0008] In an exemplary embodiment, the at least one signal line includes a first type signal line, and the first type signal line includes at least two adjacent signal lines of the same type, and one of the two adjacent signal lines of the same type is configured to be electrically connected to the i-th row of sub-pixels and the i+1-th row of sub-pixels, and the other signal line is configured to be electrically connected to the i+2-th row of sub-pixels and the i+3-th row of sub-pixels, where i is an integer greater than or equal to 1 and less than K.

[0009] In an exemplary embodiment, types of signal lines in the first-type signal lines include a first reset control line and / or a first initial signal line.

[0010] In an exemplary embodiment, the first initial signal line and the first reset control line are located in different conductive layers, and in the same row of sub-pixels, an orthographic projection of the first initial signal line and an orthographic projection of the first reset control line on the substrate at least partially overlap.

[0011] In an exemplary embodiment, the at least one signal line also includes a second type of signal line, and the second type of signal line includes at least two adjacent signal lines of the same type, and among the two adjacent signal lines of the same type, one signal line is configured to be electrically connected to the i-1th row of sub-pixels and the i-th row of sub-pixels, and the other signal line is configured to be electrically connected to the i+1th row of sub-pixels and the i+2th row of sub-pixels, where i is greater than 1.

[0012] In an exemplary embodiment, types of signal lines in the second-type signal lines include a second reset control line and / or a second initial signal line.

[0013] In an exemplary embodiment, the second reset control line and the second initial signal line are located in different conductive layers, and in the same row of sub-pixels, an orthographic projection of the second reset control line on the substrate at least partially overlaps with an orthographic projection of the second initial signal line on the substrate.

[0014] In an exemplary embodiment, the types of signal lines in the second-type signal lines further include at least one of a third initial signal line, a light emitting control line, and a second scan line.

[0015] In an exemplary embodiment, the light emission control line and the third initial signal line are located in different conductive layers, and in the same row of sub-pixels, the orthographic projection of the light emission control line on the substrate at least partially overlaps with the orthographic projection of the third initial signal line on the substrate.

[0016] In an exemplary embodiment, the second type of signal lines further includes a second scanning auxiliary line, and in the same row of sub-pixels, the second scanning auxiliary line at least partially overlaps with an orthographic projection of the second scanning line on the substrate.

[0017] In an exemplary embodiment, the K rows of sub-pixels include a plurality of first sub-pixel rows and a plurality of second sub-pixel rows, the first sub-pixel rows and the second sub-pixel rows are alternately arranged along the column direction, and at least part of the at least one signal line, each signal line is configured to be electrically connected to a first sub-pixel row and a second sub-pixel row adjacent to it.

[0018] In an exemplary embodiment, each row of sub-pixels includes a plurality of sub-pixels sequentially arranged along the row direction, the plurality of sub-pixels forming a plurality of pixel units, and at least some of the pixel units include at least three sub-pixels sequentially arranged along the row direction;

[0019] The display substrate includes a first display area, which includes multiple first sub-areas, multiple second sub-areas, multiple third sub-areas and multiple fourth sub-areas, the first sub-areas and the third sub-areas are alternately arranged along the row direction, the second sub-areas and the fourth sub-areas are alternately arranged along the row direction, the multiple pixel units in the first sub-pixel row are respectively located in the multiple first sub-areas, the multiple pixel units in the second sub-pixel row are respectively located in the multiple second sub-areas, the multiple pixel units located in the first sub-pixel row are spaced apart by the third sub-area, and the multiple pixel units located in the second sub-pixel row are spaced apart by the fourth sub-area.

[0020] In an exemplary embodiment, at least some sub-pixels include a first pixel circuit, and at least some pixel units include four sub-pixels arranged sequentially along the row direction; in the same pixel unit, the four first pixel circuits are symmetrically arranged about a first center line extending along the column direction of the four first pixel circuits, the first first pixel circuit and the second first pixel circuit of the four first pixel circuits are symmetrically arranged about a second center line extending along the column direction of the two first pixel circuits, and the third first pixel circuit and the fourth first pixel circuit are symmetrically arranged about a third center line extending along the column direction of the two first pixel circuits.

[0021] In an exemplary embodiment, the plurality of first sub-regions form a plurality of columns of first sub-regions, and the plurality of second sub-regions form a plurality of columns of second sub-regions, and in the column direction, the first sub-regions and the second sub-regions are staggered.

[0022] The third first pixel circuit and the fourth first pixel circuit of the four first pixel circuits in the pixel unit located in the first sub-area are respectively located in the same column as the first first pixel circuit and the second first pixel circuit of the four first pixel circuits in the pixel unit located in the adjacent second sub-area.

[0023] In an exemplary embodiment, the pixel unit further includes four light-emitting elements, which are electrically connected to four first pixel circuits in the pixel unit, respectively, and the light-emitting elements include anodes; in the same pixel unit, the orthographic projections of the anodes of the four light-emitting elements on the substrate at least partially do not overlap with the orthographic projections of the third sub-region and the fourth sub-region on the substrate; in the first sub-pixel row, the orthographic projections of the anodes of the four light-emitting elements on the substrate at least partially overlap with the orthographic projections of the first sub-region on the substrate; in the second sub-pixel row, the orthographic projections of the anodes of the four light-emitting elements on the substrate at least partially overlap with the second sub-region.

[0024] In an exemplary embodiment, at least part of the first pixel circuit includes first to eighth transistors;

[0025] In a first pixel circuit in a first subpixel row located in the i-th row, in the column direction, the first transistor, the second transistor, and the fourth transistor are located on a side of the third transistor close to a second subpixel row located in the (i+1)th row, and the second transistor is located between the first transistor and the third transistor; the fifth to eighth transistors are located on a side of the third transistor close to a second subpixel row located in the (i-1)th row, and the sixth transistor is located between the third transistor and the seventh transistor; wherein i is a positive integer greater than 1 and less than K;

[0026] In the first pixel circuit located in the second sub-pixel row located in the i+1th row, the first transistor, the second transistor and the fourth transistor are located on a side of the third transistor close to the first sub-pixel row located in the i+1th row, and the second transistor is located between the first transistor and the third transistor; the fifth transistor to the eighth transistor are located on a side of the third transistor close to the first sub-pixel row located in the i+2th row, and the sixth transistor is located between the third transistor and the seventh transistor.

[0027] In an exemplary embodiment, in a direction perpendicular to a plane of the display substrate, the display substrate includes: a circuit structure layer located on the substrate; the circuit structure layer includes the plurality of first pixel circuits; at least some of the plurality of first pixel circuits include: at least one first-type transistor, at least one second-type transistor, and a storage capacitor; the first-type transistors include at least the first transistor and the third to eighth transistors, and the second-type transistors include at least the second transistor;

[0028] The circuit structure layer includes: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, and a third conductive layer arranged on the substrate; the first semiconductor layer includes at least: an active layer of the first type transistor of the pixel circuit; the first conductive layer includes at least: a gate of the first type transistor of the pixel circuit and a first electrode of a storage capacitor; the second conductive layer includes at least: a second electrode of the storage capacitor of the pixel circuit; the second semiconductor layer includes at least: an active layer of the second type transistor of the pixel circuit; the third conductive layer includes at least: a gate of the second type transistor of the pixel circuit.

[0029] In an exemplary embodiment, the first type transistor may be a P-type transistor, and the second type transistor may be an N-type transistor.

[0030] In an exemplary embodiment, the first conductive layer further includes: a first scan line, the light emission control line, a first reset control line, and a second reset control line electrically connected to the first type of transistor in the first pixel circuit; the first scan line, the light emission control line, the first reset control line, and the second reset control line extend along the row direction;

[0031] In the column direction, the first scan line and the first reset control line electrically connected to the first sub-pixel row bypass one side of the third sub-region, and the light-emitting control line electrically connected to the first sub-pixel row bypasses the other side of the third sub-region; the first scan line electrically connected to the second sub-pixel row bypasses one side of the fourth sub-region, and the light-emitting control line and the second reset control line electrically connected to the second sub-pixel row bypass the other side of the fourth sub-region.

[0032] In an exemplary embodiment, the third conductive layer further includes a first initial signal line electrically connected to the first transistor in the first pixel circuit, a second initial signal line electrically connected to the seventh transistor in the first pixel circuit, and a third initial signal line electrically connected to the eighth transistor; the first initial signal line, the second initial signal line, and the third initial signal line extend along the row direction;

[0033] In the same row of sub-pixels, the orthographic projection of the first initial signal line on the substrate at least partially overlaps with the orthographic projection of the first reset control line on the substrate, the orthographic projection of the second initial signal line on the substrate at least partially overlaps with the orthographic projection of the second reset control line on the substrate, and the orthographic projection of the third initial signal line on the substrate at least partially overlaps with the orthographic projection of the light-emitting control line on the substrate.

[0034] In an exemplary embodiment, the second reset control line and the second initial signal line are located adjacent to the first subregion of the first subpixel row in the i-th row and the second subregion of the second subpixel row in the (i-1)th row, and are ring-shaped structures. In the column direction, a side of the ring-shaped structure close to the first subregion overlaps with the orthographic projections of the seventh transistor and the eighth transistor in the third to fourth first pixel circuits in the first subregion on the substrate, and a side of the ring-shaped structure close to the second subregion overlaps with the orthographic projections of the seventh transistor and the eighth transistor in the first to second first pixel circuits in the second subregion on the substrate.

[0035] At a position adjacent to the first sub-region of the first sub-pixel row in the i-th row and the second sub-region of the second sub-pixel row in the (i+1)-th row, the first reset control line and the first initial signal line are ring structures. In the column direction, a side of the ring structure close to the first sub-region overlaps with the positive projection of the first transistors in the third to fourth first pixel circuits in the first sub-region on the substrate, and a side of the ring structure close to the second sub-region overlaps with the positive projection of the first transistors in the first to second first pixel circuits in the second sub-region on the substrate.

[0036] In an exemplary embodiment, the second conductive layer further includes a second auxiliary scan line electrically connected to the second transistor in the first pixel circuit; the third conductive layer further includes a second scan line electrically connected to the second transistor in the first pixel circuit; in sub-pixels in the same row, the second auxiliary scan line and the orthographic projection of the second scan line on the substrate at least partially overlap; the second auxiliary scan line and the second scan line extend along the row direction;

[0037] In the column direction, the second scan line and the second scan auxiliary line electrically connected to the first sub-pixel row bypass one side of the third sub-region, and the second scan line and the second scan auxiliary line electrically connected to the second sub-pixel row bypass one side of the fourth sub-region; the direction in which the second scan line and the second scan auxiliary line electrically connected to the first sub-pixel row bypass the third sub-region is opposite to the direction in which the second scan line and the second scan auxiliary line electrically connected to the second sub-pixel row bypass the fourth sub-region.

[0038] In an exemplary embodiment, the display substrate further includes a fourth conductive layer, the fourth conductive layer including a fourth switching electrode; the fourth switching electrode extends along the column direction;

[0039] The second conductive layer further includes a plurality of second scan auxiliary lines and a plurality of second scan auxiliary electrodes electrically connected to the second transistor in the first pixel circuit; the third conductive layer further includes a plurality of second scan lines and a plurality of second scan electrodes electrically connected to the second transistor in the first pixel circuit; in sub-pixels in the same row, the orthographic projections of the second scan lines and the second scan lines on the substrate at least partially overlap, and the orthographic projections of the second scan electrodes and the second scan auxiliary electrodes on the substrate at least partially overlap; the second scan auxiliary electrodes, the second scan electrodes, the second scan auxiliary lines and the second scan lines extend along the row direction;

[0040] The plurality of second scan auxiliary electrodes and the plurality of second scan electrodes are respectively electrically connected to the plurality of pixel units in the second sub-pixel row, and the plurality of second scan auxiliary lines and the plurality of second scan lines are electrically connected to the plurality of first pixel circuits in the first sub-pixel row; the second scan auxiliary line and the second scan line located in the i-th row are electrically connected to the plurality of second scan auxiliary electrodes and the plurality of second scan electrodes located in the i-1-th row via a fourth switching electrode, and the second scan auxiliary line and the second scan line located in the i+2-th row are electrically connected to the plurality of second scan auxiliary electrodes and the plurality of second scan electrodes located in the i+1-th row via a fourth switching electrode;

[0041] In the column direction, the second scan line and the second scan auxiliary line electrically connected to the first sub-pixel row bypass one side of the fourth sub-region; a plurality of second scan electrodes and a plurality of second scan auxiliary electrodes electrically connected to the second sub-pixel row are located in the second sub-region.

[0042] In an exemplary embodiment, the present invention further includes a fourth conductive layer located on a side of the third conductive layer away from the substrate, the fourth conductive layer including a plurality of first switching electrodes and a plurality of second switching electrodes; the first switching electrodes and the second switching electrodes extend along the column direction;

[0043] The first conductive layer further includes: a plurality of light emitting control lines electrically connected to the plurality of first sub-pixel rows, and a plurality of light emitting control electrodes electrically connected to the plurality of second sub-pixel rows, respectively; the light emitting control lines and the light emitting control electrodes extend along the row direction; the third conductive layer further includes: a plurality of third initial signal lines electrically connected to the plurality of first sub-pixel rows, respectively, and a plurality of third initial signal electrodes electrically connected to the plurality of second sub-pixel rows, respectively; the third initial signal lines and the third initial signal electrodes extend along the row direction;

[0044] The light-emitting control line in the i-th row is electrically connected to the plurality of light-emitting control electrodes in the i-1-th row through the first adapter electrode, and the light-emitting control line in the i+2-th row is electrically connected to the plurality of light-emitting control electrodes in the i+1-th row through the first adapter electrode; the third initial signal line in the i-th row is electrically connected to the plurality of third initial signal electrodes in the i-1-th row through the second adapter electrode, and the third initial signal line in the i+2-th row is electrically connected to the plurality of third initial signal electrodes in the i+1-th row through the second adapter electrode;

[0045] The light-emitting control electrode and the third initial signal electrode are located in the second sub-region. In the column direction, the light-emitting control line and the third initial signal line electrically connected to the first sub-pixel row bypass one side of the fourth sub-region. In the same row of sub-pixels, the orthographic projections of the light-emitting control line and the third initial signal line on the substrate at least partially overlap, and the orthographic projections of the light-emitting control electrode and the third initial signal electrode on the substrate at least partially overlap.

[0046] In a second aspect, an embodiment of the present disclosure further provides a display device, comprising the display substrate described in any of the above embodiments and a sensor located on the non-display surface side of the display substrate, wherein the display substrate includes a first display area, and the sensor's orthographic projection on the display substrate at least partially overlaps with the first display area of ​​the display substrate.

[0047] In a third aspect, embodiments of the present disclosure further provide a method for driving a display substrate, configured to drive the display substrate described in any of the above embodiments, wherein the display substrate includes K rows of sub-pixels and a plurality of signal lines extending in a row direction, wherein the number of the same signal lines is a positive integer less than or equal to K, and each row of sub-pixels is electrically connected to one of the same signal lines; the driving method comprises:

[0048] At least some of the at least one signal line provide effective signals to at least two rows of sub-pixels.

[0049] In an exemplary embodiment, at least some of the at least one signal line provide effective signals to two adjacent rows of sub-pixels at the same time.

[0050] In an exemplary embodiment, the at least one signal line includes a first type signal line, and the first type signal line includes at least one of a first reset control line and a first initial signal line;

[0051] Among the first type of signal lines, two adjacent signal lines of the same type, one signal line is configured to simultaneously provide valid signals to the sub-pixels in the i-th row and the sub-pixels in the i+1-th row, and the other signal line is configured to simultaneously provide valid signals to the sub-pixels in the i+2-th row and the sub-pixels in the i+3-th row, where i is an integer greater than or equal to 1 and less than K.

[0052] In an exemplary embodiment, the at least one signal line includes a second type signal line, and the second type signal line includes one or more of a second reset control line, a second initial signal line, a third initial signal line, a light emitting control line, and a second scan line;

[0053] Among the second type of signal lines, two adjacent signal lines of the same type, one signal line is configured to simultaneously provide valid signals to the sub-pixels in the i-1th row and the sub-pixels in the i-th row, and the other signal line is configured to simultaneously provide valid signals to the sub-pixels in the i+1th row and the sub-pixels in the i+2th row, where i is an integer greater than 1 and less than K.

[0054] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of each component in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0056] FIG1 is a schematic structural diagram of a display substrate;

[0057] FIG2 shows an equivalent circuit diagram of a pixel circuit;

[0058] FIG3 is a timing diagram showing the operation of the pixel circuit provided in FIG2 ;

[0059] FIG4A is a schematic diagram showing a planar structure of a display substrate provided by an exemplary embodiment of the present disclosure;

[0060] FIG4B is a schematic diagram showing a planar structure of a display substrate provided by an exemplary embodiment of the present disclosure;

[0061] FIG4C is a partial enlarged schematic diagram of FIG4b;

[0062] FIG4D is a partially enlarged schematic diagram showing an exemplary embodiment of the present disclosure for forming an anode layer;

[0063] FIG5A is a schematic diagram showing a planar structure of a display substrate provided by an exemplary embodiment of the present disclosure;

[0064] FIG5B is a schematic diagram showing a planar structure of a display substrate provided by an exemplary embodiment of the present disclosure;

[0065] FIG5C is a partial enlarged schematic diagram showing the fourth conductive layer formed in FIG5B;

[0066] FIG6A is a schematic diagram showing a planar structure of a display substrate provided by an exemplary embodiment of the present disclosure;

[0067] FIG6B is a schematic diagram showing a planar structure of a display substrate provided by an exemplary embodiment of the present disclosure;

[0068] FIG6C is a partial enlarged schematic diagram showing the fourth conductive layer formed in FIG6B;

[0069] FIG7A is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a first semiconductor layer is formed;

[0070] FIG7B is a partial enlarged schematic diagram of FIG7A ;

[0071] FIG8A is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a first conductive layer is formed;

[0072] FIG8B is a schematic diagram showing a planar structure of the first conductive layer in FIG8A ;

[0073] FIG8C is a partial enlarged schematic diagram of FIG8A ;

[0074] FIG9A is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a second conductive layer is formed;

[0075] FIG9B is a schematic diagram showing a planar structure of the second conductive layer in FIG9A ;

[0076] FIG9C is a partial enlarged schematic diagram of FIG9A ;

[0077] FIG10A is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a second semiconductor layer is formed;

[0078] FIG10B is a schematic diagram showing a planar structure of the second conductive layer in FIG10A ;

[0079] FIG10C is a partial enlarged schematic diagram of FIG10A ;

[0080] FIG11A is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a third conductive layer is formed;

[0081] FIG11B is a schematic diagram showing a planar structure of the third conductive layer in FIG11A ;

[0082] FIG11C is a partial enlarged schematic diagram of FIG11A ;

[0083] FIG12A is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a fifth insulating layer is formed;

[0084] FIG12B is a partial enlarged schematic diagram of FIG12A;

[0085] FIG13A is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a fourth conductive layer is formed;

[0086] FIG13B is a schematic diagram showing a planar structure of the fourth conductive layer in FIG13A ;

[0087] FIG13C is a partial enlarged schematic diagram of FIG13A;

[0088] FIG13D is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a fourth conductive layer is formed;

[0089] FIG13E is a schematic diagram showing a planar structure of the fourth conductive layer in FIG13D ;

[0090] FIG13F is a partial enlarged schematic diagram of FIG13D;

[0091] FIG14A is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a seventh insulating layer is formed;

[0092] FIG14B is a partial enlarged schematic diagram of FIG14A;

[0093] FIG15A is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a fifth conductive layer is formed;

[0094] FIG15B is a schematic diagram showing a planar structure of the fifth conductive layer in FIG15A ;

[0095] FIG15C is a partial enlarged schematic diagram of FIG15A;

[0096] FIG16A is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after an eighth insulating layer is formed;

[0097] FIG. 16B is a partial enlarged schematic diagram of FIG. 16A

[0098] FIG17A is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a sixth conductive layer is formed;

[0099] FIG17B is a schematic diagram showing a planar structure of the sixth conductive layer in FIG17A ;

[0100] FIG17C is a partial enlarged schematic diagram of FIG17A;

[0101] FIG18A is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a ninth insulating layer is formed;

[0102] FIG18B is a partial enlarged schematic diagram of FIG18A;

[0103] FIG19A is a schematic diagram showing a display substrate after an anode layer is formed, provided by an exemplary embodiment of the present disclosure;

[0104] FIG19B is a schematic diagram showing the planar structure of the anode layer in FIG19A ;

[0105] FIG19C is a partial enlarged schematic diagram of FIG19A;

[0106] FIG20A is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a pixel definition layer is formed;

[0107] FIG20B is a schematic diagram showing a planar structure of the pixel definition layer in FIG20A ;

[0108] FIG20C is a partial enlarged schematic diagram of FIG19A;

[0109] FIG21A is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a first conductive layer is formed;

[0110] FIG21B is a schematic diagram showing a planar structure of the first conductive layer in FIG21A ;

[0111] FIG21C is a partial enlarged schematic diagram of FIG21A ;

[0112] FIG22A is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a third conductive layer is formed;

[0113] FIG22B is a schematic diagram showing a planar structure of the third conductive layer in FIG22A ;

[0114] FIG22C is a partial enlarged schematic diagram of FIG22A ;

[0115] FIG23A is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a fifth insulating layer is formed;

[0116] FIG23B is a partial enlarged schematic diagram of FIG23A;

[0117] FIG24A is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a fourth conductive layer is formed;

[0118] FIG24B is a schematic diagram showing a planar structure of the fourth conductive layer in FIG24A ;

[0119] FIG24C is a partial enlarged schematic diagram of FIG24A;

[0120] FIG25A is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a second conductive layer is formed;

[0121] FIG25B is a schematic diagram showing a planar structure of the second conductive layer in FIG25A ;

[0122] FIG25C is a partial enlarged schematic diagram of FIG25A;

[0123] FIG26A is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a third conductive layer is formed;

[0124] FIG26B is a schematic diagram showing a planar structure of the third conductive layer in FIG26A ;

[0125] FIG26C is a partial enlarged schematic diagram of FIG26A ;

[0126] FIG27A is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a fifth insulating layer is formed;

[0127] FIG27B is a partial enlarged schematic diagram of FIG27A;

[0128] FIG28A is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a fourth conductive layer is formed;

[0129] FIG28B is a schematic diagram showing a planar structure of the fourth conductive layer in FIG28A ;

[0130] FIG28C is a partial enlarged schematic diagram of FIG28A ;

[0131] FIG29 is a schematic diagram of a display device provided by an exemplary embodiment of the present disclosure;

[0132] FIG30 is a flow chart showing a display substrate driving method provided by an exemplary embodiment of the present disclosure;

[0133] FIG31 is a timing diagram showing an operation of a driving display substrate provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0134] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a number of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0135] The scales of the figures in this disclosure are intended to serve as a reference for actual processes, but are not intended to be limiting. For example, the thickness and spacing of each film layer, and the width and spacing of each signal line, can be adjusted based on actual conditions. The figures described in this disclosure are merely schematic diagrams of the structures, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0136] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0137] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0138] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0139] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0140] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In cases where transistors with opposite polarities are used or the direction of current changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchangeable. Therefore, in this specification, "source electrode" and "drain electrode" can be interchangeable, and "source terminal" and "drain terminal" can be interchangeable. In the disclosed embodiments, the gate electrode can be referred to as the control electrode.

[0141] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0142] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0143] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0144] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0145] The term "about" in the embodiments of the present disclosure does not strictly define the limits and allows for numerical values ​​within the range of process and measurement errors.

[0146] Figure 1 is a schematic diagram of a planar structure of a display substrate. In some examples, as shown in Figure 1, the display substrate may include: a display area AA and a peripheral area BB located outside the display area AA. The display area AA of the display substrate may include at least: a first display area A1 and a second display area A2. The second display area A2 may at least partially surround the first display area A1. For example, the second display area A2 may surround the first display area A1. The peripheral area BB may surround the second display area A2. However, this embodiment is not limited to this.

[0147] In some examples, as shown in Figure 1, the first display area A1 may be a light-transmitting display area, and may also be referred to as an under-screen camera (FDC, Full Display With Camera) area. The second display area A2 may be referred to as a normal display area. For example, the orthographic projection of a sensor (such as a camera or other hardware) on the display substrate may be located within the first display area A1 of the display substrate. In some examples, as shown in Figure 1, the first display area A1 may be circular, and the size of the orthographic projection of the sensor on the display substrate may be less than or equal to the size of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area A1 may be rectangular, and the size of the orthographic projection of the sensor on the display substrate may be less than or equal to the size of the inscribed circle of the first display area A1.

[0148] In some examples, as shown in FIG1 , the first display area A1 can be located at the top center of the display area AA. The second display area A2 can surround the first display area A1. However, this embodiment is not limited to this. For example, the first display area A1 can be located at other locations, such as the upper left corner, lower left corner, lower right corner, or upper right corner of the display area AA. For example, the second display area A2 can surround at least one side of the first display area A1.

[0149] In some examples, as shown in FIG1 , the display area AA may be a rectangle, such as a rounded rectangle. The first display area A1 may be circular or elliptical. However, this embodiment is not limited thereto. For example, the first display area A1 may be a rectangle, a semicircle, a pentagon, or other shapes.

[0150] In some examples, the display area AA may be provided with a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a pixel circuit and a light-emitting element. The pixel circuit may be configured to drive the connected light-emitting element. For example, the pixel circuit may be configured to provide a driving current to drive the light-emitting element to emit light. The pixel circuit may include a plurality of transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0151] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, which may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The light-emitting color of the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0152] Figure 2 is a schematic diagram of the structure of a pixel drive circuit. Figure 2 uses 8T1C as an example. As shown in Figure 2, the pixel drive circuit can be connected to 11 signal lines (data line Data, first scan line Gate1, second scan line Gate2, first reset line Reset1, second reset line Reset2, light-emitting line E, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, first power line VDD, and second power line VSS). Among them, the gate lines include: first scan line Gate1, second scan line Gate2, first reset line Reset1, second reset line Reset2, and light-emitting line E.

[0153] In an exemplary embodiment, as shown in FIG2 , a control electrode of the first transistor M1 is connected to the first reset line Reset1, a first electrode of the first transistor M1 is connected to the first initial signal line INIT1, and a second electrode of the first transistor is connected to a third node N3. A control electrode of the second transistor M2 is connected to the second scan line Gate2, a first electrode of the second transistor M2 is connected to the first node N1, and a second electrode of the second transistor M2 is connected to the third node N3. A control electrode of the third transistor M3 is connected to the first node N1, a first electrode of the third transistor M3 is connected to the second node N2, and a second electrode of the third transistor M3 is connected to the third node N3. A control electrode of the fourth transistor M4 is connected to the first scan line Gate1, a first electrode of the fourth transistor M4 is connected to the data line Data, and a second electrode of the fourth transistor M4 is connected to the second node N2. A control electrode of the fifth transistor M5 is connected to the emission line E, a first electrode of the fifth transistor M5 is connected to the first power line VDD, and a second electrode of the fifth transistor M5 is connected to the second node N2. A control electrode of the sixth transistor M6 is connected to the emission line E, a first electrode of the sixth transistor M6 is connected to the third node N3, and a second electrode of the sixth transistor M6 is connected to the fourth node N4. A control electrode of the seventh transistor M7 is connected to the second reset line Reset2, a first electrode of the seventh transistor M7 is connected to the second initial signal line INIT2, and a second electrode of the seventh transistor M7 is connected to the fourth node N4. A control electrode of the eighth transistor M8 is connected to the second reset line Reset2, a first electrode of the eighth transistor M8 is connected to the third initial signal line INIT3, and a second electrode of the eighth transistor M8 is connected to the second node N2. A first end of the capacitor C is connected to the first power supply line VDD, and a second end of the capacitor C is connected to the first node N1.

[0154] In an exemplary embodiment, a first electrode of the light emitting device is electrically connected to the fourth node N4, a second electrode of the light emitting device is connected to the second power line VSS,

[0155] In an exemplary embodiment, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously provided high level signal.

[0156] Transistors can be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0157] In an exemplary embodiment, the first transistor M1 to the eighth transistor M8 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor M1 to the eighth transistor M8 may include P-type transistors and N-type transistors.

[0158] In an exemplary embodiment, the first transistor M1 to the eighth transistor M8 may be low-temperature polysilicon thin-film transistors, or may be oxide thin-film transistors, or may be low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor is low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0159] In an exemplary embodiment, as shown in FIG. 2 , the second transistor M2 may be an N-type transistor, and the first transistor M1 and the third transistor M3 to the eighth transistor M8 may be P-type transistors.

[0160] FIG3 illustrates an operation process of the pixel driving circuit provided in FIG2. In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0161] The first phase P1 is called the first reset phase. The signal on the second reset line Reset2 is a low-level signal, and the signals on the first reset line Reset1, the first scan line Gate1, the second scan line Gate2, and the light-emitting line E are high-level signals. The signal on the second reset line Reset2 is a low-level signal, turning on the seventh transistor M7 and the eighth transistor M8. The signal on the second initial signal line INIT2 is supplied to the fourth node N4, initializing (resetting) the first electrode of the light-emitting device L and clearing the existing charge in the first electrode of the light-emitting device L. The signal on the third initial signal line INIT3 is supplied to the second node N2, initializing (resetting) the second node N2 and clearing the existing charge in the second node N2. During this phase, the third transistor M3 is turned on. The signal on the second scan line Gate2 is a high-level signal, turning on the second transistor M2. The signal of the second node N2 is provided to the first node N1 and the third node N3. The first node N1 and the third node N3 are initialized. The signals of the first reset line Reset1, the first scan line Gate1, and the light-emitting line E are high-level signals. The first transistor M1, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are turned off. At this stage, the light-emitting device L does not emit light.

[0162] The second phase P2, known as the second reset phase, is characterized by a low-level signal on the first reset line Reset1, while the signals on the second reset line Reset2, the first scan line Gate1, the second scan line Gate2, and the light-emitting line E are high-level signals. The low-level signal on the first reset line Reset1 causes the first transistor M1 and the signal on the first initial signal line INIT1 to be supplied to the third node N3, reinitializing (resetting) the third node N3 and clearing the existing charge in the third node N3. During this phase, the third transistor M3 remains on. The high-level signal on the second scan line Gate2 turns on the second transistor M2. The charge on the third node N3 is supplied to the first node N1, continuously initializing the first node N1. The high-level signals on the second reset line Reset2, the first scan line Gate1, and the light-emitting line E are all high-level signals. The fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are turned off. During this phase, the light-emitting device L does not emit light.

[0163] In the third phase P3, also known as the data writing phase or threshold compensation phase, the signal on the first scan line Gate1 is a low-level signal, while the signals on the first reset line Reset1, the second reset line Reset2, the second scan line Gate2, and the light-emitting line E are high-level signals. The data line Data outputs a data voltage. During this phase, the third transistor M3 is continuously turned on. The low-level signal on the first scan line Gate1 turns on the fourth transistor M4. The high-level signal on the second scan line Gate2 turns on the second transistor M2. The data voltage output by the data line Data is provided to the first node N1 through the turned-on fourth transistor M4, the second node N2, the turned-on third transistor M3, the third node N3, and the turned-on second transistor M2. The difference between the data voltage output by the data line Data and the threshold voltage of the third transistor M3 is charged into the capacitor C. The voltage at the second end of the capacitor C (the first node N1) is Vd-|Vth|, where Vd is the data voltage output by the data line Data and Vth is the threshold voltage of the third transistor M3. The signals of the first reset line Reset1, the second reset line Reset2 and the light emitting line E are high level signals, and the first transistor M1, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are turned off. In this stage, the light emitting device L does not emit light.

[0164] In the fourth phase P4, referred to as the continuous compensation phase, the signals on the first reset line Reset1, the second reset line Reset2, the first scan line Gate1, the second scan line Gate2, and the emission line E are high. The signal on the second scan line Gate2 is high, the second transistor M2 is continuously turned on, the signals on the first scan line Gate1, the first reset line Reset1, the second reset line Reset2, and the emission line E are high, and the first transistor M1, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are turned off. Although the signal on the data line Data stops being written, the signal from the second node N2 is still provided to the first node N1 via the turned-on third transistor M3, the third node N3, and the turned-on second transistor M2, continuously compensating for the threshold voltage of the third transistor M3.

[0165] The fifth stage P5, known as the bias stage, is characterized by the low-level signals on the second scan line Gate2 and the second reset line Reset2, and the high-level signals on the first reset line Reset1, the first scan line Gate1, and the light-emitting line E. The signal on the second scan line Gate2 is low, the signals on the first scan line Gate1, the first reset line Reset1, and the light-emitting line E are high, and the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are all turned off. The signal on the second reset line Reset2 is low, the seventh transistor M7 and the eighth transistor M8 are turned on, the signal on the third initial signal line INIT3 is written to the second node N2 and the third node N3, and the signal on the second initial signal line INIT2 is written to the fourth node N3. During this stage, the third transistor M3 is in a biased state, and the light-emitting device L does not emit light.

[0166] In the sixth phase P6, referred to as the light-emitting phase, the signals on the light-emitting line E and the second scan line Gate2 are low-level signals, while the signals on the first reset line Reset1, the second reset line Reset2, and the first scan line Gate1 are high-level signals. The signal on the light-emitting signal line E is low-level, turning on the fifth transistor M5 and the sixth transistor M6. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, the third transistor M3, and the sixth transistor M6, driving the light-emitting device L to emit light.

[0167] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor M3 is: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0168] Wherein, I is the driving current flowing through the third transistor M3, that is, the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output by the data line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0169] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor M3 is no longer affected by the threshold voltage of the third transistor M3, thereby eliminating the influence of the threshold voltage of the third transistor M3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0170] With the continuous development of display technology, cameras are usually installed on display devices to meet the needs of shooting or face recognition. In order to maximize the screen-to-body ratio, technologies such as bangs screen, water drop screen, and hollowing out in the screen have appeared one after another. These technologies are achieved by making holes in part of the display area and placing a camera below the hole area to reduce the area occupied by the camera, thereby increasing the screen-to-body ratio. However, the above technologies require digging out part of the display area, which will cause part of the display image to be unable to be displayed, and the screen-to-body ratio cannot be further increased. In order to avoid punching holes in the display area and to make a true full screen possible while ensuring the practicality of the display substrate, the pixel circuit external method or the pixel circuit internal method is usually adopted in the camera area under the screen.

[0171] The external pixel circuit method involves placing the pixel circuit connected to the light-emitting element in the under-screen camera area in the normal display area. By separating the light-emitting element and the pixel circuit, the light transmittance of the under-screen camera area is improved. Since the under-screen camera area does not have a pixel circuit, there is no other light-shielding layer in this area except for the anode of the light-emitting element, which can achieve a higher light transmittance. However, under this method, the pixel circuit and the light-emitting element need to be electrically connected via conductive connecting wires. Due to the limited arrangement space of the conductive connecting wires, the size (e.g., aperture) of the under-screen camera area of ​​the display substrate using the external pixel circuit method is limited. Increasing the aperture of the under-screen camera area usually requires increasing the masking process for the conductive connecting wires, resulting in increased costs. Moreover, the conductive connecting wires are usually made of transparent conductive materials, such as indium tin oxide (ITO). Due to the large square resistance of ITO, the conductive connecting wires are loaded heavily, which can easily affect the brightness of the light-emitting element in the under-screen camera area, reducing the brightness of the under-screen camera area, thereby causing poor display in the under-screen camera area, such as vertical display defect (mura).

[0172] The built-in pixel circuit method involves placing a light-emitting element and the pixel circuit connected to it in the under-screen camera area. Compared to the external pixel circuit method, the built-in method eliminates the need for long conductive wires to connect the pixel circuit and light-emitting element in the under-screen camera area, thus avoiding display issues in the under-screen camera area caused by these wires. Furthermore, the built-in method has no size restrictions for the under-screen camera area and can support large-aperture under-screen camera areas. However, in display substrates using the built-in pixel circuit method, the under-screen camera area has a large number of pixel circuit signal traces, making it difficult to avoid the light-transmitting area. Consequently, the transmittance of the under-screen camera area is affected.

[0173] The exemplary embodiments of the present disclosure provide a display substrate, which may include: a substrate, and K rows of sub-pixels disposed on the substrate, and a plurality of signal lines extending along a row direction; the number of the same signal lines may be multiple, and the multiple signal lines of the same type may be arranged at intervals along a column direction, and each row of sub-pixels is electrically connected to one of the same signal lines; on a plane parallel to the display substrate, the row direction intersects the column direction;

[0174] At least some of the at least one signal line can be configured to be electrically connected to at least two rows of sub-pixels. The number of the same signal lines in the at least one signal line is a positive integer less than K.

[0175] In a display substrate provided by an embodiment of the present disclosure, at least some of the signal lines in at least one type of signal line in the display substrate are configured to be electrically connected to at least two rows of sub-pixels, and the number of the same type of signal lines in at least one type of signal line is a positive integer less than K. Reducing the number of signal lines can improve the light transmittance of the display substrate.

[0176] As shown in FIG4A and FIG4B , the display substrate provided in the embodiment of the present disclosure may include a substrate, K rows of sub-pixels disposed on the substrate, and a plurality of signal lines extending along a row direction X. The number of the same signal lines may be multiple, and the multiple signal lines of the same type are arranged at intervals along a column direction Y. Each row of sub-pixels is electrically connected to one of the same signal lines. On a plane parallel to the display substrate, the row direction X intersects the column direction Y.

[0177] At least some of the at least one signal line, each signal line is configured to be electrically connected to at least two rows of sub-pixels, and the number of the same signal lines in the at least one signal line is a positive integer less than K.

[0178] In example embodiments, the row direction X may be referred to as a first direction, and the column direction Y may be referred to as a second direction.

[0179] In an exemplary embodiment, each signal line may be disposed to be electrically connected to at least one row of sub-pixels.

[0180] In an exemplary embodiment, at least some of the at least one signal line may be electrically connected to two adjacent rows of sub-pixels. The signal lines electrically connected to the two adjacent rows of sub-pixels can provide signals to the two adjacent rows of sub-pixels. This reduces the number of signal lines and the number of connections between the signal lines and the sub-pixel rows, thereby saving space on the display substrate and improving light transmittance.

[0181] In an exemplary embodiment, at least one signal line includes a first type signal line, and the first type signal line includes at least two adjacent signal lines of the same type. Among the two adjacent signal lines of the same type, one signal line can be set to be electrically connected to the i-th row of sub-pixels and the i+1-th row of sub-pixels, and the other signal line can be set to be electrically connected to the i+2-th row of sub-pixels and the i+3-th row of sub-pixels, where i is an integer greater than or equal to 1 and less than K.

[0182] In an exemplary embodiment, the types of signal lines in the first-type signal lines may include a first reset control line and / or a first initial signal line.

[0183] In an exemplary embodiment, as shown in FIG. 4A , the types of signal lines in the first type signal lines may include at least first reset control lines (eg, first reset control lines RST1(i) / RST1(i+1), RST1(i+2) / RST1(i+3)). A first reset control line can be configured to provide a first reset control signal to two adjacent rows of sub-pixels. That is, two adjacent rows of sub-pixels can share one first reset control line. For example, the i-th and i+1-th rows of sub-pixels can share one first reset control line RST1(i) / RST1(i+1), and the i+2-th and i+3-th rows of sub-pixels can share one first reset control line RST1(i+2) / RST1(i+3). In other words, the first reset control line RST1(i) / RST1(i+1) can provide the first reset control signal to the i-th and i+1-th rows of sub-pixels, and the first reset control line RST1(i+2) / RST1(i+3) can provide the first reset control signal to the i+2-th and i+3-th rows of sub-pixels. In the embodiment of the present disclosure, by providing the first reset control signal to two adjacent rows of sub-pixels through one first reset control line, the number of first reset control lines can be reduced, thereby reducing the space occupied by signal lines on the display substrate and improving the transmittance of the display substrate.

[0184] In an exemplary embodiment, the types of signal lines in the first type of signal lines as shown in FIG. 4B may include first initial signal lines (eg, first initial signal lines INIT1(i) / INIT1(i+1), INIT1(i+2) / INIT1(i+3)). A first initial signal line can be configured to provide a first initial signal to two adjacent rows of sub-pixels, that is, two adjacent rows of sub-pixels can share one first initial signal line. For example, the i-th row and the i+1-th row of sub-pixels can share one first initial signal line INIT1(i) / INIT1(i+1), and the i+2-th row and the i+3-th row of sub-pixels can share one first initial signal line INIT1(i+2) / INIT1(i+3). In other words, the first initial signal line INIT1(i) / INIT1(i+1) can provide the first initial signal to the i-th row and the i+1-th row of sub-pixels, and the first initial signal line INIT1(i+2) / INIT1(i+3) can provide the first initial signal to the i+2-th row and the i+3-th row of sub-pixels. In the embodiment of the present disclosure, by providing the first initial signal to two adjacent rows of sub-pixels through one first initial signal line, the number of first initial signal lines can be reduced, thereby reducing the space occupied by the signal lines on the display substrate and improving the transmittance of the display substrate.

[0185] In an exemplary embodiment, as shown in Figures 4A and 4B, the first initial signal line and the first reset control line may be located on different conductive layers. In the same row of sub-pixels, the orthographic projection of the first initial signal line on the substrate and the orthographic projection of the first reset control line on the substrate at least partially overlap. This can reduce the space occupied by the signal lines on the display substrate and improve the light transmittance of the display substrate. For example, the orthographic projections of the first initial signal line INIT1(i) / INIT1(i+1) and the first reset control line RST1(i) / RST1(i+1) on the substrate at least partially overlap.

[0186] In an exemplary embodiment, at least one signal line may further include a second type signal line, and the second type signal line may include at least two adjacent signal lines of the same type, wherein one of the two adjacent signal lines of the same type may be configured to be electrically connected to the i-1th row of sub-pixels and the i-th row of sub-pixels, and the other signal line may be configured to be electrically connected to the i+1th row of sub-pixels and the i+2th row of sub-pixels, where i is greater than 1.

[0187] In an exemplary embodiment, as shown in Figures 4A and 4B, the types of signal lines in the second type signal lines may include a second reset control line (e.g., a second reset control RST2(i-1) / RST2(i), RST2(i+1) / RST2(i+2), RST2(i+3) / RST2(i+4)) and / or a second initial signal line (e.g., a second initial signal line INIT2(i-1) / INIT2(i), INIT2(i+1) / INIT2(i+2), INIT2(i+3) / INIT2(i+4)).

[0188] In an exemplary embodiment, a second reset control line can be configured to provide a second reset signal to two adjacent rows of sub-pixels. That is, two adjacent rows of sub-pixels can share a second reset control line. For example, the i-1th and i-th rows of sub-pixels can share a second reset control line RST2(i-1) / RST2(i), and the i+1th and i+2th rows of sub-pixels can share a second reset control line RST1(i+1) / RST1(i+2). In other words, the second reset control line RST2(i-1) / RST2(i) can provide the second reset control signal to the i-1th and i-th rows of sub-pixels, and the second reset control line RST1(i+1) / RST1(i+2) can provide the second reset control signal to the i+1th and i+2th rows of sub-pixels. In the disclosed embodiment, by providing the second reset control signal to two adjacent rows of sub-pixels through a single second reset control line, the number of second reset control lines can be reduced, thereby reducing the space occupied by signal lines on the display substrate and improving the light transmittance of the display substrate.

[0189] In an exemplary embodiment, a second initial signal line can be configured to provide a second initial signal to two adjacent rows of sub-pixels. That is, two adjacent rows of sub-pixels can share a second initial signal line. For example, the i-1th and i-th rows of sub-pixels can share a second initial signal line INIT2(i-1) / INIT2(i), and the i+1th and i+2th rows of sub-pixels can share a second initial signal line INIT2(i+1) / INIT2(i+2). In other words, the second initial signal line INIT2(i-1) / INIT2(i) can provide the second initial signal to the i-1th and i-th rows of sub-pixels, and the second initial signal line INIT2(i+1) / INIT2(i+2) can provide the second initial signal to the i+1th and i+2th rows of sub-pixels. In the disclosed embodiment, by providing the second initial signal to two adjacent rows of sub-pixels through a single second initial signal line, the number of second initial signal lines can be reduced, thereby reducing the space occupied by the signal lines on the display substrate and improving the light transmittance of the display substrate.

[0190] In an exemplary embodiment, the second reset control line and the second initial signal line are located in different conductive layers. In the same row of sub-pixels, the orthographic projection of the second reset control line on the substrate at least partially overlaps with the orthographic projection of the second initial signal line on the substrate. This can reduce the space occupied by the signal lines on the display substrate and improve the light transmittance of the display substrate. For example, the orthographic projections of the second initial signal lines INIT1(i+1) / INIT1(i+2) and the second reset control lines RST1(i+1) / RST1(i+2) on the substrate at least partially overlap. In an exemplary embodiment, as shown in Figures 5A to 5C, the types of signal lines in the second type of signal lines can also include second scan lines (e.g., second scan lines GL2(i) and GL2(i+2)). In an exemplary embodiment, a second scan line can be configured to provide a second scan signal to two adjacent rows of sub-pixels. That is, two adjacent rows of sub-pixels can share one second scan line. For example, the sub-pixels in the i-1th and i-th rows can share one second scan line GL2(i), and the sub-pixels in the i+1th and i+2th rows can share one second scan line GL2(i+2). In other words, the second scan line GL2(i) can provide a second scan signal to the sub-pixels in the i-1th and i-th rows, and the second scan line GL2(i+2) can provide a second scan signal to the sub-pixels in the i+1th and i+2th rows. In the disclosed embodiment, by providing the second scan signal to two adjacent rows of sub-pixels through one second scan line, the number of second scan lines can be reduced, thereby reducing the space occupied by the signal lines on the display substrate and improving the light transmittance of the display substrate.

[0191] In an exemplary embodiment, as shown in Figures 5A to 5C , the second-type signal lines may further include second scan auxiliary lines (for example, the second scan auxiliary lines may include GL2b(i) and GL2b(i+2)). In the same row of sub-pixels, the orthographic projections of the second scan lines on the substrate at least partially overlap with those of the second scan lines. This can reduce the space occupied by the signal lines on the display substrate and improve the light transmittance of the display substrate. For example, the orthographic projections of the second scan auxiliary lines GL2b(i) and the second scan lines GL2(i) on the substrate may at least partially overlap.

[0192] In an exemplary embodiment, as shown in Figures 6A to 6C, the types of signal lines in the second type signal lines may also include at least one of a third initial signal line (for example, a third initial signal line INIT3(i), INIT3(i+2)), and a light-emitting control line (for example, a light-emitting control line EML(i), EML(i+2)).

[0193] In an exemplary embodiment, a third initial signal line can be configured to provide a third initial signal to two adjacent rows of sub-pixels. That is, two adjacent rows of sub-pixels can share one third initial signal line. For example, the i-1th and i-th rows of sub-pixels can share one third initial signal line INIT3(i), and the i+1th and i+2th rows of sub-pixels can share one third initial signal line INIT3(i+2). In other words, the third initial signal line INIT3(i) can provide the third initial signal to the i-1th and i-th rows of sub-pixels, and the third initial signal line INIT3(i+2) can provide the third initial signal to the i+1th and i+2th rows of sub-pixels. In the disclosed embodiment, by providing the third initial signal to two adjacent rows of sub-pixels through one third initial signal line, the number of third initial signal lines can be reduced, thereby reducing the space occupied by the signal lines on the display substrate and improving the light transmittance of the display substrate.

[0194] In an exemplary embodiment, a single emission control line can be configured to provide a third initial signal to two adjacent rows of sub-pixels. That is, two adjacent rows of sub-pixels can share a single emission control line. For example, the sub-pixels in the i-1th and i-th rows can share a single emission control line EML(i), and the sub-pixels in the i+1th and i+2th rows can share a single emission control line EML(i+2). In other words, the emission control line EML(i) can provide emission control signals to the sub-pixels in the i-1th and i-th rows, and the emission control line EML(i+2) can provide emission control signals to the sub-pixels in the i+1th and i+2th rows. In the disclosed embodiment, by providing emission control signals to two adjacent rows of sub-pixels through a single emission control line, the number of emission control signal lines can be reduced, thereby reducing the space occupied by the signal lines on the display substrate and improving the light transmittance of the display substrate.

[0195] In an exemplary embodiment, as shown in Figures 6A to 6C , the emission control line and the third initial signal line may be located on different conductive layers. Within the same row of sub-pixels, the orthographic projection of the emission control line on the substrate at least partially overlaps with the orthographic projection of the third initial signal line on the substrate. This can reduce the space occupied by the signal lines on the display substrate and improve the light transmittance of the display substrate. For example, the orthographic projection of the emission control line EML(i) on the substrate at least partially overlaps with the orthographic projection of the third initial signal line INIT3(i) on the substrate.

[0196] In an exemplary embodiment, as shown in Figures 4A to 4D, K rows of sub-pixel rows may include a plurality of first sub-pixel rows RL1 and a plurality of second sub-pixel rows RL2, the first sub-pixel rows RL1 and the second sub-pixel rows RL2 may be alternately arranged along the column direction Y, and at least part of the at least one signal line, each signal line is configured to be electrically connected to a first sub-pixel row RL1 and a second sub-pixel row RL2 adjacent to it.

[0197] In an exemplary embodiment, as shown in FIG. 4A to FIG. 6C , each row of sub-pixels may include a plurality of sub-pixels sequentially arranged along a row direction X, the plurality of sub-pixels forming a plurality of pixel units P, and at least some of the pixel units P may include at least three sub-pixels sequentially arranged along the row direction X;

[0198] The display substrate may include a first display area A1 (as shown in Figure 1), and the first display area A1 may include multiple first sub-areas K1, multiple second sub-areas K2, multiple third sub-areas K3 and multiple fourth sub-areas K4. The first sub-areas K1 and the third sub-areas K3 are alternately arranged along the row direction X, and the second sub-areas K2 and the fourth sub-areas K4 are alternately arranged along the row direction X. The multiple pixel units P in the first sub-pixel row RL1 are respectively located in the multiple first sub-areas K1, and the multiple pixel units P in the second sub-pixel row RL2 are respectively located in the multiple second sub-areas K2. The multiple pixel units P located in the first sub-pixel row RL1 are spaced apart by the third sub-area K3, and the multiple pixel units P located in the second sub-pixel row RL2 are spaced apart by the fourth sub-area K4. No pixel units are set in the third sub-area K3 and the fourth sub-area K4, which can improve the transmittance.

[0199] In an exemplary embodiment, as shown in Figure 4C, which is an enlarged structural diagram of the adjacent first sub-region K1 to the fourth sub-region in Figure 4B, at least some of the sub-pixels may include a first pixel circuit, and at least some of the pixel units P may include four sub-pixels (for example, first pixel circuits 11a, 11b, 11c, and 11d) arranged in sequence along the row direction X; in the same pixel unit P, the four first pixel circuits are symmetrically arranged about a first center line O1 extending along the column direction Y of the four first pixel circuits, the first first pixel circuit 11a and the second first pixel circuit 11b of the four first pixel circuits are symmetrically arranged about a second center line O2 extending along the column direction Y between the two first pixel circuits, and the third first pixel circuit 11c and the fourth first pixel circuit 11d are symmetrically arranged about a third center line O3 extending along the column direction Y between the two first pixel circuits.

[0200] In an exemplary embodiment, as shown in FIG. 4A and FIG. 4B , the plurality of first sub-regions K1 form a plurality of columns of first sub-regions K1 , and the plurality of second sub-regions K2 form a plurality of columns of second sub-regions K2 . In the column direction Y, the first sub-regions K1 and the second sub-regions K2 are staggered.

[0201] The third first pixel circuit 11c and the fourth first pixel circuit 11d of the four first pixel circuits in the pixel unit P located in the first sub-area K1 are respectively located in the same column as the first first pixel circuit 11a and the second first pixel circuit 11b of the four first pixel circuits in the pixel unit located in the adjacent second sub-area K2.

[0202] In an exemplary embodiment, as shown in FIG4D , the pixel unit P may further include four light-emitting elements, which are electrically connected to four first pixel circuits (e.g., first pixel circuits 11a, 11b, 11c, and 11d) in the pixel unit P, respectively. The light-emitting elements include anodes (e.g., anodes 211a, 211b, 211c, and 211d). In the same pixel unit P, the orthographic projections of the anodes of the four light-emitting elements (e.g., anodes 211a, 211b, 211c, and 211d) on the substrate at least partially do not overlap with the orthographic projections of the third sub-region K3 and the fourth sub-region K4 on the substrate, thereby improving the transmittance of the display substrate. In the first sub-pixel row RL1, the orthographic projections of the anodes of the four light-emitting elements on the substrate at least partially overlap with the orthographic projection of the first sub-region K1 on the substrate. In the second sub-pixel row RL2, the orthographic projections of the anodes of the four light-emitting elements on the substrate at least partially overlap with the second sub-region K2. In an exemplary embodiment, an orthographic projection of an anode of any one of the light-emitting elements and a first pixel circuit electrically connected to the anode on the substrate may at least partially overlap.

[0203] In an exemplary embodiment, as shown in FIG4C , at least a portion of the first pixel circuit may include a first transistor (eg, first transistors 31 a , 31 b ) to an eighth transistor (eg, eighth transistors 38 a , 38 b );

[0204] In a first pixel circuit in a first subpixel row RL1 located in the i-th row, in a column direction Y, the first transistor, the second transistor, and the fourth transistor are located on a side of the third transistor close to the second subpixel row RL2 located in the (i+1)th row, and the second transistor is located between the first transistor and the third transistor; the fifth to eighth transistors are located on a side of the third transistor close to the second subpixel row RL2 located in the (i-1)th row, and the sixth transistor is located between the third transistor and the seventh transistor; wherein i is a positive integer greater than 1 and less than K;

[0205] In the first pixel circuit in the second sub-pixel row RL2 located in the i+1th row, the first transistor, the second transistor and the fourth transistor are located on a side of the third transistor close to the first sub-pixel row RL1 located in the i+1th row, and the second transistor is located between the first transistor and the third transistor; the fifth transistor to the eighth transistor are located on a side of the third transistor close to the first sub-pixel row RL1 located in the i+2th row, and the sixth transistor is located between the third transistor and the seventh transistor.

[0206] In an exemplary embodiment, in a direction perpendicular to a plane on which the display substrate is located, the display substrate may include: a circuit structure layer located on a substrate; the circuit structure layer includes a plurality of first pixel circuits; at least some of the plurality of first pixel circuits may include: at least one first-type transistor, at least one second-type transistor, and a storage capacitor; the first-type transistors include at least a first transistor and third to eighth transistors, and the second-type transistors include at least a second transistor;

[0207] The circuit structure layer includes: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, and a third conductive layer arranged on a substrate; the first semiconductor layer includes at least: an active layer of a first type transistor of a pixel circuit; the first conductive layer includes at least: a gate of the first type transistor of a pixel circuit, and a first electrode of a storage capacitor; the second conductive layer includes at least: a second electrode of the storage capacitor of the pixel circuit; the second semiconductor layer includes at least: an active layer of a second type transistor of a pixel circuit; and the third conductive layer includes at least: a gate of the second type transistor of a pixel circuit.

[0208] In an exemplary embodiment, the first type transistor may be a P-type transistor, and the second type transistor may be an N-type transistor.

[0209] In an exemplary embodiment, as shown in FIG4A , the first conductive layer may further include: a first scan line (e.g., first scan lines GL1(i), GL1(i+1), GL1(i+2), GL1(i+3)) electrically connected to the first type of transistor in the first pixel circuit; a light emission control line (e.g., light emission control lines EML(i), EML(i+1), EML(i+2), EML(i+3)); a first reset control line (e.g., first reset control lines RST1(i) / RST1(i+1), RST1(i+2) / RST1(i+3)); and a second reset control line (e.g., second reset control lines RST2(i-1) / RST2(i), RST2(i+1) / RST2(i+2), RST2(i+3) / RST2(i+4)); the first scan line, the light emission control line, the first reset control line, and the second reset control line may extend along the row direction X;

[0210] In the column direction Y, the first scan line and the first reset control line electrically connected to the first sub-pixel row RL1 bypass one side of the third sub-region K3, and the light-emitting control line electrically connected to the first sub-pixel row RL1 bypasses the other side of the third sub-region K2, avoiding blocking the third sub-region and improving the transmittance of the display substrate; the first scan line electrically connected to the second sub-pixel row RL2 bypasses one side of the fourth sub-region K4, and the light-emitting control line and the second reset control line electrically connected to the second sub-pixel row RL2 bypass the other side of the fourth sub-region K4, avoiding blocking the fourth sub-region K4 and improving the transmittance of the display substrate.

[0211] In an exemplary embodiment, as shown in FIG4B , the third conductive layer may further include a first initial signal line electrically connected to the first transistor in the first pixel circuit (e.g., first initial signal lines INIT1(i) / INIT1(i+1), INIT1(i+2) / INIT1(i+3)), a second initial signal line electrically connected to the seventh transistor in the first pixel circuit (e.g., second initial signal lines INIT2(i-1) / INIT2(i), INIT2(i+1) / INIT2(i+2), INIT2(i+3) / INIT2(i+4)), and a third initial signal line electrically connected to the eighth transistor (e.g., third initial signal lines INIT3(i), INIT3(i+1), INIT3(i+2), INIT3(i+3)). The first initial signal line, the second initial signal line, and the third initial signal line may extend along the row direction X.

[0212] In the same row of sub-pixels, the orthographic projection of the first initial signal line on the substrate at least partially overlaps with the orthographic projection of the first reset control line on the substrate, the orthographic projection of the second initial signal line on the substrate at least partially overlaps with the orthographic projection of the second reset control line on the substrate, and the orthographic projection of the third initial signal line on the substrate at least partially overlaps with the orthographic projection of the light-emitting control line on the substrate. This can reduce the space occupied by the signal lines on the display substrate and improve the transmittance of the display substrate.

[0213] In an exemplary embodiment, as shown in FIG4A and FIG4B , at a position adjacent to the first subregion K1 of the first subpixel row RL1 in the i-th row and the second subregion K2 of the second subpixel row RL2 in the (i-1)th row, the second reset control line and the second initial signal line may be ring structures (e.g., the ring structure RST20 in the second reset control line and the ring structure INIT20 in the second initial signal line). In the column direction Y, a side of the ring structure (e.g., the ring structure RST20 and the ring structure INIT20) close to the first subregion K1 overlaps with the orthographic projections of the seventh transistor and the eighth transistor in the third to fourth first pixel circuits (e.g., 11 c and 11 d) in the first subregion K1 on the substrate. A side of the ring structure (e.g., the ring structure RST20 and the ring structure INIT20) close to the second subregion K2 overlaps with the orthographic projections of the seventh transistor and the eighth transistor in the first to second first pixel circuits (e.g., the first pixel circuits 11 a and 11 b) in the second subregion K2 on the substrate.

[0214] At a position adjacent to the first sub-region K1 of the first sub-pixel row RL1 in the i-th row and the second sub-region K2 of the second sub-pixel row RL2 in the (i+1)-th row, the first reset control line and the first initial signal line may be a ring structure (for example, the ring structure RST10 in the first reset control line and the ring structure INIT10 in the first initial signal line). In the column direction Y, a side of the ring structure (for example, the ring structure RST10, the ring structure INIT10) close to the first sub-region K1 overlaps with the orthographic projections of the first transistors (31a, 31b) in the third to fourth first pixel circuits (for example, the first pixel circuits 11c, 11d) in the first sub-region K1 on the substrate, and a side of the ring structure (for example, the ring structure RST10, the ring structure INIT10) close to the second sub-region K2 overlaps with the orthographic projections of the first transistors (31a, 31b) in the first to second first pixel circuits (for example, the first pixel circuits 11a, 11b) in the second sub-region K2 on the substrate.

[0215] In an exemplary embodiment, as shown in FIG4A and FIG4B , the second conductive layer may further include a second auxiliary scan line (e.g., second auxiliary scan lines GL2b(i), GL2b(i+1), GL2b(i+2), and GL2b(i+3)) electrically connected to the second transistor in the first pixel circuit; the third conductive layer may further include a second scan line (e.g., second scan lines GL2(i), GL2(i+1), GL2(i+2), and GL2(i+3)) electrically connected to the second transistor in the first pixel circuit; the orthographic projection of the second auxiliary scan line on the substrate at least partially overlaps with that of the second scan line in the same row of sub-pixels; the second auxiliary scan line and the second scan line extend along the row direction X;

[0216] In the column direction Y, the second scan line and the second scan auxiliary line electrically connected to the first sub-pixel row RL1 bypass one side of the third sub-region K3, and the second scan line and the second scan auxiliary line electrically connected to the second sub-pixel row RL2 bypass one side of the fourth sub-region K4, thereby avoiding blocking the third sub-region K3 and the fourth sub-region K4 and improving the transmittance of the display substrate; the direction in which the second scan line and the second scan auxiliary line electrically connected to the first sub-pixel row RL1 bypass the third sub-region K3 is opposite to the direction in which the second scan line and the second scan auxiliary line electrically connected to the second sub-pixel row RL2 bypass the fourth sub-region K4.

[0217] In an exemplary embodiment, as shown in FIG5A to FIG5C , FIG5A is a schematic diagram of a planar structure after forming a second conductive layer, FIG5B is a schematic diagram of a planar structure after forming a third conductive layer, and FIG5C is an enlarged schematic diagram of a structure after forming a fourth conductive layer in the first sub-region K1 to the fourth sub-region K4 in FIG5B . The display substrate may further include a fourth conductive layer, and the fourth conductive layer includes a fourth transfer electrode ZL4; the fourth transfer electrode extends along the column direction Y;

[0218] The second conductive layer may further include a plurality of second scan auxiliary lines (e.g., second scan auxiliary lines GL2b(i), GL2b(i+2)) electrically connected to the second transistor in the first pixel circuit and a plurality of second scan auxiliary electrodes (e.g., second scan auxiliary electrodes GL2b0(i+1), GL2b0(i+3)). The third conductive layer may further include a plurality of second scan lines (e.g., second scan lines GL2(i), GL2(i+2)) electrically connected to the second transistor in the first pixel circuit and a plurality of second scan electrodes (e.g., second scan electrodes GL20(i+1), GL20(i+3)). In the same row of sub-pixels, the orthographic projections of the second scan auxiliary lines and the second scan lines on the substrate at least partially overlap, and the orthographic projections of the second scan electrodes and the second scan auxiliary electrodes on the substrate at least partially overlap. The second scan auxiliary electrodes, the second scan electrodes, the second scan auxiliary lines and the second scan lines extend along the row direction X.

[0219] A plurality of second scan auxiliary electrodes and a plurality of second scan electrodes are electrically connected to a plurality of pixel units P in the second sub-pixel row RL2, respectively; a plurality of second scan auxiliary lines and a plurality of second scan lines are electrically connected to a plurality of first pixel circuits in the first sub-pixel row RL1; the second scan auxiliary line and the second scan line located in the i-th row are electrically connected to the plurality of second scan auxiliary electrodes and the plurality of second scan electrodes located in the i-1th row through the fourth switching electrode ZL4, and the second scan auxiliary line and the second scan line located in the i+2th row are electrically connected to the plurality of second scan auxiliary electrodes and the plurality of second scan electrodes located in the i+1th row through the fourth switching electrode; thereby, the second scan auxiliary line GL2b(i) and the second scan line GL2(i) located in the i-th row can provide signals to the sub-pixels in the i-th row and the i+1th row, and the second scan auxiliary line GL2(i+2) and the second scan line GL2(i+2) located in the i+2th row can provide signals to the sub-pixels in the i+2th row and the i+3th row, thereby reducing the space occupied by the signal lines on the display substrate and improving the transmittance of the display substrate;

[0220] In the column direction Y, the second scan line and the second scan auxiliary line electrically connected to the first sub-pixel row RL1 bypass one side of the fourth sub-region K4; the multiple second scan electrodes and multiple second scan auxiliary electrodes electrically connected to the second sub-pixel row RL2 are respectively located in the multiple second sub-regions K2.

[0221] In an exemplary embodiment, in the schemes of Figures 5A to 5C, signals are provided to two rows of first pixel circuits through a second scanning auxiliary line, and scanning signals are provided to two rows of first pixel circuits through a second scanning line. This can reduce the number of signal lines, save space on the display substrate, and improve the transmittance of the display substrate (the transmittance of the third sub-area and the fourth sub-area can be improved).

[0222] In an exemplary embodiment, as shown in FIG6A and FIG6B , FIG6A is a schematic diagram of a planar structure after forming a second conductive layer, FIG6B is a schematic diagram of a planar structure after forming a third conductive layer, and FIG6C is an enlarged schematic diagram of a structure after forming a fourth conductive layer in the first sub-region K1 to the fourth sub-region K4 in FIG6B . The display substrate may further include a fourth conductive layer located on a side of the third conductive layer away from the substrate, the fourth conductive layer including a plurality of first transfer electrodes ZL1 and a plurality of second transfer electrodes ZL2; the first transfer electrodes ZL1 and the second transfer electrodes ZL2 extend along a column direction Y;

[0223] The first conductive layer may further include: a plurality of light emitting control lines (e.g., light emitting control lines EML(i), EML(i+2)) electrically connected to the plurality of first sub-pixel rows RL1, and a plurality of light emitting control electrodes (e.g., light emitting control electrodes EML0(i+1), EML0(i+3)) electrically connected to the plurality of second sub-pixel rows RL2; the light emitting control lines and the light emitting control electrodes extend along the row direction X; the third conductive layer may further include: a plurality of third initial signal lines (e.g., third initial signal lines INIT3(i), INIT3(i+2)) electrically connected to the plurality of first sub-pixel rows RL1, and a plurality of third initial signal electrodes (e.g., third initial signal electrodes INIT30(i+1), INIT30(i+3)) electrically connected to the plurality of second sub-pixel rows RL2; the third initial signal lines and the third initial signal electrodes extend along the row direction X;

[0224] The light-emitting control line EML(i) located in the i-th row is electrically connected to the multiple light-emitting control electrodes EML0(i-1) located in the i-1-th row through the first switching electrode ZL1, and the light-emitting control line EML(i+2) located in the i+2-th row is electrically connected to the multiple light-emitting control electrodes EML0(i+1) located in the i+1-th row through the first switching electrode ZL1, so that the light-emitting control line EML(i) located in the i-th row can provide light-emitting control signals to the sub-pixels in the i-th row and the sub-pixels in the i-1-th row, and the light-emitting control line EML(i+2) located in the i+2-th row can provide light-emitting control signals to the sub-pixels in the i+1-th row and the sub-pixels in the i+2-th row; the third initial signal line INIT3(i) located in the i-th row is electrically connected to the multiple third initial signal electrodes INIT30(i-1) located in the i-1-th row through the second switching electrode XL2, The third initial signal line INIT3(i+2) in the (i+2)th row is electrically connected to the plurality of third initial signal electrodes INIT30(i+1) in the (i+1)th row through the second switching electrode ZL2, so that the third initial signal line INIT3(i) in the (i)th row can provide the third initial signal to the sub-pixels in the (i-1)th row and the sub-pixels in the (i+2)th row, and the third initial signal line INIT3(i+2) in the (i+2)th row can provide the third initial signal to the sub-pixels in the (i+1)th row and the sub-pixels in the (i+2)th row.

[0225] The light-emitting control electrode and the third initial signal electrode can be located in the second sub-region K2. In the column direction Y, the light-emitting control line and the third initial signal line electrically connected to the first sub-pixel row RL1 bypass one side of the fourth sub-region K4, thereby avoiding blocking the fourth sub-region K4 and improving the transmittance of the fourth sub-region K4; in the same row of sub-pixels, the orthographic projections of the light-emitting control line and the third initial signal line on the substrate at least partially overlap, and the orthographic projections of the light-emitting control electrode and the third initial signal electrode on the substrate at least partially overlap, thereby reducing the space occupied by the signal lines on the display substrate and improving the transmittance of the display substrate.

[0226] In an exemplary embodiment, in the schemes of Figures 6A to 6C, a third initial signal line provides an initial signal to two rows of first pixel circuits, and a light-emitting control line provides a light-emitting control signal to two rows of first pixel circuits, which can reduce the number of signal lines, save space on the display substrate, and improve the transmittance of the display substrate (the transmittance of the third sub-region and the fourth sub-region can be improved).

[0227] In the solution provided in the embodiment of the present disclosure, at least some of the at least one signal line, each signal line is configured to be electrically connected to at least two rows of sub-pixels, and the number of the same signal lines in the at least one signal line is less than the number of rows of sub-pixels. Signals are provided to at least two rows of sub-pixels through one signal, reducing the number of signal lines and forming a third sub-region and a fourth sub-region, which can increase the aperture ratio of the display substrate by 2% to 6%, and increase the transmittance (or light transmittance) by 1% to 4%.

[0228] In an exemplary embodiment, sensors (such as cameras or fingerprint sensors) may be provided in the third sub-region K3 and the fourth sub-region K4 to prevent the first sub-pixel circuit and the anode from blocking light and improve light transmittance.

[0229] In an exemplary embodiment, as shown in FIG1 , the display substrate may include a first display area A1 and a second display area A2, and the second display area A2 may be located on at least one side of the first display area A1, for example, the second display area A2 is disposed around the first display area A1. In an exemplary embodiment, the second display area A2 is provided with a second pixel circuit, and the arrangement of the second pixel circuit may be consistent with or inconsistent with the arrangement of the first pixel circuit, which is not limited in the present disclosure. In an exemplary embodiment, the first display area A1 and the second display area A2 may be provided with a plurality of pixel units, and the arrangement of the pixel units of the second display area A2 may be consistent with or inconsistent with the arrangement of the pixel units in the first display area A1. When the arrangement of the second pixel circuit and the pixel units in the second display area A2 is consistent with that of the first display area A1, the aperture ratio of the second display area A2 may be improved.

[0230] The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a layer of thin film made by deposition, coating, or other processes on a substrate (or base substrate) of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in the direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. This is exemplified below using the preparation process of a display substrate:

[0231] In some examples, the preparation process of the display substrate may include the following operations. The first display area circuit structure layer is described below. This example is described by taking the first pixel circuit as the aforementioned 8T1C structure as an example. Among them, the first first pixel circuit (i.e., the first pixel circuit 11a) may include: a first transistor 31a, a second transistor 32a, a third transistor 33a, a fourth transistor 34a, a fifth transistor 35a, a sixth transistor 36a, a seventh transistor 37a, an eighth transistor 38a and a storage capacitor; The second first pixel circuit (i.e., the first pixel circuit 11b) may include: a first transistor 31b, a second transistor 32b, a third transistor 33b, a fourth transistor 34b, a fifth transistor 35b, a sixth transistor 36b, a seventh transistor 37b, an eighth transistor 38b and a storage capacitor. The connection relationship between the eight transistors and the storage capacitor in each first pixel circuit can be referred to the equivalent circuit diagram shown in Figure 2.

[0232] (101) Provide a substrate. In some examples, the substrate can be a rigid substrate or a flexible substrate. For example, the rigid substrate can be, but is not limited to, one or more of glass and quartz; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In some examples, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the substrate's resistance to water and oxygen.

[0233] (102) Forming a first semiconductor layer. In some examples, a first semiconductor thin film is deposited on a substrate, and the first semiconductor thin film is patterned by a patterning process to form a first semiconductor layer disposed on the substrate. In some examples, the first semiconductor layer can be made of amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, or polythiophene.

[0234] Figure 7A is a schematic diagram of the first display area after forming the first semiconductor layer. Figure 7B is a partially enlarged schematic diagram of Figure 7A.

[0235] In some examples, as shown in Figures 7A and 7B, the first semiconductor layer of the first display area may include at least: active layers of multiple first-type transistors of multiple first pixel circuits (for example, including: the first active layer 310a of the first transistor of the first pixel circuit 11a in the first sub-region and the second sub-region, the third active layer 330a of the third transistor, the fourth active layer 340a of the fourth transistor, the fifth active layer 350a of the fifth transistor, the sixth active layer 360a of the sixth transistor, the seventh active layer 370a of the seventh transistor, and the eighth active layer 380a of the eighth transistor, as well as the first active layer 310b of the first transistor of the first pixel circuit 11b, the third active layer 330b of the third transistor, the fourth active layer 340b of the fourth transistor, the fifth active layer 350b of the fifth transistor, the sixth active layer 360b of the sixth transistor, the seventh active layer 370b of the seventh transistor, and the eighth active layer 380b of the eighth transistor).

[0236] In some examples, within the first and second sub-regions, the first semiconductor layer patterns of the four first pixel circuits can be approximately symmetrical about a first centerline O1, the first semiconductor layer patterns of the first pixel circuits 11a and 11b can be approximately symmetrical about a second centerline O2, and the first semiconductor layer patterns of the first pixel circuits 11c and 11d can be approximately symmetrical about a third centerline O3. The first semiconductor layer patterns within different first sub-regions can be independent of each other, and the first semiconductor layer patterns within different second sub-regions can be independent of each other. Within the first and second sub-regions, the first centerline O1 can be the centerline of the four first pixel circuits extending along the second direction, the second centerline O2 can be the centerline of the first pixel circuit 11a and the first pixel circuit 11b extending along the second direction, and the third centerline O3 can be the centerline of the first pixel circuit 11c and the first pixel circuit 11d extending along the second direction.

[0237] In some examples, within the first sub-region and the second sub-region, the first active layer, the third active layer, the fourth active layer, the fifth active layer, the sixth active layer, and the seventh active layer of the four first pixel circuits can be interconnected as an integrated structure. The seventh active layer 370a of the first pixel circuit 11a and the seventh active layer 370b of the first pixel circuit 11b can be interconnected. The fifth active layer 350b of the first pixel circuit 11b and the fifth active layer of the first pixel circuit 11c can be interconnected. The seventh active layer of the first pixel circuit 11c and the seventh active layer of the first pixel circuit 11d can be interconnected. In the first sub-region, the first active layer and the fourth active layer of each first pixel circuit may be located on a side of the third active layer in a direction opposite to the second direction Y, and the fifth active layer, the seventh active layer, and the eighth active layer may be located on a side of the third active layer in the second direction Y. In the second sub-region, the first active layer and the fourth active layer of each first pixel circuit may be located on a side of the third active layer in the second direction Y, and the fifth active layer, the seventh active layer, and the eighth active layer may be located on a side of the third active layer in a direction opposite to the second direction Y. One end of the sixth active layer of each first pixel circuit is connected to the third active layer, and the other end is connected to the seventh active layer. In some examples, the third active layers 330a and 330b may be shaped approximately in a U-shape (or an inverted "X" shape, or an inverted "Ω" shape), the fourth active layers 340a and 340b and the fifth active layers 350a and 350b may be shaped approximately in an I-shape, and the first active layers 310a and 310b, the sixth active layers 360a and 360b, the seventh active layers 370a and 370b, and the eighth active layers 380a and 380b may be shaped approximately in an L-shape. However, this embodiment is not limited thereto.

[0238] In some examples, the active layer of each transistor may include: a first region, a second region, and a channel region located between the first region and the second region. The material of the first semiconductor layer may include, for example, polysilicon. The channel region may not be doped with impurities and have semiconductor properties. The first region and the second region may be doped regions on both sides of the channel region, and are doped with impurities and therefore have conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. The portion of the active layer between the transistors may be interpreted as wiring doped with impurities, which can be used to electrically connect the transistors. This embodiment is not limited to this.

[0239] (103) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate forming the aforementioned structure. The first conductive film is patterned by a patterning process to form a first insulating layer and a first conductive layer disposed on the first insulating layer. In some examples, the first conductive layer may also be referred to as a first gate metal layer.

[0240] Figure 8A is a schematic diagram of the first display area after forming the first conductive layer. Figure 8B is a schematic diagram of the first conductive layer in Figure 8A. Figure 8C is a partially enlarged schematic diagram of Figure 8A.

[0241] In some examples, as shown in Figures 8A to 8C, the first conductive layer of the first display area may include at least: a plurality of first scan lines (e.g., first scan lines GL1(i), GL1(i+1), GL1(i+2), GL1(i+3)), a plurality of emission control lines (e.g., emission control lines EML(i), EML(i+1), EML(i+2), EML(i+3)), a plurality of first reset control lines (e.g., first reset control lines RST1(i), RST1(i+1), RST1(i+2), RST1(i+3)), a plurality of second reset control lines (e.g., second reset control lines RST2(i-1), RST2(i), RST2(i+1), RST2(i+2), RST2(i+3), RST2(i+4)), and a plurality of first electrodes of storage capacitors of the first pixel circuits (e.g., first electrodes 391a, 391b). In an exemplary embodiment, the first electrode of the storage capacitor can be understood as the first plate of the storage capacitor.

[0242] In some examples, within the first sub-region, the first scan line GL1(i) can be located on the side of the first electrode of the storage capacitor of the first pixel circuit (for example, 391a and 391b) in the opposite direction of the second direction Y, and the first reset control line RST1(i) can be located on the side of the first scan line GL1(i) in the opposite direction Y; the light-emitting control line EML(i) can be located on the side of the first electrode of the storage capacitor of the first pixel circuit (for example, 391a and 391b) in the second direction Y, and the second reset control line RST2(i) can be located on the side of the light-emitting control line EML(i) in the second direction Y. In the second sub-area, the first scan line GL1(i+1) can be located on the side of the first electrode of the storage capacitor of the first pixel circuit (for example, 391a and 391b) in the second direction Y, the first reset control line RST1(i+1) can be located on the side of the first scan line GL1(i) in the opposite direction of the second direction Y, and is located on the side of the first scan line GL1(i+1) in the second direction Y, that is, in the second direction Y, the first reset control line RST1(i+1) can be located between the first scan line GL1(i) and the first scan line GL1(i+1); the light-emitting control line EML(i+1) can be located on the side of the first electrode of the storage capacitor of the first pixel circuit (for example, 391a and 391b) in the opposite direction of the second direction Y, and the second reset control line RST2(i+1) can be located on the side of the light-emitting control line EML(i+1) in the opposite direction of the second direction Y.

[0243] In some examples, the first reset control line RST1(i) of the first pixel circuit in the i-th row and the first reset control line RST1(i+1) of the first pixel circuit in the i+1-th row can share one, and the second reset control line RST2(i+1) of the pixel circuit in the i+1-th row and the second reset control line RST2(i+1) of the i+2-th row can share one, where i can be a positive integer greater than 1.

[0244] In some examples, the first reset control line RST1(i) / RST1(i+1), the first scan line GL1(i), and the emission control line EML(i) can bend around a third sub-region adjacent to the first sub-region along the first direction X. For example, the first reset control line RST1(i) / RST1(i+1) and the first scan line GL1(i) can bend around the side of the third sub-region opposite to the second direction Y, and the emission control line EML(i) can bend around the side of the second sub-region along the second direction Y. In this example, by configuring the routing of the first conductive layer to bend around the third sub-region, light transmittance in the third sub-region is improved.

[0245] In some examples, the first scan line GL1(i+1), the second reset control line RST2(i+1) / RST2(i+2), and the emission control line EML(i+1) can bend around a fourth sub-region adjacent to the second sub-region along the first direction X. For example, the second reset control line RST2(i+1) / RST2(i+2) and the emission control line EML(i+1) can bend around the side of the fourth sub-region opposite to the second direction Y, and the first scan line GL1(i+1) can bend around the side of the fourth sub-region along the second direction Y. In this example, by configuring the routing of the first conductive layer to bend around the fourth sub-region, light transmittance in the fourth sub-region is improved.

[0246] In some examples, the shape of the first reset control line RST1(i) / RST1(i+1) can be substantially a zigzag line extending along the first direction X. In the first sub-region and the second sub-region, the overlapping region of the first reset control line RST1(i) / RST1(i+1) and the first active layer of the four first pixel circuits can serve as the gates of the first transistors of the four first pixel circuits (for example, including the gate of the first transistor 31a and the gate of the first transistor 31b in the first sub-region, and the gate of the first transistor 31c and the gate of the first transistor 31d in the second sub-region). In some examples, the first reset control line RST1(i) / RST1(i+1) is a first ring structure RST10 at a position adjacent to the first sub-region and the second sub-region. In the second direction Y, the side of the first ring structure RST10 close to the first sub-region overlaps with the first active layer of the first sub-pixel circuit 11c and the first pixel circuit 11d of the i-th row, and the side of the first ring structure RST10 close to the second sub-region overlaps with the first active layer of the first sub-pixel circuit 11a and the first pixel circuit 11b of the i+1-th row. The first ring structure RST10 can enable multiple first sub-pixel circuits in the i-th row and multiple first sub-pixel circuits in the i+1-th row to share a first reset control line RST1(i) / RST1(i+1), thereby reducing the number of signal lines, saving space on the display substrate, and improving the transmittance of the display substrate (the transmittance of the third sub-region and the fourth sub-region can be improved).

[0247] In some examples, the shape of the first scan line GL1(i) can be roughly a zigzag shape extending along the first direction X. In the first sub-region, the overlapping area of ​​the first scan line GL1(i) and the fourth active layer of the four first pixel circuits located in the i-th row can serve as the gate of the fourth transistor of the four first pixel circuits (for example, including the gate of the fourth transistor 34a and the gate of the fourth transistor 34b). In the second sub-region, the overlapping area of ​​the first scan line GL1(i+1) and the fourth active layer of the four first pixel circuits located in the i+1-th row can serve as the gate of the fourth transistor of the four first pixel circuits (for example, including the gate of the fourth transistor 34a and the gate of the fourth transistor 34b).

[0248] In some examples, the shape of the light-emitting control line EML(i) can be roughly a zigzag line extending along the first direction X. Within the first sub-region, the overlapping region of the light-emitting control line EML(i) and the fifth active layer of the four first pixel circuits located in the i-th row can serve as the gates of the fifth transistors of the four first pixel circuits (e.g., including the gates of the fifth transistors 35a and 35b), and the overlapping region of the light-emitting control line EML(i) and the sixth active layer of the four first pixel circuits can serve as the gates of the sixth transistors of the four first pixel circuits (e.g., including the gates of the sixth transistors 36a and 36b). Within the second sub-region, the overlapping region of the light-emitting control line EML(i+1) and the fifth active layer of the four first pixel circuits located in the i+1-th row can serve as the gates of the fifth transistors of the four first pixel circuits (e.g., including the gates of the fifth transistors 35a and 35b), and the overlapping region of the light-emitting control line EML(i) and the sixth active layer of the four first pixel circuits can serve as the gates of the sixth transistors of the four first pixel circuits (e.g., including the gates of the sixth transistors 36a and 36b).

[0249] In some examples, the shape of the second reset control line RST2(i-1) / RST2(i) can be approximately a zigzag line extending along the first direction X. In the first sub-region and the second sub-region, the overlapping region of the second reset control line RST2(i) and the seventh active layer of the four first pixel circuits located in the i-1th row and the i-th row can serve as the gate of the seventh transistor of the four first pixel circuits (for example, including the gate of the seventh transistors 37a and 37b), and the overlapping region of the second reset control line RST2(i-1) / RST2(i) and the eighth active layer of the four first pixel circuits can serve as the gate of the eighth transistor of the four first pixel circuits (for example, including the gate of the eighth transistors 38a and 38b). In some examples, the second reset control line RST2(i-1) / RST2(i) is a second ring structure RST20 at a position adjacent to the first sub-region and the second sub-region. In the second direction Y, the side of the second ring structure RST20 close to the first sub-region overlaps with the first active layer of the first sub-pixel circuit 11c and the first pixel circuit 11d of the i-th row, and the side of the second ring structure RST20 close to the second sub-region overlaps with the first active layer of the first sub-pixel circuit 11a and the first pixel circuit 11b of the i-1th row. The second ring structure RST20 can enable multiple first sub-pixel circuits in the i-th row and multiple first sub-pixel circuits in the i-1th row to share a second reset control line RST2(i-1) / RST2(i), thereby reducing the number of signal lines, saving space on the display substrate, and improving the transmittance of the display substrate (the transmittance of the third sub-region and the fourth sub-region can be improved).

[0250] In some examples, the first electrode 391a of the storage capacitor of the first pixel circuit 11a can also serve as the gate of the third transistor 33a, and the first electrode 391b of the storage capacitor of the first pixel circuit 11b can also serve as the gate of the third transistor 33b. The orthographic projections of the first electrodes 391a and 391b on the substrate can be approximately rectangular. This embodiment is not limited to this.

[0251] (104) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate forming the aforementioned structure. The second conductive film is patterned by a patterning process to form a second insulating layer and a second conductive layer disposed on the second insulating layer. In some examples, the second conductive layer may also be referred to as a second gate metal layer.

[0252] Figure 9A is a schematic diagram of the first display area after forming the second conductive layer. Figure 9B is a schematic diagram of the second conductive layer in Figure 9A. Figure 9C is a partially enlarged schematic diagram of Figure 9A.

[0253] In some examples, as shown in Figures 9A to 9C, the second conductive layer of the first display area may include at least: a plurality of second scanning auxiliary lines (for example, second scanning auxiliary lines GL2b(i), GL2b(i+1), GL2b(i+2), GL2b(i+3)), and a plurality of second electrodes of the storage capacitors of the first pixel circuits (for example, second electrodes 392a, 392b).

[0254] In some examples, the shape of the second scan auxiliary line GL2b(i) can be roughly a zigzag line extending along the first direction X. Within the first sub-region, the second scan auxiliary line GL2b(i) can be located on the side opposite to the second direction Y of the second electrode (e.g., 392a and 392b) of the storage capacitor of the first pixel circuit. The second scan auxiliary line GL2b(i) can bypass the third sub-region from the side opposite to the second direction Y and be located on the side of the first scan line GL1(i) along the second direction Y, that is, in the second direction Y, the second scan auxiliary line GL2b(i) can be located between the second electrode of the storage capacitor of the first pixel circuit and the first scan line GL1(i). Within the second sub-region, the second scan auxiliary line GL2b(i+1) can be located on the side of the second direction Y of the second electrode (e.g., 392a and 392b) of the storage capacitor of the first pixel circuit. The second scanning auxiliary line GL2b(i+1) can bypass the fourth sub-region from the side of the second direction Y and be located on the side of the first scanning line GL1(i+1) in the opposite direction of the second direction Y, that is, in the second direction Y, the second scanning auxiliary line GL2b(i+1) can be located between the second electrode of the storage capacitor of the first pixel circuit and the first scanning line GL1(i+1).

[0255] In some examples, within the first sub-region and the second sub-region, the orthographic projection of the second electrode of the storage capacitor of each first pixel circuit on the substrate can be approximately a rectangular structure with a hollowed-out area. The orthographic projection of the hollowed-out area on the substrate can be approximately rectangular, and the rectangle can have rounded or chamfered corners. The second electrode 392a of the storage capacitor of the first pixel circuit 11a and the second electrode 392b of the storage capacitor of the first pixel circuit 11b can be electrically connected through a first plate connection block 392-1, the second electrode 392b of the storage capacitor of the first pixel circuit 11b and the second electrode of the storage capacitor of the first pixel circuit 11c can be electrically connected through a second plate connection block 392-2, and the second electrode of the storage capacitor of the first pixel circuit 11c and the second electrode of the storage capacitor of the first pixel circuit 11d can be electrically connected through another first plate connection block 392-1. The second electrodes of the storage capacitors of the first pixel circuits 11a and 11d can be electrically connected to a second plate connection block 392-2 on the side away from the remaining first pixel circuits. The length L1 of the first plate connecting block 392-1 along the second direction Y can be less than the length L2 of the second plate connecting block 392-2 along the second direction Y. The second electrode of the storage capacitor can subsequently be electrically connected to the first power line via the second plate connecting block. In this example, the second electrodes of the storage capacitors of the four first pixel circuits in the first sub-region can be interconnected as an integrated structure, which helps ensure uniform transmission of the first voltage signal along the first direction X. The second electrodes of the storage capacitors of the four first pixel circuits in the second sub-region can be interconnected as an integrated structure, which helps ensure uniform transmission of the first voltage signal along the first direction X.

[0256] In an exemplary embodiment, the second electrode of the storage capacitor may be understood as the second plate of the storage capacitor.

[0257] (105) Forming a second semiconductor layer. In some examples, a third insulating film and a second semiconductor film are sequentially deposited on the substrate having the aforementioned pattern formed thereon. The second semiconductor film is patterned by a patterning process to form a third insulating layer and a second semiconductor layer disposed on the third insulating layer. In some examples, the material of the second semiconductor layer may include indium gallium zinc oxide (IGZO).

[0258] Figure 10A is a schematic diagram of the first display area after forming the second semiconductor layer. Figure 10B is a schematic diagram of the second semiconductor layer in Figure 10A. Figure 10C is a partially enlarged schematic diagram of Figure 10A.

[0259] In some examples, as shown in Figures 10A to 10C, the second semiconductor layer of the first display area may include at least: an active layer of a second type transistor of a plurality of first pixel circuits (for example, including: a second active layer 320a of the second transistor 32a of the first pixel circuit 11a within the first sub-region and the second sub-region, and a second active layer 320b of the second transistor 32b of the first pixel circuit 11b).

[0260] In some examples, within the first sub-region and the second sub-region, the second semiconductor layer patterns of the four first pixel circuits can be roughly symmetrical about the first center line O1, the second semiconductor layer patterns of the first pixel circuits 11a and 11b can be roughly symmetrical about the second center line O2, and the second semiconductor layer patterns of the first pixel circuits 11c and 11d can be roughly symmetrical about the third center line O3.

[0261] In some examples, the second active layers 320a and 320b can be roughly L-shaped. In the first sub-region, the overlapping region between the second scan auxiliary line GL2b(i) and the second active layer 320a can serve as the bottom gate of the second transistor 32a, and the overlapping region between the second scan auxiliary line GL2b(i) and the second active layer 320b can serve as the bottom gate of the second transistor 32b. In the second sub-region, the overlapping region between the second scan auxiliary line GL2b(i+1) and the second active layer 320a can serve as the bottom gate of the second transistor 32a, and the overlapping region between the second scan auxiliary line GL2b(i+1) and the second active layer 320b can serve as the bottom gate of the second transistor 32b.

[0262] (106) Forming a third conductive layer. In some examples, a fourth insulating film and a third conductive film are sequentially deposited on the substrate having the aforementioned pattern formed thereon. The third conductive film is patterned by a patterning process to form a fourth insulating layer and a third conductive layer disposed on the fourth insulating layer. In some examples, the third conductive layer may also be referred to as a third gate metal layer.

[0263] Figure 11A is a schematic diagram of the first display area after forming the third conductive layer. Figure 11B is a schematic diagram of the third conductive layer in Figure 11A. Figure 11C is a partially enlarged schematic diagram of Figure 11A.

[0264] In some examples, as shown in Figures 11A to 11C, the third conductive layer of the first display area may include at least: a plurality of second scan lines (e.g., second scan lines GL2(i), GL2(i+1), GL2(i+2), GL2(i+3)), a plurality of first initial signal lines (e.g., first initial signal lines INIT1(i), INIT1(i+1), INIT1(i+2), INIT1(i+3)), a plurality of second initial signal lines (e.g., second initial signal lines INIT2(i-1), INIT2(i), INIT2(i+1), INIT2(i+2), INIT2(i+3), INIT2(i+4)), and a plurality of third initial signal lines (e.g., third initial signal lines INIT3(i), INIT3(i+1), INIT3(i+2), INIT3(i+3)). The first initial signal lines, the second scan lines, the second initial signal lines, and the third initial signal lines may each be substantially in the shape of a zigzag line extending along the first direction X.

[0265] In some examples, within the first sub-region, the first initial signal line INIT1(i) / INIT1(i+1) and the second scan line GL2(i) may be located on a side of the storage capacitor in the opposite direction along the second direction Y, and the second initial signal line INIT2(i-1) / INIT2(i) and the third initial signal line INIT3(i) may be located on a side of the storage capacitor in the second direction Y. The first initial signal line INIT1(i) / INIT1(i+1) may be located on a side of the second scan line GL2(i) in the opposite direction along the second direction Y; the second initial signal line INIT2(i-1) / INIT2(i) may be located on a side of the third initial signal line INIT3(i) in the second direction Y. In the second sub-region, the first initial signal line INIT1(i) / INIT1(i+1) and the second scan line GL2(i+1) may be located on one side of the storage capacitor along the second direction Y, and the second initial signal line INIT2(i+1) / INIT2(i+2) and the third initial signal line INIT3(i+1) may be located on the side of the storage capacitor in the opposite direction of the second direction Y. The first initial signal line INIT1(i) / INIT1(i+1) may be located on one side of the second scan line GL2(i+1) along the second direction Y; the second initial signal line INIT2(i+1) / INIT2(i+2) may be located on the side of the third initial signal line INIT3(i+1) in the opposite direction of the second direction Y.

[0266] In some examples, the first initial signal line INIT1(i) / INIT1(i+1), the second scan line GL2(i), and the third initial signal line INIT3(i) can bend around a third sub-region adjacent to the first sub-region along the first direction X. For example, the first initial signal line INIT1(i) / INIT1(i+1) and the second scan line GL2(i) can bend around the side of the third sub-region opposite to the second direction Y, and the third initial signal line INIT3(i) can bend around the side of the third sub-region along the second direction Y. In this example, by setting the routing of the third conductive layer to bend around the third sub-region, the light transmittance of the third sub-region is improved.

[0267] In some examples, the second scan line GL2(i+1), the second initial signal line INIT2(i+1) / INIT2(i+2), and the third initial signal line INIT3(i+1) can bend around the fourth sub-region adjacent to the second sub-region along the first direction X. For example, the second scan line GL2(i+1) can bend around the fourth sub-region along the second direction Y, the third initial signal line INIT3(i+1) can bend around the fourth sub-region along the opposite direction of the second direction Y, and the second initial signal line INIT2(i+1) / INIT2(i+2) can bend around the fourth sub-region along the opposite direction of the second direction Y. In this example, by setting the routing of the third conductive layer to bend around the fourth sub-region, the light transmittance of the fourth sub-region is improved.

[0268] In some examples, the orthographic projection of the first initial signal line INIT1(i) / INIT1(i+1) on the substrate may at least partially overlap with the orthographic projection of the first reset control line RST1(i) / RST1(i+1) on the substrate, the orthographic projection of the second scan line GL2(i) on the substrate may at least partially overlap with the orthographic projection of the second scan auxiliary line GL2b(i) on the substrate, the orthographic projection of the third initial signal line INIT3(i) on the substrate may at least partially overlap with the orthographic projection of the light-emitting control line EML(i) on the substrate, and the orthographic projection of the second initial signal line INIT2(i-1) / INIT2(i) on the substrate may at least partially overlap with the orthographic projection of the second reset control line RST2(i-1) / RST2(i) on the substrate. In some examples, the orthographic projection of the first initial signal line INIT1(i+2) / INIT1(i+3) on the substrate may at least partially overlap with the orthographic projection of the first reset control line RST1(i+2) / RST1(i+3) on the substrate, the orthographic projection of the second scan line GL2(i+1) on the substrate may at least partially overlap with the orthographic projection of the second scan auxiliary line GL2b(i+1) on the substrate, the orthographic projection of the third initial signal line INIT3(i+1) on the substrate may at least partially overlap with the orthographic projection of the emission control line EML(i+1) on the substrate, and the orthographic projection of the second initial signal line INIT2(i+1) / INIT2(i+2) on the substrate may at least partially overlap with the orthographic projection of the second reset control line RST2(i+1) / RST2(i+2) on the substrate. This example avoids occupying too much routing space by designing the routing of different conductive layers in a stacked manner, which helps save wiring space and thereby improves the light transmittance of the first display area.

[0269] In some examples, the first initial signal line INIT1(i) / INIT1(i+1) is a third ring structure INIT10 at a position adjacent to the first sub-region and the second sub-region. In the second direction Y, the side of the third ring structure INIT10 close to the first sub-region overlaps with the first active layer of the first sub-pixel circuit 11c and the first pixel circuit 11d of the i-th row, and the side of the third ring structure INIT10 close to the second sub-region overlaps with the first active layer of the first sub-pixel circuit 11a and the first pixel circuit 11b of the i+1-th row. The third ring structure INIT10 can enable multiple first sub-pixel circuits in the i-th row and multiple first sub-pixel circuits in the i+1-th row to share a first initial signal line INIT1(i) / INIT1(i+1), thereby reducing the number of signal lines, saving space on the display substrate, and improving the transmittance of the display substrate (the transmittance of the third sub-region and the fourth sub-region can be improved).

[0270] In some examples, the second initial signal line INIT2(i-1) / INIT2(i) is a fourth annular structure INIT20 at a position adjacent to the first sub-region and the second sub-region. In the second direction Y, the side of the fourth annular structure INIT20 close to the first sub-region overlaps with the first active layer of the first sub-pixel circuit 11c and the first pixel circuit 11d of the i-th row, and the side of the fourth annular structure INIT20 close to the second sub-region overlaps with the first active layer of the first sub-pixel circuit 11a and the first pixel circuit 11b of the i-1-th row. The fourth annular structure INIT20 can enable multiple first sub-pixel circuits in the i-th row and multiple first sub-pixel circuits in the i-1-th row to share a second reset control line RST2(i-1) / RST2(i), thereby reducing the number of signal lines, saving space on the display substrate, and improving the transmittance of the display substrate (the transmittance of the third sub-region and the fourth sub-region can be improved).

[0271] In some examples, the area where the second scan line overlaps with the active layer of the second transistor can serve as the gate of the second transistor (which can be called a control electrode or top gate), and the signal of the second scan auxiliary line and the corresponding second scan line can be the same, that is, the two are connected in parallel and connected to the same signal source, so that the second scan auxiliary line can serve as the bottom gate electrode (that is, the bottom control electrode) of the second transistor, forming a second transistor T2 with a dual-gate structure.

[0272] (107) Forming a fifth insulating layer. In some examples, a fifth insulating film is deposited on the substrate having the aforementioned pattern formed thereon, and the fifth insulating film is patterned by a patterning process to form the fifth insulating layer.

[0273] Figure 12A is a schematic diagram of a first sub-region and a second sub-region after forming the fifth insulating layer, and Figure 12B is a partially enlarged schematic diagram of Figure 12A. In some examples, as shown in Figures 12A and 12B, the fifth insulating layer of the first display area can have multiple vias, for example, including first via V1 to seventeenth via V17.

[0274] In some examples, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer in the first through holes V1 to V10 can be removed to expose a portion of the surface of the first semiconductor layer. The fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the eleventh through hole V11 can be removed to expose a portion of the surface of the first conductive layer. The fifth insulating layer, the fourth insulating layer, and the third insulating layer in the twelfth through hole V12 can be removed to expose a portion of the surface of the second conductive layer. The fifth insulating layer and the fourth insulating layer in the thirteenth through hole V13 and the fourteenth through hole V14 can be removed to expose the surface of the second semiconductor layer. The fifth insulating layer in the fifteenth through hole V15 to the seventeenth through hole V17 can be removed to expose a portion of the surface of the third conductive layer.

[0275] In some examples, the orthographic projection of the first via V1 on the substrate is within the range of the orthographic projection of the first active layer of the first transistor on the substrate. The fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the first via V1 can be removed to expose the surface of the first region of the first active layer. The first via V1 is configured to connect the first electrode of a subsequently formed first transistor to the first active layer of the first transistor through the via.

[0276] In some examples, the orthographic projection of the second via V2 on the substrate is within the range of the orthographic projection of the second active layer of the first transistor on the substrate. The fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the second via V2 can be removed to expose the surface of the second region of the second active layer. The second via V2 is configured to connect the second electrode of the subsequently formed first transistor to the first active layer of the first transistor through the via.

[0277] In some examples, the orthographic projection of the third via V3 on the substrate is within the range of the orthographic projection of the fourth active layer of the fourth transistor on the substrate. The fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the third via V3 can be removed to expose the surface of the first region of the fourth active layer. The third via V3 is configured to connect the first electrode of a subsequently formed fourth transistor to the fourth active layer of the fourth transistor through the via.

[0278] In some examples, the orthographic projection of the third-fourth via V4 on the substrate is located within the range of the orthographic projection of the fourth active layer of the fourth transistor on the substrate. The fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the third-fourth via V4 can be removed, exposing the surface of the second region of the fourth active layer. The third-fourth via V4 is configured to connect the second electrode of a subsequently formed fourth transistor to the fourth active layer of the fourth transistor through the via.

[0279] In some examples, the orthographic projection of the fifth via V5 on the substrate is within the range of the orthographic projection of the fifth active layer of the fifth transistor on the substrate. The fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the fifth via V5 can be removed, exposing the surface of the first region of the fifth active layer. The fifth via V5 is configured to connect the first electrode of a subsequently formed fifth transistor to the fifth active layer of the fifth transistor through the via.

[0280] In some examples, the orthographic projection of the sixth via V6 on the substrate is within the range of the orthographic projection of the sixth active layer of the fifth transistor on the substrate. The fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the sixth via V6 can be removed, exposing the surface of the first region of the sixth active layer. The sixth via V6 is configured to connect the first electrode of a subsequently formed sixth transistor to the sixth active layer of the sixth transistor through the via.

[0281] In some examples, the orthographic projection of the seventh via V7 on the substrate is within the range of the orthographic projection of the sixth active layer of the sixth transistor on the substrate, and the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the seventh via V7 can be removed, exposing the surface of the second region of the sixth active layer (which is also the surface of the second region of the seventh transistor). The seventh via V7 is configured to connect the second electrode of a subsequently formed sixth transistor to the sixth active layer of the sixth transistor through the via, and to connect the second electrode of a subsequently formed seventh transistor to the seventh active layer of the seventh transistor through the via.

[0282] In some examples, the orthographic projection of the eighth via V8 on the substrate is within the range of the orthographic projection of the seventh active layer of the seventh transistor on the substrate, and the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the eighth via V8 can be removed to expose the surface of the first region of the seventh active layer. The eighth via V8 is configured to connect the first electrode of the subsequently formed seventh transistor to the seventh active layer of the seventh transistor through the via. In some examples, the first pixel circuit 11a and the first pixel circuit 11b can share an eighth via, and the first pixel circuit 11c and the first pixel circuit 11d can share an eighth via.

[0283] In some examples, the orthographic projection of the ninth via V9 on the substrate is within the range of the orthographic projection of the eighth active layer of the eighth transistor on the substrate. The fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the ninth via V9 can be removed, exposing the surface of the first region of the eighth active layer. The ninth via V9 is configured to connect the first electrode of a subsequently formed eighth transistor to the eighth active layer of the eighth transistor through the ninth via V9.

[0284] In some examples, the orthographic projection of the tenth via V10 on the substrate is located within the range of the orthographic projection of the eighth active layer of the eighth transistor on the substrate. The fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the tenth via V10 can be removed, exposing the surface of the second region of the eighth active layer. The tenth via V10 is configured to connect the second electrode of the subsequently formed eighth transistor to the eighth active layer of the eighth transistor through the via.

[0285] In some examples, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the first electrode of the storage capacitor on the substrate. The fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the eleventh via hole V11 can be removed to expose the surface of the first electrode of the storage capacitor. The eleventh via hole V11 is configured to connect a subsequently formed second connecting electrode to the first electrode of the storage capacitor through the via hole.

[0286] In some examples, the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the second plate connection block 392-2 of the storage capacitor on the substrate. The fifth insulating layer, the fourth insulating layer, and the third insulating layer within the twelfth via V12 can be removed to expose the surface of the second plate connection block 392-2. The twelfth via V12 is configured to connect a subsequently formed fifth connection electrode to the second plate connection block 392-2 through the via.

[0287] In some examples, the orthographic projection of the thirteenth via V13 on the substrate is located within the range of the orthographic projection of the second active layer of the second transistor on the substrate. The fifth insulating layer and the fourth insulating layer within the thirteenth via V13 can be removed to expose the surface of the first region of the second active layer. The thirteenth via V13 is configured to connect the first electrode of a subsequently formed second transistor to the second active layer of the second transistor through the via.

[0288] In some examples, the orthographic projection of the fourteenth via V14 on the substrate is located within the orthographic projection of the second active layer of the second transistor on the substrate. The fifth insulating layer and the fourth insulating layer within the fourteenth via V14 can be removed to expose the surface of the second region of the second active layer. The fourteenth via V14 is configured to connect the second electrode of a subsequently formed second transistor to the second active layer of the second transistor through the via.

[0289] In some examples, the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the first initial signal line INIT1(i) / INIT1(i+1) on the substrate, and the fifth insulating layer within the fifteenth via hole V15 can be removed to expose the surface of the first initial signal line INIT1(i) / INIT1(i+1). The fifteenth via hole V15 is configured to connect a subsequently formed ninth connection electrode to the first initial signal line INIT1(i) / INIT1(i+1) through the via hole.

[0290] In some examples, the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the second initial signal line INIT2(i-1) / INIT2(i) on the substrate, and the fifth insulating layer within the sixteenth via hole V16 can be removed to expose the surface of the second initial signal line INIT2(i-1) / INIT2(i). The sixteenth via hole V16 is configured to connect a subsequently formed ninth connection electrode to the second initial signal line INIT2(i-1) / INIT2(i) through the via hole.

[0291] In some examples, the orthographic projection of the seventeenth via V17 on the substrate is within the range of the orthographic projection of the third initial signal line INIT3(i) on the substrate, and the fifth insulating layer within the seventeenth via V17 can be removed to expose the surface of the third initial signal line INIT3(i). The seventeenth via V17 is configured to connect a subsequently formed seventh connection electrode (the first electrode of the eighth transistor) to the third initial signal line INIT3(i) through the via.

[0292] (108) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate having the aforementioned pattern, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer on the fifth insulating layer. In some examples, the fourth conductive layer may also be referred to as a first source / drain metal layer.

[0293] Figure 13A is a schematic diagram of the first display area after forming the fourth conductive layer. Figure 13B is a schematic diagram of the fourth conductive layer in Figure 13A. Figure 13C is a partially enlarged schematic diagram of Figure 13A.

[0294] In some examples, as shown in FIG. 13A to FIG. 13C , the fourth conductive layer of the first display region may include at least: a plurality of connection electrodes (eg, including the first connection electrode 401 to the ninth connection electrode 409 ).

[0295] In some examples, the shape of the first connection electrode 401 can be substantially rectangular. The first connection electrode 401 can be electrically connected to the fourth active layer of the fourth transistor 34a of the first pixel circuit 11a through the third via V3. In some examples, the first connection electrode 401 can serve as the first electrode of the fourth transistor 34a.

[0296] In some examples, the second connection electrode 402 can be shaped substantially like a strip extending along the second direction Y. One end of the second connection electrode 402 can be electrically connected to the second active layer of the second transistor 32a of the first pixel circuit 11a through the thirteenth via hole V13, and the other end can be electrically connected to the first electrode 391a of the storage capacitor through the eleventh via hole V11. The second connection electrode 402 can serve as the first electrode of the second transistor 32a, electrically connected to the gate of the third transistor 33a and the first electrode 391a of the storage capacitor through the eleventh via hole V11, and electrically connected to the second active layer of the second transistor 32a through the thirteenth via hole V13. The second connection electrode 402 can serve as the first node of the first pixel circuit 11a.

[0297] In some examples, the third connection electrode 403 can be shaped substantially like a strip extending along the second direction Y. One end of the third connection electrode 403 can be electrically connected to the first active layer of the first transistor 31a of the first pixel circuit 11a through the second via V2, and the other end can be electrically connected to the second active layer of the second transistor 32a through the fourteenth via V14. The third connection electrode 403 can also be electrically connected to the third active layer of the third transistor 33a (also the sixth active layer of the sixth transistor 36a) through the sixth via V6. In some examples, the third connection electrode 403 can serve as the second electrode of the first transistor, the second electrode of the second transistor, the second electrode of the third transistor, and the first electrode of the sixth transistor in the first pixel circuit.

[0298] In some examples, the fourth connection electrode 404 can be shaped substantially like a zigzag line extending along the second direction Y. The fourth connection electrode 404 can be electrically connected to the fourth active layer of the fourth transistor 34a of the first pixel circuit 11a through a fourth via V4, and can also be electrically connected to the eighth active layer of the eighth transistor 38a through a tenth via V10. In some examples, the fourth connection electrode 404 can serve as the second electrode of the fourth transistor and the eighth transistor in the first pixel circuit.

[0299] In some examples, the fifth connection electrode 405 can be shaped roughly like a strip extending along the second direction Y. The fifth connection electrode 405 can be electrically connected to the fifth active layer of the fifth transistor 35a of the first pixel circuit 11a through a fifth via V5, and can also be electrically connected to the second plate connection block 392-2 through a twelfth via V12, thereby achieving electrical connection to the second electrode 392a of the storage capacitor. In some examples, the fifth connection electrode 405 can serve as the first electrode of the fifth transistor of the first pixel circuit. In some examples, in the first sub-region, the first sub-pixel 11b and the first sub-pixel 11c can share one fifth connection electrode 405; in the first sub-region, the first sub-pixel 11b and the first sub-pixel 11c can share one fifth connection electrode 405.

[0300] In some examples, the sixth connection electrode 406 can be substantially rectangular in shape. The sixth connection electrode 406 can be electrically connected to the sixth active layer of the sixth transistor 36a and the seventh active layer of the seventh transistor 37a of the first pixel circuit 11a through the seventh via V7. In some examples, the sixth connection electrode 406 can serve as the second electrode of the sixth transistor and the seventh transistor in the first pixel circuit.

[0301] In some examples, the shape of the seventh connection electrode 407 can be substantially L-shaped. The seventh connection electrode 407 can be electrically connected to the eighth active layer of the eighth transistor 38a of the first pixel circuit 11a through the ninth via hole V9, and can also be electrically connected to the third initial signal line INIT3(i) through the seventeenth via hole V17. In some examples, the seventh connection electrode 407 can serve as the first electrode of the eighth transistor in the first pixel circuit.

[0302] In some examples, the shape of the eighth connection electrode 408 can be approximately a strip extending along the second direction Y. The eighth connection electrode 408 can be electrically connected to the seventh active layer of the seventh transistor 37a of the first pixel circuit 11a through the eighth via V8, and can also be electrically connected to the second initial signal line INIT2(i-1) / INIT2(i) through the sixteenth via V16. In some examples, the eighth connection electrode 408 can serve as the first electrode of the seventh transistor in the first pixel circuit. In some examples, the first pixel circuit 11a and the first pixel circuit 11b can share one eighth connection electrode 408, and the first pixel circuit 11c and the first pixel circuit 11d can share one eighth connection electrode 408.

[0303] In some examples, the shape of the ninth connection electrode 409 can be substantially an arch extending along the second direction Y. One end of the ninth connection electrode 409 (located at one end of the first sub-pixel circuit 11a) can be electrically connected to the first active layer of the first transistor 31a of the first pixel circuit 11a through the first via hole V1 located in the first sub-pixel circuit 11a, and can also be electrically connected to the first initial signal line INIT1(i) / INIT1(i+1) through the fifteenth via hole V15 located in the first sub-pixel circuit 11a, and the other end (located at one end of the first sub-pixel circuit 11b) can be electrically connected to the first active layer of the first transistor 31b of the first pixel circuit 11b through the first via hole V1 located in the first sub-pixel circuit 11b, and can also be electrically connected to the first initial signal line INIT1(i) / INIT1(i+1) through the fifteenth via hole V15 located in the first sub-pixel circuit 11b. In some examples, the first pixel circuit 11a and the first pixel circuit 11b may share a ninth connection electrode 409, and the first pixel circuit 11c and the first pixel circuit 11d may share a ninth connection electrode 409. In some examples, the ninth connection electrode 409 may serve as a first terminal of a first transistor in the first pixel circuit.

[0304] In some examples, within the first sub-region, the first pixel circuits 11a and 11b may be approximately symmetrical about the second center line O2, the first pixel circuits 11c and 11d may be approximately symmetrical about the third center line O3, and the first pixel circuits 11a and 11b, and the first pixel circuits 11c and 11d may be approximately symmetrical about the first center line O1. Within the second sub-region, the first pixel circuits 11a and 11b may be approximately symmetrical about the second center line O2, the first pixel circuits 11c and 11d may be approximately symmetrical about the third center line O3, and the first pixel circuits 11a and 11b, and the first pixel circuits 11c and 11d may be approximately symmetrical about the first center line O1.

[0305] In some examples, the first pixel circuits within a plurality of first sub-regions arranged along a first direction X may be aligned in the first direction X, and the first pixel circuits within a plurality of first sub-regions arranged along a second direction Y may be aligned in the second direction Y. For example, four columns of first pixel circuits may be arranged within a column of first sub-regions. In some examples, the first pixel circuits within a plurality of second sub-regions arranged along the first direction X may be aligned in the first direction X, and the first pixel circuits within a plurality of second sub-regions arranged along the second direction Y may be aligned in the second direction Y. For example, four columns of first pixel circuits may be arranged within a column of second sub-regions.

[0306] In some examples, multiple rows of first sub-regions and multiple rows of second sub-regions can be arranged alternately along the second direction Y. For example, the first sub-region can be located at the i-th row and the i+2-th row, and the second sub-region can be located at the i+1-th row and the i+3-th row; the first pixel circuit 11c and the first pixel circuit 11d in the first sub-region can be roughly aligned with the first pixel circuit 11a and the first pixel circuit 11b in the adjacent second sub-region in the second direction Y, respectively.

[0307] In some examples, the fourth conductive layer may further include a plurality of tenth connection electrodes 410, each of which may be substantially strip-shaped and extend along the second direction Y. In the second direction Y, one end of the tenth connection electrode 410 is connected to the seventh connection electrode 407 located in the first sub-region, and the other end is connected to the seventh connection electrode 407 located in the second sub-region. For example, taking the first sub-region located in the (i+2)th row and the second sub-region located in the (i+1)th row as an example, the seventh connection electrode 407 in the first pixel circuit 11c in the first sub-region may be electrically connected to the seventh connection electrode 407 in the first pixel circuit 11a in the adjacent second sub-region via the tenth connection electrode 410, and the seventh connection electrode 407 in the first pixel circuit 11d in the first sub-region may be electrically connected to the seventh connection electrode 407 in the first pixel circuit 11b in the adjacent second sub-region via the tenth connection electrode 410, thereby electrically connecting the third initial signal line INIT3(i+1) in the (i+1)th row to the third initial signal line INIT3(i+2) in the (i+2)th row. In some examples, the tenth connection electrode 410 can be integrally formed with the seventh connection electrode 407 to which it is connected. The solution provided by the embodiments of the present disclosure connects the third initial signal lines of two adjacent rows together (for example, the third initial signal lines of the i+1th row are electrically connected to the third initial signal lines of the i+2th row, and the third initial signal lines of the i+3th row are electrically connected to the third initial signal lines of the i+4th row) via the seventh connection electrode 407 and the tenth connection electrode 410. This allows the initial signals provided to the first pixel circuits of the two adjacent rows to be substantially consistent, thereby improving display uniformity.

[0308] In other embodiments, FIG13D is a schematic diagram of the first display area after the fourth conductive layer is formed in FIG6 . FIG13E is a schematic diagram of the fourth conductive layer in FIG13D . FIG13C is a schematic diagram of a first sub-region and a second sub-region in FIG13A . As shown in FIG13D to FIG13F , the first pixel circuit 11a and the first pixel circuit 11b may not share a ninth connection electrode 409, and the first pixel circuit 11c and the first pixel circuit 11d may not share a ninth connection electrode 409. That is, the first pixel circuit 11a, the first pixel circuit 11b, the first pixel circuit 11c, and the first pixel circuit 11d are electrically connected to four ninth connection electrodes 409, respectively.

[0309] (109) A sixth insulating layer and a seventh insulating layer are formed. In some examples, a sixth insulating film is deposited on the substrate on which the aforementioned pattern is formed, and then a seventh insulating film is coated. The seventh insulating film and the sixth insulating film are patterned by a patterning process to form the sixth insulating layer and the seventh insulating layer. In some examples, the sixth insulating layer may also be referred to as a passivation layer, and the seventh insulating layer may also be referred to as a first planarization layer.

[0310] Figure 14A is a schematic diagram of a first sub-region and a second sub-region after forming the seventh insulating layer, and Figure 14B is a partially enlarged schematic diagram of Figure 14A. In some examples, as shown in Figures 14A and 14B, the seventh insulating layer of the first display area can be provided with multiple vias, for example, including vias 18 through 20 (V18 through V20). The seventh and sixth insulating layers within vias 18 through V20 can be removed, exposing a portion of the surface of the fourth conductive layer.

[0311] In some examples, the orthographic projection of the eighteenth via hole V18 on the substrate is located within the range of the orthographic projection of the first connection electrode 401 on the substrate, and the seventh insulating layer and the sixth insulating layer in the eighteenth via hole V18 can be removed to expose the surface of the first connection electrode 401. The eighteenth via hole V18 is configured to allow a subsequently formed data line to be connected to the first connection electrode 401 through the via hole.

[0312] In some examples, the orthographic projection of the nineteenth via hole V19 on the substrate is within the range of the orthographic projection of the fifth connection electrode 405 on the substrate. The seventh insulating layer and the sixth insulating layer within the nineteenth via hole V19 can be removed, exposing the surface of the fifth connection electrode 405. The nineteenth via hole V19 is configured to connect a subsequently formed first power connection electrode to the fifth connection electrode 405 through the via hole. In some examples, in the first sub-region, the first sub-pixel 11b and the first sub-pixel 11c can share one nineteenth via hole V19; and in the first sub-region, the first sub-pixel 11b and the first sub-pixel 11c can share one nineteenth via hole V19.

[0313] In some examples, the orthographic projection of the twentieth via hole V20 on the substrate is within the range of the orthographic projection of the sixth connection electrode 406 on the substrate, and the seventh insulating layer and the sixth insulating layer within the twentieth via hole V20 can be removed to expose the surface of the sixth connection electrode 406. The twentieth via hole V20 is configured to connect a subsequently formed first anode connection electrode to the sixth connection electrode 406 through the via hole.

[0314] (110) Forming a fifth conductive layer. In some examples, a fifth conductive film is deposited on the substrate having the aforementioned pattern formed thereon, and the fifth conductive film is patterned by a patterning process to form a fifth conductive layer on the seventh insulating layer. In some examples, the fifth conductive layer may also be referred to as a second source / drain metal layer.

[0315] Figure 15A is a schematic diagram of the first display area after forming the fifth conductive layer. Figure 15B is a schematic diagram of the fifth conductive layer in Figure 15A. Figure 15C is a partially enlarged schematic diagram of Figure 15A.

[0316] In some examples, as shown in Figures 15A to 15C, the fifth conductive layer of the first display area may include at least: multiple data lines (for example, data lines DL(j-4), DL(j-3), DL(j-2), DL(j-1), DL(j), DL(j+1), DL(j+2), DL(j+3), DL(j+4), DL(j+5), DL(j+6), DL(j+7)), multiple first anode connecting electrodes (for example, first anode connecting electrodes 422a, 422b, 422c and 422d), multiple first power connecting electrodes (for example, first power connecting electrodes 423a, 423b and 423c), and multiple first shielding electrodes (for example, first shielding electrodes 421a and 421b).

[0317] In some examples, the plurality of data lines may be roughly in the shape of a zigzag line extending along the second direction Y. The four first sub-pixels in each first sub-region are electrically connected to the four data lines in a one-to-one correspondence, and the four first sub-pixels in each second sub-region are electrically connected to the four data lines in a one-to-one correspondence. The data line may be electrically connected to the corresponding first connection electrode 401 through the eighteenth via hole V18, thereby being electrically connected to the fourth transistor of the first pixel circuit. For example, in the first sub-region, the data line DL(j+2) may be electrically connected to the corresponding first connection electrode 401 through the eighteenth via hole V18, thereby being electrically connected to the fourth transistor of the first pixel circuit 11a, the data line DL(j+3) may be electrically connected to the first connection electrode 401 through the eighteenth via hole V18, thereby being electrically connected to the fourth transistor of the first pixel circuit 11b, the data line DL(j+4) may be electrically connected to the fourth transistor of the first pixel circuit 11c, and the data line DL (j+5) can be electrically connected to the fourth transistor of the first pixel circuit 11d; in the second sub-area, the data line DL(j+4) can be electrically connected to the corresponding first connection electrode 401 through the eighteenth via hole V18, thereby being electrically connected to the fourth transistor of the first pixel circuit 11a, the data line DL(j+5) can be electrically connected to the first connection electrode 401 through the eighteenth via hole V18, thereby being electrically connected to the fourth transistor of the first pixel circuit 11b, the data line DL(j+6) can be electrically connected to the fourth transistor of the first pixel circuit 11c, and the data line DL(j+7) can be electrically connected to the fourth transistor of the first pixel circuit 11d.

[0318] In some examples, two data lines electrically connected to two first pixel circuits in the first sub-region can be divided into two groups to bypass the fourth sub-region adjacent to the first sub-region in the second direction Y. The other two data lines electrically connected to the first pixel circuits can extend to the second sub-region and can be electrically connected to the two first pixel circuits in the second sub-region, respectively. For example, the data line DL(j+2) connected to the first pixel circuit 11a can bypass the adjacent fourth sub-region in the second direction Y from the side opposite to the first direction X; the data line DL(j+3) connected to the first pixel circuit 11b can bypass the adjacent fourth sub-region in the second direction Y from the side of the first direction X; the data line DL(j+4) connected to the first pixel circuit 11c can extend along the second direction Y to the second sub-region and be electrically connected to the first pixel circuit 11a in the second sub-region; and the data line DL(j+5) connected to the first pixel circuit 11d can extend along the second direction Y to the second sub-region and be electrically connected to the first pixel circuit 11b in the second sub-region. In this example, by setting the data lines to bend and bypass the fourth sub-region, the space occupied by the wiring can be reduced, thereby improving the light transmittance of the first display area. In the embodiment of the present disclosure, the number of data lines can be reduced by sharing a data line between the first pixel circuit 11c in the first sub-area and the first pixel circuit 11a in the second sub-area, and sharing a data line between the first pixel circuit 11d in the first sub-area and the first pixel circuit 11b in the second sub-area, which is beneficial to reducing the space occupied by the wiring, thereby improving the light transmittance of the first display area.

[0319] In some examples, two data lines electrically connected to two first pixel circuits in the second sub-region can be divided into two groups to bypass a third sub-region adjacent to the first sub-region in the second direction Y. The other two data lines electrically connected to the first pixel circuits can extend to the first sub-region and can be electrically connected to the two first pixel circuits in the first sub-region, respectively. For example, the data line DL(j+1) connected to the first pixel circuit 11d can bypass the adjacent third sub-region in the second direction Y from one side of the first direction X; the data line DL(j) connected to the first pixel circuit 11c can bypass the adjacent third sub-region in the second direction Y from the side opposite to the first direction X; the data line DL(j-1) connected to the first pixel circuit 11b can extend along the second direction Y to the first sub-region and be electrically connected to the first pixel circuit 11d in the first sub-region; and the data line DL(j-2) connected to the first pixel circuit 11a can extend along the second direction Y to the first sub-region and be electrically connected to the first pixel circuit 11c in the first sub-region. In this example, by setting the data lines to bend and bypass the third sub-region, the space occupied by the wiring can be reduced, thereby improving the light transmittance of the first display area. In the embodiment of the present disclosure, the number of data lines can be reduced by sharing a data line between the first pixel circuit 11c in the first sub-area and the first pixel circuit 11a in the second sub-area, and sharing a data line between the first pixel circuit 11d in the first sub-area and the first pixel circuit 11b in the second sub-area, which is beneficial to reducing the space occupied by the wiring, thereby improving the light transmittance of the first display area.

[0320] In some examples, the shape of the first anode connection electrodes 422a, 422b, 422c, and 422d can be substantially rectangular. In the first sub-region, the first anode connection electrodes 422a and 422b can be located between the data lines DL(j+2) and DL(j+3), and the first anode connection electrodes 422c and 422d can be located between the data lines DL(j+4) and DL(j+5). In the second sub-region, the first anode connection electrodes 422a and 422b can be located between the data lines DL(j+4) and DL(j+5), and the first anode connection electrodes 422c and 422d can be located between the data lines DL(j+6) and DL(j+7).

[0321] In some examples, the first anode connection electrode can be electrically connected to the sixth connection electrode 406 through the twentieth via hole V20. For example, the first anode connection electrode 422a can be electrically connected to the corresponding sixth connection electrode 406 through the twentieth via hole V20, thereby achieving electrical connection with the sixth transistor of the corresponding first pixel circuit 11a; the first anode connection electrode 422b can be electrically connected to the corresponding sixth connection electrode 406 through the twentieth via hole V20, thereby achieving electrical connection with the sixth transistor of the first pixel circuit 11b; the first anode connection electrode 422c can be electrically connected to the sixth transistor of the first pixel circuit 11c; and the first anode connection electrode 422d can be electrically connected to the sixth transistor of the first pixel circuit 11d.

[0322] In some examples, the shapes of the first power connection electrodes 423a, 423b, and 423c can be substantially rectangular. Within the first sub-region, in the first direction X, the first power connection electrode 423a can be located on the side of the data line DL(j+2) opposite to the first direction X, the first power connection electrode 423b can be located between the data lines DL(j+3) and DL(j+4), and the first power connection electrode 423c can be located between the data lines DL(j+5) and DL(j+6). Within the second sub-region, in the first direction X, the first power connection electrode 423a can be located between the data lines DL(j+3) and DL(j+4), the first power connection electrode 423b can be located between the data lines DL(j+5) and DL(j+6), and the first power connection electrode 423c can be located on the side of the data line DL(j+5) in the first direction X.

[0323] In some examples, the first power connection electrode can be electrically connected to the fifth connection electrode 405 through the nineteenth via hole V19, thereby achieving electrical connection with the fifth transistor and storage capacitor of the first pixel circuit. For example, the first power connection electrode 423a can be electrically connected to the fifth connection electrode 405 through the nineteenth via hole V19, thereby achieving electrical connection with the fifth transistor and storage capacitor of the first pixel circuit 11a; the second power connection electrode 423b can be electrically connected to the corresponding fifth connection electrode 405 through the nineteenth via hole V19, thereby achieving electrical connection with the fifth transistor and storage capacitor of the first pixel circuits 11b and 11c; and the third power connection electrode 423c can be electrically connected to the fifth transistor and storage capacitor of the first pixel circuit 11d.

[0324] In some examples, within the first sub-region, the first shielding electrodes 421a and 421b can be shaped approximately like an inverted n-shape; within the second sub-region, the first shielding electrodes 421a and 421b can be shaped approximately like an n-shape. Within the first sub-region, in the first direction X, the first shielding electrode 421a can be located between the data lines DL(j+2) and DL(j+3), and the first shielding electrode 421b can be located between the data lines DL(j+4) and DL(j+5). Within the second sub-region, in the first direction X, the first shielding electrode 421a can be located between the data lines DL(j+4) and DL(j+5), and the first shielding electrode 421b can be located between the data lines DL(j+6) and DL(j+7). The orthographic projection of the first shielding electrode 421a on the substrate can cover the orthographic projection of the second connecting electrode 402 on the substrate, thereby shielding the first node of the first pixel circuit 11a and the first node of the first pixel circuit 11b, thereby shielding the first nodes of the first pixel circuits 11a and 11b from the effects of other signals on the first nodes of the first pixel circuits 11a and 11b. The second shielding electrode 421b can shield the first node of the first pixel circuit 11c and the first node of the first pixel circuit 11d, thereby shielding the influence of other signals on the first nodes of the first pixel circuits 11c and 11d.

[0325] (111) Forming an eighth insulating layer. In some examples, an eighth insulating film is coated on the substrate having the aforementioned pattern, and the eighth insulating film is patterned by a patterning process to form the eighth insulating layer. In some examples, the eighth insulating layer may also be referred to as a second planar layer.

[0326] Figure 16A is a schematic diagram of a first sub-region and a second sub-region after the eighth insulating layer is formed in Figure 6 , and Figure 16B is a partially enlarged schematic diagram of Figure 16A . In some examples, as shown in Figures 16A and 16B , the eighth insulating layer in the first display area can be provided with a plurality of vias, such as vias V21 through V23. The eighth insulating layer within vias V21 through V23 can be removed, exposing a portion of the surface of the fifth conductive layer.

[0327] In some examples, the orthographic projection of the twenty-first via V21 on the substrate is within the range of the orthographic projection of the first shielding electrode on the substrate. The eighth insulating layer within the twenty-first via V21 can be removed to expose the surface of the first shielding electrode. The twenty-first via V21 is configured to connect a subsequently formed first planarization electrode to the first shielding electrode through the via.

[0328] In some examples, the orthographic projection of the twenty-second via hole V22 on the substrate is within the range of the orthographic projection of the first power connection electrode on the substrate, and the eighth insulating layer within the twenty-second via hole V22 can be removed to expose the surface of the first power connection electrode. The twenty-second via hole V22 is configured to connect a subsequently formed first power line to the first power connection electrode through the via hole.

[0329] In some examples, the orthographic projection of the twenty-third via hole V23 on the substrate is within the range of the orthographic projection of the first anode connecting electrode on the substrate. The eighth insulating layer within the twenty-third via hole V23 can be removed to expose the surface of the first anode connecting electrode. The twenty-third via hole V23 is configured to connect a subsequently formed second anode connecting electrode to the first anode connecting electrode through the via hole.

[0330] (112) Forming a sixth conductive layer. In some examples, a sixth conductive film is deposited on the substrate having the aforementioned pattern formed thereon, and the sixth conductive film is patterned by a patterning process to form a sixth conductive layer on the eighth insulating layer. In some examples, the sixth conductive layer may also be referred to as a third source / drain metal layer.

[0331] Figure 17A is a schematic diagram of the first display area after forming the sixth conductive layer. Figure 17B is a schematic diagram of the sixth conductive layer in Figure 17A. Figure 17C is a partially enlarged schematic diagram of Figure 17A.

[0332] In some examples, as shown in Figures 17A to 17C, the sixth conductive layer of the first display area may include at least: a plurality of second anode connecting electrodes (for example, second anode connecting electrodes 431a, 431b, 431c and 431d), a plurality of first power lines (for example, first power lines 44a, 44b, 44c), a plurality of first power connection lines (for example, first power connection lines 45a, 45b), and a plurality of second power connection lines (for example, second power connection lines 46a, 46b).

[0333] In some examples, the first power line can be roughly in the shape of a zigzag line extending along the second direction Y. Of the four first pixel circuits in each first sub-region, in the first direction X, the two first pixel circuits located on both sides can be electrically connected to one first power line respectively, and the two first pixel circuits located in the middle can be electrically connected to one of the first power lines; of the four first pixel circuits in each second sub-region, in the first direction X, the two first pixel circuits located on both sides can be electrically connected to one first power line respectively, and the two first pixel circuits located in the middle can be electrically connected to one of the first power lines. The first power line can be electrically connected to the fifth transistor of the corresponding first pixel circuit through the twenty-second via V22. For example, in the first sub-region, the first power line 44a can be electrically connected to the first power connection electrode 423a through the 22nd via hole V22, thereby realizing electrical connection with the fifth transistor of the first pixel circuit 11a, the first power line 44b can be electrically connected to the first power connection electrode 423b through the 22nd via hole V22, thereby realizing electrical connection with the fifth transistors of the first pixel circuits 11b and 11c, and the first power line 44c can be electrically connected to the first power connection electrode 423c through the 22nd via hole V22, thereby realizing electrical connection with the fifth transistor of the first pixel circuit 11d. In the second sub-region, the first power line 44a can be electrically connected to the first power connection electrode 423c through the twenty-second via hole V22, thereby realizing electrical connection with the fifth transistor of the first pixel circuit 11d, and the first power line 44b can be electrically connected to the first power connection electrode 423b through the twenty-second via hole V22, thereby realizing electrical connection with the fifth transistors of the first pixel circuits 11b and 11c, and the first power line 44c can be electrically connected to the first power connection electrode 423a through the twenty-second via hole V22, thereby realizing electrical connection with the fifth transistor of the first pixel circuit 11a.

[0334] In some examples, two of the first power lines in the first sub-region can be divided into two groups to bypass the fourth sub-region adjacent to the first sub-region in the second direction Y, and be electrically connected to one of the first pixel circuits located at both ends of the second sub-region in the first direction X. Another first power line can extend to the second sub-region and can be electrically connected to the two first pixel circuits located in the middle of the second sub-region in the first direction X. For example, within the first sub-region, the first power line 44a connected to the first pixel circuit 11a can bypass the adjacent fourth sub-region in the second direction Y from the side opposite to the first direction X and electrically connect to the first pixel circuit 11c in the second sub-region. The first power line 44b connected to the first pixel circuit 11b and the first pixel circuit 11c can bypass the adjacent fourth sub-region in the second direction Y from the side of the first direction X and electrically connect to the first pixel circuit 11a in the second sub-region. The first power line 44c connected to the first pixel circuit 11d can extend along the second direction Y to the second sub-region and electrically connect to the first pixel circuit 11b and the first pixel circuit 11c in the second sub-region. In this example, by bending the data line around the fourth sub-region, the space occupied by the wiring is reduced, the obstruction of the fourth sub-region is reduced, and the light transmittance of the first display region is improved. The three first power lines located within the first sub-region do not overlap with the orthographic projections of the third sub-region adjacent to the first sub-region in the first direction X on the substrate, and will not obstruct the third sub-region, thereby improving the light transmittance of the first display region.

[0335] In some examples, the first power connection line 45 a may be shaped substantially like a strip extending along the second direction Y. In the first sub-region, the first power connection line 45 a may be electrically connected to the first shielding electrode 421 a through the twenty-first via hole V21; in the second sub-region, the first power connection line 45 a may be electrically connected to the first shielding electrode 421 b through the twenty-first via hole V21.

[0336] In some examples, the first power connection line 45b may be shaped substantially like a zigzag line extending along the second direction Y. In the first sub-region, the first power connection line 45b is electrically connected to the first shielding electrode 421b through the twenty-first via V21. In the second sub-region, the first power connection line is electrically connected to the first shielding electrode 421a through the twenty-first via V21. Multiple first shielding electrodes 421b and first shielding electrode 421a in the same column may be electrically connected to the same first power connection line 45b.

[0337] In some examples, the second power connection lines 46a and 46b are in the shape of a broken line extending along the first direction X. In the second direction Y, in the first sub-area and the second sub-area, the second power connection lines 46a and the second power connection lines 46b are respectively roughly located at the two ends of the first power connection line 45a, and are integrally formed with the first power connection lines 45a, 45b and the first power lines 44a, 44b, and 44c. The second power connection lines 46a and 46b are interconnected with the first power lines (44a, 44b, and 44c) and the first power connection lines (45a and 45b) to form a grid structure, so that the power signal provided by the first power line 44 to the display substrate is kept as consistent as possible. In the first sub-region and the second sub-region, the second power connection lines 46a, 46b are interconnected with the first power connection lines (45a, 45b) and the first power lines 44a, 44b, 44c) to form four accommodating areas, which respectively accommodate the four second anode connection electrodes 431a, 431b, 431c and 431d in the first sub-region and the second sub-region. In an exemplary embodiment, in the second direction, the second power connection lines 46a and 46b bypass along both sides of the third sub-region, so that the second power connection lines 46a and 46b and the first power connection lines 45a and 45b form a first hollow area K01 in the third sub-region, and the orthographic projection of the first hollow area K01 on the substrate at least partially overlaps with the orthographic projection of the third sub-region on the substrate, thereby preventing the second power connection lines 46a and 46b and the first power connection lines 45a and 45b from blocking the third sub-region; in the second direction, the second power connection lines 46a and 46b bypass along both sides of the fourth sub-region, so that the second power connection lines 46a and 46b and the first power connection lines 45a and 45b form a second hollow area K02 in the fourth sub-region, and the orthographic projection of the second hollow area K02 on the substrate at least partially overlaps with the orthographic projection of the fourth sub-region on the substrate, thereby preventing the second power connection lines 46a and 46b and the first power connection lines 45a and 45b from blocking the fourth sub-region.

[0338] In some examples, the second anode connection electrode 431a can be electrically connected to the first anode connection electrode 422a through the twenty-third via V23 to achieve electrical connection to the sixth transistor of the first pixel circuit 11a; in the first sub-region, the shape of the second anode connection electrode 431a can be roughly a rectangle extending along the second direction Y, and in the first direction X, the second anode connection electrode 431a can be located between the first power line 44a and the first planarization electrode 45a; in the second sub-region, the shape of the second anode connection electrode 431a can be roughly a rectangle extending along a direction intersecting both the first direction X and the second direction Y, and in the first direction X, the second anode connection electrode 431a can be located between the first power line 44b and the first planarization electrode 45b.

[0339] In some examples, the second anode connection electrode 431b can be electrically connected to the first anode connection electrode 422b through the twenty-third via V23 to achieve electrical connection to the sixth transistor of the first pixel circuit 11b; within the first sub-region, the shape of the second anode connection electrode 431b can be roughly a rectangle extending along the second direction Y, and in the first direction X, the second anode connection electrode 431b can be located between the first power line 44b and the first planarization electrode 45a; in the second sub-region, the shape of the second anode connection electrode 431b can be roughly a rectangle extending along the second direction Y, and in the first direction X, the second anode connection electrode 431b can be located between the first power line 44c and the first planarization electrode 45b.

[0340] In some examples, the second anode connection electrode 431c can be electrically connected to the first anode connection electrode 422c through the twenty-third via V23 to achieve electrical connection to the sixth transistor of the first pixel circuit 11c; within the first sub-region, the shape of the second anode connection electrode 431c can be roughly a rectangle extending along the first direction X, and in the first direction X, the second anode connection electrode 431c can be located between the first power line 44b and the first planarization electrode 45b; in the second sub-region, the shape of the second anode connection electrode 431c can be roughly a rectangle extending along the second direction Y, and in the first direction X, the second anode connection electrode 431c can be located between the first power line 44c and the first planarization electrode 45a.

[0341] In some examples, in some examples, the second anode connection electrode 431d can be electrically connected to the first anode connection electrode 422d through the twenty-third via V23 to achieve electrical connection to the sixth transistor of the first pixel circuit 11d; within the first sub-region, the shape of the second anode connection electrode 431d can be approximately a rectangle extending along a direction intersecting both the first direction X and the second direction Y, and in the first direction X, the second anode connection electrode 431d can be located between the first power line 44c and the first planarization electrode 45b; in the second sub-region, the shape of the second anode connection electrode 431d can be approximately a rectangle extending along a direction intersecting both the first direction X and the second direction Y, and in the first direction X, the second anode connection electrode 431d can be located between the first power line 44a and the first planarization electrode 45a.

[0342] (113) Forming a ninth insulating layer. In some examples, a ninth insulating film is coated on the substrate on which the aforementioned pattern is formed, and the ninth insulating film is patterned by a patterning process to form a ninth insulating layer. In some examples, the ninth insulating layer may also be referred to as a third planar layer.

[0343] Figure 18A is a schematic diagram of the first display area after the ninth insulating layer is formed, and Figure 18B is a partially enlarged schematic diagram of Figure 18A. In some examples, as shown in Figures 18A and 18B, the ninth insulating layer in the first display area can have multiple vias, such as multiple twenty-fourth vias V24. The ninth insulating layer within the twenty-fourth vias V24 can be removed, exposing a portion of the surface of the sixth conductive layer.

[0344] In some examples, the orthographic projection of the twenty-fourth via hole V24 on the substrate is within the range of the orthographic projection of the second anode connecting electrode on the substrate. The ninth insulating layer within the twenty-fourth via hole V24 can be removed to expose the surface of the second anode connecting electrode. The twenty-fourth via hole V24 is configured to allow a subsequently formed second anode connecting electrode to be connected to the second anode connecting electrode through the via hole.

[0345] At this point, the circuit structure layer can be prepared. The film structure of the circuit structure layer in the second display area is similar to that of the first display area, so it will not be described in detail here.

[0346] In an exemplary embodiment, after the circuit structure layer is prepared, a light-emitting structure layer is prepared on the circuit structure layer. The preparation process of the light-emitting structure layer may include the following operations: forming a fourth flat layer pattern, wherein at least an anode via is provided on the fourth flat layer; forming an anode pattern (i.e., an anode conductive layer), wherein the anode is connected to the anode connection electrode through the anode via; forming a pixel definition layer, wherein a pixel opening is provided on the pixel definition layer, wherein the pixel opening exposes the anode; forming an organic light-emitting layer by a vapor deposition or inkjet printing process, wherein the organic light-emitting layer is connected to the anode through the pixel opening, and a cathode is formed on the organic light-emitting layer; forming an encapsulation layer, wherein the encapsulation layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together, wherein the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials, and the second encapsulation layer is provided between the first encapsulation layer and the third encapsulation layer, to ensure that external water vapor cannot enter the light-emitting structure layer. The steps for forming the anode conductive layer and the pixel definition layer are as follows:

[0347] (114) Forming an anode conductive layer. In some examples, a tenth insulating film is coated on the substrate on which the aforementioned pattern is formed, and the tenth insulating film is patterned by a patterning process to form a tenth insulating layer. In some examples, the tenth insulating layer can also be referred to as a fourth flat layer. The tenth insulating layer can be provided with a plurality of anode vias, and the plurality of anode vias can expose a portion of the surface of the conductive connection layer. The orthographic projections of the plurality of anode vias on the substrate respectively overlap at least partially with the orthographic projections of the plurality of twenty-fourth vias V24 on the substrate. Subsequently, an anode film is deposited on the substrate on which the aforementioned pattern is formed, and the anode film is patterned by a patterning process to form an anode conductive layer.

[0348] Figure 19A is a schematic diagram of the first display area after forming the anode layer. Figure 19B is a schematic diagram of the anode conductive layer in Figure 19A. Figure 19C is a partially enlarged schematic diagram of Figure 19A.

[0349] In some examples, as shown in Figures 19A to 19C, the first display area can include: anodes of multiple light-emitting elements (e.g., anode 211a of the light-emitting element, anode 211b of the light-emitting element, anode 211c of the light-emitting element, anode 211d of the light-emitting element).

[0350] In some examples, in the first and second subregions, the anode 211a of the light-emitting element emitting the first color light can be electrically connected to the second anode connection electrode 431a through the anode via hole on the tenth insulating layer and the twenty-fourth via hole V24 opened in the ninth insulating layer. The anode 211b of the light-emitting element emitting the second color light can be electrically connected to the second anode connection electrode 431b through the anode via hole on the tenth insulating layer and the twenty-fourth via hole V24 opened in the ninth insulating layer. The anode 211c of the light-emitting element emitting the third color light can be electrically connected to the second anode connection electrode 431c through the anode via hole on the tenth insulating layer and the twenty-fourth via hole V24 opened in the ninth insulating layer. The anode 211d of the light-emitting element emitting the fourth color light can be electrically connected to the second anode connection electrode 431d through the anode via hole on the tenth insulating layer and the twenty-fourth via hole V24 opened in the ninth insulating layer. In another first sub-region and second sub-region adjacent to one of the first sub-regions and second sub-regions in the row direction, the anode 211a of the light-emitting element emitting the first color light can be electrically connected to the second anode connection electrode 431c via the anode via hole on the tenth insulating layer and the twenty-fourth via hole V24 provided in the ninth insulating layer. The anode 211b of the light-emitting element emitting the second color light can be electrically connected to the second anode connection electrode 431b via the anode via hole on the tenth insulating layer and the twenty-fourth via hole V24 provided in the ninth insulating layer. The anode 211c of the light-emitting element emitting the third color light can be electrically connected to the second anode connection electrode 431a via the anode via hole on the tenth insulating layer and the twenty-fourth via hole V24 provided in the ninth insulating layer. The anode 211d of the light-emitting element emitting the fourth color light can be electrically connected to the second anode connection electrode 431d via the anode via hole on the tenth insulating layer and the twenty-fourth via hole V24 provided in the ninth insulating layer.

[0351] In an exemplary embodiment, the area of ​​the anode 211a of the light-emitting element emitting the first color light may be larger than the area of ​​the anode 211b of the light-emitting element emitting the second color light and the area of ​​the anode 211d of the light-emitting element emitting the fourth color light. The area of ​​the anode 211c of the light-emitting element emitting the third color light may be smaller than the area of ​​the anode 211a of the light-emitting element emitting the first color light and larger than the area of ​​the anode 211b of the light-emitting element emitting the second color light and the area of ​​the anode 211d of the light-emitting element emitting the fourth color light. In an exemplary embodiment, the area of ​​the anode 211b of the light-emitting element emitting the second color light and the area of ​​the anode 211d of the light-emitting element emitting the fourth color light may be equal. In an exemplary embodiment, the light-emitting element emitting the first color light may be light-emitting element B that emits blue light, the light-emitting element emitting the second color light and the light-emitting element emitting the fourth color light may be light-emitting element G that emits green light, and the light-emitting element emitting the third color light may be light-emitting element R that emits red light.

[0352] In some examples, the anode of the light-emitting element may include a main body 210 and a connecting portion 200, the connecting portion 212 is provided on one side of the main body 210, and may be an integrally formed structure with the main body 210, and the connecting portion 200 is electrically connected to the corresponding second anode connection electrode through the anode via on the tenth insulating layer and the twenty-fourth via V24 opened in the ninth insulating layer. The main body 210 of the anode may be circular or elliptical, and the connecting portion 200 may be a roughly strip-shaped structure extending in one direction. In an exemplary embodiment of the present disclosure, the main body 210 is connected to the corresponding second anode connection electrode through the connecting portion 200, so that the orthographic projection of the main body 210 of the anode on the substrate does not overlap with the orthographic projection of the anode via and the twenty-fourth via on the substrate, thereby avoiding the via causing the flatness of the anode main body 210 to decrease, and the flatness of the main body 210 of the anode can be improved.

[0353] (115) Forming a pixel definition layer. In some examples, a pixel definition film is coated on the substrate formed with the aforementioned pattern, and the pixel definition layer is formed through masking, exposure, and development processes. The pixel definition layer may be formed with a plurality of pixel openings that expose the anode layer.

[0354] Figure 20A is a schematic diagram of the first display area after forming the pixel definition layer. Figure 20B is a schematic diagram of the pixel definition layer in Figure 20A. Figure 20C is a partially enlarged schematic diagram of Figure 20A.

[0355] In some examples, as shown in Figures 20A to 20C, the first display area may include: a plurality of pixel openings (e.g., pixel opening 212a, pixel opening 212b, pixel opening 212c, and pixel opening 212d). The orthographic projection of pixel opening 212a on the substrate at least partially overlaps with the orthographic projection of the corresponding anode 211a on the substrate, the orthographic projection of pixel opening 212b on the substrate at least partially overlaps with the orthographic projection of the corresponding anode 211b on the substrate, the orthographic projection of pixel opening 212c on the substrate at least partially overlaps with the orthographic projection of the corresponding anode 211c on the substrate, and the orthographic projection of pixel opening 212d on the substrate at least partially overlaps with the orthographic projection of the corresponding anode 211d on the substrate. For example, the orthographic projection of the pixel opening 212a on the substrate is located within the range of the orthographic projection of the main body 210 of the corresponding anode 211a on the substrate, and can expose a portion of the surface of the main body 210 of the anode 211a; the orthographic projection of the pixel opening 212b on the substrate is located within the range of the orthographic projection of the main body 210 of the corresponding anode 211b on the substrate, and can expose a portion of the surface of the main body 210 of the anode 211b; the orthographic projection of the pixel opening 212c on the substrate is located within the range of the orthographic projection of the main body 210 of the corresponding anode 211c on the substrate, and can expose a portion of the surface of the main body 210 of the anode 211c; the orthographic projection of the pixel opening 212d on the substrate is located within the range of the orthographic projection of the main body 210 of the corresponding anode 211d on the substrate, and can expose a portion of the surface of the main body 210 of the anode 211d.

[0356] In some examples, the shape of the pixel opening can be generally circular or elliptical.

[0357] In some examples, subsequent steps may include forming an organic light-emitting layer within the aforementioned pixel opening, the organic light-emitting layer being connected to the anode layer, and subsequently depositing a cathode film, patterning the cathode film through a patterning process to form a cathode pattern, the cathode being connected to the organic light-emitting layer.

[0358] In some examples, the light-emitting area of ​​a light-emitting element emitting the first color light can be larger than the light-emitting area of ​​a light-emitting element emitting the third color light. The light-emitting area of ​​a light-emitting element emitting the third color light can be larger than the light-emitting area of ​​a light-emitting element emitting the second color light or the light-emitting area of ​​a light-emitting element emitting the fourth extended light. The light-emitting areas of the light-emitting element emitting the second color light and the light-emitting element emitting the fourth color light can be the same, and the second and fourth colors of light can be the same. The light-emitting area of ​​a light-emitting element in this example can refer to the area of ​​the overlapping region of the anode, the organic light-emitting layer, and the cathode exposed by the pixel opening of the pixel definition layer.

[0359] In some examples, after the light emitting structure layer is prepared, an encapsulation layer may be formed on the cathode. The encapsulation layer may include a stacked structure of inorganic material / organic material / inorganic material.

[0360] In some examples, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON), and can be a single layer, a multi-layer, or a composite layer. The seventh insulating layer, the eighth insulating layer, and the ninth insulating layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The anode layer may be made of a reflective material such as metal, and the cathode layer may be made of a transparent conductive material. However, this embodiment is not limited thereto.

[0361] The structure of the display substrate of this embodiment and its preparation process are merely exemplary. In some exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. The preparation process of this exemplary embodiment can be implemented using currently mature preparation equipment and is well compatible with existing preparation processes. The process is simple to implement, easy to implement, with high production efficiency, low production cost, and high yield rate. The display substrate of the embodiment of the present disclosure can be applied to other display devices having pixel driving circuits, such as quantum dot displays, etc., and the present disclosure is not limited thereto.

[0362] In other embodiments, the preparation process of the display substrate is substantially the same as the above steps (101) to (115), except that the first conductive layer is formed in step (103), the third conductive layer is formed in step (106), the fifth insulating layer is formed in step (107), and the fourth conductive layer is formed in step (108). The differences between the first conductive layer, the third conductive layer, the fifth insulating layer, and the fourth conductive layer and the above embodiment are described in detail below in conjunction with Figures 21A to 24C:

[0363] In an exemplary embodiment, FIG21A is a schematic diagram of a planar structure after forming a first conductive layer, and FIG21B is a schematic diagram of the first conductive layer in FIG21A . FIG21C is a partially enlarged schematic diagram of FIG21A . As shown in FIG21A to FIG21C , the difference from FIG8A to FIG8C is that the emission control line EML(i+1) in the i+1th row and the emission control line EML(i+3) in the i+3th row are disconnected at the fourth sub-region, forming emission control electrodes EML0(i+1) and EML0(i+3).

[0364] In an exemplary embodiment, FIG22A is a schematic diagram of the planar structure after forming the third conductive layer, and FIG22B is a schematic diagram of the third conductive layer in FIG22A. FIG22C is an enlarged schematic diagram of a portion of FIG22A. As shown in FIG22A to FIG22C, the difference from FIG11A to FIG11C is that the third initial signal line INIT3(i+1) in the i+1th row and the third initial signal line INIT3(i+3) in the i+3th row are disconnected at the fourth sub-region, forming third initial signal electrodes INIT30(i+1) and INIT30(i+3). In an exemplary embodiment, the orthographic projection of the third initial signal electrode INIT30(i+1) on the substrate overlaps with the orthographic projection of the emission control electrode EML0(i+1) on the substrate, and the orthographic projection of the third initial signal electrode INIT30(i+3) on the substrate overlaps with and does not overlap with the orthographic projection of the emission control electrode EML0(i+3). For example, there is an overlapping area between the main part of the third initial signal electrode INIT30(i+1) and the main part of the light-emitting control electrode EML0(i+1) in their orthographic projections on the substrate, and at least one end of the third initial signal electrode INIT30(i+1) and at least one end of the light-emitting control electrode EML0(i+1) do not overlap in their orthographic projections on the substrate; there is an overlapping area between the main part of the third initial signal electrode INIT30(i+3) and the main part of the light-emitting control electrode EML0(i+3) in their orthographic projections on the substrate, and at least one end of the third initial signal electrode INIT30(i+3) and at least one end of the light-emitting control electrode EML0(i+3) do not overlap in their orthographic projections on the substrate.In an exemplary embodiment, the orthographic projection of the third initial signal line INIT30(i) on the substrate and the orthographic projection of the light-emitting control wire EML(i) on the substrate have overlapping areas and non-overlapping areas, and the orthographic projection of the third initial signal line INIT30(i+2) on the substrate and the orthographic projection of the light-emitting control wire EML(i+2) on the substrate have overlapping areas and non-overlapping areas; the orthographic projection of the third initial signal line INIT3(i) on the substrate and the non-overlapping area of ​​the orthographic projection of the light-emitting control wire EML(i) on the substrate, and the orthographic projection of the third initial signal electrode INIT30(i-1) on the substrate and the light-emitting control wire EML(i-1) on the substrate have overlapping areas and non-overlapping areas. The non-overlapping area of ​​the orthogonal projection of the light-emitting control electrode EML0(i-1) on the substrate is located on the same side of the third sub-region along the first direction X and on the same side of the fourth sub-region along the first direction X; the non-overlapping area of ​​the orthogonal projection of the third initial signal line INIT30(i+2) on the substrate and the orthogonal projection of the light-emitting control electrode EML(i+2) on the substrate, and the non-overlapping area of ​​the orthogonal projection of the third initial signal electrode INIT30(i+1) on the substrate and the orthogonal projection of the light-emitting control electrode EML0(i+1) on the substrate are located on the same side of the third sub-region along the first direction X and on the same side of the fourth sub-region along the first direction X.

[0365] In an exemplary embodiment, FIG23A is a schematic diagram of a planar structure after forming a fifth insulating layer, and FIG23B is a partially enlarged schematic diagram of FIG23A. As shown in FIG23A and FIG23B, the difference from FIG12A and FIG12B is that a first transfer via VM1, a second transfer via VM2, a third transfer via VM3, and a fourth transfer via VM4 are newly added. In an exemplary embodiment, the orthographic projection of the first transfer via VM1 on the substrate is located between the light-emitting control electrodes EML0(i+1) and EML0(i+3). Within the range of the orthographic projection on the substrate, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the first transfer via VM1 can be removed to expose the surfaces of the light-emitting control electrodes EML0(i+1) and EML0(i+3). The first transfer via VM1 is configured to electrically connect the first transfer electrode of the subsequent shape to the corresponding light-emitting control electrode through the via. The orthographic projection of the second transfer via VM2 on the substrate is within the range of the orthographic projection of the third initial signal electrodes INIT30(i+1) and INIT30(i+3) on the substrate. , the fifth insulating layer in the second transfer via VM2 can be removed to expose the surface of the third initial signal electrodes INIT30(i+1) and INIT30(i+3). The second transfer via VM2 is configured to electrically connect the subsequently formed second transfer electrode to the third initial signal electrodes INIT30(i+1) and INIT30(i+3) through the via. The orthographic projection of the third transfer via VM3 on the substrate is located within the range of the orthographic projection of the light emitting control electrode EML(i+2) in the i-th row and the light emitting control line EML(i+2) in the i+2-th row on the substrate. Within the enclosure, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the third transfer via VM3 can be removed to expose the surfaces of the light-emitting control line EML(i) in the i-th row and the light-emitting control line EML(i+2) in the i+2-th row. The third transfer via VM3 is configured to electrically connect the first transfer electrode of the subsequent shape to the corresponding light-emitting control line EML(i) in the i-th row and the light-emitting control line EML(i+2) in the i+2-th row through the via. The orthographic projection of the fourth transfer via VM4 on the substrate is located at the third initial signal line INIT3 in the i-th row. (i) and the third initial signal line INIT3(i+2) of the i+2th row are within the range of the positive projection on the substrate, the fifth insulating layer in the fourth transfer via VM4 can be removed to expose the surface of the third initial signal line INIT3(i) of the i-th row and the third initial signal line INIT3(i+2) of the i+2th row, and the fourth transfer via VM4 is configured to electrically connect the second transfer electrode of a subsequent shape to the corresponding third initial signal line INIT3(i) of the i-th row and the third initial signal line INIT3(i+2) of the i+2th row through the via.

[0366] In an exemplary embodiment, FIG24A is a schematic diagram of the planar structure after forming the fourth conductive layer, and FIG24B is a schematic diagram of the fourth conductive layer in FIG24A . FIG24C is a partially enlarged schematic diagram of FIG24A . As shown in FIG24A to FIG24C , the difference from FIG13A to FIG13C is the addition of a first transfer electrode ZL1 and a second transfer electrode ZL2. In an exemplary embodiment, in the first direction X, the first transfer electrode ZL1 and the second transfer electrode ZL2 are located on a side of the first pixel circuit 11d away from the first pixel circuit 11a, and the second transfer electrode ZL2 is located on a side of the first transfer electrode ZL1 away from the first pixel circuit 11d; in the second direction Y, the shapes of the first transfer electrode ZL1 and the second transfer electrode ZL2 can be roughly zigzag lines extending along the second direction Y. The first transfer electrode ZL1 and the second transfer electrode ZL2 can be located in two adjacent first pixel circuits. For example, in the first pixel circuits in the i+1th row and the i+2th row: the first transfer electrode ZL1 and the second transfer electrode ZL2 can extend along the second direction Y from the first pixel circuit in the i+1th row to the pixel circuit in the i+2th row, and one end of the first transfer electrode ZL1 passes through the first transfer via V M1 is electrically connected to the light-emitting control electrode EML0(i+1) of the i+1th row, and the other end is electrically connected to the light-emitting control wire EML(i+2) of the i+2th row through the third transfer via VM3, so that the light-emitting control wire EML(i+2) of the i+2th row can provide a light-emitting control signal to the first pixel circuit of the i+2th row and the first pixel circuit of the i+1th row; one end of the second transfer electrode ZL2 is electrically connected to the third initial signal electrode INIT30(i+1) located in the i+1th row through the second transfer via VM2, and the other end is electrically connected to the third initial signal line INIT3(i+2) located in the i+2th row through the fourth transfer via, so that the third initial signal line INIT3(i+2) of the i+2th row can provide an initial signal to the first pixel circuit of the i+2th row and the first pixel circuit of the i+1th row. Similarly, the emission control line EML(i+4) located in the i+4th row can provide emission control signals to the first pixel circuit in the i+4th row and the first pixel circuit in the i+3th row, and the third initial signal line INIT3(i+4) located in the i+4th row can provide initial signals to the first pixel circuit in the i+4th row and the first pixel circuit in the i+3th row. The solution provided by the embodiments of the present disclosure, in which one third initial signal line provides initial signals to two rows of first pixel circuits and one emission control line provides emission control signals to two rows of first pixel circuits, can reduce the number of signal traces, save space on the display substrate, and improve the transmittance of the display substrate (the transmittance of the third and fourth sub-regions can be improved).

[0367] In other embodiments, the preparation process of the display substrate is substantially the same as the above steps (101) to (115), except that the second conductive layer is formed in step (104), the third conductive layer is formed in step (106), the fifth insulating layer is formed in step (107), and the fourth conductive layer is formed in step (108). The differences between the second conductive layer, the third conductive layer, the fifth insulating layer, and the fourth conductive layer and the above embodiment are described in detail below in conjunction with Figures 25A to 28C:

[0368] In an exemplary embodiment, FIG25A is a schematic diagram of the planar structure after forming the second conductive layer, and FIG25B is a schematic diagram of the second conductive layer in FIG25A . FIG25C is a partially enlarged schematic diagram of FIG25A . As shown in FIG25A to FIG25C , the difference from FIG9A to FIG9C is that the second scanning auxiliary line GL2b(i+1) in the i+1th row and the second scanning auxiliary line GL2b(i+3) in the i+3th row are disconnected at the fourth sub-region, forming the second scanning auxiliary electrode GL2b0(i+1) and the second scanning auxiliary electrode GL2b0(i+3), and a plurality of third transfer electrodes ZL3 are added. In an exemplary embodiment, in the first direction X, the third switching electrode ZL3 is arranged on a side of the second scanning auxiliary line GL2b(i) and the second scanning auxiliary line GL2b(i+2) of the i+2th row close to the third sub-region, and in the second direction Y, the third switching connection electrode ZL3 is arranged on a side of the second scanning auxiliary line GL2b(i) of the i-th row and the second scanning auxiliary line GL2b(i+2) of the i+2th row along the second direction Y.

[0369] In an exemplary embodiment, FIG26A is a schematic diagram of the planar structure after forming the third conductive layer, and FIG26B is a schematic diagram of the third conductive layer in FIG26A. FIG26C is an enlarged schematic diagram of a portion of FIG26A. As shown in FIG26A to FIG26C, the difference from FIG11A to FIG11C is that the second scan line GL2(i+1) in the i+1th row and the second scan line GL2(i+3) in the i+3th row are disconnected at the fourth sub-region, forming the second scan electrode GL20(i+1) and the second scan electrode GL20(i+3). In an exemplary embodiment, the orthographic projection of the second scan electrode GL20(i+1) on the substrate overlaps with the orthographic projection of the second scan auxiliary electrode GL2b0(i+1) on the substrate, and the orthographic projection of the second scan auxiliary electrode GL2b0(i+3) on the substrate overlaps with and does not overlap with the orthographic projection of the second scan auxiliary electrode GL2b0(i+3). For example, the orthographic projections of the main portion of the second scan electrode GL20(i+1) and the main portion of the second scan auxiliary electrode GL2b0(i+1) on the substrate overlap, while the orthographic projections of at least one end portion of the second scan electrode GL20(i+1) and at least one end portion of the second scan auxiliary electrode GL2b0(i+1) on the substrate do not overlap. The orthographic projections of the main portion of the second scan electrode GL20(i+3) and the main portion of the second scan auxiliary electrode GL2b0(i+3) on the substrate overlap, while the orthographic projections of at least one end portion of the second scan electrode GL20(i+3) and at least one end portion of the second scan auxiliary electrode GL2b0(i+3) on the substrate do not overlap. In an exemplary embodiment, the non-overlapping region of the orthographic projections of the second scan electrode GL20(i+1) and the second scan auxiliary electrode GL2b0(i+1) on the substrate are located on the same side of the third sub-region along the first direction X and on the same side of the fourth sub-region along the first direction X as the orthographic projection of the third switching electrode ZL3 on the substrate.

[0370] In an exemplary embodiment, FIG27A is a schematic diagram of the planar structure after forming the fifth insulating layer, and FIG27B is a partially enlarged schematic diagram of FIG27A. As shown in FIG27A and FIG27B, the difference from FIG12A and FIG12B is that a fifth transfer via VM5, a sixth transfer via VM6, a seventh transfer via VM7, and an eighth transfer via VM8 are newly added. In an exemplary embodiment, the orthographic projection of the fifth transfer via VM5 on the substrate is within the range of the orthographic projection of the second scan auxiliary electrode on the substrate, the fifth insulating layer and the fourth insulating layer in the fifth transfer via VM5 can be removed to expose the surface of the second scan auxiliary electrode, and the fifth transfer via VM5 is configured to electrically connect a fourth transfer electrode of a subsequent shape to the corresponding second scan auxiliary electrode through the via; the orthographic projection of the sixth transfer via VM6 on the substrate is within the range of the orthographic projection of the third transfer electrode on the substrate, the fifth insulating layer and the fourth insulating layer in the sixth transfer via VM6 can be removed to expose the surface of the third transfer electrode, and the sixth transfer via VM6 is configured to electrically connect a fourth transfer electrode formed subsequently to the third transfer electrode through the via; the orthographic projection of the seventh transfer via VM7 on the substrate is within the range of the orthographic projection of the second scan electrode GL20(i+1) and the second scan electrode GL20(i+3) on the substrate, and the fifth insulating layer in the seventh transfer via VM7 can be removed. The surfaces of the second scanning electrode GL20(i+1) of the i+1th row and the second scanning electrode GL20(i+3) of the i+3th row are exposed, and the seventh transfer via VM7 is configured to electrically connect the fourth transfer electrode of the subsequent shape to the corresponding second scanning electrode GL20(i+1) of the i+1th row and the second scanning electrode GL20(i+3) of the i+3th row through the via; the orthographic projection of the eighth transfer via VM8 on the substrate is located at the second scanning line GL2(i+1) of the i+1th row and the second scanning electrode GL20(i+3) of the i+3th row. The second scan line GL2(i+3) is within the range of the positive projection on the substrate, the fifth insulating layer in the eighth transfer via VM8 can be removed to expose the surface of the second scan line GL2(i+1) of the i+1th row and the second scan line GL2(i+3) of the i+3th row, and the eighth transfer via VM8 is configured to electrically connect the fourth transfer electrode of the subsequent shape to the corresponding second scan line GL2(i+1) of the i+1th row and the second scan line GL2(i+3) of the i+3th row through the via.

[0371] In an exemplary embodiment, FIG28A is a schematic diagram of the planar structure after forming the fourth conductive layer, and FIG28B is a schematic diagram of the fourth conductive layer in FIG28A . FIG28C is a partially enlarged schematic diagram of FIG28A . As shown in FIG28A to FIG28C , the difference from FIG13A to FIG13C is the addition of a fourth transfer electrode ZL4. In an exemplary embodiment, in the first direction X, the four transfer electrodes ZL4 may be located on a side of the first pixel circuit 11a away from the first pixel circuit 11d; in the second direction Y, the shape of the four transfer electrodes ZL4 may be approximately a zigzag shape extending along the second direction Y, and the four transfer electrodes ZL4 may be located in two adjacent first pixel circuits. For example, in the first pixel circuits of the i+1th row and the i+2th row: the fourth transfer electrode ZL4 may extend from the first pixel circuit of the i+1th row to the pixel circuit of the i+2th row along the second direction Y, one end of the four transfer electrodes ZL4 is electrically connected to the second scanning auxiliary electrode GL2b0(i+1) of the i+1th row through the fifth transfer via VM5, and the other end is electrically connected to the second scanning auxiliary electrode GL2b0(i+1) of the i+1th row through the sixth transfer via VM5. The via VM6 is electrically connected to the second scanning auxiliary line GL2b(i+2) in the i+2th row, so that the second scanning auxiliary line GL2b(i+2) in the i+2th row can provide signals to the first pixel circuit in the i+2th row and the first pixel circuit in the i+1th row; one end of the fourth transfer electrode ZL4 can also be electrically connected to the second scanning electrode GL20(i+1) located in the i+1th row through the seventh transfer via VM7, and the other end is electrically connected to the second scanning line GL2(i+2) located in the i+2th row through the eighth transfer via VM8, so that the second scanning line GL2(i+2) in the i+2th row can provide the second scanning signal to the first pixel circuit in the i+2th row and the first pixel circuit in the i+1th row. Similarly, the second scan line GL2(i+4) located in the i+4th row can provide a second scan signal to the first pixel circuit in the i+4th row and the first pixel circuit in the i+3th row, and the second scan auxiliary electrode GL2b0(i+4) located in the i+4th row can provide a signal to the first pixel circuit in the i+4th row and the first pixel circuit in the i+3th row. The solution provided by the embodiment of the present disclosure can provide signals to two rows of first pixel circuits through a second scan auxiliary line and provide scan signals to two rows of first pixel circuits through a second scan line, which can reduce the number of signal lines, save space on the display substrate, and improve the transmittance of the display substrate (the transmittance of the third sub-area and the fourth sub-area can be improved).

[0372] In an exemplary embodiment, the first direction X may be the row direction X described above, and the second direction Y may be the column direction Y described above.

[0373] An embodiment of the present disclosure also provides a display device, as shown in Figure 29, the display device may include the display substrate described in any of the above embodiments and a sensor located on the non-display surface side of the display substrate, the display substrate may include a first display area, and the sensor's orthographic projection on the display substrate at least partially overlaps with the first display area of ​​the display substrate.

[0374] In an exemplary embodiment, as shown in FIG1 , the display substrate may include a first display area A1 and a second display area A2. The second display area A2 may be located on at least one side of the first display area A1. For example, the second display area A2 may be disposed around the first display area A1. In some examples, as shown in FIG1 , the first display area A1 may be a light-transmitting display area, which may also be referred to as a Full Display With Camera (FDC) area; the second display area A2 may be referred to as a normal display area. For example, the orthographic projection of a sensor (e.g., hardware such as a camera) on the display substrate may be located within the first display area A1 of the display substrate. In some examples, as shown in FIG1 , the first display area A1 may be circular, and the size of the orthographic projection of the sensor on the display substrate may be less than or equal to the size of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area A1 may be rectangular, and the size of the orthographic projection of the sensor on the display substrate may be less than or equal to the size of the inscribed circle of the first display area A1.

[0375] In an exemplary embodiment, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation device.

[0376] The present disclosure also provides a method for driving a display substrate, configured to drive the display substrate described in any of the above embodiments, wherein the display substrate includes K rows of sub-pixels and a plurality of signal lines extending along the row direction, wherein the number of the same signal lines is a positive integer less than or equal to K, and each row of sub-pixels is electrically connected to one of the same signal lines. As shown in FIG30 , the driving method includes:

[0377] At least some of the at least one signal line provide effective signals to at least two rows of sub-pixels.

[0378] In an exemplary embodiment, at least some of the at least one signal line provide effective signals to two adjacent rows of sub-pixels at the same time.

[0379] In an exemplary embodiment, the at least one signal line includes a first type of signal line, and the first type of signal line includes at least a first reset control line and a first initial signal line;

[0380] Among the first type of signal lines, of two adjacent signal lines of the same type, one signal line is configured to simultaneously provide valid signals to sub-pixels in the i-th row and sub-pixels in the i+1-th row, and the other signal line is configured to simultaneously provide valid signals to sub-pixels in the i+2-th row and sub-pixels in the i+3-th row, where i is an integer greater than or equal to 1 and less than K. For example, as shown in FIG4A and FIG31 , of two adjacent first reset control lines among the plurality of first reset control lines, one first reset control line (e.g., the first reset control line Reset1(i) / Reset1(i+1) shared by sub-pixels in the i-th row and the i+1-th row) is configured to simultaneously provide first reset signals to sub-pixels in the i-th row and sub-pixels in the i+1-th row, and the other first reset control line (e.g., the first reset control line Reset1(i+2) / Reset1(i+3) shared by sub-pixels in the i+2-th row and the i+3-th row) is configured to simultaneously provide first reset signals to sub-pixels in the i+2-th row and sub-pixels in the i+3-th row. As shown in Figure 4B, two adjacent first initial signal lines among the multiple first initial signal lines, one of the first initial signal lines (for example, the first initial signal line INIT1(i) / INIT1((i+1)) shared by the sub-pixels in the i-th row and the i+1-th row) is set to simultaneously provide the first reset signal to the sub-pixels in the i-th row and the sub-pixels in the i+1-th row, and the other first reset control line (for example, the first reset control line INIT1((i+2) / INIT1((i+3)) shared by the sub-pixels in the i+2-th row and the i+3-th row) is set to simultaneously provide the first reset signal to the sub-pixels in the i+2-th row and the sub-pixels in the i+3-th row.

[0381] In an exemplary embodiment, the at least one signal line includes a second type of signal line, and the second type of signal line includes one or more of a second reset control line, a second initial signal line, a third initial signal line, a light emitting control line, and a second scan line;

[0382] Among the second type of signal lines, two adjacent signal lines of the same type, one of which is configured to simultaneously provide valid signals to sub-pixels in the i-1th row and sub-pixels in the i-th row, and the other of which is configured to simultaneously provide valid signals to sub-pixels in the i+1th row and sub-pixels in the i+2th row, where i is an integer greater than 1 and less than K. In the display substrate and its driving method, as well as the display device provided in the embodiments of the present disclosure, at least some of the at least one type of signal lines in the display substrate are configured to be electrically connected to at least two rows of sub-pixels, and the number of the at least one type of signal lines is a positive integer less than K. Reducing the number of signal lines can improve the light transmittance of the display substrate. For example, as shown in Figures 4A, 4B and 31, two adjacent second reset control lines among the multiple second reset control lines, one of the second reset control lines (for example, the second reset control line Reset2(i-1) / Reset2(i) shared by the i-1th row and the i-th row sub-pixels) is set to simultaneously provide the second reset signal to the i-1th row sub-pixels and the i-th row sub-pixels, and the other second reset control line (for example, the second reset control line Reset2(i+1) / Reset1(i+2) shared by the i+1th row and the i+2th row sub-pixels) is set to simultaneously provide the first reset signal to the i+1th row sub-pixels and the i+2th row sub-pixels.

[0383] As shown in Figure 4B, two adjacent second initial signal lines among the multiple second initial signal lines, one of the second initial signal lines (for example, the second initial signal line INIT2(i-1) / INIT2(i) shared by the sub-pixels in the i-1th row and the i-th row) is set to simultaneously provide the second initial signal to the sub-pixels in the i-1th row and the sub-pixels in the i-th row, and the other second initial signal line (for example, the second initial signal line INIT2(i+1) / INIT2(i+2) shared by the sub-pixels in the i+1th row and the i+2th row) is set to simultaneously provide the second initial signal to the sub-pixels in the i+1th row and the sub-pixels in the i+2th row.

[0384] As shown in Figures 6B to 6C, two adjacent third initial signal lines among the multiple third initial signal lines, one of the third initial signal lines (for example, the third initial signal line INIT3(i) shared by the i-1th row and the i-th row sub-pixels) is set to simultaneously provide the third initial signal to the i-1th row sub-pixels and the i-th row sub-pixels, and the other third initial signal line (for example, the third initial signal line INIT2(i+2) shared by the i+1th row and the i+2th row sub-pixels) is set to simultaneously provide the third initial signal to the i+1th row sub-pixels and the i+2th row sub-pixels.

[0385] As shown in Figures 6A, 6C and 31, two adjacent light-emitting control lines among the multiple light-emitting control lines, one of the light-emitting control lines (for example, the light-emitting control line EML(i) shared by the i-1th row and the i-th row sub-pixels) is set to simultaneously provide light-emitting control signals to the i-1th row sub-pixels and the i-th row sub-pixels, and the other light-emitting control line (for example, the light-emitting control line EML(i+2) shared by the i+1th row and the i+2th row sub-pixels) is set to simultaneously provide light-emitting control signals to the i+1th row sub-pixels and the i+2th row sub-pixels.

[0386] As shown in Figures 5A to 5C and Figure 31, two adjacent second scan lines among the multiple second scan lines, one of the second scan lines (for example, the second scan line GL2(i) shared by the i-1th row and the i-th row sub-pixels) is configured to simultaneously provide the second scan signal to the i-1th row sub-pixels and the i-th row sub-pixels, and the other second scan line (for example, the second scan line GL2L(i+2) shared by the i+1th row and the i+2th row sub-pixels) is configured to simultaneously provide the second scan signal to the i+1th row sub-pixels and the i+2th row sub-pixels.

[0387] In an exemplary embodiment, the effective signal can be a signal provided by the signal line that enables the sub-pixel electrically connected thereto to operate normally. For example, as shown in FIG31 , the effective signals of the light emitting control line, the first reset control line, the second reset control line, and the first scan line can be low-level, and the effective signal provided by the second scan line can be high-level. That is, the light emitting control signal provided by the light emitting control line, the first reset control signal provided by the first reset control line, the second reset control signal provided by the second reset control line, and the first scan signal provided by the first scan line can be low-level signals, and the second scan signal provided by the second scan line can be high-level. Whether the effective signal is high-level or low-level can be set in combination with the transistors in the first pixel circuit and is not limited to the high-level or low-level setting described above. In an exemplary embodiment, the effective signals provided by the first initial signal line, the second initial signal provided by the second initial signal line, and the third initial signal provided by the third initial signal line can be, but are not limited to, low-level signals. The first to third initial signals can also be set as high-level signals according to the first pixel circuit, which is not limited in the embodiments of the present disclosure.

[0388] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0389] In the absence of conflict, the embodiments of the present disclosure, i.e., features in the embodiments, can be combined with each other to form new embodiments.

[0390] Although the embodiments disclosed in the present disclosure are as described above, the contents are only embodiments adopted to facilitate understanding of the embodiments of the present disclosure and are not intended to limit the embodiments of the present disclosure. Any person skilled in the art in the field to which the embodiments of the present disclosure belong may make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the embodiments of the present disclosure, but the scope of patent protection of the embodiments of the present disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate, comprising a substrate, K rows of sub-pixels arranged on the substrate, and a plurality of signal lines extending in a row direction; the number of the same signal lines is multiple, the multiple signal lines of the same kind are arranged at intervals in a column direction, and each row of sub-pixels is electrically connected to one of the signal lines of the same kind; on a plane parallel to the display substrate, the row direction intersects the column direction; At least some of the at least one signal line, each signal line is configured to be electrically connected to at least two rows of sub-pixels, and the number of the same signal lines in the at least one signal line is a positive integer less than K.

2. The display substrate according to claim 1, wherein: In at least some of the at least one signal line, each signal line is configured to be electrically connected to two adjacent rows of sub-pixels.

3. The display substrate according to claim 2, wherein: The at least one signal line includes a first type signal line, the first type signal line includes at least two adjacent signal lines of the same type, one of the two adjacent signal lines of the same type is configured to be electrically connected to the i-th row of sub-pixels and the i+1-th row of sub-pixels, and the other signal line is configured to be electrically connected to the i+2-th row of sub-pixels and the i+3-th row of sub-pixels, wherein i is an integer greater than or equal to 1 and less than K.

4. The display substrate according to claim 3, wherein: The types of signal lines in the first type of signal lines include first reset control lines and / or first initial signal lines.

5. The display substrate according to claim 4, wherein: The first initial signal line and the first reset control line are located in different conductive layers. In the same row of sub-pixels, an orthographic projection of the first initial signal line on the substrate at least partially overlaps with an orthographic projection of the first reset control line on the substrate.

6. The display substrate according to claim 3, wherein: The at least one signal line also includes a second type signal line, and the second type signal line includes at least two adjacent signal lines of the same type, and one of the two adjacent signal lines of the same type is configured to be electrically connected to the i-1th row of sub-pixels and the i-th row of sub-pixels, and the other signal line is configured to be electrically connected to the i+1th row of sub-pixels and the i+2th row of sub-pixels, wherein i is greater than 1.

7. The display substrate according to claim 6, wherein: The types of signal lines in the second type of signal lines include second reset control lines and / or second initial signal lines.

8. The display substrate according to claim 7, wherein: The second reset control line and the second initial signal line are located in different conductive layers. In the same row of sub-pixels, an orthographic projection of the second reset control line on the substrate at least partially overlaps with an orthographic projection of the second initial signal line on the substrate.

9. The display substrate according to claim 7, wherein: The types of signal lines in the second type signal lines also include at least one of a third initial signal line, a light emitting control line, and a second scanning line.

10. The display substrate according to claim 9, wherein: The light emitting control line and the third initial signal line are located in different conductive layers. In the same row of sub-pixels, the orthographic projection of the light emitting control line on the substrate at least partially overlaps with the orthographic projection of the third initial signal line on the substrate.

11. The display substrate according to claim 9, wherein: The types of signal lines in the second type signal lines also include second scanning auxiliary lines. In the same row of sub-pixels, the second scanning auxiliary lines at least partially overlap with the orthographic projections of the second scanning lines on the substrate.

12. The display substrate according to any one of claims 1 to 11, wherein: The K rows of sub-pixels include a plurality of first sub-pixel rows and a plurality of second sub-pixel rows, wherein the first sub-pixel rows and the second sub-pixel rows are alternately arranged along the column direction, and each signal line is configured to be electrically connected to a first sub-pixel row and a second sub-pixel row adjacent to it, among at least some of the at least one signal line.

13. The display substrate according to claim 12, wherein: Each row of sub-pixels includes a plurality of sub-pixels sequentially arranged along the row direction, the plurality of sub-pixels form a plurality of pixel units, and at least part of the pixel units include at least three sub-pixels sequentially arranged along the row direction; The display substrate includes a first display area, the first display area includes a plurality of first sub-areas, a plurality of second sub-areas, a plurality of third sub-areas and a plurality of fourth sub-areas, the first sub-areas and the third sub-areas are alternately arranged along the row direction, the second sub-areas and the fourth sub-areas are alternately arranged along the row direction, a plurality of pixel units in the first sub-pixel row are respectively located in the plurality of first sub-areas, a plurality of pixel units in the second sub-pixel row are respectively located in the plurality of second sub-areas, a plurality of pixel units located in the first sub-pixel row are spaced apart by the third sub-areas, and a plurality of pixel units located in the second sub-pixel row are spaced apart by the fourth sub-areas.

14. The display substrate according to claim 13, wherein: At least some of the sub-pixels include a first pixel circuit, and at least some of the pixel units include four sub-pixels arranged in sequence along the row direction; in the same pixel unit, the four first pixel circuits are symmetrically arranged about a first center line extending along the column direction of the four first pixel circuits, the first first pixel circuit and the second first pixel circuit of the four first pixel circuits are symmetrically arranged about a second center line extending along the column direction of the two first pixel circuits, and the third first pixel circuit and the fourth first pixel circuit are symmetrically arranged about a third center line extending along the column direction of the two first pixel circuits.

15. The display substrate according to claim 14, wherein: The plurality of first sub-regions form a plurality of columns of first sub-regions, the plurality of second sub-regions form a plurality of columns of second sub-regions, and in the column direction, the first sub-regions and the second sub-regions are staggered; The third first pixel circuit and the fourth first pixel circuit of the four first pixel circuits in the pixel unit located in the first sub-area are respectively located in the same column as the first first pixel circuit and the second first pixel circuit of the four first pixel circuits in the pixel unit located in the adjacent second sub-area.

16. The display substrate according to claim 14, wherein: The pixel unit further includes four light-emitting elements, the four light-emitting elements are electrically connected to four first pixel circuits in the pixel unit respectively, and the light-emitting elements include anodes; in the same pixel unit, the orthographic projections of the anodes of the four light-emitting elements on the substrate at least partially do not overlap with the orthographic projections of the third sub-region and the fourth sub-region on the substrate; In the first sub-pixel row, the orthographic projections of the anodes of the four light-emitting elements on the substrate at least partially overlap with the orthographic projections of the first sub-region on the substrate; In the second sub-pixel row, orthographic projections of the anodes of the four light-emitting elements on the substrate at least partially overlap with the second sub-region.

17. The display substrate according to claim 15, wherein: At least part of the first pixel circuit includes first to eighth transistors; In the first pixel circuit in the first sub-pixel row located in the i-th row, in the column direction, the first transistor, the second transistor and the fourth transistor are located on a side of the third transistor close to the second sub-pixel row located in the i+1-th row, and the second transistor is located between the first transistor and the third transistor; the fifth transistor to the eighth transistor are located on a side of the third transistor close to the second sub-pixel row located in the i-1-th row, and the sixth transistor is located between the third transistor and the seventh transistor; wherein i is a positive integer greater than 1 and less than K; In the first pixel circuit in the second sub-pixel row located in the (i+1)th row, the first transistor, The second transistor and the fourth transistor are located on a side of the third transistor close to the first sub-pixel row in the i-th row, and the second transistor is located between the first transistor and the third transistor; the fifth transistor to the eighth transistor are located on a side of the third transistor close to the first sub-pixel row in the i+2-th row, and the sixth transistor is located between the third transistor and the seventh transistor.

18. The display substrate according to claim 17, wherein: In a direction perpendicular to the plane where the display substrate is located, the display substrate comprises: a circuit structure layer located on the substrate; the circuit structure layer comprises the plurality of first pixel circuits; at least some of the plurality of first pixel circuits comprise: at least one first type transistor, at least one second type transistor and a storage capacitor; the first type transistors at least comprise the first transistor and the third transistor to the eighth transistor, and the second type transistors at least comprise the second transistor; The circuit structure layer includes: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, and a third conductive layer arranged on the substrate; the first semiconductor layer includes at least: an active layer of a first type transistor of the pixel circuit; the first conductive layer includes at least: a gate of the first type transistor of the pixel circuit and a first electrode of a storage capacitor; the second conductive layer includes at least: a second electrode of the storage capacitor of the pixel circuit; the second semiconductor layer includes at least: an active layer of a second type transistor of the pixel circuit; the third conductive layer includes at least: a gate of the second type transistor of the pixel circuit.

19. The display substrate according to claim 18, wherein: The first conductive layer further includes: a first scan line, the light emission control line, a first reset control line, and a second reset control line electrically connected to the first type of transistor in the first pixel circuit; the first scan line, the light emission control line, the first reset control line, and the second reset control line extend along the row direction; In the column direction, the first scan line and the first reset control line electrically connected to the first sub-pixel row bypass one side of the third sub-region, and the light-emitting control line electrically connected to the first sub-pixel row bypasses the other side of the third sub-region; the first scan line electrically connected to the second sub-pixel row bypasses one side of the fourth sub-region, and the light-emitting control line and the second reset control line electrically connected to the second sub-pixel row bypass the other side of the fourth sub-region.

20. The display substrate according to claim 19, wherein: The third conductive layer further comprises a first initial signal line electrically connected to the first transistor in the first pixel circuit, a second initial signal line electrically connected to the seventh transistor in the first pixel circuit, and a third initial signal line electrically connected to the eighth transistor; the first initial signal line, the second initial signal line and the third initial signal line extend along the row direction; In the same row of sub-pixels, the orthographic projection of the first initial signal line on the substrate at least partially overlaps with the orthographic projection of the first reset control line on the substrate, the orthographic projection of the second initial signal line on the substrate at least partially overlaps with the orthographic projection of the second reset control line on the substrate, and the orthographic projection of the third initial signal line on the substrate at least partially overlaps with the orthographic projection of the light-emitting control line on the substrate.

21. The display substrate according to claim 20, wherein: At a position adjacent to the first sub-region of the first sub-pixel row in the i-th row and the second sub-region of the second sub-pixel row in the i-1th row, the second reset control line and the second initial signal line are ring structures, in the column direction, a side of the ring structure close to the first sub-region overlaps with the positive projections of the seventh transistor and the eighth transistor in the third to fourth first pixel circuits in the first sub-region on the substrate, and a side of the ring structure close to the second sub-region overlaps with the positive projections of the seventh transistor and the eighth transistor in the first to second first pixel circuits in the second sub-region on the substrate; At a position adjacent to the first sub-region of the first sub-pixel row located in the i-th row and the second sub-region of the second sub-pixel row located in the (i+1)-th row, the first reset control line and the first initial signal line are ring structures, and in the column direction, a side of the ring structure close to the first sub-region overlaps with the orthographic projection of the first transistors in the third to fourth first pixel circuits in the first sub-region on the substrate, and a side of the ring structure close to the second sub-region overlaps with the orthographic projection of the first transistors in the first to second first pixel circuits in the second sub-region on the substrate.

22. The display substrate according to claim 18, wherein: The second conductive layer further includes a second scanning auxiliary line electrically connected to the second transistor in the first pixel circuit; the third conductive layer further includes a second scanning line electrically connected to the second transistor in the first pixel circuit; in the same row of sub-pixels, the second scanning auxiliary line and the orthographic projection of the second scanning line on the substrate at least partially overlap; the second scanning auxiliary line and the second scanning line extend along the row direction; In the column direction, the second scan line and the second scan auxiliary line electrically connected to the first sub-pixel row bypass one side of the third sub-region, and the second scan line and the second scan auxiliary line electrically connected to the second sub-pixel row bypass one side of the fourth sub-region; the direction in which the second scan line and the second scan auxiliary line electrically connected to the first sub-pixel row bypass the third sub-region is opposite to the direction in which the second scan line and the second scan auxiliary line electrically connected to the second sub-pixel row bypass the fourth sub-region.

23. The display substrate according to claim 18, further comprising a fourth conductive layer, wherein the fourth conductive layer comprises a fourth switching electrode; the fourth switching electrode extends along the column direction; The second conductive layer further comprises a plurality of second scanning auxiliary lines and a plurality of second scanning auxiliary electrodes electrically connected to the second transistor in the first pixel circuit; the third conductive layer further comprises a plurality of second scanning lines and a plurality of second scanning electrodes electrically connected to the second transistor in the first pixel circuit; in the same row of sub-pixels, the second scanning auxiliary lines and the second scanning lines at least partially overlap in their positive projections on the substrate, and the second scanning electrodes and the second scanning auxiliary electrodes at least partially overlap in their positive projections on the substrate; the second scanning auxiliary electrodes, the second scanning electrodes, the second scanning auxiliary lines and the second scanning lines extend along the row direction; The plurality of second scanning auxiliary electrodes and the plurality of second scanning electrodes are electrically connected to the plurality of pixel units in the second sub-pixel row, respectively, and the plurality of second scanning auxiliary lines and the plurality of second scanning lines are electrically connected to the plurality of first pixel circuits in the first sub-pixel row; The second scanning auxiliary line and the second scanning line located in the i-th row are electrically connected to the plurality of second scanning auxiliary electrodes and the plurality of second scanning electrodes located in the i-1th row through the fourth switching electrode, and the second scanning auxiliary line and the second scanning line located in the i+2th row are electrically connected to the plurality of second scanning auxiliary electrodes and the plurality of second scanning electrodes located in the i+1th row through the fourth switching electrode; In the column direction, the second scanning line and the second scanning auxiliary line electrically connected to the first sub-pixel row bypass one side of the fourth sub-region; A plurality of second scanning electrodes and a plurality of second scanning auxiliary electrodes electrically connected to the second sub-pixel rows are respectively located in a plurality of second sub-regions.

24. The display substrate according to claim 18, further comprising a fourth conductive layer located on a side of the third conductive layer away from the substrate, the fourth conductive layer comprising a plurality of first switching electrodes and a plurality of second switching electrodes; The first switching electrode and the second switching electrode extend along the column direction; The first conductive layer further comprises: a plurality of light emitting control lines electrically connected to the plurality of first sub-pixel rows respectively and a plurality of light emitting control electrodes electrically connected to the plurality of second sub-pixel rows respectively; the light emitting control lines and the light emitting control electrodes extend along the row direction; the third conductive layer further comprises: a plurality of third initial signal lines electrically connected to the plurality of first sub-pixel rows respectively and a plurality of third initial signal electrodes electrically connected to the plurality of second sub-pixel rows respectively; the third initial signal lines and the third initial signal electrodes extend along the row direction; The light-emitting control line located in the i-th row is electrically connected to the plurality of light-emitting control electrodes located in the i-1th row through the first adapter electrode, and the light-emitting control line located in the i+2th row is electrically connected to the plurality of light-emitting control electrodes located in the i+1th row through the first adapter electrode; the third initial signal line located in the i-th row is electrically connected to the plurality of third initial signal electrodes located in the i-1th row through the second adapter electrode, and the third initial signal line located in the i+2th row is electrically connected to the plurality of third initial signal electrodes located in the i+1th row through the second adapter electrode; The light-emitting control electrode and the third initial signal electrode are located in the second sub-region, and in the column direction, the light-emitting control line and the third initial signal line electrically connected to the first sub-pixel row bypass one side of the fourth sub-region; in the same row of sub-pixels, the orthographic projections of the light-emitting control line and the third initial signal line on the substrate at least partially overlap, and the orthographic projections of the light-emitting control electrode and the third initial signal electrode on the substrate at least partially overlap.

25. A display device, comprising a display substrate as described in any one of claims 1 to 24 and a sensor located on a non-display surface side of the display substrate, the display substrate comprising a first display area, and the sensor's orthographic projection on the display substrate at least partially overlaps with the first display area of ​​the display substrate.

26. A method for driving a display substrate, configured to drive the display substrate according to any one of claims 1 to 24, wherein the display substrate comprises K rows of sub-pixels and a plurality of signal lines extending in a row direction, the number of the same signal lines being a positive integer less than or equal to K, and each row of sub-pixels being electrically connected to one of the same signal lines; the driving method comprising: At least some of the at least one signal line, each signal line provides effective signals to at least two rows of sub-pixels.

27. The driving method according to claim 26, wherein: At least some of the at least one signal line, each signal line provides effective signals to two adjacent rows of sub-pixels simultaneously.

28. The driving method according to claim 27, wherein: The at least one signal line includes a first type of signal line, and the first type of signal line includes at least one of a first reset control line and a first initial signal line; Among the first type of signal lines, two adjacent signal lines of the same type, one signal line is configured to simultaneously provide valid signals to the i-th row of sub-pixels and the i+1-th row of sub-pixels, and the other signal line is configured to simultaneously provide valid signals to the i+2-th row of sub-pixels and the i+3-th row of sub-pixels, where i is an integer greater than or equal to 1 and less than K.

29. The driving method according to claim 27 or 28, wherein: The at least one signal line includes a second type signal line, and the second type signal line includes one or more of a second reset control line, a second initial signal line, a third initial signal line, a light emitting control line, and a second scan line; Among the second type of signal lines, two adjacent signal lines of the same type, one signal line is configured to simultaneously provide valid signals to the sub-pixels in the i-1th row and the sub-pixels in the i-th row, and the other signal line is configured to simultaneously provide valid signals to the sub-pixels in the i+1th row and the sub-pixels in the i+2th row, where i is an integer greater than 1 and less than K.

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