LVDS signal open circuit and short circuit detection system and detection method

Abstract

The invention discloses an LVDS (Low Voltage Differential Signaling) open and short circuit detection method and system, which are characterized in that the start and stop of differential signals are controlled through an FPGA (Field Programmable Gate Array), the current change of an LVDS forwarding bridge sheet is measured in combination with a current acquisition module, the independent current value of each differential pair is deduced, and the independent current value is compared with a standard interval to accurately identify micro short circuit, micro breaking and impedance abnormity. The method solves the problem that hidden defects cannot be detected through a traditional point screen method, and the detection precision and the production efficiency are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuit detection and related fields of display panel detection equipment or instruments, and particularly relates to a method and system for detecting open / short circuit and impedance abnormality of a low-voltage differential signal (LVDS) link based on current analysis. Background Art

[0002] During the production process of display panels, the reliability of the LVDS signal link directly affects product quality. Currently, the industry generally uses the method of observing the screen to detect LVDS signal abnormalities, but this method can only identify obvious short circuits (such as P-P, N-N, P-N short circuits) or disconnections (P / N disconnections), and cannot detect the following hidden dangers: micro short circuit: there is a weak short circuit (such as impedance abnormality) between differential pairs or between signals of the same polarity; micro disconnection: there is poor contact or partial disconnection of the signal line; impedance abnormality: impedance mismatch caused by the virtual soldering or missing of the matching resistor.

[0003] The limitations of traditional methods lead to defective products flowing into the client, causing display abnormalities (such as picture abnormalities, lines, etc.). Therefore, there is an urgent need for a high-precision and low-cost LVDS link detection solution. Summary of the Invention

[0004] Aiming at the deficiencies of the existing technology, the purpose of the present invention is to provide a method and system for detecting LVDS signal links based on current analysis, which can identify micro shorts, micro breaks and impedance abnormalities, improve product yield and reduce detection costs. By controlling the start-stop state of the LVDS differential signal output, combined with the current acquisition module to measure the total current change of the LVDS forwarding bridge chip, the independent current values of each differential pair are deduced and compared with the standard interval to judge the link state.

[0005] The present invention proposes an open / short circuit detection system for LVDS signals, including an FPGA control module for generating controllable LVDS differential signals and supporting independent start-stop of each differential pair; an LVDS forwarding bridge chip for enhancing signal driving ability and supporting pre-emphasis adjustment; a current acquisition module for real-time collecting the total working current of the LVDS forwarding bridge chip; and a processing unit for analyzing current data and judging the type of link abnormality. This system is mainly composed of an FPGA control module, an LVDS forwarding bridge chip, a current acquisition module and a processing unit. Each module works together to achieve the detection of the LVDS signal link; the FPGA control module generates controllable LVDS differential signals, supports independent start-stop of each differential pair, and uses a high-performance FPGA chip, such as the Kintex series of Xilinx. A stable clock signal is generated through the internal clock management module, and the LVDS differential signal is generated by the signal generator module. Each differential pair corresponds to an independent enable pin, which is controlled by the GPIO of the FPGA.

[0006] Furthermore, an LVDS forwarding bridge chip is used to enhance the signal driving ability and support pre - emphasis adjustment. Select a bridge chip with high driving ability and adjustable pre - emphasis function, such as DS90UR928 from TI, and configure the bridge chip through the I2C or SPI interface to set the amplitude of pre - emphasis and other parameters.

[0007] A current acquisition module is used to collect the total working current of the LVDS forwarding bridge chip in real - time.

[0008] A processing unit receives the current data transmitted by the current acquisition module, stores it in the internal memory, and calculates the independent current values of each differential pair based on the collected total current data and in combination with the start - stop control of the differential pairs by the FPGA. Compare the calculated independent current values with the pre - set standard range to determine whether there are micro - shorts, micro - breaks or impedance anomalies in the link.

[0009] As a further solution of the present invention, the FPGA control module outputs an LVDS differential signal with a preset duty cycle to enable the LVDS forwarding bridge chip and pre - emphasis. The specific implementation process can be as follows: Connect the LVDS output pin of the FPGA to the input pin of the LVDS forwarding bridge chip; Provide power and enable signal for the LVDS forwarding bridge chip, and the enable signal can be controlled by the general I / O pin of the FPGA. If pre - emphasis is configured through the I2C or SPI interface, connect the corresponding communication pins of the FPGA to the communication interface of the LVDS forwarding bridge chip. Through the above - mentioned hardware design, FPGA code implementation and LVDS forwarding bridge chip configuration, the FPGA control module can output an LVDS differential signal with a preset duty cycle and enable the LVDS forwarding bridge chip and pre - emphasis.

[0010] As a further solution of the present invention, the FPGA control module supports differential control of the clock pair and data pair. The clock pair is generated by an independent PLL and has strict duty - cycle control to ensure timing synchronization (clock jitter < 100ps); When the data pairs are cut off one by one, the clock pair continues to work to avoid repeated calibration (the detection time is shortened by 40%); The reference intervals of the clock pair and data pair are separated, and the misjudgment rate is reduced from 0.1% to 0.01%; Through the above design, the FPGA control module realizes differential processing of the clock pair and data pair in four dimensions: signal generation, enable control, pre - emphasis adjustment, and reference analysis, providing a high - precision and high - reliability underlying control architecture for LVDS link detection, especially suitable for timing - sensitive scenarios such as 8K display and high - speed data transmission.

[0011] As a further solution of the present invention, the LVDS forwarding bridge chip provides multiple differential pair outputs. Pre-emphasis can compensate for the high-frequency loss of the signal during transmission and improve the signal quality. The bridge chip should support the pre-emphasis adjustment function and be able to set different pre-emphasis amplitudes according to actual requirements; it is necessary to test and verify the multiple differential pair outputs of the bridge chip to ensure that its performance meets the requirements. Instruments such as oscilloscopes and logic analyzers can be used to measure and analyze parameters such as the waveform, rate, and swing of the output signal. At the same time, the bit error rate test can also be carried out to evaluate the reliability of signal transmission, and the function of the multiple differential pair outputs of the LVDS forwarding bridge chip can be fully utilized.

[0012] The present invention also discloses an LVDS signal open / short circuit detection method, including the following steps: Initialization: The FPGA control module outputs an LVDS differential signal with a preset duty cycle, and enables the LVDS forwarding bridge chip and pre-emphasis; the FPGA needs to accurately generate an LVDS differential signal with a preset duty cycle. For example, an enable signal is output to the bridge chip through the GPIO pin of the FPGA, and the pre-emphasis parameters of the bridge chip are configured using the I2C or SPI interface.

[0013] Reference current acquisition: Measure the total current T when all differential pairs are activated through the current acquisition module; use a high-precision current sensor or a method based on resistance sampling for current measurement. For example, a sampling resistor with a small resistance value (such as 1Ω) is used to convert the current into a voltage signal, and then sampled through an ADC.

[0014] Differential pair cut-off one by one: Close a single differential pair (Dn / Cn) in turn, measure the remaining total current Tn, and calculate the current value Tx = T - Tn of this differential pair; the FPGA closes a single differential pair in turn according to a preset order. For example, a state machine can be used to implement this process to ensure that the closing and current measurement operations of each differential pair are carried out in sequence; after closing a single differential pair each time, it is necessary to wait for a period of time (such as 50ms) for the system to reach a stable state again before measuring the remaining total current.

[0015] Establish a standard range: Obtain the reference current range of each differential pair through normal samples; for example, select a certain number (such as 100) of normal samples, test according to the above steps, and record the current value of each differential pair. Statistical analysis can also be carried out on the current values of each differential pair to calculate the average value μ and standard deviation σ . Usually, the standard range can be set to μ 3 σ , μ 3 σ , so that about 99.7% of normal situations can be covered.

[0016] Abnormality determination: If the Tx of the sample to be tested is lower than the standard lower limit, it is determined as open / micro-open; if it is higher than the upper limit, it is determined as short / micro-short; abnormal matching resistance is manifested as the deviation of the current of a specific differential pair. Specifically, when the Tx of the sample to be tested is lower than the standard lower limit μ 3 σ at this time, it is determined that there is an open / micro-open fault in this differential pair. Possible reasons include line breakage, poor pin contact, etc.; if the Tx is higher than the standard upper limit μ 3 σ , then it is determined that there is a short / micro-short fault in this differential pair. It may be caused by insulation damage between lines, pin short circuit, etc. When the current value Tx of a specific differential pair deviates from the standard range but does not belong to an obvious open or short situation, it may be an abnormal matching resistance. It can be further confirmed by measuring the impedance of this differential pair. The present invention can effectively detect the open and short circuits of LVDS signals. This method has high accuracy and reliability, can timely detect potential faults in the LVDS link, and improve the quality and stability of products.

[0017] As a further solution of the present invention, for the detection of 2Link10bit LVDS signals, the specific process is as follows: Configuration parameters: The LVDS signal is of 2Link structure, and the differential pair numbers are D00 / D01 / D02 / D03 / D04 / C0 (Link0), D10 / D11 / D12 / D13 / D14 / C1 (Link1); Output of the FPGA control module: Generate differential signals with a frequency of 100MHz and a duty cycle of 50%; the FPGA control module generates differential signals with a frequency of 100MHz and a duty cycle of 50%, and enables the enable and pre-emphasis functions of the LVDS forwarding bridge chip. Wait for the system to be stable for a period of time (such as 100ms) to ensure that the current reaches a stable state.

[0018] Current acquisition: Turn on all differential pairs and measure the total current T; turn off D00 in sequence and measure T0, then the current of D00 is T00 = T - T0; repeat the operation to obtain T01~TC1; turn on all differential pairs and measure the total current T through the current acquisition module. To improve the measurement accuracy, multiple samplings can be performed and the average value can be taken. Turn off a single differential pair in sequence. For example, first turn off D00, wait for the system to be stable again (such as 50ms), and then measure the remaining total current; repeat the above operation, turn off differential pairs such as D01 and D02 in sequence, measure the remaining total current respectively and calculate the currents of each differential pair T01, T01, etc. until the current values of all differential pairs (D00-D04, C0, D10-D14, C1) are obtained.

[0019] Standard range setting: The current range of each differential pair for normal samples is Rx ± 10%; for each differential pair, calculate the average value Rx of the current values of the normal samples, and then set the standard range as Rx ± 10%. For example, if the average value Rx of a certain differential pair is 30 mA, then its standard range is [27 mA, 33 mA].

[0020] Abnormal detection: If the T10 of the sample under test is lower than the lower limit of R10, it is determined that there is a micro-disconnection in D10. For each differential pair of the sample under test, compare its current value with the corresponding standard range. If the current value T10 of a certain differential pair (such as D10) is lower than the lower limit R10 of the standard range, it is determined that there is a micro-disconnection fault in this differential pair. Through the above hardware design, code implementation and detection process, the 2Link10bitLVDS signal can be effectively detected, and abnormal conditions such as micro-disconnections of differential pairs can be discovered and determined in a timely manner, improving the reliability and stability of the system.

[0021] The present invention has the following beneficial effects: The high-precision detection ability of the present invention, precise identification of micro-faults: This solution can accurately identify micro-disconnections and micro-short-circuit faults in the LVDS signal link. By independently measuring and analyzing the currents of each differential pair and combining with the standard range determination, even a tiny current change can be captured. For example, it can detect a micro-disconnection fault caused by a slight loosening of the pin, avoiding the possible missed detection of traditional detection methods and greatly improving the accuracy of fault detection.

[0022] Precise positioning of impedance anomalies: For situations such as abnormal matching resistors, the solution can also accurately position through the deviation of the current of a specific differential pair. When the matching resistor changes, it will cause the current of this differential pair to deviate from the normal range, and the system can detect it in a timely manner and determine it as an impedance anomaly, providing a clear direction for fault troubleshooting and repair.

[0023] Signal quality guarantee, stable signal output: The stable differential signal generated by the FPGA control module with a frequency of 100 MHz and a duty cycle of 50% provides a reliable signal source for the entire LVDS signal link. The stable signal helps to reduce signal distortion and interference, ensuring the accuracy and integrity of data during transmission, especially suitable for application scenarios with high requirements for signal quality, such as high-definition video transmission, high-speed data communication, etc. Pre-emphasis adjustment optimization: The pre-emphasis adjustment function supported by the LVDS forwarding bridge chip can effectively compensate for the high-frequency loss of the signal during transmission. By reasonably setting the pre-emphasis parameters, the edge characteristics of the signal can be improved, the anti-interference ability of the signal can be enhanced, and the signal quality and transmission reliability can be further improved.

[0024] Compatibility and expandability, 2Link structure adaptation: The solution is specifically designed for the 2Link 10-bit LVDS signal structure, which can well adapt to this complex signal link and meet the requirements of multi-link and high-bandwidth data transmission in specific application scenarios. Easy to expand: The hardware and software design of the system has good expandability. In terms of hardware, the number of differential pairs can be easily increased or decreased to adapt to LVDS signal detection requirements of different scales; in terms of software, by modifying configuration parameters and algorithms, it is easy to achieve the detection of different types of LVDS signals. Enhanced quality stability: By testing a large number of normal samples and setting standard intervals, the solution can establish a set of scientific and accurate quality standards. During the production process, products are strictly detected and screened according to this set of standards to ensure that the LVDS signal link of each product meets the quality requirements, thereby improving the stability and consistency of product quality. Automated detection process: The entire detection process is highly automated. From the signal output of the FPGA control module, the current measurement of the current acquisition module to the data analysis and anomaly determination of the processing unit, it can be completed in a short time. This automated detection process greatly shortens the detection time and improves production efficiency, especially suitable for large-scale production scenarios. Quick fault location: The solution can quickly and accurately locate the faulty differential pair, reducing the time and workload of fault troubleshooting. Once an anomaly is detected, the system can immediately give the number of the faulty differential pair and the type of anomaly, and maintenance personnel can quickly take corresponding repair measures, shortening the repair cycle of the product and further improving production efficiency. Optimized hardware cost: The solution uses common electronic components and chips, such as FPGA, LVDS forwarding bridge chips, current sensors, and ADCs. The prices of these components are relatively low and easy to obtain. At the same time, through reasonable hardware design and layout, unnecessary hardware overhead is reduced, and the overall cost of the detection system is lowered.

[0025] To more clearly illustrate the structural features and functions of the present invention, the present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments. Description of the Drawings

[0026] Figure 1 is a schematic structural diagram of the detection system of the present invention.

[0027] Figure 2 is a schematic diagram of the detection process of the present invention. Detailed Embodiments

[0028] The following will further illustrate the present invention in conjunction with the accompanying drawings and relevant knowledge, and describe it clearly and completely. Obviously, the described applications are only a part of the embodiments of the present invention, rather than all embodiments.

[0029] Embodiment 1, LVDS signal open / short circuit detection system, refer toFigure 1 As shown, it shows the connection relationship among the FPGA, the LVDS forwarding bridge chip, and the current acquisition module, including the FPGA control module: generating controllable LVDS differential signals and supporting independent start / stop of each differential pair (including the clock pair and the data pair); the LVDS forwarding bridge chip: enhancing the signal driving ability and supporting pre-emphasis adjustment; the current acquisition module: real-time collecting the total working current of the LVDS enhanced bridge chip; the processing unit: analyzing the current data to judge the type of link abnormality. By controlling the start / stop state of the LVDS differential signal output, combining with the measurement of the total current change of the LVDS forwarding bridge chip by the current acquisition module, deducing the independent current value of each differential pair, and comparing it with the standard interval to judge the link state, the present invention can identify micro-shorts, micro-breaks, and impedance abnormalities, improve the product yield, and reduce the detection cost.

[0030] In the present invention, the FPGA module is used to output controllable LVDS differential signals and support independent start / stop of each differential pair; the LVDS forwarding bridge chip is connected to the FPGA to enhance the signal driving ability; the current acquisition module real-time collects the total working current of the LVDS enhanced bridge chip; the processing unit calculates the current value of each differential pair according to the current change and judges the abnormality by comparing with the standard interval.

[0031] In this embodiment, the FPGA control module realizes its functions as follows: Controllable signal generation: generating LVDS differential signals with a frequency of 100 MHz and a duty cycle of 50% (such as the PRBS7 sequence), ensuring the clock accuracy (±0.1%) through an internal PLL, and supporting independent configuration of the clock pair (C0 / C1) and the data pair (D00~D14). Independent start / stop control: allocating an independent enable signal (EN) for each differential pair. For example, the enable signal for the C0 clock pair of Link0 is EN_C0, and the enable signal for the D00 data pair is EN_D00. Driving the NMOS switch (such as AO3400) through the IO port of the FPGA (such as the LVCMOS33 interface of Xilinx Artix-7) to achieve start / stop at the nanosecond level (switching time < 1 μs).

[0032] Hardware interface: Signal output: The LVDS differential signal is output through the OBUFDS primitive (such as OBUFDS#(.IOSTANDARD("LVDS_25"))) to match the input impedance of the bridge chip (100 Ω).

[0033] Enable control: 12 enable signals (6 pairs / Link × 2Link) are connected to the channel enable pins of the bridge chip (such as OE0~OE11 of DS90UR928).

[0034] LVDS Forwarding Bridge Chip, Signal Driving Enhancement: Convert the 3.3V LVDS signal output by the FPGA into a differential current drive of 35mA, support PCB trace transmission up to 15cm or coaxial cable transmission up to 50cm, and compensate for signal attenuation (insertion loss ≤ 3dB at 1GHz). Pre-emphasis Adjustment: Configure the pre-emphasis level (0dB / +3dB / +6dB) through the I2C interface (such as address 0x40). For example, set the clock pair to +6dB to compensate for high-frequency loss, and the data pair is default +3dB.

[0035] Hardware Connection: Input Side: Receive the LVDS differential signals from the FPGA (such as CLK_IN_P / N, DATA_IN_P / N). Output Side: Output 24 differential pairs (Link0: C0 / D00~D04; Link1: C1 / D10~D14), which are connected to the connector of the link under test (such as HSD interface). Power Supply Side: 3.3V power supply input, in series with a 1Ω / 0.1% precision shunt resistor (such as Vishay S1225) for current acquisition.

[0036] Current Acquisition Module, High-precision Acquisition Scheme: Signal Conversion: The current at the power supply terminal of the bridge chip is converted into voltage through a 1Ω resistor (such as 35mA corresponding to 35mV), amplified to 3.5V by an INA128 instrumentation amplifier (gain G = 100), and connected to a 24-bit ADC (ADS1256, resolution 0.05μV / LSB). Anti-interference Design: Parallel 100μF tantalum capacitor + 100nH inductor for filtering at the power supply terminal. When laying out the PCB, the analog ground and digital ground are connected together at a single point to reduce ripple (<10mVpp).

[0037] Acquisition Process: When all differential pairs are enabled, collect the total current T. After cutting off each one in turn, collect the remaining current Tn, and calculate Tx = T - Tn (such as the current of D00 = 35mA ± 10%).

[0038] Processing Unit, Data Analysis Algorithm: Benchmark Library Establishment: Measure 100 qualified samples to generate the average current value Rx of each differential pair (such as C0 = 35mA, D00 = 34.8mA), and set the standard interval Rx ± 10% (such as D00: 31.3mA~38.3mA). Abnormality Judgment: Micro-disconnection: Tx < lower limit (such as D10 = 25mA < 31.3mA), judge that the pin is soldered poorly or the contact resistance increases (>10Ω). Micro-short circuit: Tx > upper limit (such as D01 = 40mA > 38.3mA), judge that there is a poor solder joint or insulation breakage between differential pairs (leakage resistance < 10kΩ). Impedance Abnormality: Tx deviates by ±20% and is independently abnormal (such as C1 = 28mA, non-adjacent pair is abnormal), judge that the matching resistor is missing / soldered poorly (impedance ≠ 100Ω ± 20%). Output Interface: Upload the results to the MES system through RS-485 or Ethernet, or drive the indicator light through GPIO (green = qualified, red = micro-disconnection, yellow = micro-short circuit).

[0039] Embodiment 2. Refer to Figure 2 As shown, the differential pair control, current acquisition, and determination logic, and the LVDS signal open / short circuit detection method are described. The method includes the following processes: Initialization: The FPGA outputs an LVDS signal with a preset duty cycle (such as 50%), enables the forwarding bridge chip, and enables pre-emphasis; Reference current acquisition: Measure the total current T when all differential pairs are activated; Differential pair cutting one by one: Turn off a single differential pair (Dn / Cn) in sequence, measure the remaining total current Tn, and calculate the current value Tx of this differential pair as Tx = T - Tn; Establish a standard range: Obtain the reference current range (±10%) of each differential pair through normal samples; Abnormality determination: If the Tx of the sample to be tested is lower than the standard lower limit, it is determined to be open / micro-open; if it is higher than the upper limit, it is determined to be short / micro-short; If the matching resistor is abnormal, it is manifested as the current deviation of a specific differential pair. The present invention can detect micro-shorts, micro-opens, and impedance abnormalities, covering the blind spots of traditional methods; Automatically detect, reduce labor costs; Improve the yield rate and reduce the risk of client-side failures.

[0040] In the present invention, by controlling the FPGA to output a preset LVDS signal, the total current T is acquired; Each differential pair is cut off one by one, the remaining current Tn is acquired, and the single-pair current Tx = T - Tn is calculated; Compare Tx with the standard range to determine short circuit, micro-short circuit, open circuit, micro-open circuit, or impedance abnormality. The standard range is set by ±10% of the current value of normal samples, and this range is not limited to ±10%; This detection method is not limited to the LVDS signal open / short circuit detection system, and is also applied to similar display differential signal open / short circuit detection systems.

[0041] In this embodiment, FPGA signal output: The FPGA control module generates an LVDS differential signal with a preset duty cycle (such as 50%) and a frequency of 100 MHz. Inside the FPGA, a stable clock signal is generated using a clock management module (such as Xilinx's MMCM), and then the differential signal is output through an LVDS output primitive (such as OBUFDS). Forwarding bridge chip configuration: An enable signal is output through the GPIO pins of the FPGA to turn on the LVDS forwarding bridge chip. At the same time, the pre-emphasis of the bridge chip is configured using the I2C or SPI interface. For example, the pre-emphasis of the clock pair is set to +6 dB, and the data pair is set to +3 dB to compensate for the high-frequency loss during signal transmission. Reference current acquisition, stabilization period waiting: After all differential pairs are activated, wait for the system to reach a stable state, usually set to 100 ms, to ensure the stability of the current value. Current acquisition: The current acquisition module uses a high-precision ADC (such as the 24-bit ADS1256) to sample the total operating current of the LVDS forwarding bridge chip. To improve the measurement accuracy, multiple samples (such as 20 times) are taken, and the sampling results are averaged to obtain the total current T. Differential pairs are cut off one by one, and the FPGA sequentially turns off individual differential pairs in a preset order (such as D00, D01,..., C1). The turning off of each differential pair is achieved by controlling the corresponding enable signal. After turning off one differential pair each time, wait for 50 ms for the system to stabilize again, then measure the remaining total current and calculate the current value of this differential pair. Establishing a standard range, normal sample testing: Select a certain number (such as 100) of normal samples, perform current acquisition and calculation according to the above process, and obtain the current values of each differential pair in each normal sample. Statistical analysis: Statistical analysis is performed on the current values of each differential pair, and the average value Rx is calculated. The standard range is set to Rx ± 10%, but this range can be adjusted according to the actual situation. Abnormal determination Open / micro-open determination: When the Tx of the sample under test is lower than the lower limit Rx 10% of the standard range, it is determined that there is an open / micro-open fault in this differential pair. Possible reasons include pin soldering defects, line breaks, etc. Short circuit / micro-short determination: If Tx is higher than the upper limit Rx + 10% of the standard range, it is determined that there is a short circuit / micro-short fault in this differential pair. This may be caused by insulation damage between differential pairs, soldering omissions, etc. Matching resistor abnormal determination: When the current value Tx of a specific differential pair deviates from the standard range but does not belong to an obvious open or short circuit situation, it may be an abnormal matching resistor. For example, if the current value of a certain differential pair deviates from the standard range by more than 20% and the adjacent differential pairs are normal, it is determined that the matching resistor is abnormal.

[0042] The present invention can detect tiny current changes, identify faults such as micro-shorts, micro-breaks, and impedance anomalies that are difficult to discover by traditional detection methods, effectively covering the blind spots of traditional methods. The entire detection process is automated, from FPGA signal output, current acquisition to anomaly determination, without manual intervention, greatly reducing labor costs and improving detection efficiency. By promptly discovering and handling faults in the LVDS signal link, defective products are prevented from entering the market, effectively improving the product yield rate and reducing the failure risk at the client side.

[0043] The present invention controls the start and stop of differential signals through an FPGA, combines a current acquisition module to measure the current changes of the LVDS forwarding bridge chip, deduces the independent current values of each differential pair, and compares them with the standard range to accurately identify micro-shorts, micro-breaks, and impedance anomalies. The present invention solves the problem that traditional dot-screen methods cannot detect hidden defects, significantly improving detection accuracy and production efficiency.

[0044] Example 3, Detection method for 2Link10bit LVDS signals, the specific process is as follows: 1. Configure parameters: The LVDS signal has a 2Link structure, and the differential pair numbers are D00 / D01 / D02 / D03 / D04 / C0 (Link0), D10 / D11 / D12 / D13 / D14 / C1 (Link1); when detecting 2Link10bit LVDS signals, first, it is necessary to clarify the signal structure and differential pair numbers. The 2Link structure includes two links (Link0 and Link1), each link has 5 data differential pairs (D00 - D04 correspond to Link0, D10 - D14 correspond to Link1) and 1 clock differential pair (C0 corresponds to Link0, C1 corresponds to Link1). These differential pair numbers are used to identify and distinguish different signal channels in the subsequent detection process and are the basis for accurate detection and fault location.

[0045] 2. FPGA output: Generate differential signals with a frequency of 100MHz and a duty cycle of 50%; the FPGA needs to generate a stable 100MHz clock signal. This can be achieved by leveraging the phase-locked loop (PLL) or digital clock manager (DCM) inside the FPGA. Using the generated 100MHz clock signal, differential signals with a duty cycle of 50% are generated through the I / O unit of the FPGA.

[0046] 3. Current acquisition: a. Turn on all differential pairs and measure the total current T; b. Turn off D00 in sequence and measure T0, then the current of D00 is T00 = T - T0; c. Repeat the operation to obtain T01~TC1; Turn off a single differential pair in sequence, wait for the system to stabilize for a period of time (such as 50ms) after each turn-off, and then measure the remaining total current Tn. Through the formula Tx = T Tn calculates the current value of the differential pair. For example, when D00 is turned off and T0 is measured, the current of D00, T00 = T T0. Repeat this operation until the current values of all differential pairs (D00 - D04, C0, D10 - D14, C1) are obtained.

[0047] 4. Standard range setting: The current range of each differential pair of normal samples is Rx ± 10%, and this range is not limited to ± 10%; 5. Abnormality detection: If T10 of the sample to be measured is lower than the lower limit of R10, it is determined that there is a micro-disconnection in D10.

[0048] The technical principle of the present invention is described above in combination with specific embodiments, which are only the preferred embodiments of the present invention. The protection scope of the present invention is not limited to the above embodiments. All technical solutions within the idea of the present invention belong to the protection scope of the present invention. Those skilled in the art can think of other specific embodiments of the present invention without creative labor, and these embodiments will fall within the protection scope of the present invention.

Claims

1. LVDS signal open and short circuit detection system, characterized in that: It includes an FPGA control module, which is used to generate controllable LVDS differential signals and support independent start and stop of each differential pair; an LVDS forwarding bridge chip, which is used to enhance the signal driving capability and support pre-emphasis adjustment; The current acquisition module is used to collect the total working current of the LVDS forwarding bridge chip in real time; the processing unit is used to analyze the current data and determine the type of link abnormality.

2. The LVDS signal open-short circuit detection system according to claim 1, characterized in that: The FPGA control module outputs an LVDS differential signal with a preset duty cycle, and turns on the LVDS forwarding bridge chip enable and pre-emphasis.

3. The LVDS signal open-short circuit detection system according to claim 2, characterized in that: The FPGA control module supports differentiated control of clock pairs and data pairs.

4. The LVDS signal open-short circuit detection system according to claim 3, characterized in that: The LVDS forwarding bridge chip provides multiple differential pair outputs.

5. A detection method using the LVDS signal open-short circuit detection system according to claim 1, characterized in that: The following steps are involved: Initialization: The FPGA control module outputs the LVDS differential signal with a preset duty cycle, and turns on the LVDS forwarding bridge chip enable and pre-emphasis; Reference current acquisition: The total current T when all differential pairs are activated is measured through the current acquisition module; Cut off the differential pairs one by one: turn off the individual differential pairs (Dn / Cn) in turn, measure the remaining total current Tn, and calculate the current value of the differential pair Tx=T-Tn; Establishing a standard range: Obtaining the reference current range of each differential pair through normal samples; Abnormal judgment: If the Tx of the sample to be tested is lower than the standard lower limit, it is judged as disconnected / slightly disconnected; If it is higher than the upper limit, it is judged as short circuit / micro short; Matching resistance anomalies manifest themselves as deviations in current for a specific differential pair.

6. The method according to claim 5, characterized in that Used for 2Link10bitLVDS signal detection.

7. The method according to claim 6, characterized in that The specific process of 2Link10bitLVDS signal detection is as follows: Configuration parameters: LVDS signal is a 2Link structure, and the differential pair numbers are D00 / D01 / D02 / D03 / D04 / C0 (Link0), D10 / D11 / D12 / D13 / D14 / C1 (Link1); FPGA control module output: generates a differential signal with a frequency of 100MHz and a duty cycle of 50%; Current acquisition: turn on all differential pairs and measure the total current T; turn off D00 in sequence and measure T0, then the D00 current is T00=T-T0; repeat the operation to obtain T01~TC1; Standard range setting: The current range of each differential pair of normal samples is Rx±10%; Abnormal detection: T10 of the sample to be tested is lower than the lower limit of R10, and it is determined that D10 is slightly disconnected.

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