Improved on-chip capacitor standard cell and manufacturing method thereof

Abstract

The application belongs to the technical field of standard capacitance, and discloses an improved on-chip capacitance standard unit and a manufacturing method thereof, which comprises a basic structure and a standard structure with added interdigital electrode pairs, and adjacent interdigital electrode pairs are adjacent on the same side. The standard capacitance value is the difference between the capacitance values of the standard structure and the basic structure, and has a linear relationship with the number of interdigital electrode pairs, and is characterized by a nominal step capacitance value. To achieve a preset target step capacitance value, first, the capacitance standard unit is simulated and calculated to obtain corresponding structure parameters. Then, a plurality of actual objects are manufactured within the left and right ranges of the parameters, and the step capacitance values thereof are measured. The structure parameters corresponding to the actual object closest to the target are selected as the optimal design parameters, and are applied to the design of the capacitance standard unit. The technical scheme disclosed by the application can ensure the accurate measurement and stability of the capacitance.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of standard capacitors, and particularly relates to an improved on-chip capacitor standard unit and a manufacturing method thereof. BACKGROUND

[0002] Capacitors are basic elements in electricity, and the metric unit thereof is farad (F), which is a key derived unit in the International System of Units (SI). Process control monitoring (PCM) in a semiconductor process monitors the key process quality in a semiconductor production process by measuring the electrical parameters on the PCM pattern, and the capacitance is an important parameter for judging whether the medium thickness meets the design requirement. Once the capacitance value deviates, the corresponding process link is immediately returned to confirm, thereby effectively ensuring the process consistency. With the continuous reduction of the size of nanometer devices in integrated circuits, the demand for high-sensitivity capacitance measurement in the fF range becomes crucial for various applications, such as measuring metal-to-metal capacitance, interconnection capacitance on a wafer, or capacitance between terminals on a nanometer device. Many commercial LCR meters, capacitance bridges, or capacitance-voltage (C-V) meters can be used to make these measurements. The measurement of fF-level on-chip capacitance has inherent difficulties. In order to make these instruments achieve optimal performance and accurately measure small capacitance, it is necessary to develop fF-level on-chip capacitance standards.

[0003] In the prior art, the adjacent interdigital electrode pairs in the interdigital capacitor structure will affect each other, thereby affecting the accuracy of the capacitance value and the step value. SUMMARY

[0004] The application aims to provide an improved on-chip capacitor standard unit and a manufacturing method thereof to solve the problems in the prior art.

[0005] To achieve the above-mentioned purpose, the application provides an improved on-chip capacitor standard unit, which comprises a basic structure and a standard structure. The basic structure is composed of a probe contact electrode and a connecting line. The standard structure is composed of a plurality of pairs of interdigital electrodes added to the basic structure. Adjacent electrodes on the same side of adjacent pairs of interdigital electrodes are adjacent. The standard capacitance value of the on-chip capacitor standard unit is the difference between the capacitance value of the standard structure and the capacitance value of the basic structure. The nominal step capacitance of the standard structure has a linear relationship with the number of pairs of interdigital electrodes of the standard capacitance. The nominal step capacitance value refers to the capacitance value corresponding to the increase of each pair of interdigital electrodes.

[0006] Optionally, the pair of interdigital electrodes comprises two interdigital electrodes, a plate capacitor and a plurality of side capacitors, each interdigital electrode is located on the same horizontal plane, the plate capacitor is arranged at the center position between the interdigital electrodes, and each side capacitor is arranged on the side of the plate capacitor.

[0007] Optionally, the base of the basic structure or the standard structure is made of borosilicate glass, sapphire or fused quartz.

[0008] A manufacturing method of an improved standard unit of on-chip capacitor, comprising:

[0009] Based on a preset target step capacitor value, a structure parameter corresponding to the preset target step capacitor value is obtained by simulating and calculating the standard unit of on-chip capacitor.

[0010] A plurality of physical objects of the standard unit of on-chip capacitor are manufactured within the left and right ranges of the structure parameter.

[0011] The step capacitor value of the physical object is measured, and the structure parameter corresponding to the physical object closest to the target step capacitor value is selected as the optimal structure design parameter.

[0012] The optimal structure design parameter is applied to the design of the standard unit of on-chip capacitor.

[0013] Optionally, the structure parameter of the standard unit of on-chip capacitor corresponding to the preset target step capacitor value is obtained by simulating and calculating, and specifically comprises:

[0014] The standard unit of on-chip capacitor is simulated, the structure parameter of the interdigital electrode is adjusted in the simulation process, the structure parameter of the simulated standard unit of on-chip capacitor with the preset target step capacitor value is obtained, and the capacitance value is increased close to the target step capacitor value when each pair of interdigital electrode is increased.

[0015] Optionally, the process of obtaining the optimal structure design parameter comprises:

[0016] The capacitance value of each physical object under different numbers of interdigital electrode pairs is measured, and the change amount of the capacitance value when each pair of interdigital electrode is increased is calculated to obtain the nominal step capacitor value corresponding to each physical object.

[0017] The nominal step capacitor values of the physical objects are compared, and the structure parameter corresponding to the physical object closest to the target step capacitor value is selected as the optimal structure design parameter.

[0018] Optionally, the process of calculating the nominal step capacitor value comprises:

[0019] C Sp = C w

[0020] In the formula, C Sp represents the nominal step capacitor value, and Cw This represents the theoretical capacitance between a pair of independent interdigital electrodes.

[0021] The technical effects of this invention are as follows:

[0022] The basic structure of this invention enables linear changes in capacitance value through variations in the number of electrode pairs without requiring interdigitated electrode pairs, thus reducing the area of ​​the basic structure. Furthermore, since the basic structure does not include interdigitated electrode pairs, the influence of the basic structure capacitance can be ignored when performing large capacitance steps, allowing measurement only of the standard structure capacitance.

[0023] In this invention, the capacitance of the standard capacitor cell and the number of interdigitated electrode pairs are linearly related; the capacitance value is changed by alternating the number of interdigitated electrode pairs. If different interdigitated electrodes are arranged alternately when adding interdigitated electrode pairs, adjacent interdigitated electrode pairs will influence each other, introducing an influence coefficient between interdigitated electrode pairs. If, when adding the number of interdigitated electrode pairs, the electrodes on the same side of adjacent interdigitated electrode pairs are adjacent—that is, when adding interdigitated electrode pairs, the existing interdigitated electrode pairs are first horizontally mirrored before adding, ensuring that adjacent interdigitated electrode pairs are horizontally mirrored and thus achieving a shielding effect between adjacent electrode pairs—the influence of the coefficient m can be eliminated, and the capacitance step is completely determined independently by the added interdigitated electrode pairs. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0026] Figure 1 These are schematic diagrams of two interdigitated capacitor structures in embodiments of the present invention;

[0027] Figure 2 The comparison results of equipotential lines for the two structures in the embodiments of the present invention;

[0028] Figure 3 This is a schematic diagram of the standard on-chip capacitor cell structure in an embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram of the improved interdigitated capacitor structure in an embodiment of the present invention. Detailed Implementation

[0030] The following detailed description of various example embodiments of the application is not to be taken as limiting the application as the application can be practiced with modification and alteration, and not to be limited only by the detailed description.

[0031] It should be understood that the terms used herein are for the purpose of describing particular embodiments and are not intended to limit the application. Additionally, for numerical ranges that are expressed in a range format, it is intended that any numerical value encompassed within the lower and upper limits of the range is also specifically contemplated. For example, if a range of 2.0- 6.0 is stated, it is intended that any number, for example 3.14, between the lower value of 2.0 and the upper value of 6.0, is expressly identified as being expressly stated. Each smaller range between the upper and lower limit of a cited range is also explicitly stated unless a context suggests that a smaller range is not intended. The use of "about" in connection with a value means that the variable "about" has the same meaning as "approximately," i.e., ± 10% of the value.

[0032] Many modifications and variations of this application can be made in the light of the above teachings without departing from the spirit and scope thereof. Additional implementations of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. Each feature disclosed in this specification, and / or the specification of any document incorporated by reference herein, can be provided independently of any other feature. Each combination of features disclosed in this specification, and / or the specification of any document incorporated by reference herein, is also specifically contemplated unless it is explicitly stated to the contrary.

[0033] In this document, the terms "comprise", "comprising", "include", "including", and the like, are open-ended language, i.e., are intended to mean the inclusion of but not limited to.

[0034] It should be noted that the embodiments and features of the application disclosed in the specification and drawings can be combined with each other, unless specifically stated to the contrary. The application will be described in detail with reference to the drawings and embodiments.

[0035] As shown in the drawings, Figure 1 - Figure 4 The improved on-chip capacitor standard unit in the embodiment includes a basic structure and a standard structure, the basic structure is composed of a probe contact electrode and a connection line, the standard structure is composed of a plurality of pairs of interdigital electrodes added on the basic structure, adjacent electrodes on the same side between adjacent pairs of interdigital electrodes, the standard capacitance value of the on-chip capacitor standard unit is the difference between the standard structure capacitance and the capacitance value of the basic structure, the nominal step capacitance of the standard structure capacitance has a linear relationship with the number of pairs of interdigital electrodes of the standard capacitance, and the nominal step capacitance value refers to the corresponding increased capacitance value of each added pair of interdigital electrodes.

[0036] The improved interdigital capacitor structure in the embodiment specifically includes:

[0037] The application discloses a standard on-chip capacitor unit, which comprises a basic structure and a standard structure, the standard structure is obtained by adding a logarithm of interdigital electrode pairs on the basic structure, a standard capacitance value of the standard on-chip capacitor unit is a difference between a standard structure capacitance and a capacitance value of the basic structure, and a nominal step capacitance of the standard structure capacitance has a linear relationship with the logarithm of the interdigital electrode pairs of the standard capacitance, the nominal step capacitance value refers to an increased capacitance value corresponding to an increase of one pair of interdigital electrodes. The basic structure is composed of a probe contact electrode and a connecting line. The standard structure is composed of the basic structure and the added interdigital electrode pairs. The number of the interdigital electrode pairs is n, and n is greater than or equal to 1. Adjacent electrodes on the same side between adjacent interdigital electrode pairs are adjacent, that is, the existing interdigital electrode pairs are first horizontally mirror-inverted and then increased when the interdigital electrode pairs are added, so that the adjacent interdigital electrode pairs are horizontally mirror-inverted to each other, and a shielding effect between the adjacent interdigital electrode pairs is achieved. The capacitance value of the standard on-chip capacitor unit is obtained by subtracting the capacitance value of the basic structure from the capacitance value of the standard structure. The substrate is made of silicate glass, sapphire or fused quartz.

[0038] The manufacturing steps of the embodiment are as follows:

[0039] (1) Under a set step capacitance value, simulation and calculation are performed on the standard on-chip capacitor unit to obtain structure parameters under the corresponding step value.

[0040] (2) According to the structure parameters, a plurality of physical standard on-chip capacitor units are manufactured in a core and left and right range of the parameters.

[0041] (3) The step capacitance values of the physical units are measured, and structure parameters of a physical unit closest to the set step capacitance value are obtained.

[0042] The calculation formula of the nominal step capacitance value is as follows:

[0043] C Sp =C w (1)

[0044] In the formula, C Sp represents the nominal step capacitance value, and C w represents a theoretical capacitance value between a pair of independent interdigital electrode pairs.

[0045] The calculation formula of the standard capacitance value is as follows:

[0046] C=n×C Sp (2)

[0047] In the formula, C represents the standard capacitance value, C Sp represents the nominal step capacitance value, n represents the logarithm of the interdigital electrode pairs of the standard capacitance, and n is greater than or equal to 1.

[0048] The basic structure of the embodiment can realize linear change of the capacitance value by changing the number of electrode pairs without including the interdigital electrode pairs, thereby reducing the area of the basic structure. Moreover, since the basic structure does not include the interdigital electrode pairs, when large-capacitance stepping is performed, the influence of the basic structure capacitance can be ignored, and only the standard structure capacitance is measured.

[0049] In the embodiment, the capacitance of the capacitance standard unit and the number of interdigital electrode pairs are in linear relationship, and the capacitance value is changed by changing the number of interdigital electrode pairs. If the interdigital electrode pairs are alternately arranged between different interdigital electrode pairs when the interdigital electrode pairs are increased, the influence coefficient m between the interdigital electrode pairs is introduced. If the electrodes on the same side between adjacent interdigital electrode pairs are adjacent when the number of interdigital electrode pairs is increased, that is, the existing interdigital electrode pairs are first horizontally mirrored and then increased when the interdigital electrode pairs are increased, the adjacent interdigital electrode pairs are horizontally mirrored to each other, and the shielding effect between the adjacent electrode pairs is achieved, so that the influence of the coefficient m can be removed, and the capacitance stepping is completely determined by the increased interdigital electrode pairs.

[0050] Figure 1 For comparison between the two structures, structure one is the improved structure provided in the embodiment, and structure two is a traditional structure. When the interdigital electrode width a is equal to the relative distance b, the interdigital capacitance with different numbers of interdigital electrode pairs is simulated by COMSOL software, the influence of the connecting line is considered, the dislocation length C is 120 μm, and the relative distance L is 160 μm. In the case that the width of the connecting line is much larger than 12 μm, 1V voltage is added to one end of the interdigital capacitance, and the other end is grounded. As shown in FIG. 6, the potential contour lines of the front and side of the interdigital capacitance with different numbers of interdigital electrode pairs are shown. Figure 2 The influence coefficient m between the interdigital electrode pairs is obtained by simulation and calculation, and the value of the influence coefficient m is about 0.68-0.7.

[0051] Due to the influence of m, when the same length of interdigital electrode is added to the two structures in the same environment, the added capacitance values are different. When the same length, width and relative distance of the interdigital electrode pairs are added to structure 1 and structure 2, the added capacitances are C1 and C2 respectively. C1 and C2 are shown in formula 3 and formula 4. When the interdigital electrode structure is changed, the influence on structure 2 is smaller. Since the electrodes on the same side between adjacent interdigital electrode pairs are adjacent, the shielding effect between the adjacent electrode pairs is achieved, the manufacturing error of the interdigital electrode does not affect the adjacent interdigital electrode, and the stepping capacitance value of structure 2 is completely determined by the increased interdigital electrode pairs.

[0052] When one pair of interdigital electrode is added, the capacitance stepping value of structure 1 is C Sp1 , the capacitance stepping value of structure 2 is C Sp2 , and C wLet m represent the theoretical capacitance of a pair of independent interdigital electrodes, with the influence coefficient between the interdigital electrodes being m.

[0053] C Sp1 =C w (3

[0054] C Sp1 =2mC w (4

[0055] The specific implementation plan of this embodiment is as follows:

[0056] 1) Modeling of the Standard Capacitor Unit: The basic structure consists of probe contact electrodes and connecting wires. The standard structure is constructed by adding interdigitated electrode pairs to the basic structure. The number of interdigitated electrodes is n, where n≥1. Electrodes on the same side of adjacent interdigitated electrode pairs are adjacent; that is, when adding an interdigitated electrode pair, the existing interdigitated electrode pairs are first horizontally mirrored before being added, ensuring that adjacent interdigitated electrode pairs are horizontally mirrored and thus providing shielding between adjacent electrode pairs. The capacitance value of the standard capacitor unit is obtained by subtracting the capacitance value of the basic structure from the capacitance value of the standard structure.

[0057] Because standard capacitors include additional capacitance structures besides interdigital capacitors, such as the capacitance between probe contacts and electrodes, and the capacitance between connecting wires, it is difficult to directly measure the capacitance value of standard interdigital capacitors. To eliminate the influence of these additional capacitances, a base capacitor is introduced.

[0058] The only difference between a basic capacitor and a standard capacitor is the number of interdigitated electrode pairs; a basic capacitor has zero interdigitated electrode pairs.

[0059] The capacitance value of a standard capacitor unit can be obtained by subtracting the capacitance value of the base capacitor from the standard capacitance value, expressed by the formula:

[0060] C = C T -C0 (5)

[0061] Where C represents the capacitance value of a standard capacitor unit, C T C0 represents the total capacitance of the standard capacitors, while C0 represents the capacitance of the base capacitor.

[0062] The basic capacitor structure serves to eliminate interference from external sources, capacitance between transmission lines, capacitance between test probes, and interference from redundant structures other than the interdigitated electrodes.

[0063] 2) Determine the step capacitor value C Sp1 :like Figure 4 The diagram shows a top view and a cross-sectional view of an interdigital electrode pair, with the capacitance C between the two interdigital electrodes shown. wC1, C2, C3, wherein C2 is the capacitance of the interdigital electrode facing the flat plate capacitor structure; C1 and C3 are the side capacitances of the flat plate capacitor structure, and the calculation formula is as follows:

[0064] C w = C1 + C2 + C3 (6

[0065] C Sp1 = C w (7

[0066] C2 is the common flat plate capacitor structure, which can be calculated by formula (8):

[0067]

[0068] C1 and C3 can be calculated by the method of Schwart-Z Kristof angle transformation, as formula (9):

[0069]

[0070] The calculation formula of the standard capacitance value is as follows:

[0071] C = n x C Sp1 (10

[0072] Wherein, C represents the standard capacitance value, C Sp represents the nominal step capacitance value, n represents the logarithm of the interdigital electrode of the standard capacitance, and n≥1.

[0073] The structure parameters (length L, width b, and relative distance a between electrodes) of the interdigital electrode are determined as follows:

[0074] S1: Under the set step capacitance value, the structure parameters under the corresponding step value are obtained by simulating and theoretically calculating the on-chip capacitance standard unit.

[0075] S2: According to the structure parameters, a plurality of physical on-chip capacitance standard units are manufactured in the core and left and right range of the parameters.

[0076] S3: The step capacitance value of the physical object is measured, and the optimal structure parameter closest to the set step capacitance value physical object is obtained;

[0077] The process steps are as follows: (1) substrate cleaning: including acetone, ethanol, isopropyl alcohol (IPA) cleaning to remove borosilicate glass surface organic pollution, concentrated sulfuric acid and hydrogen peroxide cleaning to remove metal pollution ions remaining on the substrate surface; (2) photolithography: using a designed photomask for photolithography exposure to define the capacitance structure pattern; (3) using metal sputtering or evaporation process to deposit metal. (4) using wet etching process to remove excess metal.

[0078] Thirdly, the linear variation of standard capacitance value is realized by the variation of the number of interdigital electrodes:

[0079] On the Fused Silica Wafer substrate, on-chip capacitors with step values of 100 fF in the range of 100 fF-1 pF are fabricated.

[0080] The Fused Silica Wafer has a low thermal expansion coefficient and a dielectric constant of 3.79. The measured values are shown in Table 1. The test instrument uses an EB series probe station, a 73CT-APTA coaxial probe, and an AH2700A multi-frequency capacitance bridge.

[0081] When measuring, the standard capacitance value C of the capacitance standard sample is calculated using formula (11):

[0082] C = C T -C0 (11)

[0083] Table 1 100 fF step capacitance values measured

[0084]

[0085] This embodiment realizes the linear variation of the capacitance value by optimizing the interdigital capacitor structure design and introducing a basic capacitance to eliminate the influence of additional capacitance. The structure parameters are optimized through simulation and experiment, and the low thermal expansion coefficient of the fused silica substrate ensures the accuracy of the capacitance measurement and stability.

[0086] The above is only the preferred specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An improved on-chip capacitor standard cell comprising a base structure and a standard structure, the base structure consisting of a probe contact electrode and a connection line, the standard structure being constituted by adding a pair of interdigital electrodes on the base structure, characterized in that, The interdigital electrode pairs are arranged in several pairs, and the electrodes on the same side between adjacent interdigital electrode pairs are adjacent, and the existing interdigital electrode pairs are first horizontally mirrored and then increased when increasing the interdigital electrode pairs, so as to ensure that the adjacent interdigital electrode pairs are horizontally mirrored, the standard capacitance value of the on-chip capacitance standard unit is the difference between the standard structure capacitance and the capacitance value of the basic structure, the nominal step capacitance of the standard structure capacitance has a linear relationship with the number of interdigital electrode pairs of the standard capacitance, and the nominal step capacitance value refers to the corresponding increased capacitance value of each increased interdigital electrode pair.

2. The improved on-chip capacitor standard cell of claim 1, wherein, The interdigital electrode pair includes two interdigital electrodes, a flat plate capacitor and a plurality of side capacitors, each interdigital electrode is located on the same horizontal plane, the flat plate capacitor is arranged at the center position between the interdigital electrodes, and each side capacitor is arranged on the side of the flat plate capacitor.

3. The improved on-chip capacitor standard cell of claim 1, wherein, The base of the basic structure or the standard structure is made of borosilicate glass, sapphire or fused quartz.

4. The method of claim 1-3, wherein the method further comprises: forming a first metal layer on the substrate; forming a first dielectric layer on the first metal layer; forming a second metal layer on the first dielectric layer; forming a second dielectric layer on the second metal layer; and forming a third metal layer on the second dielectric layer. Comprise: Based on the preset target step capacitance value, the structure parameters corresponding to the preset target step capacitance value are obtained by simulating and calculating the on-chip capacitance standard unit; A plurality of physical on-chip capacitance standard units are manufactured within the left and right ranges of the structure parameters; The step capacitance value of the physical object is measured, and the structure parameters corresponding to the physical object closest to the target step capacitance value are selected as the optimal structure design parameters; The optimal structure design parameters are applied to the design of the capacitance standard unit.

5. The method of manufacturing according to claim 4, wherein, The structure parameters of the preset target step capacitance value are obtained by simulating and calculating the on-chip capacitance standard unit, and the structure parameters of the simulation on-chip capacitance standard unit with the preset target step capacitance value are obtained by adjusting the structure parameters of the interdigital electrode in the simulation process, so that the capacitance value increases close to the target step capacitance value when each interdigital electrode pair is increased. The optimal structure design parameters are obtained by simulating and calculating the on-chip capacitance standard unit, and the structure parameters of the simulation on-chip capacitance standard unit with the preset target step capacitance value are obtained by adjusting the structure parameters of the interdigital electrode in the simulation process, so that the capacitance value increases close to the target step capacitance value when each interdigital electrode pair is increased.

6. The method of manufacturing according to claim 4, wherein, The optimal structure design parameters are obtained by simulating and calculating the on-chip capacitance standard unit, and the structure parameters of the simulation on-chip capacitance standard unit with the preset target step capacitance value are obtained by adjusting the structure parameters of the interdigital electrode in the simulation process, so that the capacitance value increases close to the target step capacitance value when each interdigital electrode pair is increased. The calculation process of the nominal step capacitance value comprises: ​ 7. The method of manufacturing according to claim 6, wherein, ​ ； wherein represents a nominal step capacitance value, represents a theoretical capacitance value between a pair of independent interdigital electrode pairs.

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