Multi-channel signal processing system and method in intelligent controller hardware

Abstract

The invention discloses a multichannel signal processing system and method in intelligent controller hardware, and the system comprises controller hardware which provides a plurality of groups of signal processing programs. According to the invention, by optimizing the allocation of the actuators, the time delay and unnecessary resource consumption in the signal processing process are reduced, the operation efficiency of the whole system is improved, the system can meet different signal processing requirements through the setting of multiple groups of signal processing programs, the flexibility and adaptability of the system are enhanced, and the system is suitable for popularization and application. The safety verification step ensures that the system is not damaged due to wrong or malicious requests, the overall safety of the system is improved, the system can more effectively utilize the existing actuator resources by screening the actuators which cannot meet the requirement of a signal processing program and constructing an auxiliary optimization scheme, the waste of the resources is avoided, and the safety of the system is improved. And the maintenance cost is lower, the system can be self-adjusted and optimized, and the requirement of manual intervention is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing, and specifically relates to a multi-channel signal processing system and method in an intelligent controller hardware. Background Art

[0002] Existing multi-channel control systems rely on multiplexers. The working principle of a multiplexer is to cascade multiple switching switches to adjust the phase and amplitude of different signals. The opening and closing states of these switches are controlled by a system controller.

[0003] However, the system controller will issue a control instruction only after receiving the corresponding signal. There is a lack of judgment on whether the signal is safe in the system, resulting in the system being vulnerable to damage. And when each multiplexer receives a signal, it needs a corresponding actuator to execute. Due to the large number of actuators and the poor distribution strategy of the actuators, it will consume a lot of time and is difficult to meet the needs of the staff. Summary of the Invention

[0004] To solve the above technical problems, the present invention provides a multi-channel signal processing system in an intelligent controller hardware. This technical solution solves the problems in the above background art that the system controller will issue a control instruction only after receiving the corresponding signal, there is a lack of judgment on whether the signal is safe in the system, resulting in the system being vulnerable to damage, and when each multiplexer receives a signal, it needs a corresponding actuator to execute. Due to the large number of actuators and the poor distribution strategy of the actuators, it will consume a lot of time.

[0005] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0006] In the first aspect of the present invention, there is provided a multi-channel signal processing system in an intelligent controller hardware, including:

[0007] Controller hardware, the controller hardware provides multiple sets of signal processing programs, and each set of signal processing programs is used to control different numbers of actuators;

[0008] A first judgment module, the first judgment module is used to receive a signal processing request and judge whether the signal processing request is safe;

[0009] A first acquisition module, the first acquisition module is used to obtain the current signal processing scenario and the user-mode code that needs to be recognized for the current signal processing according to the signal processing request;

[0010] A second judgment module, the second judgment module is used to judge whether each actuator can meet multiple sets of signal processing programs according to the signal processing scenario and the recognized user-mode code;

[0011] A second acquisition module, which is used to acquire factors affecting signal processing delay. The signal processing delay factors include transmission medium characteristics, circuit impedance and matching, and network topology. A first actuator allocation optimization scheme is formulated using profiling and simulation evaluation methods;

[0012] A screening module, which is used to screen out actuators that cannot meet the signal processing program and construct a second actuator auxiliary optimization scheme;

[0013] An execution module, which is used to collectively refer to the first actuator allocation optimization scheme and the second actuator auxiliary optimization scheme as the actuator comprehensive optimization allocation optimization scheme, and perform it according to the actuator comprehensive optimization allocation optimization scheme for multiple groups of signal processing program requirements.

[0014] In a second aspect of the present invention, a multi-channel signal processing method in an intelligent controller hardware is further provided, including:

[0015] The controller hardware provides multiple groups of signal processing programs, where each group of signal processing programs is used to control different numbers of actuators;

[0016] Receive a signal processing request and determine whether the signal processing request is secure;

[0017] Obtain the current signal processing scenario and the user-mode code to be recognized for the current signal processing according to the signal processing request;

[0018] Judge whether each actuator can meet multiple groups of signal processing programs according to the signal processing scenario and the recognized user-mode code;

[0019] Obtain factors affecting signal processing delay. The signal processing delay factors include transmission medium characteristics, circuit impedance and matching, and network topology. A first actuator allocation optimization scheme is formulated using profiling and simulation evaluation methods;

[0020] Screen out actuators that cannot meet the signal processing program and construct a second actuator auxiliary optimization scheme;

[0021] Collectively refer to the first actuator allocation optimization scheme and the second actuator auxiliary optimization scheme as the actuator comprehensive optimization allocation optimization scheme, and perform it according to the actuator comprehensive optimization allocation optimization scheme for multiple groups of signal processing program requirements.

[0022] Preferably, the step of receiving the signal processing request and determining whether the signal processing request is secure specifically includes the following steps:

[0023] Obtain the communication protocol of the virus database;

[0024] The controller hardware establishes a communication connection with the virus database based on the communication protocol of the virus database;

[0025] The controller hardware scans and judges the request data for signal processing according to the virus data stored in the virus database;

[0026] If part of the content in the request data coincides with the virus data stored in the virus database, the controller hardware refuses to receive the request data;

[0027] If the content in the request data does not coincide with the virus data stored in the virus database, the controller hardware conducts a secondary verification of the request data to determine the security of the request data.

[0028] Preferably, the controller hardware conducts a secondary verification of the request data to determine the security of the request data, which specifically includes the following steps:

[0029] The controller hardware sends a data reading instruction to the sending device to obtain the historical metadata of the request data, including creator information, modification date information, and file size information;

[0030] The controller hardware extracts data from the request data to obtain real-time metadata;

[0031] Compare the historical metadata and the real-time metadata. If they are exactly the same, the request data is secure; otherwise, the request data is at risk;

[0032] The controller hardware receives or rejects the request data according to the judgment result.

[0033] Preferably, according to the current signal processing scenario and the user-mode code to be recognized for the current signal processing need, determine the executor for signal processing, receive the system call request, and check the permissions, and recognize the user-mode code based on the system permissions.

[0034] Preferably, the judgment of whether each executor can meet multiple groups of signal processing programs specifically includes the following steps:

[0035] Based on the multiple historical requirement data of the executor, perform fitting calculation on the requirement-time period change curve of each executor;

[0036] Obtain the maximum capacity of the executor;

[0037] Based on the maximum capacity of the executor and the requirement-time period change curve of each executor, calculate the change curve of the redundancy value-time period;

[0038] Determine whether there is a negative value in the redundancy value. If so, it is determined that the actuator cannot meet the requested data for signal processing. Based on the change curve of the redundancy value over time segments, filter out the time segments when the redundancy value is negative, denoted as the actuator overrun time segments, and mark the actuator as an overrun actuator. If not, it is determined that the actuator can meet the signal processing request.

[0039] Preferably, the expression of the change curve of the redundancy value over time segments is:

[0040]

[0041] In the formula, A(t) is the expression of the change curve of the redundancy value over time segments, Ad is the maximum capacity of the actuator, n is the total number of registers, and Sd(t)i is the expression of the change curve of the demand over time segments of the i-th actuator.

[0042] Preferably, the specific steps for filtering out the actuators that cannot meet the signal processing program are as follows:

[0043] Determine the absolute value of the redundancy value of the actuator in each actuator overrun time segment, denoted as the overrun amount;

[0044] Filter out the actuators whose signal processing requests in all overrun time segments exceed the overrun amount, denoted as the actuators to be verified;

[0045] Filter out those among all the actuators to be verified whose processing time is less than the threshold as the actuators to be allocated.

[0046] Preferably, the specific steps for constructing the second actuator auxiliary optimization scheme are as follows:

[0047] Compare the running time of all the actuators to be verified with the preset threshold in the system;

[0048] If the running time of the actuator to be verified is greater than or equal to the preset threshold, then the actuator is not within the allocation optimization scheme;

[0049] If the running time of the actuator to be verified is less than the preset threshold, then it is within the allocation optimization scheme, form an actuator set, and use this actuator set to allocate signal processing requests.

[0050] In the third aspect of the present invention, there is also provided an electronic device. The electronic device includes at least one processor; and a memory communicatively connected to the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method of the first aspect of the present invention.

[0051] Compared with the prior art, the present invention provides a multi-channel signal processing system and method in an intelligent controller hardware, having the following beneficial effects:

[0052] By optimizing the allocation of actuators, the present invention reduces the delay and unnecessary resource consumption in the signal processing process, improves the operation efficiency of the entire system. The setting of multiple groups of signal processing programs enables the system to handle different signal processing requirements, enhancing the flexibility and adaptability of the system. The security verification step ensures that the system will not be damaged due to incorrect or malicious requests, improving the overall security of the system. By screening the actuators that cannot meet the signal processing programs and constructing an auxiliary optimization scheme, the system can more effectively utilize the existing actuator resources, avoid waste of resources, and has lower maintenance costs. The system can self-adjust and optimize, reducing the need for manual intervention. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 Schematic diagram of the multi-channel signal processing method in the intelligent controller hardware of the present invention;

[0054] Figure 2 Schematic diagram of the method for receiving a signal processing request and determining whether the signal processing request is safe in the present invention;

[0055] Figure 3 Schematic diagram of the method for the controller hardware to perform secondary verification on the request data and determine the security of the request data in the present invention;

[0056] Figure 4 Schematic diagram of the method for determining whether each actuator can meet multiple groups of signal processing programs in the present invention;

[0057] Figure 5 Schematic diagram of the method for screening out the actuators that cannot meet the signal processing programs in the present invention;

[0058] Figure 6 Schematic diagram of the method for constructing a second actuator auxiliary optimization scheme in the present invention;

[0059] Figure 7 Block diagram of an exemplary electronic device capable of implementing the embodiments of the present invention is shown;

[0060] Among them, 700 is the electronic device, 701 is the computing unit, 702 is the ROM, 703 is the RAM, 704 is the bus, 705 is the I / O interface, 706 is the input unit, 707 is the output unit, 708 is the storage unit, and 709 is the communication unit. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0061] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments in the following description are only examples, and other obvious variations can be conceived by those skilled in the art.

[0062] Embodiment 1

[0063] In a first aspect of the present invention, a multi-channel signal processing system in intelligent controller hardware is provided, including:

[0064] Controller hardware that provides multiple sets of signal processing programs, where each set of signal processing programs is used to control a different number of actuators;

[0065] A first judgment module that is used to receive a signal processing request and judge whether the signal processing request is safe;

[0066] A first acquisition module that is used to obtain the current signal processing scenario and the user-mode code that needs to be recognized for the current signal processing according to the signal processing request;

[0067] A second judgment module that is used to judge whether each actuator can meet multiple sets of signal processing programs according to the signal processing scenario and the recognized user-mode code;

[0068] A second acquisition module that is used to obtain factors affecting signal processing delay. The signal processing delay factors include transmission medium characteristics, circuit impedance and matching, and network topology. A first actuator allocation optimization scheme is formulated using profiling and simulation evaluation methods;

[0069] A screening module that is used to screen out the actuators that cannot meet the signal processing program and construct a second actuator auxiliary optimization scheme;

[0070] An execution module that is used to collectively refer to the first actuator allocation optimization scheme and the second actuator auxiliary optimization scheme as an actuator comprehensive optimization allocation optimization scheme, and perform according to the actuator comprehensive optimization allocation optimization scheme for the requirements of multiple sets of signal processing programs.

[0071] Please refer to Figure 1 As shown, in a second aspect of the present invention, a multi-channel signal processing method in intelligent controller hardware is further provided, including:

[0072] S101. The controller hardware provides multiple sets of signal processing programs, where each set of signal processing programs is used to control a different number of actuators;

[0073] S102. Receive a signal processing request and judge whether the signal processing request is safe;

[0074] S103. Obtain the current signal processing scenario and the user-mode code to be recognized for the current signal processing according to the signal processing request;

[0075] S104. Determine whether each actuator can meet multiple groups of signal processing programs according to the signal processing scenario and the recognized user-mode code;

[0076] S105. Obtain the factors affecting signal processing delay, where the signal processing delay factors include transmission medium characteristics, circuit impedance and matching, and network topology. Use profiling and simulation evaluation methods to formulate the first actuator allocation optimization plan;

[0077] S106. Screen out the actuators that cannot meet the signal processing programs and construct the second actuator auxiliary optimization plan;

[0078] S107. Collectively refer to the first actuator allocation optimization plan and the second actuator auxiliary optimization plan as the actuator comprehensive optimization allocation plan, and perform according to the actuator comprehensive optimization allocation plan for the requirements of multiple groups of signal processing programs.

[0079] Those skilled in the art can understand that by optimizing the allocation of actuators, the present invention reduces the delay and unnecessary resource consumption in the signal processing process, improves the operation efficiency of the entire system. The setting of multiple groups of signal processing programs enables the system to handle different signal processing requirements, enhances the flexibility and adaptability of the system. The security verification step ensures that the system will not be damaged due to incorrect or malicious requests, improving the overall security of the system. By screening out the actuators that cannot meet the signal processing programs and constructing an auxiliary optimization plan, the system can more effectively utilize the existing actuator resources, avoid waste of resources, have lower maintenance costs, the system can self-adjust and optimize, reducing the need for manual intervention.

[0080] Please refer to Figure 2 As shown, accept the signal processing request and determine whether the signal processing request is secure, which specifically includes the following steps:

[0081] S201. Obtain the communication protocol of the virus database;

[0082] S202. The controller hardware establishes a communication connection with the virus database based on the communication protocol of the virus database;

[0083] S203. The controller hardware scans and judges the request data for signal processing according to the virus data stored in the virus database;

[0084] S204. If some content in the request data coincides with the virus data stored in the virus database, the controller hardware refuses to receive the request data;

[0085] S205. If the content in the request data does not overlap with the virus data stored in the virus database, the controller hardware performs a secondary verification on the request data to determine the security of the request data.

[0086] Those skilled in the art can understand that through comparison with the virus database, the present invention can effectively identify and reject request data containing viruses or malicious codes, improve the security of the system, reject malicious request data to prevent the system from being attacked, thereby avoiding the leakage of sensitive data and data damage. Through a strict data verification process, it is ensured that only secure request data is received and processed by the system, which helps to maintain the stability and normal operation of the system. A secure system can reduce system paralysis and data loss caused by viruses or malicious attacks, thereby reducing the maintenance cost of the system. For users, a secure system can provide more reliable services, enhancing user trust and satisfaction.

[0087] Please refer to Figure 3 As shown, the controller hardware performs a secondary verification on the request data to determine the security of the request data, which specifically includes the following steps:

[0088] S301. The controller hardware sends a data reading instruction to the sending device to obtain the historical metadata of the request data, including creator information, modification date information, and file size information.

[0089] S302. The controller hardware extracts data from the request data to obtain real-time metadata.

[0090] S303. Compare the historical metadata and the real-time metadata. If they are exactly the same, the request data is secure; otherwise, the request data is at risk.

[0091] S304. The controller hardware receives or rejects the request data according to the judgment result.

[0092] Those skilled in the art can understand that by comparing the historical metadata and the real-time metadata, the present invention can effectively identify tampered or damaged request data, thereby improving data security. This process can detect whether the data has been illegally modified during transmission or processing, thereby preventing data tampering. By ensuring the consistency of the metadata of the data during transmission, it helps to maintain data integrity. The process of comparing metadata helps to identify data problems caused by transmission errors or improper processing, thereby reducing data errors. The reliability of a system that can accurately identify and reject insecure data will be significantly improved.

[0093] Identify the executor for signal processing according to the current signal processing scenario and the user-mode code to be identified in the current signal processing need, receive the system call request, check the permissions, and identify the user-mode code based on the system permissions.

[0094] Please refer to Figure 4 as shown below, to determine whether each actuator can meet multiple signal handlers, the specific steps are as follows:

[0095] S401. Based on multiple historical demand data of the actuator, perform fitting calculations on the demand - time period change curve of each actuator;

[0096] S402. Obtain the maximum capacity of the actuator;

[0097] S403. Based on the maximum capacity of the actuator and the demand - time period change curve of each actuator, calculate the change curve of the redundancy value - time period;

[0098] S404. Determine whether there is a negative value in the redundancy value. If so, determine that the actuator cannot meet the requested data for signal processing, and based on the change curve of the redundancy value - time period, screen out the time periods with negative redundancy values, denoted as the actuator over - limit time periods, and mark the actuator as an over - limit actuator. If not, determine that the actuator can meet the signal processing request.

[0099] Those skilled in the art can understand that through fitting calculations based on multiple historical demand data of the actuator, the demand change curve of each actuator at different time periods can be obtained. This helps to understand the historical workload and change trend of the actuator, obtain the maximum capacity of each actuator (i.e., the maximum signal or task volume it can handle), which is the basis for evaluating whether the actuator meets the current signal processing request. Based on the maximum capacity of the actuator and the demand - time period change curve, the change curve of the redundancy value - time period can be calculated. The redundancy value reflects the remaining processing capacity of the actuator relative to its maximum capacity in the current time period. By determining whether there is a negative value in the redundancy value, it can be evaluated whether the actuator can meet the requested data for signal processing. If the redundancy value is negative, it means that the processing capacity of the actuator in the current time period is insufficient and cannot meet the request; otherwise, it is considered that the actuator can meet the request.

[0100] The expression of the change curve of the redundancy value - time period is:

[0101]

[0102] In the formula, A(t) is the expression of the change curve of the redundancy value - time period, Ad is the maximum capacity of the actuator, n is the total number of registers, and Sd(t)i is the expression of the demand - time period change curve of the i - th actuator.

[0103] Please refer to Figure 5 as shown below, to screen out the actuators that cannot meet the signal processing program, the specific steps are as follows:

[0104] S501. Determine the absolute value of the redundancy value of the actuator in each actuator overrun time period, which is denoted as the overrun amount.

[0105] S502. Screen out the actuators whose signal processing requests in all overrun time periods exceed the overrun amount, which are denoted as the actuators to be verified.

[0106] S503. Screen out those among all the actuators to be verified whose processing time is less than the threshold as the actuators to be allocated.

[0107] Please refer to Figure 6 As shown, constructing the second actuator auxiliary optimization scheme specifically includes the following steps:

[0108] S601. Compare the running time of all the actuators to be verified with the preset threshold in the system.

[0109] S602. If the running time of the actuator to be verified is greater than or equal to the preset threshold, then this actuator is not within the allocation optimization scheme.

[0110] S603. If the running time of the actuator to be verified is less than the preset threshold, then it is within the allocation optimization scheme, form an actuator set, and use this actuator set to allocate signal processing requests.

[0111] In the third aspect of the present invention, an electronic device is further provided.

[0112] Figure 7 The schematic block diagram of an electronic device 700 that can be used to implement the embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as, a laptop computer, a desktop computer, a workbench, a personal digital assistant, a server, a blade server, a mainframe computer, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as, a personal digital processor, a cellular phone, a smart phone, a wearable device, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are only examples and are not intended to limit the implementation of the present invention described herein and / or claimed.

[0113] The electronic device 700 includes a computing unit 701, which can execute various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 702 or the computer program loaded from the storage unit 708 into the random access memory (RAM) 703. In the RAM 703, various programs and data required for the operation of the electronic device 700 can also be stored. The computing unit 701, the ROM 702, and the RAM 703 are connected to each other through a bus 704. The input / output (I / O) interface 705 is also connected to the bus 704.

[0114] Multiple components in the electronic device 700 are connected to the I / O interface 705, including: an input unit 706, such as a keyboard, a mouse, etc.; an output unit 707, such as various types of displays, speakers, etc.; a storage unit 708, such as a magnetic disk, an optical disc, etc.; and a communication unit 709, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 709 allows the electronic device 700 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0115] The computing unit 701 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 701 include but are not limited to a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 701 executes the various methods and processes described above, such as methods S100 - S600. For example, in some embodiments, methods S101 - S107 can be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as the storage unit 708. In some embodiments, part or all of the computer program can be loaded and / or installed onto the electronic device 700 via the ROM 702 and / or the communication unit 709. When the computer program is loaded into the RAM 703 and executed by the computing unit 701, one or more steps of methods S101 - S107 described above can be executed. Alternatively, in other embodiments, the computing unit 701 can be configured to execute methods S101 - S107 in any other suitable manner (e.g., by means of firmware).

[0116] The various embodiments of the systems and technologies described above in this article can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGA), application-specific integrated circuits (ASIC), application-specific standard products (ASSP), systems on a chip (SOC), complex programmable logic devices (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: implemented in one or more computer programs, the one or more computer programs can be executed and / or interpreted on a programmable system including at least one programmable processor, the programmable processor can be a special or general-purpose programmable processor, can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit the data and instructions to the storage system, the at least one input device, and the at least one output device.

[0117] The program code for implementing the method of the present invention can be written in any combination of one or more programming languages. These program codes can be provided to the processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing devices, such that when the program codes are executed by the processor or controller, the functions / operations specified in the flowchart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, executed partially on the machine as an independent software package and partially on a remote machine, or executed entirely on a remote machine or server.

[0118] In the context of the present invention, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0119] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which the user can provide input to the computer. Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0120] The systems and techniques described herein can be implemented in a computing system including backend components (e.g., as a data server), or a computing system including middleware components (e.g., an application server), or a computing system including frontend components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described herein), or a computing system including any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected to each other by digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include: local area network (LAN), wide area network (WAN), and the Internet.

[0121] A computer system can include a client and a server. The client and the server are generally remote from each other and typically interact through a communication network. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, can also be a server of a distributed system, or a server incorporating a blockchain.

[0122] In summary, the present invention optimizes the allocation of actuators, reduces delays and unnecessary resource consumption in the signal processing process, improves the operating efficiency of the entire system. The setting of multiple groups of signal processing programs enables the system to handle different signal processing requirements, enhancing the flexibility and adaptability of the system. The security verification step ensures that the system will not be damaged due to incorrect or malicious requests, improving the overall security of the system. By screening actuators that cannot meet the signal processing programs and constructing an auxiliary optimization scheme, the system can more effectively utilize the existing actuator resources, avoid waste of resources, and has lower maintenance costs. The system can self-adjust and optimize, reducing the need for manual intervention.

[0123] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art of this industry should understand that the present invention is not limited by the above embodiments. What is described in the above embodiments and the specification is only the principle of the present invention. Without departing from the spirit and scope of the present invention, the present invention will have various changes and improvements, and these changes and improvements all fall within the scope of the present invention claimed. The scope of protection claimed by the present invention is defined by the appended claims and their equivalents.

Claims

1. A multi-channel signal processing system in intelligent controller hardware, characterized in that ,include: Controller hardware, the controller hardware providing multiple groups of signal processing programs, wherein each group of signal processing programs is used to control a different number of actuators; A first determination module, configured to accept a signal processing request and determine whether the signal processing request is safe; A first acquisition module, the first acquisition module is used to acquire the current signal processing scenario and the user state code required to be identified for the current signal processing according to the signal processing request; A second judgment module, the second judgment module is used to judge whether each actuator can satisfy multiple groups of signal processing procedures according to the signal processing scenario and the identified user mode code; A second acquisition module, the second acquisition module is used to acquire factors affecting signal processing delay, the signal processing delay factors include transmission medium characteristics, circuit impedance and matching, and network topology, and formulate a first actuator allocation optimization plan using profiling and simulation evaluation methods; A screening module, wherein the screening module is used to screen out actuators that cannot meet the signal processing program and construct a second actuator auxiliary optimization solution; An execution module is used to collectively refer to the first actuator allocation optimization scheme and the second actuator auxiliary optimization scheme as an actuator comprehensive optimization allocation optimization scheme, and to perform multiple groups of signal processing program requirements according to the actuator comprehensive optimization allocation optimization scheme.

2. A multi-channel signal processing method in intelligent controller hardware, characterized in that: include: The controller hardware provides multiple groups of signal processing programs, where each group of signal processing programs is used to control a different number of actuators; Accept the signal processing request and determine whether the signal processing request is safe; Obtain the current signal processing scenario and the user-mode code that needs to be identified for the current signal processing according to the signal processing request; Determining whether each executor can satisfy multiple groups of signal processing procedures according to the signal processing scenario and the identified user-mode code; Obtaining factors affecting signal processing delay, wherein the signal processing delay factors include transmission medium characteristics, circuit impedance and matching, and network topology, and formulating a first actuator allocation optimization plan using profiling and simulation evaluation methods; Screen out the actuators that cannot meet the signal processing procedures and build a second actuator auxiliary optimization solution; The first actuator allocation optimization scheme and the second actuator auxiliary optimization scheme are collectively referred to as an actuator comprehensive optimization allocation optimization scheme, and multiple groups of signal processing program requirements are performed according to the actuator comprehensive optimization allocation optimization scheme.

3. The multi-channel signal processing method in intelligent controller hardware according to claim 2, characterized in that: The step of accepting a signal processing request and determining whether the signal processing request is safe specifically includes the following steps: Communication protocol for obtaining virus database; The controller hardware establishes a communication connection with the virus database based on the communication protocol of the virus database; The controller hardware scans and judges the request data for signal processing according to the virus data stored in the virus database; If part of the content in the request data coincides with the virus data stored in the virus database, the controller hardware refuses to receive the request data; If the content in the request data does not overlap with the virus data stored in the virus database, the controller hardware performs a secondary verification on the request data to determine the security of the request data.

4. The multi-channel signal processing method in intelligent controller hardware according to claim 3 is characterized in that: The controller hardware performs a secondary verification on the request data to determine the security of the request data, specifically including the following steps: The controller hardware sends a data read instruction to the sending device to obtain historical metadata of the requested data, including creator information, modification date information, and file size information; The controller hardware extracts the requested data and obtains real-time metadata; Compare historical metadata with real-time metadata. If they are exactly the same, the requested data is safe. Otherwise, the requested data is risky. The controller hardware accepts or rejects the request data based on the judgment result.

5. The multi-channel signal processing method in intelligent controller hardware according to claim 4, characterized in that: According to the current signal processing scenario and the user-mode code that needs to be identified for the current signal processing, the executor that performs the signal processing is determined, the system call request is received, and the permissions are checked. Based on the system permissions, the user-mode code is identified.

6. The multi-channel signal processing method in intelligent controller hardware according to claim 5, characterized in that: The step of judging whether each actuator can satisfy multiple groups of signal processing procedures specifically includes the following steps: Based on multiple historical demand data of the actuator, the demand-time period change curve of each actuator is fitted and calculated; Get the maximum capacity of the actuator; Calculate the redundancy value-time period change curve based on the maximum capacity of the actuator and the demand-time period change curve of each actuator; Determine whether the redundancy value has a negative value. If so, determine that the executor cannot meet the request data for signal processing, and based on the redundancy value-time period change curve, filter out the time period with a negative redundancy value, record it as the executor over-limit time period, and mark the executor as an over-limit executor. If not, determine that the executor can meet the signal processing request.

7. The multi-channel signal processing method in intelligent controller hardware according to claim 6, characterized in that: The expression of the change curve of the redundancy value-time period is: Where A(t) is the expression of the redundancy value-time period change curve, Ad is the maximum capacity of the actuator, n is the total number of registers, and Sd(t)i is the expression of the demand-time period change curve of the i-th actuator.

8. The multi-channel signal processing method in intelligent controller hardware according to claim 7, characterized in that: The method of screening out the executors that cannot satisfy the signal processing procedure specifically comprises the following steps: Determine the absolute value of the redundancy value of the actuator in each actuator over-limit time period, and record it as the over-limit amount; Filter out the executors whose signal processing requests in all over-limit time periods exceed the over-limit amount and record them as the executors to be verified; Filter out all executors to be verified whose processing time is less than the threshold as executors to be assigned.

9. The multi-channel signal processing method in intelligent controller hardware according to claim 8, characterized in that: The construction of the second actuator auxiliary optimization scheme specifically includes the following steps: Compare the running time of all actuators to be verified with the preset threshold in the system; If the running time of the executor to be verified is greater than or equal to the preset threshold, the executor is not included in the allocation optimization plan; If the running time of the executor to be verified is less than a preset threshold, an executor set is formed within the allocation optimization scheme, and the executor set is used to allocate the signal processing request.

10. An electronic device comprising at least one processor; and a memory connected to the at least one processor in communication; characterized in that: The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 2 to 9.

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