Mirror image switching method and device of logic processing unit, controller and storage medium
By receiving the switching instructions on the external controller of the logic processing unit and triggering the mirror switching, the problem in the prior art that the mirror cannot be switched when the working mirror is started normally is solved, improving the flexibility of mirror switching and avoiding misoperation.
Patent Information
- Application Number
- CN202510312090.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-17
- Publication Date
- 2025-06-27
AI Technical Summary
In the prior art, mirror switching cannot be performed when the working mirror is not damaged and is started normally, reducing the flexibility of mirror switching.
Through a controller independent of the logic processing unit, it receives the backup image switching instructions sent by the upper control system, sets the startup configuration pins of the logic processing unit, and uses an external excitation trigger method to switch to the backup image and restart.
When the working image is not damaged, the switch of backup images is realized, which improves the flexibility of mirror switching, and avoids misoperation by enabling protection registers and external excitation triggering.
Smart Images
Figure CN120216135A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of mirror switching, and particularly to a method, device, controller and storage medium for mirror switching of a logic processing unit. Background Art
[0002] In a switch system, a logic processing unit is a core component for implementing data layer management, and there are dual mirrors for components in the logic processing unit. Among them, a mirror is program code or configuration data stored in an external flash memory of the logic processing unit, and includes hardware logic configuration information and function implementation.
[0003] Currently, in related technologies, mirror switching is only performed passively when a cyclic redundancy check fails or the like is detected during the startup phase of the logic processing unit. It is impossible to perform mirror switching when the working mirror is not damaged and starts up normally, which reduces the flexibility of mirror switching. Summary of the Invention
[0004] This application provides a method, device, controller and storage medium for mirror switching of a logic processing unit to at least solve the problem of reduced flexibility of mirror switching in related technologies.
[0005] This application provides a method for mirror switching of a logic processing unit, including:
[0006] Starting the working mirror of the logic processing unit;
[0007] After the working mirror starts up and a switching instruction for the backup mirror sent by the upper control system is received, enabling the protection register is started; wherein the switching instruction includes the starting address of the backup mirror;
[0008] Setting the startup configuration pins of the logic processing unit according to the starting address of the backup mirror;
[0009] Adopting an external excitation trigger mode to trigger the logic processing unit to switch to the backup mirror and restart according to the startup configuration pins;
[0010] Closing the enabling protection register so that when the logic processing unit starts up next time, it starts from the working mirror.
[0011] This application also provides a device for mirror switching of a logic processing unit, including:
[0012] A first startup module for starting the working mirror of the logic processing unit;
[0013] A second startup module for starting the enabling protection register after the working mirror starts up and a switching instruction for the backup mirror sent by the upper control system is received; wherein the switching instruction includes the starting address of the backup mirror;
[0014] A setting module, configured to set the startup configuration pins of the logic processing unit according to the start address of the backup image;
[0015] A switching module, configured to trigger, in an external excitation triggering manner, the logic processing unit to switch to the backup image and restart according to the startup configuration pins;
[0016] A shutdown module, configured to disable the enable protection register, so that when the logic processing unit starts up next time, it starts from the working image.
[0017] This application also provides a controller, including: a memory, configured to store a computer program; a processor, configured to implement the steps of any of the above-mentioned mirror switching methods of the logic processing unit when executing the computer program.
[0018] This application also provides a computer-readable storage medium, in which a computer program is stored, and wherein the computer program implements the steps of any of the above-mentioned mirror switching methods of the logic processing unit when executed by a processor.
[0019] This application also provides a computer program product, including a computer program, and the computer program implements the steps of any of the above-mentioned mirror switching methods of the logic processing unit when executed by a processor.
[0020] Through this application, after the working image of the logic processing unit starts up and a switching instruction of the backup image sent by the upper control system is received, the startup configuration pins of the logic processing unit are set according to the start address of the backup image, and in an external excitation triggering manner, the logic processing unit is triggered to switch to the backup image and restart according to the startup configuration pins. By means of a controller independent of the external of the logic processing unit, the reception and execution of the backup image switching instruction are realized, and the backup image is switched under the condition that the working image is not damaged and starts up normally, improving the flexibility of mirror switching. In addition, by means of the operation of enabling the protection register to confirm the startup configuration pins of the logic processing unit and the operation of the external excitation triggering manner, misoperations are avoided. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] In order to more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.
[0022] Figure 1 It is a principle framework diagram of the mirror switching method of the logic processing unit provided by the embodiment of the present application;
[0023] Figure 2Schematic flowchart of the mirror switching method for the logic processing unit provided by the embodiment of the present application;
[0024] Figure 3 Principle framework diagram for monitoring abnormal events of the logic processing unit provided by the embodiment of the present application;
[0025] Figure 4 Schematic structural diagram of the mirror switching device for the logic processing unit provided by the embodiment of the present application;
[0026] Figure 5 Schematic structural diagram of the controller provided by the embodiment of the present application. Detailed implementation manners
[0027] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.
[0028] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not explicitly listed, or further includes elements inherent to such a process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.
[0029] In order to solve the problem in the prior art that mirror switching cannot be performed when the working mirror is not damaged and starts normally, which reduces the flexibility of mirror switching, the embodiment of the present application proposes the following technical concept: The inventor considered that the logic processing unit cannot perform mirror switching when the working mirror is not damaged and starts normally. It was thought to implement the reception and execution of the mirror switching instruction through a controller independent of the external of the logic processing unit, breaking through the passive switching mode that only depends on the startup failure detection. The controller receives the switching instruction of the backup mirror sent by the upper control system, sets the startup configuration pin of the logic processing unit according to the starting address of the backup mirror, and adopts an external excitation trigger method to trigger the logic processing unit to switch to the backup mirror and restart according to the startup configuration pin. The flexibility of mirror switching is improved. In addition, by enabling the protection register to confirm the operation of the startup configuration pin of the logic processing unit and the operation of the external excitation trigger method, misoperation is avoided.
[0030] To enable those skilled in the art of the present technology to better understand the solution of this application, the following further detailed description of this application will be given in conjunction with the accompanying drawings and specific embodiments.
[0031] In combination with the specific application environment architecture or specific hardware architecture on which the execution of the mirror switching method of the logic processing unit depends, the specific application environment architecture or specific hardware architecture will be described herein.
[0032] Reference Figure 1 , Figure 1 is the principle framework diagram of the mirror switching method of the logic processing unit provided by the embodiment of this application. As Figure 1 shown, it includes an upper-layer control system, a controller, a logic processing unit, and a flash memory.
[0033] The upper-layer control system is connected to the controller through a low-speed control bus. After the controller starts the working mirror of the logic processing unit, the upper-layer control system sends a switching instruction for the backup mirror. The controller sets the startup configuration pin of the logic processing unit, and sets the startup start address of the startup configuration pin of the logic processing unit to the start address of the backup mirror. And an external excitation trigger method is adopted to trigger the logic processing unit to switch to the backup mirror and restart.
[0034] The logic processing unit is connected to the flash memory through a serial device interface bus. When the logic processing unit restarts, according to the startup configuration pin, it reads the configured backup mirror from the flash memory through the serial device interface bus, parses and loads the content of the backup mirror, completes the internal logic initialization, and switches to running with the backup mirror.
[0035] Figure 2 is the flow schematic diagram of the mirror switching method of the logic processing unit provided by the embodiment of this application. As Figure 2 shown, the embodiment of this application provides a mirror switching method for a logic processing unit, and the method will be described in detail as follows:
[0036] S201: Start the working mirror of the logic processing unit.
[0037] Optionally, the logic processing unit may be a Complicated Programmable Logic Device (CPLD)-Field Programmable Gate Array (FPGA). CPLD-FPGA is a semi-custom application-specific integrated circuit, which has a series of advantages such as flexible programming, fast response, and high integration.
[0038] In this embodiment, the logic processing unit is introduced as CPLD-FPGA.
[0039] Optionally, when the CPLD-FPGA starts up, it preferentially starts from the working image.
[0040] S202: After the working image starts up and a switching instruction for the backup image sent by the upper-layer control system is received, the enable protection register is started; the switching instruction includes the starting address of the backup image.
[0041] In this embodiment, when starting from the backup image is required according to requirements or different system configurations, the upper-layer control system will send a switching instruction for the backup image.
[0042] Optionally, the upper-layer control system can be a Central Processor Unit (CPU) system or a Baseboard Management Controller (BMC) system.
[0043] S203: Set the startup configuration pins of the logic processing unit according to the starting address of the backup image.
[0044] Specifically, set the startup starting address of the startup configuration pins of the logic processing unit to the starting address of the backup image.
[0045] S204: Adopt an external excitation trigger method to trigger the logic processing unit to switch to the backup image and restart according to the startup configuration pins.
[0046] Optionally, the external excitation trigger method includes an electrical signal trigger method and a communication instruction trigger method, etc. Among them, for the electrical signal trigger method, by pulling down the pins of the CPLD-FPGA, the signal level corresponding to the pins changes from high level to low level; for the communication instruction trigger method, an instruction for reloading the image is sent to the CPLD-FPGA through a communication protocol.
[0047] Optionally, the PROGRAM pin and the NONCONFIG pin of the CPLD-FPGA can be pulled down to change the signal level corresponding to the pins from high level to low level.
[0048] In this embodiment, the PROGRAM pin and the NONCONFIG pin on the CPLD-FPGA are pulled down. The PROGRAM pin is usually related to the configuration and startup process of the CPLD-FPGA and is used to control operations such as the CPLD-FPGA entering the configuration mode. The NONCONFIG pin is also a pin related to configuration, and its specific function may vary depending on different CPLD-FPGA models, but generally it is related to the control of the configuration state.
[0049] In a digital circuit, the high and low levels of a signal can represent different logical states. Pulling down the PROGRAM or NONCONFIG pin of a CPLD-FPGA means changing the signal level corresponding to these pins from high to low. By changing the pin level state, the CPLD-FPGA is triggered to restart according to the startup configuration pin and switch to the backup image.
[0050] Optionally, when the PROGRAM or NONCONFIG pin is pulled down, the CPLD-FPGA receives this signal and starts reloading the startup process according to the internal design logic. When the CPLD-FPGA restarts, it reads the configured backup image from the flash memory through the serial device interface bus according to the startup configuration pin, parses and loads the backup image content, completes the internal logic initialization, and switches to running with the backup image.
[0051] S205: Disable the enable protection register so that the logic processing unit starts from the working image the next time it starts.
[0052] In this embodiment, the enable protection register is used to confirm the operations of the startup configuration pins of the CPLD-FPGA and the external excitation trigger mode, to avoid misoperations.
[0053] Optionally, since the operation of the CPLD-FPGA switching to the backup image and restarting is implemented by a switching instruction actively sent by the upper control system, it is not necessary to report the interruption situation of the working image to the upper control system.
[0054] In this embodiment, if a switching instruction of the backup image sent by the upper control system is received before starting the logic processing unit, the starting address of the startup configuration pin of the logic processing unit is set to the starting address of the backup image; the backup image of the logic processing unit is started.
[0055] In this embodiment, the controller starts earlier than the CPLD-FPG. If a switching instruction of the backup image sent by the upper control system is received before starting the CPLD-FPGA, it is not necessary to trigger the CPLD-FPGA to restart through the external excitation trigger mode. Only the starting address of the startup configuration pin of the CPLD-FPGA needs to be set to the starting address of the backup image; when starting the CPLD-FPGA, the backup image of the CPLD-FPGA will be directly started according to the startup configuration pin.
[0056] In summary, after the working image of the logic processing unit is started and a switching instruction for the backup image sent by the upper control system is received, according to the starting address of the backup image, the startup configuration pins of the logic processing unit are set, and the external excitation trigger method is used to trigger the logic processing unit to restart with the backup image according to the startup configuration pins. By means of a controller independent of the external of the logic processing unit, the reception and execution of the image switching instruction are realized, breaking through the passive switching mode that only depends on startup failure detection, and improving the flexibility of the image switching of the logic processing unit. In addition, by enabling the protection register to confirm the operation of the startup configuration pins of the logic processing unit and the operation of the external excitation trigger method, misoperation is avoided. In addition, if a switching instruction for the backup image sent by the upper control system is received before starting the logic processing unit, there is no need to use the external excitation trigger method. It is only necessary to set the starting address at which the startup configuration pins of the logic processing unit are started to the starting address of the backup image; when starting the logic processing unit, the backup image of the logic processing unit will be directly started, further improving the flexibility of the image switching of the logic processing unit.
[0057] Optionally, the trigger conditions for backup image switching can be set, such as performance thresholds and error rate indicators, etc.
[0058] Optionally, after the working image of the logic processing unit is started, during the operation of the logic processing unit, for performance thresholds, such as the CPU utilization rate exceeding the CUP utilization rate threshold and the memory occupancy exceeding the memory occupancy threshold; for error rate indicators, such as the port bit error rate exceeding the port bit error rate threshold, the trigger conditions for backup image switching are met. After the trigger conditions for backup image switching are met, a switching request for the backup image is sent to the upper control system to enable the upper control system to confirm whether to switch the backup image. If a switching instruction from the upper control system is received, the backup image is switched; if a non-switching instruction sent by the upper control system is received, the backup image is not switched.
[0059] In summary, by setting the trigger conditions for backup image switching, after the trigger conditions for backup image switching are met, it is decided by the upper control system whether to switch the backup image. Through real-time monitoring and intelligent decision-making, the flexibility of the image switching of the logic processing unit is further improved.
[0060] Based on the above embodiments, in this embodiment, the specific process of monitoring abnormal events of the logic processing unit and performing abnormal processing on the abnormal events to restore the normal operation of the logic processing unit during the operation of the logic processing unit after switching to the backup image is introduced. Refer to Figure 3 , Figure 3 is the principle framework diagram for monitoring abnormal events of the logic processing unit provided by the embodiment of the present application; as Figure 3As shown in the figure, it includes an upper-layer control system, a controller, and a logic processing unit. When an abnormality occurs in the logic processing unit, an abnormality warning signal will be triggered and sent to the controller. The controller switches the working state of the logic processing unit to the reset state, cuts off multiple power supplies of the logic processing unit, and sends the abnormal event to the upper-layer control system for display. Details are as follows:
[0061] S301: Enable the abnormality monitoring function of the logic processing unit; the abnormality monitoring function will trigger an abnormality warning signal when an abnormality occurs in the logic processing unit.
[0062] In this embodiment, the logic processing unit is introduced as a CPLD-FPGA.
[0063] In this embodiment, when the CPLD-FPGA starts to work, the abnormality monitoring function of the CPLD-FPGA is enabled. This can be achieved by writing a specific value to the control register inside the CPLD-FPGA to activate the internal abnormality monitoring circuit. The monitoring circuit inside the CPLD-FPGA collects the working state data of itself in real time, such as temperature data. The monitoring circuit can obtain real-time temperature data through devices such as temperature sensors.
[0064] Exemplarily, when the CPLD-FPGA has a high-temperature abnormality, an abnormality warning signal is triggered. Optionally, the temperature protection point of the CPLD-FPGA is set through its own threshold. For example, if the highest working temperature of the CPLD-FPGA is 120 degrees Celsius, the temperature threshold of the CPLD-FPGA is set to 115 degrees Celsius. When the temperature of the CPLD-FPGA exceeds 115, an abnormality warning signal is triggered.
[0065] In the switch system, as the high-speed data interaction core module, the FPGA design faces significant thermal management challenges. Due to undertaking high-density data processing tasks, the FPGA will generate high power consumption during operation, resulting in a temperature rise. Although passive heat dissipation measures such as heat sinks are usually adopted in engineering, and the working temperature is maintained within the specification range through temperature control strategies, thermal runaway may still occur under extreme working conditions. When the temperature exceeds the threshold, it will not only cause functional failures such as logic timing disorders and signal integrity degradation, but may also cause physical layer damage, leading to irreversible failure. Therefore, when the CPLD-FPGA exceeds the temperature threshold, a protection mechanism for the CPLD-FPGA is enabled in a timely manner. Solve the cost increase caused by heat sinks and cooling fans in high-temperature situations.
[0066] In this embodiment, the abnormality is not limited to the temperature abnormality of the CPLD or FPGA. Optionally, in addition to temperature abnormalities, other possible abnormality situations can also be monitored, such as logic errors and voltage abnormalities.
[0067] S302: Receive the abnormal alarm signal sent by the logic processing unit; the abnormal data is carried in the abnormal alarm signal.
[0068] In this embodiment, the input interface of the controller continuously monitors the abnormal alarm signal line from the CPLD-FPGA. After receiving the abnormal alarm signal, the validity of the signal is initially confirmed to prevent false triggering caused by interference and other factors.
[0069] In this embodiment, once the abnormal alarm signal is confirmed to be valid, the internal Finite State Machine (FSM) will be started to gradually execute subsequent operations according to the established rules.
[0070] In this embodiment, when the CPLD-FPGA has an abnormality and performs a switching reset state and cuts off the power supply, there are timing requirements, and the operations need to be carried out in a specific sequence and time point. The FSM is a logical model that decomposes the control process into different states, and different states correspond to specific operations and conditions. Using the FSM to design the control logic can clearly sort out the conversion relationships and corresponding operations between various states, making the entire control process well-organized and facilitating design, debugging, and maintenance.
[0071] S303: Switch the working state of the logic processing unit to the reset state.
[0072] Specifically, step S303 includes S3031 to S3035:
[0073] S3031: Generate a reset signal; the reset signal includes a reset level and a reset duration.
[0074] In this embodiment, parameters such as the reset level and reset duration of the reset signal are set according to the reset requirements of the CPLD-FPGA. The reset duration needs to be long enough to ensure that the registers, state machines, and logic circuits inside the CPLD-FPGA can be correctly reset to the initial state, but not too long to avoid affecting the system recovery speed. Specifically, the reset duration is usually determined according to the specification of the CPLD-FPGA and the actual application scenario.
[0075] S3032: Enhance the reset signal through a buffer driver.
[0076] In this embodiment, a buffer driver is adopted to enhance the driving ability of the reset signal. The reset signal output by the controller is connected to the input pin of the buffer. The reset signal generated by the controller will be input into the buffer. The internal circuit of the buffer processes the input reset signal to enhance its driving ability. The signal processed by the buffer is connected from the output pin of the buffer to the CPLD-FPGA reset pin through a circuit line. Finally, the enhanced reset signal is transmitted to the CPLD-FPGA to ensure that it can reliably receive the reset instruction and enter the reset state.
[0077] S3033: Send the enhanced reset signal to the logic processing unit through the reset line, and monitor the reset level and reset duration during the sending process.
[0078] In this embodiment, the enhanced reset signal is sent to the CPLD-FPGA. The enhanced reset signal will be transmitted to the reset pin of the CPLD-FPGA to trigger the internal reset circuit of the CPLD-FPGA.
[0079] S3034: Determine whether the reset level is within the preset reset level range and whether the reset duration reaches the preset duration.
[0080] In this embodiment, during the sending process of the enhanced reset signal, the reset process will be continuously monitored. Check whether the reset level is stable within the preset reset level range and whether the reset duration reaches the preset duration.
[0081] S3035: If the reset level is within the preset reset level range and the reset duration reaches the preset duration, it is determined that the reset signal has been successfully sent to the logic processing unit, so that the logic processing unit switches its working state to the reset state.
[0082] In this embodiment, during the sending process of the enhanced reset signal, if the reset level is within the preset reset level range and the reset time reaches the preset duration, it is considered that the reset operation is completed. At this time, it is necessary to check the state of the CPLD-FPGA to confirm whether the CPLD-FPGA has been successfully reset to the initial state.
[0083] Optionally, if the reset level is not within the preset reset level range, or / and the reset duration does not reach the preset duration, a reset signal is regenerated; if the number of times of regenerating the reset signal exceeds the preset number of times, the operation of switching the working state of the logic processing unit to the reset state is interrupted.
[0084] Optionally, during the transmission of the enhanced reset signal, if the reset level is not within the preset reset level range, or / and the reset duration does not reach the preset duration, a reset signal is regenerated. After the number of times of regenerating the reset signal exceeds 3 times, if there is still a situation where the reset level is not within the preset reset level range, or / and the reset duration does not reach the preset duration, the reset operation is interrupted. At the same time, an interrupt signal is sent to the upper-layer control system.
[0085] S304: Cut off multiple power supplies of the logic processing unit according to the preset timing requirements.
[0086] In this embodiment, the power-on and power-off of the CPLD-FPGA have timing requirements, so it is necessary to cut off multiple power supplies of the logic processing unit in sequence according to the preset timing requirements.
[0087] S305: Determine whether multiple power supplies of the logic processing unit are successfully cut off.
[0088] S306: Monitor the power supply voltages of each power supply of the logic processing unit through the voltage detection circuit; if the power supply voltages of each power supply are lower than the power supply voltage safety threshold, it is determined that multiple power supplies of the logic processing unit are successfully cut off;
[0089] S307: Save the abnormal data and send the abnormal data to the upper-layer control system through the low-speed signal bus so that the upper-layer control system can display the abnormal data.
[0090] Among them, the low-speed signal bus is a data transmission channel dedicated to transmitting data between different hardware components.
[0091] Optionally, the low-speed signal bus includes but is not limited to the Inter-Integrated Circuit (I2C), Low Pin Count (LPC), and Serial Peripheral Interface (SPI), etc.
[0092] Optionally, the abnormal data can be saved to the general register or the user storage space (User Flash Memory, UFM).
[0093] In this embodiment, the general register has a simple design and does not cause pressure on logic resources, but there is a problem of data loss after power-off; the UFM is a storage resource that can be used by users, and the data will not be lost after power-off, but there is a problem of relatively complex driving, which will increase the logic resources. The storage method can be selected according to the actual situation.
[0094] In this embodiment, to save abnormal data, the abnormal data can be saved in a general-purpose register or UFM. At the same time, the abnormal data that caused this interruption is reported to the upper-layer control system, facilitating users to understand the abnormal situation and trace the cause.
[0095] S308: Turn off the abnormal monitoring function of the logic processing unit.
[0096] S309: After the abnormal situation of the logic processing unit is eliminated, restart the abnormal monitoring function of the logic processing unit.
[0097] In this embodiment, actively turn off the abnormal monitoring function for CPLD-FPGA to avoid false abnormal reports caused by uncontrollable pins when CPLD-FPGA restarts.
[0098] In summary, after switching the backup image, through the abnormal monitoring function, the logic processing unit is monitored for abnormalities, and abnormal protection is performed when an abnormality occurs. When an abnormality occurs in the logic processing unit, an abnormal alarm signal is triggered, and abnormal processing is performed on the logic processing unit, including switching the working state of the logic processing unit to the reset state, cutting off multiple power supplies of the logic processing unit, saving the abnormal data, and reporting it to the upper-layer control system, which can protect the logic processing unit in a timely manner while ensuring that the cause of the abnormality of the logic processing unit can be traced. In addition, on the one hand, after switching to the reset state and cutting off multiple power supplies, turning off the abnormal monitoring function of the logic processing unit can avoid false abnormal reports caused by uncontrollable pins when the logic processing unit restarts; on the other hand, implementing the abnormal protection of the logic processing unit through a finite state machine can flexibly customize the logic function according to functional requirements, providing support for the abnormal processing of the logic processing unit.
[0099] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general-purpose hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.
[0100] Figure 4 It is a schematic structural diagram of an image switching device for a logic processing unit provided by an embodiment of the present application. As Figure 4 shown, an embodiment of the present application also provides an image switching device for a logic processing unit, including: a first startup module 401, a second startup module 402, a setting module 403, a switching module 404, and a shutdown module 405.
[0101] The first startup module 401 is used to start the working image of the logic processing unit.
[0102] The second startup module 402 is used to enable the protection register after the working image is started and a switching instruction for the backup image sent by the upper control system is received; the switching instruction includes the starting address of the backup image.
[0103] The setting module 403 is used to set the startup configuration pins of the logic processing unit according to the starting address of the backup image.
[0104] The switching module 404 is used to trigger the logic processing unit to restart with the backup image according to the startup configuration pins by using an external excitation trigger method.
[0105] The shutdown module 405 is used to disable the protection register, so that when the logic processing unit starts up next time, it starts from the working image.
[0106] In a possible implementation manner, the setting module 403 is specifically used to: set the startup starting address of the startup configuration pins of the logic processing unit to the starting address of the backup image.
[0107] In a possible implementation manner, the image switching device of the logic processing unit further includes: a third startup module, which is used to, if a switching instruction for the backup image sent by the upper control system is received before starting the logic processing unit, set the startup starting address of the startup configuration pins of the logic processing unit to the starting address of the backup image; and start the backup image of the logic processing unit.
[0108] In a possible implementation manner, the image switching device of the logic processing unit further includes: an abnormal event monitoring module, which is used to monitor the abnormal events of the logic processing unit during the operation of the logic processing unit and perform abnormal processing on the abnormal events to restore the normal operation of the logic processing unit.
[0109] In a possible implementation manner, the abnormal event monitoring module includes:
[0110] The first enabling unit is used to enable the abnormal monitoring function of the logic processing unit; the abnormal monitoring function will trigger an abnormal alarm signal when the logic processing unit has an abnormality.
[0111] The receiving unit is used to receive the abnormal alarm signal sent by the logic processing unit; the abnormal data is carried in the abnormal alarm signal.
[0112] The first switching unit is used to switch the working state of the logic processing unit to the reset state.
[0113] The cutting-off unit is used to cut off multiple power supplies of the logic processing unit according to the preset timing requirements.
[0114] The judging unit is used to judge whether the multiple power supplies of the logic processing unit are successfully cut off.
[0115] A determination unit, configured to monitor the power supply voltages of the power supplies of the logic processing unit through a voltage detection circuit; if the power supply voltages of the power supplies are lower than the power supply voltage safety threshold, it is determined that the multiple power supplies of the logic processing unit are successfully cut off.
[0116] A sending unit, configured to save abnormal data and send the abnormal data to an upper control system through a low-speed signal bus, so that the upper control system can display the abnormal data.
[0117] A closing unit, configured to close the abnormal monitoring function of the logic processing unit.
[0118] A second enabling unit, configured to restart the abnormal monitoring function of the logic processing unit after the abnormality of the logic processing unit is eliminated.
[0119] In a possible implementation manner, the first switching unit includes:
[0120] A generating subunit, configured to generate a reset signal; wherein the reset signal includes a reset level and a reset duration.
[0121] An enhancing subunit, configured to enhance the reset signal through a buffer driver.
[0122] A monitoring subunit, configured to send the enhanced reset signal to the logic processing unit through a reset circuit, and monitor the reset level and the reset duration during the sending process.
[0123] A judging subunit, configured to judge whether the reset level is within a preset reset level range and whether the reset duration reaches a preset duration.
[0124] A switching subunit, configured to determine that the reset signal has been successfully sent to the logic processing unit if the reset level is within the preset reset level range and the reset duration reaches the preset duration, so that the logic processing unit switches its working state to the reset state.
[0125] In a possible implementation manner, the abnormal event monitoring module further includes a second switching unit. The second switching unit includes:
[0126] A regenerating subunit, configured to regenerate the reset signal if the reset level is not within the preset reset level range or / and the reset duration does not reach the preset duration.
[0127] An interrupting subunit, configured to interrupt the switching of the working state of the logic processing unit to the reset state if the number of times of regenerating the reset signal exceeds a preset number of times.
[0128] For the description of the features in the corresponding embodiment of the mirror switching device of the logic processing unit, reference can be made to the relevant description in the corresponding embodiment of the mirror switching method of the logic processing unit, which will not be elaborated here one by one.
[0129] Figure 5 This is a schematic structural diagram of the controller provided by the embodiment of the present application. As Figure 5 shown, the controller provided in this embodiment includes: at least one processor 501 and a memory 502. Optionally, the controller further includes a communication component 503. Among them, the processor 501, the memory 502, and the communication component 503 are connected through a bus.
[0130] In the specific implementation process, at least one processor 501 executes the computer-executable instructions stored in the memory 502, so that at least one processor 501 executes the above-mentioned embodiment of the mirror switching method of the logic processing unit.
[0131] For the specific implementation process of the processor 501, reference can be made to the above method embodiment, and its implementation principle and technical effects are similar, which will not be elaborated here in this embodiment.
[0132] In the above embodiment, it should be understood that the processor may be a central processing unit (Central Processing Unit, abbreviated as: CPU), or other general-purpose processors, digital signal processors (Digital Signal Processor, abbreviated as: DSP), application specific integrated circuits (Application Specific Integrated Circuit, abbreviated as: ASIC), etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the application can be directly embodied as being executed by a hardware processor, or executed by a combination of hardware and software modules in the processor.
[0133] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (Non-volatile Memory, NVM), such as at least one disk memory.
[0134] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience in representation, the buses in the drawings of this application are not limited to only one bus or one type of bus.
[0135] An embodiment of the present application also provides a computer-readable storage medium, in which a computer program is stored. Wherein, the computer program is configured to execute the steps in the embodiment of the mirror switching method of any one of the above-mentioned logic processing units when running.
[0136] In an exemplary embodiment, the above-mentioned computer-readable storage medium may include, but is not limited to: various media such as a USB flash drive, a read-only memory (ROM for short), a random access memory (RAM for short), a mobile hard disk, a magnetic disk, or an optical disc that can store a computer program.
[0137] An embodiment of the present application also provides a computer program product. The above-mentioned computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in the embodiment of the mirror switching method of any one of the above-mentioned logic processing units.
[0138] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in the embodiment of the mirror switching method of any one of the above-mentioned logic processing units.
[0139] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.
[0140] The above has introduced in detail a method, apparatus, controller, and storage medium for mirror switching of a logic processing unit provided by this application. Specific examples are used in this article to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art, without departing from the principle of this application, several improvements and modifications can still be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.
Claims
1. A mirror switching method of a logic processing unit, characterized in that: include: Starting a working image of the logic processing unit; After the working image is started, and when a switch instruction of a backup image sent by an upper control system is received, the enabling protection register is started; wherein the switch instruction includes a starting address of the backup image; According to the starting address of the backup image, setting the startup configuration pin of the logic processing unit; Using an external stimulus triggering method, triggering the logic processing unit to switch to the backup image and restart according to the startup configuration pin; The enable protection register is closed so that the logic processing unit is started from the working image when it is started next time.
2. The method according to claim 1, characterized in that The step of setting the startup configuration pin of the logic processing unit according to the starting address of the backup image includes: The startup start address of the startup configuration pin of the logic processing unit is set to the start address of the backup image.
3. The method according to claim 2, characterized in that Also includes: If a backup image switching instruction is received from the upper control system before the logic processing unit is started, the starting address of the startup configuration pin of the logic processing unit is set to the starting address of the backup image; The backup image of the logical processing unit is started.
4. The method according to claim 1, characterized in that: The enabling protection register is closed so that the logic processing unit is started from the working image the next time it is started, and further includes: During the operation of the logic processing unit, abnormal events of the logic processing unit are monitored, and abnormal processing is performed on the abnormal events to restore the normal operation of the logic processing unit.
5. The method according to claim 4, characterized in that During the operation of the logic processing unit, monitoring abnormal events of the logic processing unit and performing abnormal processing on the abnormal events include: Turning on the abnormality monitoring function of the logic processing unit; the abnormality monitoring function will trigger an abnormality alarm signal when an abnormality occurs in the logic processing unit; Receiving the abnormal alarm signal sent by the logic processing unit; wherein the abnormal alarm signal carries abnormal data; Switching the working state of the logic processing unit to a reset state; Cutting off multiple power supplies of the logic processing unit according to preset timing requirements; Determining whether multiple power supplies of the logic processing unit are successfully cut off; The power supply voltage of each power supply of the logic processing unit is monitored through a voltage detection circuit; if the power supply voltage of each power supply is lower than the power supply voltage safety threshold, it is determined that the multiple power supplies of the logic processing unit are successfully cut off; The abnormal data is saved, and the abnormal data is sent to an upper control system through a low-speed signal bus, so that the upper control system displays the abnormal data; Turning off the abnormality monitoring function of the logic processing unit; After the logic processing unit eliminates the abnormality, the abnormality monitoring function of the logic processing unit is reopened.
6. The method according to claim 5, characterized in that The step of switching the working state of the logic processing unit to a reset state includes: Generate a reset signal; wherein the reset signal includes a reset level and a reset duration; enhancing the reset signal through a buffer driver; The enhanced reset signal is sent to the logic processing unit through a reset line, and during the sending process, the reset level and reset duration are monitored; Determine whether the reset level is within a preset reset level range and whether the reset duration reaches a preset duration; If the reset level is within the preset reset level range and the reset duration reaches the preset duration, it is determined that the reset signal has been successfully sent to the logic processing unit, so that the logic processing unit switches the working state to the reset state.
7. The method according to claim 6, characterized in that After determining whether the reset level is within a preset reset level range and whether the reset duration reaches a preset duration, the method further includes: If the reset level is not within the preset reset level range, or / and the reset duration does not reach the preset duration, regenerating a reset signal; If the number of times the reset signal is regenerated exceeds a preset number, the working state of the logic processing unit is switched to a reset state by interruption.
8. A mirror switching device for a logic processing unit, characterized in that: include: A first startup module, used to start the working image of the logic processing unit; A second startup module, configured to start the enabling protection register after the working image is started and a switch instruction of the backup image sent by the upper control system is received; wherein the switch instruction includes the starting address of the backup image; A setting module, used to set the startup configuration pin of the logic processing unit according to the starting address of the backup image; A switching module, used to trigger the logic processing unit to switch to the backup image and restart according to the startup configuration pin by using an external stimulus triggering method; The shutdown module is used to close the enable protection register so that the logic processing unit starts from the working image when it is started next time.
9. A controller, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the mirror switching method of the logic processing unit as claimed in any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the mirror switching method of the logic processing unit according to any one of claims 1 to 7.