Firmware debugging method of FPGA debugger and FPGA debugger

Abstract

The invention discloses a firmware debugging method of an FPGA debugger and the FPGA debugger. The method comprises the steps that the FPGA debugger executes chip end write request operation and / or chip end read request operation to a chip end based on running of firmware to be debugged; meanwhile, the FPGA debugger detects whether a chip end total interrupt signal is received or not in real time in the running process of the firmware to be debugged, and when the FPGA debugger detects that the chip end total interrupt signal is received, the FPGA debugger is controlled to execute an interrupt response process on the chip end; wherein the firmware to be debugged is stored in the FPGA debugger. According to the FPGA debugger, firmware debugging is carried out on the target debugging chip on the basis of the to-be-debugged firmware stored in the FPGA debugger, the chip does not need to be burnt during firmware updating, only the to-be-debugged firmware stored in the FPGA debugger needs to be burnt again, and the problem that the firmware debugging and updating times of the chip are limited due to the fact that the burning times of the chip are limited is solved.

Description

Technical Field

[0001] This application relates to the field of firmware debugging, and specifically relates to a firmware debugging method for an FPGA debugger and an FPGA debugger. Background Art

[0002] Currently, when a chip is in the firmware debugging stage, the firmware to be debugged needs to be burned into the chip. Since the firmware changes after debugging, the burned firmware in the chip needs to be burned again to update the debugged firmware. Due to the limitation of the number of burns for some chips, such as chips using one-time programmable memories to store firmware, or chips with limited burn times, etc., the number of firmware debugging and updating times in the firmware debugging stage is limited, thus affecting the cost and efficiency of chip firmware debugging. Summary of the Invention

[0003] This application provides a firmware debugging method for an FPGA debugger and an FPGA debugger. The specific technical solutions are as follows: A firmware debugging method for an FPGA debugger includes: the FPGA debugger performs a chip - side write request operation and / or a chip - side read request operation on the chip side based on the operation of the firmware to be debugged; meanwhile, the FPGA debugger detects in real time whether a chip - side total interrupt signal is received during the operation of the firmware to be debugged. When the FPGA debugger detects and receives the chip - side total interrupt signal, it controls the FPGA debugger to execute an interrupt response process for the chip side; wherein, the firmware to be debugged is stored in the FPGA debugger.

[0004] Further, the FPGA debugger executes an interrupt response process for the chip side, which specifically includes: performing a chip - side read request operation to read the chip - side total interrupt status register; determining the peripheral component status register of the peripheral component that issues a peripheral interrupt signal on the chip side according to the read chip - side total interrupt status register; performing a chip - side read request operation to read the peripheral component status register of the peripheral component that issues a peripheral interrupt signal on the chip side; and determining the reason for the peripheral component on the chip side to issue a peripheral interrupt signal according to the read peripheral component status register of the peripheral component that issues a peripheral interrupt signal on the chip side.

[0005] Further, the FPGA debugger executing an interrupt response process for the chip side further includes: when the FPGA debugger determines the reason for the peripheral component on the chip side to issue a peripheral interrupt signal, it controls the FPGA debugger to perform a chip - side write request operation based on the peripheral component that issues a peripheral interrupt signal on the chip side to clear the peripheral component status register; when the clearing of the peripheral component status register is completed, it controls the FPGA debugger to perform a chip - side write request operation to clear the chip - side total interrupt status register.

[0006] Further, a method for the FPGA debugger to execute a chip - side read request operation specifically includes: the central processor of the FPGA debugger generates a chip - side read request instruction based on the chip - side communication slave address, the target read register address, and combines a read flag; the central processor of the FPGA debugger transmits the chip - side read request instruction to the conversion module of the FPGA debugger; the conversion module controls the communication host module of the FPGA debugger to output a corresponding communication read request instruction to the chip - side according to the communication protocol based on the chip - side read request instruction.

[0007] Further, the method for the FPGA debugger to execute a chip - side read request operation further includes: when the conversion module of the FPGA debugger receives the chip - side read request instruction transmitted by the central processor, the conversion module controls the central processor to stop running the firmware to be debugged.

[0008] Further, when the communication host module receives the target read register information fed back by the chip - side, the communication host module transmits the target read register information to the conversion module, the conversion module transmits the target read register information to the central processor, the central processor transmits a target read handshake signal to the conversion module based on the received target read register information, and the conversion module controls the central processor to resume running the firmware to be debugged based on the target read handshake signal.

[0009] Further, a method for the FPGA debugger to execute a chip - side write request operation specifically includes: the central processor of the FPGA debugger generates a chip - side write request instruction based on the chip - side communication slave address, the target write register address, the target write data, and combines a write flag; the central processor of the FPGA debugger transmits the chip - side write request instruction to the conversion module of the FPGA debugger; the conversion module controls the communication host module of the FPGA debugger to output a corresponding communication write request instruction to the chip - side according to the communication protocol based on the chip - side write request instruction.

[0010] Further, the method for the FPGA debugger to execute a chip - side write request operation further includes: when the conversion module of the FPGA debugger receives the chip - side write request instruction transmitted by the central processor, the conversion module controls the central processor to stop running the firmware to be debugged.

[0011] Further, after the communication host module sends the communication write request instruction to the chip - side, the communication host module sends a communication write request end signal to the conversion module, and the conversion module controls the central processor to resume running the firmware to be debugged based on the received communication write request end signal.

[0012] An FPGA debugger is used to execute the firmware debugging method of the FPGA debugger described in any one of the foregoing; wherein, the FPGA debugger includes: a firmware memory to be debugged, which is used for erasable storage of the firmware to be debugged; a central processing unit, which is used to run the firmware to be debugged and transmit a chip-side read request instruction and / or a chip-side write request instruction to the conversion module based on the operation of the firmware to be debugged; a conversion module, which is used to receive the chip-side read request instruction and / or the chip-side write request instruction transmitted by the central processing unit, and control the communication host module to output corresponding communication read request instructions and / or communication write request instructions to the chip side according to the communication protocol based on the chip-side read request instruction and / or the chip-side write request instruction; a communication host module, which is used to output corresponding communication read request instructions and / or communication write request instructions to the chip side according to the communication protocol under the control of the conversion module based on the chip-side read request instruction and / or the chip-side write request instruction.

[0013] Further, the conversion module is further used to control the central processing unit to stop or resume the operation of the firmware to be debugged based on the execution progress of the chip-side read request operation and / or the chip-side write request operation.

[0014] Further, the FPGA debugger further includes: an interrupt signal receiving port, connected to the central processing unit, which is used to receive the chip-side total interrupt signal transmitted by the chip side and transmit it to the central processing unit; the central processing unit is further used to execute an interrupt response process based on the received chip-side total interrupt signal.

[0015] Further, the FPGA debugger further includes: a random access memory, which is used to store the intermediate data generated during the operation of the firmware to be debugged by the central processing unit.

[0016] The firmware debugging method of the FPGA debugger and the FPGA debugger described in this application store the firmware to be debugged by the chip in the FPGA debugger, and communicate through the FPGA debugger with the target debugging chip, so that the FPGA debugger can implement firmware debugging on the target debugging chip based on the firmware to be debugged stored therein, such that when the firmware is updated, it is not necessary to burn the chip, and only the firmware to be debugged stored in the FPGA debugger needs to be re-burned, solving the problem that the number of firmware debugging and updating times of the chip is limited due to the limitation of the number of burning times. Description of the Drawings

[0017] Figure 1 It is a schematic flowchart of the firmware debugging method of the FPGA debugger according to an embodiment of this application.

[0018] Figure 2 It is a schematic flowchart of the interrupt response process according to an embodiment of this application.

[0019] Figure 3Schematic diagram of the modules of an FPGA debugger according to an embodiment of the present application.

[0020] Figure 4 Schematic diagram of the modules of an FPGA debugger according to another embodiment of the present application. Embodiment

[0021] The embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described below are only for explaining the present application and are not used to limit the present application.

[0022] When the chip is currently in the firmware debugging stage, it is necessary to burn the firmware to be debugged into the chip. Since the firmware changes after debugging, it is necessary to re-burn the firmware burned in the chip to update the debugged firmware. Since some chips have restrictions on the number of burns, such as: chips using one-time programmable memories to store firmware, or chips with restricted burn times, etc., the number of firmware debug updates in the firmware debugging stage is restricted, thus affecting the cost and efficiency of chip firmware debugging. To solve the problem that the number of firmware debug updates is restricted due to the burn times limit of the chip, the present application proposes a firmware debugging method for an FPGA debugger, as Figure 1 shown, which specifically includes: the FPGA debugger performs a chip-side write request operation and / or a chip-side read request operation on the chip side based on the operation of the firmware to be debugged; at the same time, the FPGA debugger detects in real time whether a chip-side total interrupt signal is received during the operation of the firmware to be debugged. When the FPGA debugger detects and receives the chip-side total interrupt signal, it controls the FPGA debugger to execute an interrupt response process on the chip side; wherein, the firmware to be debugged is stored in the FPGA debugger. Among them, the full name of FPGA in the FPGA debugger is Field-Programmable Gate Array, that is, a programmable gate array, which is a chip whose internal structure can be changed by programming. In the present application, an FPGA debugger is used, which has the advantages of being reusable and not requiring repeated manual configuration.

[0023] Specifically, the chip - side write request operation refers to the request information for the FPGA debugger to perform a write operation on the target debug chip side; the chip - side read request operation refers to the request information for the FPGA debugger to perform a read operation on the target debug chip side; the chip - side total interrupt signal is used to indicate that a new event has occurred inside the chip side. The FPGA debugger obtains the occurrence of new events inside the chip side by detecting the chip - side total interrupt signal; the interrupt response process refers to that after the FPGA debugger detects the occurrence of a new event inside the chip side, it performs corresponding chip - side write request operations and / or chip - side read request operations on the chip side, so that the FPGA debugger can feedback to the chip side that it has successfully detected the occurrence of a new event inside the chip side and understand the specific content of the new event that has occurred inside the chip side. In this application, the firmware to be debugged by the chip is stored in the FPGA debugger. By communicating between the FPGA debugger and the target debug chip, the FPGA debugger can perform firmware debugging on the target debug chip based on the firmware to be debugged stored in it. When the firmware is updated, there is no need to burn the chip, but only to re - burn the firmware to be debugged stored in the FPGA debugger, without being limited by the number of chip burn - in times.

[0024] As a preferred embodiment of this application, the FPGA debugger performs an interrupt response process on the chip side, as Figure 2 shown, which specifically includes: Performing a chip - side read request operation to read the chip - side total interrupt status register; according to the read chip - side total interrupt status register, determining the peripheral component status register that issues the peripheral interrupt signal on the chip side. Specifically, the FPGA debugger reads the chip - side total interrupt status register by performing a chip - side read request operation on the chip side, so as to enable the FPGA debugger to understand the content of the new event that has occurred in the chip side. Since the peripheral interrupt signal issued by the peripheral component on the chip side is received by the chip - side total interrupt status register, the FPGA debugger can determine the peripheral component status register that issues the peripheral interrupt signal on the chip side by reading the chip - side total interrupt status register.

[0025] Performing a chip - side read request operation to read the peripheral component status register that issues the peripheral interrupt signal on the chip side. Specifically, although both this step and the previous step control the FPGA debugger to perform a chip - side read request operation, the reading purposes of the two chip - side read request operations are different. The previous step is to read the chip - side total interrupt status register, while this step is to read the peripheral component status register.

[0026] Based on the peripheral component status register that reads the peripheral interrupt signal sent from the chip side, determine the reason for the peripheral component on the chip side to send the peripheral interrupt signal; based on the reason for the peripheral component on the chip side to send the peripheral interrupt signal, combined with the operation of the firmware to be debugged, perform corresponding chip-side write request operations and / or perform corresponding chip-side read request operations on the chip side. Specifically, the peripheral component sends a peripheral interrupt signal because a new event occurs on the peripheral component. In this step, the reason for the peripheral component to send the peripheral interrupt signal refers to the new event that occurs on the peripheral component; among them, the peripheral component can be but is not limited to a UART peripheral component, a timer peripheral component, a pulse width modulation peripheral component, etc.

[0027] This embodiment controls the FPGA debugger to first read the chip-side total interrupt register to determine the specific peripheral component that sends the peripheral interrupt signal, and then controls the FPGA debugger to read the status register of the specific peripheral component that sends the peripheral interrupt signal, so as to gradually complete the chip-side interrupt response process, understand the reason for the chip-side to send the chip-side total interrupt signal, and enable the FPGA debugger to respond based on the new events that occur inside the chip side in addition to actively debugging the firmware on the chip side during the process of debugging the firmware on the chip side.

[0028] As a preferred embodiment of the present application, when the FPGA debugger executes the interrupt response process on the chip side, it further includes: when the FPGA debugger determines the reason for the peripheral component to send the peripheral interrupt signal, control the FPGA debugger to perform a chip-side write request operation based on the peripheral component that sends the peripheral interrupt signal on the chip side to clear the peripheral component status register; among them, by performing the chip-side write request operation, the target write object of the write request operation is the peripheral component status register, and the information related to the peripheral interrupt signal stored in the peripheral component status register is overwritten by writing, so as to achieve the purpose of clearing the peripheral component status register.

[0029] When the clearing of the peripheral component status register is completed, control the FPGA debugger to perform a chip-side write request operation to clear the chip-side total interrupt status register. In this step, after the clearing of the peripheral component status register is completed, control the FPGA debugger to perform a chip-side write request operation again. The target write object of the write request operation is the chip-side total interrupt status register, and the information related to the chip total interrupt signal stored in the chip-side total interrupt status register is overwritten by writing to achieve the clearing of the chip-side total interrupt status register.

[0030] Specifically, since the total chip - side interrupt signal sent from the chip side is generated based on the peripheral interrupt signal sent from the internal peripheral components on the chip side, to avoid the situation where the total chip - side interrupt status register is cleared first, causing the peripheral components to send another peripheral interrupt signal to the total chip - side interrupt status register based on the peripheral component status register, resulting in the total chip - side interrupt status register generating the chip total interrupt signal again. This embodiment adopts the method of first clearing the peripheral component status register and then clearing the total chip - side interrupt status register. After the peripheral component status register is cleared first, the problem that the peripheral component status register sends the same peripheral interrupt signal again to trigger the regeneration of the chip total interrupt signal will not occur, optimizing the interrupt signal clearing logic of the interrupt response process.

[0031] As a preferred embodiment of the present application, the method for the FPGA debugger to execute the chip - side read request operation specifically includes: the central processor of the FPGA debugger generates a chip - side read request instruction based on the chip - side communication slave address, the target read register address, and the read flag; the central processor of the FPGA debugger transmits the chip - side read request instruction to the conversion module of the FPGA debugger; the conversion module controls the communication host module of the FPGA debugger to output a corresponding communication read request instruction to the chip side according to the communication protocol based on the chip - side read request instruction. Among them, the chip - side communication slave address refers to the communication slave address of the target firmware debugging chip side of the FPGA debugger, which can be, but is not limited to, the communication address of the chip side, the identity code of the chip side, etc., which can confirm the unique information of the chip side, and is used to ensure the uniqueness and accuracy of the FPGA debugger for firmware debugging of the chip side, preventing the FPGA debugger from performing firmware debugging on other chip sides. By controlling the communication host module through the conversion module to output the corresponding communication read request instruction according to the communication protocol for the chip - side read request instruction, the FPGA debugger can, based on the control of the conversion module, realize the conversion of request instructions for different communication protocols and is applicable to the transmission of a variety of different communication protocols.

[0032] As a preferred embodiment of the present application, the method for the FPGA debugger to execute the chip - end read request operation further includes: when the conversion module of the FPGA debugger receives the chip - end read request instruction transmitted by the central processing unit, the conversion module controls the central processing unit to stop running the firmware to be debugged. Specifically, to prevent the situation that when the FPGA debugger performs a read operation on the chip - end based on the chip - end read request instruction, the central processing unit is still running the firmware to be debugged, which may result in continuously outputting multiple chip - end read request instructions and / or chip - end write request instructions waiting to be debugged on the chip - end. Multiple chip - end read request instructions and / or chip - end write request instructions are likely to affect the firmware debugging execution logic of the FPGA debugger for the chip - end. Therefore, in this embodiment, it is specified that when the conversion module receives a chip - end read request instruction once, it controls the central processing unit to pause running the firmware to be debugged.

[0033] As a preferred embodiment of the present application, when the communication host module receives the target read register information fed back by the chip - end, the communication host module transmits the target read register information to the conversion module, the conversion module transmits the target read register information to the central processing unit, the central processing unit transmits the target read handshake signal to the conversion module based on the received target read register information, and the conversion module controls the central processing unit to resume running the firmware to be debugged based on the target read handshake signal. This embodiment specifies that taking the transmission of the target read register information to the central processing unit as the trigger node, by the central processing unit sending the target read handshake signal to the conversion module, so that the conversion module determines that the last received chip - end read request instruction has been completed based on the target read handshake signal, and thus the conversion module controls the central processing unit to resume running the firmware to be debugged, effectively solving the problem of instruction disorder caused by the parallel operation of multiple chip - end read request instructions and / or chip - end write request instructions.

[0034] As a preferred embodiment of the present application, a method for the FPGA debugger to execute a chip - side write request operation specifically includes: The central processor of the FPGA debugger generates a chip - side write request instruction based on the chip - side communication slave address, the target write register address, the target write data, and the write flag; The central processor of the FPGA debugger transmits the chip - side write request instruction to the conversion module of the FPGA debugger; The conversion module controls the communication host module of the FPGA debugger to output a corresponding communication write request instruction to the chip - side according to the communication protocol based on the chip - side write request instruction. Among them, the chip - side communication slave address is used to determine the target transmission address of the chip - side write request instruction, and is used to assist the communication module of the FPGA debugger to determine the unique address of the chip - side for communication; The target write register address refers to the register address inside the chip - side for performing write operations, and is used to perform a write operation to this target write register address to write the target write data. By controlling the communication host module through the conversion module to output a corresponding communication write request instruction according to the communication protocol for the chip - side write request instruction, the FPGA debugger can, based on the control of the conversion module, achieve the conversion of request instructions for different communication protocols and be applicable to the transmission of a variety of different communication protocols.

[0035] As a preferred embodiment of the present application, a method for the FPGA debugger to execute a chip - side write request operation further includes: When the conversion module of the FPGA debugger receives the chip - side write request instruction transmitted by the central processor, the conversion module controls the central processor to stop running the firmware to be debugged. Specifically, in order to prevent the situation that when the FPGA debugger performs a write operation on the chip - side based on the chip - side write request instruction, the central processor still runs the firmware to be debugged, which may result in the continuous output of multiple chip - side read request instructions and / or chip - side write request instructions waiting to be debugged on the chip - side. Multiple chip - side read request instructions and / or chip - side write request instructions are likely to affect the firmware debugging execution logic of the FPGA debugger for the chip - side. Therefore, in this embodiment, it is specified that when the conversion module receives a chip - side write request instruction once, it controls the central processor to pause running the firmware to be debugged.

[0036] As a preferred embodiment of the present application, after the communication host module sends the communication write request instruction to the chip - side, the communication host module sends a communication write request end signal to the conversion module, and the conversion module controls the central processor to resume running the firmware to be debugged based on the received communication write request end signal. This embodiment specifies that taking the communication host module sending a communication write request end signal to the conversion module as a trigger node, so that the conversion module determines that the last received chip - side write request instruction has been completed based on the communication write request end signal, and thus the conversion module controls the central processor to resume running the firmware to be debugged, effectively solving the problem of instruction disorder caused by the parallel operation of multiple chip - side read request instructions and / or chip - side write request instructions.

[0037] As a preferred embodiment of the present application, a FPGA debugger is provided for executing the firmware debugging method of the FPGA debugger described in any of the previous embodiments; wherein, as Figure 3 shown, the FPGA debugger includes: a firmware to be debugged memory, a central processing unit, a conversion module, and a communication host module; wherein, The firmware to be debugged memory is used for erasable storage of the firmware to be debugged; specifically, the firmware to be debugged is stored in an erasable manner so that when the firmware to be debugged on the chip side in the FPGA debugger changes, the upgrade and change of the firmware to be debugged can be realized by erasing and rewriting the firmware to be debugged stored in the firmware to be debugged memory.

[0038] The central processing unit is used to run the firmware to be debugged and transmit a chip-side read request instruction and / or a chip-side write request instruction to the conversion module based on the operation of the firmware to be debugged; specifically, the chip read request instruction is generated based on the chip-side communication slave address, the target read register address, and the read flag; the chip-side write request instruction is generated based on the chip-side communication slave address, the target write register address, and the target write data combined with the write flag.

[0039] The conversion module is used to receive the chip-side read request instruction and / or the chip-side write request instruction transmitted by the central processing unit, and control the communication host module to output corresponding communication read request instructions and / or communication write request instructions to the chip side according to the communication protocol based on the chip-side read request instruction and / or the chip-side write request instruction; specifically, the conversion module realizes the conversion control of the chip-side read request instruction / chip-side write request instruction from the output of the central processing unit to the output of the communication host module.

[0040] The communication host module is used to output corresponding communication read request instructions and / or communication write request instructions to the chip side according to the communication protocol under the control of the conversion module; wherein, the communication protocol adopted by the communication host module can be, but is not limited to, full-duplex communication protocols such as I2C communication protocol, SPI communication protocol, and UART communication protocol.

[0041] As a preferred embodiment of the present application, the conversion module is further used to control the central processing unit to stop or resume the operation of the firmware to be debugged based on the execution progress of the chip-side read request operation and / or the chip-side write request operation. This embodiment defines the control of the conversion module over the operation of the central processing unit running the firmware to be debugged, and ensures that the execution of a chip-side read request instruction / chip-side write request instruction by the FPGA debugger is not interfered with through the control of stopping and resuming the operation of the firmware to be debugged.

[0042] As a preferred embodiment of the present application, the FPGA debugger, such as Figure 4 shown, further includes: an interrupt signal receiving port, connected to the central processing unit, for receiving the chip-side total interrupt signal transmitted from the chip side and transmitting it to the central processing unit; the central processing unit is further configured to execute an interrupt response process based on the received chip-side total interrupt signal. Specifically, the chip-side total interrupt signal received by the FPGA debugger is directly transmitted to the central processing unit through a dedicated interrupt signal receiving port without passing through the communication host module and the conversion module, making the reception of the trigger signal (i.e., the chip-side total interrupt signal) of the interrupt response process independent of the transmission path of the chip-side read request instruction / chip-side write request instruction, so that during the execution of the chip-side read request instruction / chip-side write request instruction, the central processing unit can still quickly receive the chip-side total interrupt signal generated by the chip side.

[0043] As a preferred embodiment of the present application, the FPGA debugger further includes: a random access memory, for storing the intermediate data generated during the operation of the central processing unit running the firmware to be debugged. Specifically, the random access memory has the characteristic of data loss when powered off, so that after each power-off of the FPGA debugger, the intermediate data generated during the operation of the firmware to be debugged stored inside the random access memory is lost, and there is no need to perform additional cleaning work on the data stored in the random access memory, ensuring that the intermediate data stored in the random access memory is all generated during the operation of the current firmware to be debugged.

[0044] It should be noted that any process or method description in the flowchart or described in other ways herein can be understood as: representing including: one or more modules, segments or parts of executable instructions for implementing a specific logical function or process, and the scope of the preferred embodiments of the present application includes additional implementations, where the functions can be executed in a manner that is not in the order shown or discussed, including in a substantially simultaneous manner or in the reverse order according to the functions involved, which should be understood by those skilled in the technical field to which the embodiments of the present application belong.

[0045] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A firmware debugging method for an FPGA debugger, characterized in that The firmware debugging method includes: Based on the operation of the firmware to be debugged, the FPGA debugger performs a chip - side write request operation and / or a chip - side read request operation on the chip side; Meanwhile, during the operation of the firmware to be debugged, the FPGA debugger detects in real - time whether it receives the chip - side total interrupt signal. When the FPGA debugger detects and receives the chip - side total interrupt signal, it controls the FPGA debugger to execute an interrupt response process for the chip side; Among them, the firmware to be debugged is stored in the FPGA debugger.

2. The firmware debugging method of the FPGA debugger according to claim 1, wherein The FPGA debugger executes the interrupt response process for the chip side, specifically including: Performing a chip - side read request operation to read the chip - side total interrupt status register; Based on the read chip - side total interrupt status register, determining the peripheral component status register of the peripheral component that issues the peripheral interrupt signal on the chip side; Performing a chip - side read request operation to read the peripheral component status register of the peripheral component that issues the peripheral interrupt signal on the chip side; Based on the read peripheral component status register of the peripheral component that issues the peripheral interrupt signal on the chip side, determining the reason for the peripheral component on the chip side to issue the peripheral interrupt signal.

3. The firmware debugging method of the FPGA debugger according to claim 2, characterized in that, The FPGA debugger executes the interrupt response process for the chip side, and further includes: When the FPGA debugger determines the reason for the peripheral component on the chip side to issue the peripheral interrupt signal, it controls the FPGA debugger to perform a chip - side write request operation based on the peripheral component that issues the peripheral interrupt signal on the chip side to clear the peripheral component status register; When the clearing of the peripheral component status register is completed, it controls the FPGA debugger to perform a chip - side write request operation to clear the chip - side total interrupt status register.

4. The firmware debugging method of the FPGA debugger according to claim 3, wherein The method for the FPGA debugger to perform a chip - side read request operation specifically includes: The central processor of the FPGA debugger generates a chip - side read request instruction based on the chip - side communication slave address, the target read register address, and the read flag; The central processor of the FPGA debugger transmits the chip - side read request instruction to the conversion module of the FPGA debugger; The conversion module controls the communication host module of the FPGA debugger to output a corresponding communication read request instruction to the chip side according to the communication protocol based on the chip - side read request instruction.

5. The firmware debugging method of the FPGA debugger according to claim 4, wherein The method for the FPGA debugger to perform a chip - side read request operation further includes: when the conversion module of the FPGA debugger receives the chip - side read request instruction transmitted by the central processor, the conversion module controls the central processor to stop running the firmware to be debugged.

6. The firmware debugging method of the FPGA debugger according to claim 5, wherein When the communication host module receives the target read register information fed back by the chip side, the communication host module transmits the target read register information to the conversion module, the conversion module transmits the target read register information to the central processor, and the central processor transmits a target read handshake signal to the conversion module based on the received target read register information, and the conversion module controls the central processor to resume running the firmware to be debugged based on the target read handshake signal.

7. The firmware debugging method of the FPGA debugger according to claim 3, characterized in that, The method for the FPGA debugger to perform a chip - side write request operation specifically includes: The central processor of the FPGA debugger generates a chip - side write request instruction based on the chip - side communication slave address, the target write register address, the target write data, and the write flag; The central processor of the FPGA debugger transmits the chip - side write request instruction to the conversion module of the FPGA debugger; The conversion module controls the communication host module of the FPGA debugger to output the corresponding communication write request instruction to the chip - side according to the communication protocol based on the chip - side write request instruction.

8. The firmware debugging method of the FPGA debugger according to claim 7, characterized in that, The method for the FPGA debugger to execute the chip - side write request operation further includes: when the conversion module of the FPGA debugger receives the chip - side write request instruction transmitted by the central processor, the conversion module controls the central processor to stop running the firmware to be debugged.

9. The firmware debugging method of the FPGA debugger according to claim 8, wherein After the communication host module sends the communication write request instruction to the chip - side, the communication host module sends a communication write request end signal to the conversion module, and the conversion module controls the central processor to resume running the firmware to be debugged based on the received communication write request end signal.

10. An FPGA debugger, characterized in that, The FPGA debugger is used to execute the firmware debugging method of the FPGA debugger according to any one of claims 1 to 9; wherein, the FPGA debugger includes: A firmware - to - be - debugged memory for erasable storage of the firmware to be debugged; A central processor for running the firmware to be debugged and transmitting chip - side read request instructions and / or chip - side write request instructions to the conversion module based on the operation of the firmware to be debugged; A conversion module for receiving the chip - side read request instructions and / or chip - side write request instructions transmitted by the central processor, and controlling the communication host module to output the corresponding communication read request instructions and / or communication write request instructions to the chip - side according to the communication protocol based on the chip - side read request instructions and / or chip - side write request instructions; A communication host module for outputting the chip - side read request instructions and / or chip - side write request instructions as the corresponding communication read request instructions and / or communication write request instructions to the chip - side under the control of the conversion module according to the communication protocol.

11. The FPGA debugger according to claim 10, wherein The conversion module is further used to control the central processor to stop or resume the operation of the firmware to be debugged based on the execution progress of the chip - side read request operation and / or chip - side write request operation.

12. The FPGA debugger according to claim 11, wherein The FPGA debugger further includes: an interrupt signal receiving port, connected to the central processor, for receiving the chip - side total interrupt signal transmitted by the chip - side and transmitting it to the central processor; the central processor is further used to execute the interrupt response process based on the received chip - side total interrupt signal.

13. The FPGA debugger according to claim 12, characterized in that, The FPGA debugger further includes: a random access memory for storing the intermediate data generated during the process of the central processor running the firmware to be debugged.

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