Debugging information generation method and related product

Abstract

The invention provides a debugging information generation method and a related product, and the debugging information generation method can block an ended debugging information record in a current basic block to continue to be transmitted to a subsequent basic block, thereby reducing redundant information, and correctly generating debugging information.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and in particular, to a method for generating debugging information and related products. Background Art

[0002] Before or during the execution of program code, a programmer can manually or use tools to debug the program code, and a compilation tool can obtain debugging information based on the debugging data during the debugging process. The debugging information can record relevant information during the execution of the program, and the debugging information can be used to solve problems that occur during the execution of the program. How to correctly generate debugging information is a problem worthy of attention. Summary of the Invention

[0003] The present disclosure provides a method, an apparatus, and an electronic device for generating debugging information, which can correctly generate debugging information according to the debugging information records of instructions.

[0004] According to a first aspect of the present disclosure, there is provided a method for generating debugging information, the method including:

[0005] Obtaining at least one debugging information record of a current basic block;

[0006] When it is determined that the debugging information record of the current basic block ends, blocking the transfer of the ended debugging information record in the current basic block to a successor basic block of the current basic block;

[0007] Generating the debugging information according to the debugging information records of the at least one basic block.

[0008] According to a second aspect of the present disclosure, there is further provided a debugging information generation tool, including: a processor and a memory;

[0009] The memory is used to store computer-executable instructions;

[0010] The processor is used to execute the computer-executable instructions stored in the memory, so that the processor executes the above-mentioned method for generating debugging information.

[0011] According to a third aspect of the present disclosure, there is provided a computer-readable storage medium, in which computer-executable instructions are stored, and when a processor executes the computer-executable instructions, the above-mentioned method for generating debugging information is implemented.

[0012] According to a fourth aspect of the present disclosure, there is provided a computer program product, including a computer program, and when the computer program is executed by a processor, the above-mentioned method for generating debugging information is implemented.

[0013] The debugging information generation method and related products disclosed in the present invention reduce redundant information by blocking the debug information record that has been completed in the current basic block from being continuously transferred to its subsequent basic block, so as to correctly generate the debug information. Based on this, in the scenario of multiple fixed values, it is possible to avoid the situation where multiple debug information records are always recorded and transferred, so that the debug information can be correctly generated.

[0014] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are used to better understand the scheme of the present disclosure, and they do not constitute specific limitations of the scheme of the present disclosure.

[0016] Figure 1 is a schematic diagram of an application scenario of a method according to an embodiment of the present disclosure;

[0017] Figure 2 is a schematic diagram of the structure of a compiler in an embodiment of the present disclosure;

[0018] Figure 3 is a flow chart of a method for generating debugging information according to an embodiment of the present disclosure;

[0019] Figure 4 is an example of an assembly program code in an embodiment of the present disclosure;

[0020] Figure 5 yes Figure 4 An example of a preset intermediate representation corresponding to the assembler code in ;

[0021] Figure 6 is a memory optimization flow chart of debugging record encoding in one embodiment of the present disclosure;

[0022] Figure 7 It is an optimization flow chart of the delay slot instruction in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0024] Figure 1 An application scenario of the technical solution of the present disclosure is provided as an example. Figure 1As shown, the computer system 100 can be a heterogeneous computer system including a computing device 110 and a processing device 130, and the computing device 110 and the processing device 130 have different instruction set architectures.

[0025] Among them, the computing device 110 is configured to execute user-specified operations for performing deep learning or machine learning computations. It can interact with the processing device 130 through the interface device 120 to jointly complete user-specified tasks (including but not limited to tasks such as image recognition and speech recognition). The above tasks can include various computations, including but not limited to scalar operations, vector operations, and matrix operations, etc., to implement the corresponding tasks.

[0026] The processing device 130, as a general-purpose processing device, performs basic controls including but not limited to data transfer, starting and / or stopping of the computing device. Depending on different implementation manners, the processing device 130 can be a central processing unit (CPU), a graphics processing unit (GPU), or one or more types of processors in other general-purpose and / or computing devices, including but not limited to digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., and the number thereof can be determined according to actual needs. As mentioned above, only for the computing device of the present disclosure, it can be regarded as having a single-core structure or a homogeneous multi-core structure. However, when considering the integration of the computing device 110 and the processing device 130 together, the two are regarded as forming a heterogeneous multi-core structure.

[0027] The interface device 120 is used to transfer data and control instructions between the computing device 110 and the processing device 130. The storage device 140 is used to store data to be processed. It can be a DDR memory (DRAM) for storing data of the computing device 110 and / or the processing device 130. This storage device 140 can be regarded as an external storage resource of the computing device 110.

[0028] Since the computing device 110 and the processing device 130 have different instruction set architectures, a programmer can program according to the instruction sets of the two respectively to obtain the first program code corresponding to the computing device and the second program code corresponding to the processing device. The first program code and the second program code can be mixed together to form heterogeneous programming code. The heterogeneous programming code can be compiled by a compiler to generate a first executable file that can run on the computing device and a second executable file that can run on the processing device.

[0029] Optionally, a compiler can run on the processing device. Among them, the compiler can be implemented as a computer program for converting a source program written by a user into an executable file (such as a binary file) that can be executed by the computing device and the processing device. As Figure 2 shown, the compiler can include a compilation module 210 and an assembly module 220, and the compiler can support the compilation of two-level programming languages. Among them, the input of the compilation module 210 can be the first code written by the user using a high-level programming language, such as heterogeneous programming code written in the C language. The output of the compilation module 210 can be the second code, such as an assembly program code. The input of the assembly module 220 can be the above-mentioned assembly program code, and the output of the assembly module 220 can be the target code. Here, the target code can be machine code that can be executed by the processor, such as the above-mentioned first executable file and second executable file. Figure 2 Only an implementation manner of the compiler of the present disclosure is described by way of example. In other embodiments, the compiler can also support the compilation of two or more levels of programming languages (for example, three levels of programming languages), which is not specifically limited here.

[0030] Furthermore, the compiler can also generate debugging information. The debugging information can record relevant information during the running of the program, and the debugging information is used to solve problems that occur during the running of the program. Optionally, the debugging information can include the mapping relationship between program codes at each level. For example, the debugging information can include the mapping relationship between heterogeneous programming code and assembly program code, and the mapping relationship between assembly program code and target code. Among them, the mapping relationship between heterogeneous programming code and assembly program code includes the mapping relationship between the line numbers of heterogeneous programming code and the line numbers of assembly program code, and the mapping relationship between registers in heterogeneous programming code and registers in assembly program code. The mapping relationship between assembly program code and target code can include the corresponding relationship between registers in assembly program code and the corresponding hardware resources of the target code, and the mapping relationship between assembly program code and the corresponding hardware PC (Program Counter) value of the target code.

[0031] Further, the assembly module may first convert the assembly program code into a preset intermediate representation and then convert the preset intermediate representation into target code. Accordingly, in the process of converting the assembly program code into target code, the assembly module may first determine the mapping relationship between the assembly program code and the preset intermediate representation (including but not limited to the mapping relationship between the registers in the assembly program code and the registers in the intermediate representation, and the mapping relationship between the line numbers of the assembly program code and the line numbers of the intermediate representation), and then determine the mapping relationship between the preset intermediate representation and the target code (including but not limited to the mapping relationship between the registers in the intermediate representation and the hardware resources, and the mapping relationship between the line numbers of the intermediate representation and the hardware PC). Thus, the assembly module can determine the mapping relationship between the assembly program code and the target code.

[0032] Still further, the mapping relationship between the above-mentioned assembly program code and the target code may be stored in a file in a preset format. For example, the Dbx class is used to record the mapping relationship between the registers in the assembly program code and the registers in the preset intermediate representation, and the registers in the preset intermediate representation can be corresponding to the corresponding hardware resources. The compiler may generate a debug information record corresponding to the assembly program code according to the mapping relationship recorded in the Dbx class.

[0033] Optionally, the compiler compiles the program code and generates debug information based on a control flow algorithm. Based on the control flow algorithm, the compiler may divide the program code into at least one basic block, and at least one basic block may form a control flow graph. Among them, the control flow graph includes nodes and edges, the nodes represent basic blocks, each basic block contains at least one program instruction of the program code, and the edges of the control flow graph indicate which basic blocks may run immediately after a basic block. For the convenience of description, the present disclosure denotes the basic block that runs first as the predecessor basic block, and the basic block that runs after the predecessor basic block as the successor basic block.

[0034] Further, each program instruction in the basic block may correspond to at least one debug information record, each basic block may correspondingly store the debug information records corresponding to the program instructions therein, and the debug information records corresponding to the basic blocks may be passed between the basic blocks according to the control flow graph. Specifically, the present disclosure may record the debug information records corresponding to each basic block at the entrance and the exit of each basic block respectively. The debug information record at the entrance of the basic block may be the debug information record at the exit of its predecessor basic block; the debug information record at the exit of the basic block may be passed to its successor basic block. In one embodiment, the debug information record at the entrance of the basic block may be the same as or different from the debug information record at its exit.

[0035] In some scenarios, redundant debug information records will still be recorded and passed between basic blocks, causing the compiler to be unable to correctly generate debug information records. For example, in scenarios where a program instruction has multiple fixed values, multiple debug information records may be generated, and the multiple debug information records may have different survival intervals, but multiple debug information records with different survival intervals may be recorded until the program code execution ends, causing the compiler to be unable to correctly generate debug information. How to correctly generate debug information is the technical problem to be solved by this application.

[0036] In order to solve the above problems, the debugging information generation method provided by the present disclosure can correctly record the survival interval of each debugging information record, so that the debugging information can still be correctly generated in a multi-setting scenario. The execution subject of the debugging information generation method disclosed in the present disclosure can be a compiler, which can run on a terminal device, such as the above-mentioned processing device, and the compiler can support the compilation of multi-level programming languages ​​and the generation of debugging information.

[0037] The method for generating debugging information disclosed in the present invention can generate debugging information during the process of converting program code into target code. The program code can be an assembly program code containing multiple program instructions. The method disclosed in the present invention can first convert the program code into a preset intermediate representation, then convert the preset intermediate representation into target code, and generate debugging information. Figure 3 As shown, the above-mentioned method for generating debugging information includes:

[0038] S310, obtaining at least one debugging information record of the current basic block;

[0039] The method disclosed herein uses a control flow algorithm to implement the compilation of the above program code to the target code, and the assembly program code and the preset intermediate representation can be represented by a control flow graph composed of multiple basic blocks. Among them, the current basic block can be any basic block in the control flow graph. The entry and exit of each basic block are recorded with corresponding debugging information records, and the debugging information records can be transferred in the basic block according to the control flow graph, that is, the debugging information record at the exit of the current basic block can be transferred to the successor basic block of the current basic block.

[0040] When compiling the program code, the compiler may convert the program instructions in the program code into a preset intermediate representation and generate a debugging information record accordingly. The debugging information record is used to record the mapping relationship between the program instructions and the preset intermediate representation, including but not limited to the mapping relationship between the line number of the program instruction and the line number of the preset intermediate representation, the mapping relationship between the register in the program instruction and the register in the preset intermediate representation, the number of the preset intermediate representation and the hardware resources corresponding to the register in the preset intermediate representation, the number of each debugging information record and the effective PC range of each debugging information record.

[0041] The above-mentioned obtaining of at least one debugging information record of the current basic block may include: the debugging information record determined by the compiler according to the mapping relationship between the program instructions in the current basic block and the preset intermediate representation. In addition, since the debugging information record can be passed between each basic block, the above-mentioned obtaining of at least one debugging information record of the current basic block may further include: obtaining the debugging information record at the entrance of the current basic block, and the debugging information record at the entrance of the current basic block may be the debugging information record passed from the predecessor basic block of the current basic block to the current basic block.

[0042] S320. When it is determined that the debugging information record of the current basic block ends, block the transfer of the ended debugging information record in the current basic block to the successor basic block of the current basic block.

[0043] Wherein, each debugging information record may have a lifetime interval, which is used to represent the start point and the end point of the debugging information record; the start point of the debugging information record indicates the first generation of the debugging information record, and the end point of the debugging information record indicates the end of the debugging information record. The compiler can determine the lifetime interval of the debugging information record, and determine whether each debugging information record has ended according to the lifetime interval.

[0044] When the compiler determines that there is an ended debugging information record in the current basic block, it may block the transfer of the ended debugging information record in the current basic block to the successor basic block of the current basic block. Among them, the ended debugging information record is redundant for the generation of debugging information and should be deleted. The method of the embodiment of the present disclosure can avoid redundant information in the generated debugging information by blocking the transfer of the ended debugging information record between basic blocks, so as to support the correct generation of debugging information in the multi-definition scenario.

[0045] S330. Generate the debugging information according to the debugging information records of the at least one basic block.

[0046] The compiler can traverse all basic blocks and generate debugging information according to the debugging information records corresponding to each basic block. Among them, the debugging information may include at least one debugging information record.

[0047] The method for generating the debugging information of the present disclosure reduces redundant information by blocking the continued transfer of the ended debugging information record in the current basic block to its successor basic block, and in the multi-definition scenario, can avoid the situation where multiple debugging information records are continuously recorded and transferred, so as to be able to correctly generate the debugging information.

[0048] Optionally, the disclosed embodiment can improve the storage data structure of the mapping relationship between program instructions and preset intermediate representations in the debugging information framework of the traditional compiler. Specifically, the compiler of the disclosed embodiment also provides a DbxRecord class for storing the mapping relationship between program instructions in the assembly program code and the preset intermediate representation, and updates the original Dbx to a storage record list.

[0049] The above Dbxrecord can be used to record hardware-independent debugging records, specifically registers for storing program instructions, registers for preset intermediate representations, numbers of preset intermediate representations, and identifiers of debugging records. For example, the Dbxrecord can be expressed as:

[0050]

[0051] Among them, IR_pr_name represents the name of the register of the program instruction, which is used to indicate the register of the program instruction; pr_id represents the register of the preset intermediate representation; stmt_id represents the number of the preset intermediate representation; dbx_record_id represents the identifier of the debug record corresponding to the program instruction, and the identifier of the debug record is used to indicate which debug record the debug record is. The identifier of the debug record can be represented by a numerical value, and each debug record has a globally unique serial number. During the process of the compiler compiling the program, the serial number of the debug record increases in sequence. For example, the identifier of the first debug record is record id=1, and the identifier of the second debug record is record id=2. If the compiler converts the program instruction into the intermediate representation, and the intermediate representation simultaneously sets the values ​​of two registers in the program instruction, more than two debug records will be generated accordingly, and the serial numbers of the more than two debug records will be numbered sequentially.

[0052] Furthermore, the compiler of the embodiment of the present disclosure may update the original Dbx to a storage record list. For example, Dbx is updated to

[0053]

[0054] Among them, lineno is used to record the mapping relationship between the line number of the program instruction and the line number of the preset intermediate representation; List<DbxRecord*> * can be a linked list for recording Dbxrecord, wherein the storage content of each Dbxrecord can be found above.

[0055] Furthermore, the compiler can generate at least one debug information record based on each debug record in the above Dbx class and its corresponding hardware information (including the valid pc range and hardware resources of the debug information record), so as to generate debug information based on at least one debug information record. Specifically, each preset intermediate representation can be stored corresponding to its Dbxrecord, and the compiler can generate at least one debug information record in the current basic block by traversing the Dbxrecord corresponding to the preset intermediate representation in the current basic block. Each debug information record can include a debug record code, the register corresponding to the preset intermediate representation, the valid pc range of the debug information record, and hardware resources.

[0056] For example, the debug information record can adopt the following data structure:

[0057] struct DebugValueRecord{

[0058] UNIT dbx_id;

[0059] UNIT start_pc;

[0060] UNIT end_pc;

[0061] UNIT pr_id;

[0062] UNIT hw_resource;

[0063] };

[0064] Among them, dbx_id represents the debug record code, start_pc and end_pc are used for the start pc value and end pc value of the debug information record respectively, which can represent the valid pc range of the debug information record; pr_id represents the register of the preset intermediate representation; hw_resource represents the hardware resource.

[0065] Based on this, the method of the present disclosure can record each debug information record through the debug record code and transfer it between basic blocks, which is beneficial to the processing of debug information in the multi-definition scenario. Each debug information record has a unique debug record code, and the debug record code can be represented in a numerical manner, and its value increases sequentially according to the generation order of the debug information record. For example, the debug record code of the first debug information record is dbx_id = 1, and the debug record code of the second debug information record is dbx_id = 2. The debug record code of each debug information record can be determined according to the identifier of the corresponding debug record.

[0066] Optionally, after obtaining at least one debugging information record of the current basic block, the compiler can also determine whether each debugging information record has ended. If the compiler determines that the debugging information record has ended, it can block the encoding of the ended debugging record from being passed to the successor basic block of the current basic block, thereby avoiding passing the ended debugging information record to the successor basic block of the current basic block.

[0067] In the traditional technology, the compiler uses the above-mentioned intermediate representation number to realize the transfer of debugging information records between basic blocks. However, if the compiler converts the program instruction into the intermediate representation, the intermediate representation simultaneously sets the value of two registers in the program instruction, and there may be two debugging information records, and both debugging information records correspond to the same preset intermediate representation number. This makes the multiple debugging information records corresponding to the program instruction be transferred according to the control flow. Figure 1 The debug information generated may contain redundant information.

[0068] In the disclosed solution, the compiler uses debug record encoding to implement the transfer of debug information records between basic blocks, and each debug information record has a unique debug record encoding. When the compiler determines that the debug information record in the current basic block has ended, the debug record encoding corresponding to the ended debug information record can be blocked from being transferred to the subsequent basic block. Compared with the traditional technology, the disclosed solution can reduce redundant debug information records to correctly generate debug information.

[0069] In an optional embodiment, since each debug information record also has a unique debug record identifier, the compiler can also implement the transfer of debug information records between basic blocks through the debug record identifier, and when it is determined that the debug information record in the current basic block has ended, the debug information identifier corresponding to the ended debug information record is blocked from being transferred to the subsequent basic block.

[0070] In one embodiment, each debug information record may have a survival interval, and the survival interval of the debug information record may be used to record the active interval of the debug information record from generation to end. The survival interval of the debug information record may be determined based on the preset intermediate representation of the fixed value of the register in the program instruction. The fixed value of the register in the program instruction by the preset intermediate representation may refer to determining the mapping relationship between the preset intermediate representation and its corresponding hardware resources and the register in the program instruction. If the compiler determines the register of the preset intermediate representation corresponding to the register in the program instruction when converting the program instruction into the intermediate representation, and determines the hardware resource corresponding to the register in the program instruction based on the preset intermediate representation, then the preset intermediate representation sets the value of the register in the program instruction.

[0071] When the compiler traverses the program instructions in the current basic block, if the preset intermediate representation assigns a value to a register in the current program instruction, the compiler can generate corresponding debug information records based on this value assignment, denoted as the first debug information record, and the value assignment point is determined as the starting point of the first debug information record. If the compiler determines that the value assignment of a register in the current program is overwritten by the value assignment of a register in a subsequent program instruction, that is, the value assignment of the register in the current program instruction will be killed by the value assignment of the register in the subsequent program instruction, the compiler can determine the end of the first debug information record and generate a second debug information record based on the preset intermediate representation for the value assignment of the register in the subsequent program instruction. At this time, the value assignment point of the register in the subsequent program instruction can be determined as the end point of the first debug information record. The starting point and the end point of the first debug information record can determine the survival interval of this debug information record. Among them, the current program instruction can be any program instruction in the current basic block, and the subsequent program instruction can be a program instruction executed after the current program instruction.

[0072] The following combines Figure 4 and Figure 5 the shown program code and its corresponding intermediate representation to illustrate the debug information generation process:

[0073] For example, the assembly program code is as Figure 4 shown, which includes the predicate program instruction setp.lt.pred.u16 %p1,%r1,3. The above program code can be compiled by the assembly module to generate a preset intermediate representation (such as XOC IR) as Figure 5 shown, where the preset intermediate representation corresponding to the above predicate program instruction is: setp.lt %p61(P2),%r28(R1),3,%p62(P1).

[0074] It can be seen from this that this preset intermediate representation assigns values to the predicate register %p1 and the anti-predicate register.revert_%p1. Among them, the predicate register %p1 in the assembly program code corresponds to the preset intermediate representation %p61 and its hardware resource P2; the anti-predicate register.revert_%p1 in the assembly program code corresponds to the preset intermediate representation %p62 and its hardware resource P1. At the same time, when the assembly module converts this assembly program code into a preset intermediate representation, two debug information records will be generated to record the mapping relationship of the registers in the assembly program code to the registers in this intermediate representation. These two debug information records can be:

[0075] %p1->(stmt_id = 9,pc = 97,pc = 105,vir_resource = PR61,hw_resource = Pred,P2);

[0076] .revert_ %p1->(stmt_id = 9, pc = 97, pc = 105, vir_resource = PR62, hw_resource = Pred, P1);

[0077] Among them, stmt_id represents the number of the preset intermediate representation; the two pc values are respectively used for the starting pc value and the ending pc value of debug information recording, which can represent the pc range where the debug information recording is valid; vir_resource represents the register of the preset intermediate representation; hw_resource represents the hardware resource.

[0078] Both of the above two debug information records correspond to the same number stmt_id = 9 of the preset intermediate representation. In the traditional technology, the above two debug information records can be passed backward to the successor basic block BB2 according to the number of the preset intermediate representation.

[0079] Specifically, after the debug information record of the above BB1 is passed into the successor basic block BB2, the compiler first traverses Dbx corresponding to the number stmt_id = 9 of the intermediate representation and generates two debug information records:

[0080] %p1->(stmt_id = 9, pc = 97, pc = 105, vir_resource = PR61, hw_resource = Pred, P2);

[0081] .revert_ %p1->(stmt_id = 9, pc = 97, pc = 105, vir_resource = PR62, hw_resource = Pred, P1).

[0082] When the compiler traverses to the assembly program code and.pred %p2,!%p1, %p1 in the successor basic block BB2, the preset intermediate representation corresponding to this assembly program code is: and.pred.bool %p63(P1), %p62(P1), %p61(P2). It can be seen that the register %p2 of the assembly program code corresponds to the register %p63 of the preset intermediate representation and the hardware resource P1. The debug information record after BB2 is processed is as follows:

[0083] %p1->(stmt_id = 9, pc = 108, pc = 109, vir_resource = PR61, hw_resource = Pred, P2);

[0084] %p2->(stmt_id = 18, pc = 108, pc = 109, vir_resource = PR63, hw_resource = Pred, P1);

[0085] .revert_%p1->(stmt_id = 9, pc = 108, pc = 108, vir_resource = PR62, hw_resource = Pred, P1).

[0086] Since register %p2 and the anti-predicate register.revert_%p1 use the same hardware resource P1, the debugging information recording of the original anti-predicate register.revert_%p1 ends here. However, since the debugging information recording of the predicate register %p1 has not ended, the corresponding intermediate representation number (stmt_id = 9) still needs to be passed to the successor basic block BB3. At the same time, the intermediate representation number (stmt_id = 18) corresponding to the debugging information recording of register %p2 is also passed to the successor basic block BB3.

[0087] In this way, in basic block BB3, all the Dbx on the XOC IR corresponding to the passed stmt_id will still be traversed to generate debugging information records. Finally, the debugging information records in basic block BB3 are as follows:

[0088] %p1->(stmt_id = 9, pc = 112, pc = 112, vir_resource = PR61, hw_resource = Pred, P2);

[0089] %p2->(stmt_id = 18, pc = 112, pc = 112, vir_resource = PR63, hw_resource = Pred, P1);

[0090] .revert_%p1->(stmt_id = 9, pc = 112, pc = 112, vir_resource = PR62, hw_resource = Pred, P1).

[0091] Obviously, the record of.revert_%p1 generated by the traditional technology in BB3 is redundant, which leads to incorrect generated debugging information.

[0092] Compared with the traditional technology, the embodiment of the present disclosure realizes the transfer of debugging information records between basic blocks through the transfer of debugging record encodings between each basic block. And in the embodiment of the present disclosure, after the compiler determines that the current debugging information record has ended, the debugging record encoding of the current debugging information record can be blocked from being transferred to the successor basic block, thereby reducing redundant information, being able to correctly generate debugging information, and supporting the generation of debugging information in the multi-definition scenario. The following combines Figure 4 and Figure 5Describe the debug information generation process of the embodiments of the present disclosure:

[0093] Process the predicate program instruction "setp.lt%p61(P2),%r28(R1),3,%p62(P1)" in basic block BB1. Two debug records DbxRecord will be generated in the m_dbx_record_list in Dbx as follows:

[0094] {IR_pr_name = “%p1”, xoc_pr = 61, stmt_id = 9, dbx_record_id = 1};

[0095] {IR_pr_name = ”“.revert_%p1, xoc_pr = 62, stmt_id = 9, dbx_record_id = 2};

[0096] Among them, IR_pr_name represents the register in the program instruction; xoc_pr represents the register in the preset intermediate representation; stmt_id represents the number of the preset intermediate representation; dbx_record_id represents the identifier of the debug record.

[0097] According to the above debug records, the debug information records generated in basic block BB1 are:

[0098] %p1->(stmt_id = 9, dbx_id = 1, pc = 97, pc = 105, vir_resource = PR61, hw_resource = Pred, P2);

[0099] .revert_%p1->(stmt_id = 9, dbx_id = 2, pc = 97, pc = 105, vir_resource = PR62, hw_resource = Pred, P1); Among them, dbx_id represents the debug record code.

[0100] The above two debug information records can be passed to the successor basic block BB2 through their debug record codes dbx_id 1 and 2.

[0101] After the above debug record codes dbx_id 1 and 2 are passed into the successor basic block BB2, the compiler can traverse Dbxrecord according to the debug record code and generate the following debug information records:

[0102] %p1->(stmt_id = 9, pc = 108, pc = 109, vir_resource = PR61, hw_resource = Pred, P2);

[0103] .revert_ %p1->(stmt_id = 9, pc = 108, pc = 109, vir_resource = PR62, hw_resource = Pred, P1).

[0104] When the compiler continues to traverse and processes the intermediate representation "and.pred.bool %p63(P1), %p62(P1), %p61(P2)" in BB2, Dbx is set on it, and there is a DbxRecord in the corresponding m_dbx_record_list:

[0105] {IR_pr_name = "%p2", xoc_pr = 63, stmt_id = 18, dbx_record_id = 3}

[0106] Since the hardware resource P1 is assigned to the intermediate representation XOC PR %p63, the debug information record of the original anti-predicate register.revert_ %p1 ends here. After processing the basic block BB2, the debug information record is as follows:

[0107] %p1->(stmt_id = 9, dbx_id = 1, pc = 108, pc = 109, vir_resource = PR61, hw_resource = Pred, P2);

[0108] %p2->(stmt_id = 18, dbx_id = 3, pc = 108, pc = 109, vir_resource = PR63, hw_resource = Pred, P1);

[0109] .revert_ %p1->(stmt_id = 9, dbx_id = 2, pc = 108, pc = 108, vir_resource = PR62, hw_resource = Pred, P1).

[0110] Since the debug information record of the anti-predicate register.revert_ %p1 has ended, the compiler passes only the debug record encodings dbx_id 1 and 3 corresponding to %p1 and %p2 to the successor basic block BB3.

[0111] After the above debug record encodings dbx_id 1 and 3 are passed into the successor basic block BB3, the compiler can generate the corresponding debug information record as follows:

[0112] %p1->(stmt_id=9,pc=112,pc=112,vir_resource=PR61,hw_resource=Pred,P2);

[0113] %p2->(stmt_id=18,pc=112,pc=112,vir_resource=PR63,hw_resource=Pred,P1).

[0114] It can be seen that the debugging information generation method of the embodiment of the present disclosure will no longer pass the redundant debugging information record of the anti-predicate register .revert_%p1 to the subsequent basic block, so that it can correctly handle the scenario of multiple values ​​of a single intermediate representation and correctly generate debugging information.

[0115] In one embodiment, the debug record code is recorded and transmitted in the form of a bit set, and the debug record code is stored in the bit set after being compressed to reduce the memory occupation of the bit set. Wherein, the bit set is an n-bit binary number, and each eight bits occupy one byte. The debug record code can be stored in a bit set and transmitted between basic blocks. Optionally, the bit set can be a sparse bit set for storing compressed data, such as DefBitset. The compressed debug record code can be stored at the entrance and exit of each basic block. Specifically, the entrance of each basic block can be respectively provided with a corresponding sparse bit set:

[0116] DefSBitSet*m_dbgvalue_in; used to store the debug record code at the entry of the basic block;

[0117] DefSBitSet*m_dbgvalue_out; used to store the debug record code at the exit of the basic block.

[0118] Furthermore, if Figure 6 As shown, the method of the present disclosure may also include the following steps:

[0119] S610: Determine a compression amount according to the size of the debug record code and the capacity of the sparse bit set; wherein the capacity of each sparse bit set may be preset, for example, the capacity of each sparse bit set may be 512 bits.

[0120] The compiler may determine the compression amount according to the size of the debug record code and the preset capacity of each sparse bit set. Optionally, the compression amount may be obtained by performing a modulo operation on the size of the debug record code relative to the preset capacity of each sparse bit set.

[0121] S620. Determine the size of the compressed debug record code according to the size of the debug record code encoded and the compression amount, and store the debug record code in the sparse bit set according to the size of the compressed debug record code.

[0122] The compiler can determine the size of the compressed debug record code according to the size of the debug record code and the calculated compression amount. Optionally, the size of the compressed debug record code can be equal to the difference between the size of the debug record code and the above compression amount.

[0123] Based on this, the memory occupied by the debug record code in the embodiments of the present disclosure can be expressed as follows:

[0124]

[0125] Where elem represents the debug record code before compression, SEG represents each sparse bit set; BitsPerSeg represents the capacity of each sparse bit set; x->start represents the compression amount; x->bs.bunion represents the compressed debug record code.

[0126] In the embodiments of the present disclosure, the capacity of each sparse bit set can be 512 bit. After the debug record code to be stored is compressed, the size of the compressed debug record code can be controlled between 0 and 511 bit, so as to ensure that the maximum number of elements stored in each sparse bit set (SEG) is 64 (512 / 8 = 64). When the sparse bit set is full, a new sparse bit set can be applied for to store new data. The data structure adopted in the embodiments of the present disclosure for storing the debug record code can effectively improve the utilization rate of memory and greatly reduce the memory usage.

[0127] In the traditional technology, the compiler passes the number of the intermediate representation between basic blocks to implement the transfer of the corresponding debug information records between basic blocks, and the number of the intermediate representation is stored in the data structure of the bit set. Among them, a pair of bit sets (for example, BitSet m_dbgvalue_in; BitSet m_dbgvalue_out) are correspondingly set in each basic block, which are respectively used to store the debug record codes at the entrance and exit of the basic block. At this time, the data memory occupied by the number of the intermediate representation is as follows:

[0128]

[0129]

[0130] Among them, the memory size occupied by the array used to store data in the bit set is related to the largest element stored in the array. When the compiled file is large, the corresponding number of the intermediate representation is also large, resulting in a large amount of memory occupied by the bit set. Moreover, due to the large number of basic blocks, the peak memory usage during compilation seriously exceeds the standard.

[0131] In the embodiments of the present disclosure, the compiler passes the debug record encoding between basic blocks to enable the corresponding debug information to be passed between basic blocks. However, when storing the debug record encoding in the manner of traditional technologies, there is still a problem of excessive memory occupation. Based on this, compared with traditional technologies, the present disclosure compresses the debug record encoding, thereby reducing the memory occupation of the bit set and improving the memory utilization rate. Experiments show that the method of the present disclosure compresses the debug record encoding, and the memory peak during debug compilation is reduced from more than 109G to 11.9G.

[0132] In one embodiment, in the embodiments of the present disclosure, the compiler can also optimize the delay slot instructions to correctly generate debug information.

[0133] In traditional technologies, when the compiler converts program code into intermediate representation, special program instructions in the program code (including but not limited to conditional jumps, unconditional jumps, exit, and function calls call) will generate delay slot instructions. For example, Figure 5 In the preset intermediate representation shown, both jump instructions generate two delay slot instructions snop, and the exit instruction generates three delay slot instructions sync. When analyzing the program code based on the data flow, the compiler takes the delay slot basic block where the delay slot instruction is located as the successor basic block of the basic block where the special program instruction that generates the delay slot instruction is located, so as to ensure that the corresponding delay slot instruction can be found in the lexical order. Correspondingly, the intermediate representation corresponding to the delay slot instruction can be directly placed in the basic block where the special program instruction is located, as Figure 5 shown. However, these delay slot instructions are not added to the control flow graph to avoid redundant processing in some graph optimization processes. This results in that when the compiler generates debug information, these delay slot instructions will not be traversed either. However, the intermediate representation corresponding to the delay slot instruction itself will be assigned a pc value, resulting in an interruption of the pc range in the debug information records of adjacent basic blocks when there are delay slot instructions, and the merging of debug information records cannot be carried out normally to correctly generate debug information.

[0134] Continue to refer to Figure 4 and Figure 5 the code compilation process shown, where the debug information record finally obtained by the predicate register %p1 is as follows:

[0135] %p1->(stmt_id = 9, dbx_id = 1, pc = 96, pc = 105, vir_resource = PR61, hw_resource = Pred, P2);

[0136] %p1->(stmt_id = 9, dbx_id = 1, pc = 108, pc = 109, vir_resource = PR61, hw_resource = Pred, P2);

[0137] %p1->(stmt_id = 9, dbx_id = 1, pc = 112, pc = 112, vir_resource = PR61, hw_resource = Pred, P2).

[0138] The post - processing operations such as merging of the three debug information records corresponding to the same register %p1 cannot be performed due to the interruption of the pc range, so that the debug information cannot be correctly generated.

[0139] In the embodiments of the present disclosure, the compiler can expand the scope of the basic block and directly add the delayed - slot instruction to the basic block to which the special program instruction that generates the delayed - slot instruction belongs, rather than placing it in a separate delayed - slot basic block. In this way, during the process of generating the debug information record, if the current basic block contains a delayed - slot instruction, the compiler can use the pc range corresponding to the delayed - slot instruction as the valid pc range of the basic block and record the valid pc range of the basic block in each debug information record. As Figure 7 shown, the method of the present disclosure may further include:

[0140] S710. Merge the delayed - slot instructions generated by the special program instructions in the current basic block into the current basic block;

[0141] The compiler can first determine whether the current basic block has generated a delayed - slot instruction, and the delayed - slot instruction is divided into a separate delayed - slot basic block. When it is determined that the current basic block has generated a delayed - slot instruction, the compiler can find the subsequent delayed - slot basic block through the lexical order in the basic - block list (BB list) and traverse the delayed - slot instructions in the subsequent delayed - slot basic block to merge the delayed - slot instructions into the current basic block.

[0142] S720. Update the pc range of the current basic block according to the delayed - slot instruction and determine the updated pc range of the current basic block.

[0143] In the method of the present disclosure, after the compiler merges the delayed - slot instruction into the current basic block, it can update the pc range of the current basic block so that the updated pc range of the current basic block includes the pc value corresponding to the delayed - slot instruction.

[0144] S730. Determine the PC range in at least one debug information record of the current basic block according to the updated PC range of the current basic block.

[0145] In the method of the present disclosure, if the debug information record in the current basic block is active until the end of the current basic block, the compiler can determine the PC range in the active debug information record according to the updated PC range of the current basic block.

[0146] Further, the delay slot instruction may also carry a debug information record. The method of the present disclosure can also perform statistics and processing on the debug information record corresponding to the delay slot instruction. If the current basic block contains a delay slot instruction and there is a corresponding debug information record for the delay slot instruction, then count and record the debug information record corresponding to the delay slot instruction in the current basic block, and update the debug information record of the current basic block. After the update, the debug information record of the current basic block includes the debug information record corresponding to the delay slot instruction.

[0147] Continuing with the above example, continue to refer to Figure 4 and Figure 5 the code compilation process shown. After the compiler optimizes the delay slot instruction therein, the debug information record obtained for the predicate register %p1 is as follows:

[0148] %p1->(stmt_id = 9, dbx_id = 1, pc = 96, pc = 107, vir_resource = PR61, hw_resource = Pred, P2);

[0149] %p1->(stmt_id = 9, dbx_id = 1, pc = 108, pc = 111, vir_resource = PR61, hw_resource = Pred, P2);

[0150] %p1->(stmt_id = 9, dbx_id = 1, pc = 112, pc = 115, vir_resource = PR61, hw_resource = Pred, P2);

[0151] It can be seen that after the optimization process of the delay slot instruction, the PC ranges of the debug information records of the same register %p1 in different basic blocks are continuous. The compiler can merge the multiple debug information records corresponding to the same register as above to obtain the final debug information record. The predicate register %p1 can finally be simplified and merged as follows:

[0152] %p1 -> (stmt_id = 9, dbx_id = 1, pc = 97, pc = 115, vir_resource = PR61, hw_resource = Pred, P2).

[0153] Further, the compiler according to the embodiments of the present disclosure will additionally supplement the traversal processing of the debug information records of the delayed slot instructions, and update the debug information records corresponding to the delayed slot instructions to the debug information records of the current basic block. Continuing to refer to Figure 4 and Figure 5 , taking %p2 as an example at this time, the debug information records generated by this register in each basic block BB become:

[0154] %p2 -> (stmt_id = 18, dbx_id = 3, pc = 108, pc = 109, vir_resource = PR63, hw_resource = Pred, P1); which is the debug information record corresponding to the delayed slot instruction;

[0155] %p2 -> (stmt_id = 18, dbx_id = 3, pc = 110, pc = 113, vir_resource = PR63, hw_resource = Pred, P1).

[0156] The compiler can perform traversal processing on the debug information records of the above-mentioned delayed slot instructions, and perform post-processing operations such as merging processing on multiple debug information records corresponding to the same register to obtain the final debug information record. After merging and simplification, the debug information record corresponding to %p2 is as follows:

[0157] %p2 -> (stmt_id = 18, dbx_id = 3, pc = 108, pc = 113, vir_resource = PR63, hw_resource = Pred, P1).

[0158] In the embodiments of the present disclosure, by performing the above processing on the delayed slot instructions, the compiler can not only ensure the continuity of the pc valid range between each basic block of the debug information record, but also perform statistical processing on the debug information records corresponding to the delayed slot instructions, so as to correctly generate the debug information. For example, after the above optimization processing, the compiler can obtain the following debug information m_final_debug_value_info (only the predicate register part is shown in this debug information):

[0159] %p1 -> (stmt_id = 9, dbx_id = 1, pc = 97, pc = 115, vir_resource = PR61, hw_resource = Pred, P2);

[0160] %p2->(stmt_id = 18, dbx_id = 3, pc = 108, pc = 115, vir_resource = PR63, hw_resource = Pred, P1);

[0161] .revert_%p1->(stmt_id = 9, dbx_id = 2, pc = 97, pc = 108, vir_resource = PR62, hw_resource = Pred, P1).

[0162] In one embodiment, the debugging information is recorded and stored in the form of a list, and the list may include multiple pieces of debugging information. In the embodiments of the present disclosure, each piece of debugging information is encapsulated into the DebugValueInfoRecord class to reduce the time complexity and improve the readability of the debugging information.

[0163] In the prior art, the compiler uses a vector to store debugging information, std::vector<std::tuple<uint32_t, uint32_t, uint32_t>>. When the compiler performs unified processing (such as merging) on the intermediate data of the debugging information, it is necessary to perform several sequential traversals on the vector data structure and perform operations of adding and deleting elements multiple times therein. The following is the pseudo-code:

[0164]

[0165] The time complexity of the compiler for adding or deleting a single element in the vector data structure is O(n), so the time complexity reaches O(n^2) after completing the entire traversal.

[0166] In order to reduce the time complexity of the debugging information during post-processing such as merging and improve the readability of the debugging information, the method of the embodiments of the present disclosure can encapsulate a single piece of debugging information into the following DebugValueInfoRecord class:

[0167]

[0168] Among them, dbx_id represents the debugging record code; start_pc represents the starting pc value of the debugging information; end_pc represents the ending pc value of the debugging information; record_idx represents the debugging record identifier; xoc_pr represents the register of the preset intermediate representation; hw_idx represents the hardware resource.

[0169] On this basis, the method of the embodiments of the present disclosure can also use a custom list List to store multiple pieces of debugging information:

[0170] List<DebugValueInfoRecord*>

[0171] Under the condition that the call process of the debug information remains unchanged, compared with the traditional vector data structure, the time complexity of adding or deleting a single element in the list data structure used in this disclosure is reduced to O(1), so that the time complexity of completing the entire traversal is reduced from the original O(n^2) to O(n).

[0172] Experiments show that by optimizing the data structure of the debug information in the embodiments of this disclosure, the compilation time is optimized from 13119s to 159s, greatly reducing the compilation time.

[0173] In some embodiments, the above debug information can be visually output. For example, the last debug information can be displayed in the corresponding display interface of the program according to the user's call instruction. By visually outputting the above debug information, the user can locate the problems that occur in the program according to the above debug information.

[0174] An embodiment of this disclosure also provides a debug information generation tool, including: a processor and a memory;

[0175] The memory is used to store computer-executable instructions;

[0176] The processor executes the computer-executable instructions stored in the memory, so that the processor executes the above-mentioned debug information generation method.

[0177] It should be clear that when the processor executes the above-mentioned computer-executable instructions, the debug information generation method of the above embodiments can be implemented. For the specific implementation, reference can be made to the above embodiments, which will not be elaborated here.

[0178] An embodiment of this disclosure also provides a computer program product, including a computer program, characterized in that when the computer program is executed by a processor, the above-mentioned debug information generation method is implemented. Among them, when the processor executes the above-mentioned computer program, the debug information generation method of the above embodiments can be implemented. For the specific implementation, reference can be made to the above embodiments, which will not be elaborated here.

[0179] An embodiment of this disclosure also provides a computer-readable storage medium, in which computer-execution instructions are stored. When the processor executes the computer-execution instructions, the above-mentioned debug information generation method is implemented.

[0180] It should be noted that the computer-readable medium described above in the present disclosure can be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, the computer-readable storage medium can be any tangible medium that contains or stores a program, and this program can be used by or in combination with an instruction execution system, apparatus, or device. In the present disclosure, a computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, and this computer-readable signal medium can send, propagate, or transmit a program for use by or in combination with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0181] The above computer-readable medium can be included in the above electronic device; it can also exist separately and not be assembled into the electronic device. The above computer-readable medium carries one or more programs, and when the one or more programs are executed by the electronic device, the electronic device is caused to execute the method shown in the above embodiments.

[0182] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a segment of a program, or a portion of code that contains one or more executable instructions for implementing a specified logical function. It should also be noted that, in some alternative implementations, the functions noted in the blocks may occur in a different order than that noted in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, or they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or by a combination of dedicated hardware and computer instructions.

[0183] The functions described above herein may be performed, at least in part, by one or more hardware logic components. By way of example, and without limitation, the types of hardware logic components that may be used include: field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems on a chip (SOCs), complex programmable logic devices (CPLDs), and the like.

[0184] In the context of the present disclosure, a machine-readable medium may be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0185] The above specific embodiments do not constitute a limitation on the scope of protection of the present disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

1. A method for generating debugging information, characterized in that, The method comprises: Obtain at least one debug information record for the current basic block; When determining that the debugging information record of the current basic block is finished, blocking the debugging information record that has been finished in the current basic block from being transferred to the subsequent basic block of the current basic block; The debugging information is generated according to the debugging information record of the at least one basic block.

2. The method according to claim 1, characterized in that, The debugging information record includes a debugging record code; and the blocking of the current debugging information record from being transferred to a subsequent basic block further includes: The debug record code that blocks the current debug information record from being passed to the subsequent basic block.

3. The method according to claim 2, wherein The debugging record code is recorded in a sparse bit set manner, and the debugging record code is stored in the sparse bit set after being compressed.

4. The method according to claim 3, characterized in that The method further comprises: Determining a compression amount according to the size of the debug record code and the capacity of the sparse bit set; The size of the debug record code after compression is determined according to the size of the debug record code and the compression amount, and the debug record code is stored in the sparse bit set according to the size of the debug record code after compression.

5. The method according to any one of claims 1-4, characterized in that, The method further comprises: Generate the debugging information record according to the preset intermediate representation for the fixed value of the register in the current program instruction; If the fixed value of the register in the current program instruction is overwritten by the fixed value of the register in the subsequent program instruction, it is determined that the debugging information recording is ended.

6. The method according to any one of claims 1-5, characterized in that, The debugging information record also includes a PC range; the method also includes: Merging delay slot instructions generated by special program instructions in the current basic block into the current basic block; Update the PC range of the current basic block according to the delay slot instruction, and determine the updated PC range of the current basic block; According to the updated pc range of the current basic block, a pc range in at least one debugging information record of the current basic block is determined.

7. The method according to claim 6, wherein The method further comprises: If the current basic block includes a delay slot instruction, and the delay slot instruction has a corresponding debugging information record, then the debugging information records corresponding to the delay slot instructions in the current basic block are counted and recorded, and the debugging information records of the current basic block are updated.

8. The method according to any one of claims 1 to 7, characterized in that, The generating the debugging information according to the debugging information record of the at least one basic block further comprises: Traversing the debugging information records of the at least one basic block and post-processing the debugging information records; Debug information is generated according to the debug information record after post-processing, and the debug information can be output visually.

9. The method according to claim 8, wherein The debugging information is recorded in a list format.

10. A debugging information generation tool, characterized in that, include: Processor and memory; The memory is used to store computer executable instructions; The processor is used to execute the computer executable instructions stored in the memory, so that the processor executes the method for generating debugging information according to any one of claims 1 to 9.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions. When a processor executes the computer-executable instructions, the method for generating debugging information according to any one of claims 1 to 9 is implemented.

12. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, the method for generating debugging information according to any one of claims 1 to 9 is implemented.

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