A pre-emphasis circuit with bidirectional regulation of time and current

Abstract

The present application provides a pre-emphasis circuit with bidirectional adjustment of time and current, comprising: a pre-emphasis main circuit including multiple transistors; a bidirectional adjustment circuit including configurable transistors, a controllable switch circuit, and an inverter chain, wherein the configurable transistors include a first configuration transistor and a second configuration transistor, and by adjusting the number of the first configuration transistors, the delay time of the differential signal passing through the inverter chain is adjusted to adjust the magnitude of the pre-emphasis time; the inverter chain is used to convert the differential signal into an inverse delayed signal; by adjusting the number of the second configuration transistors and combining the controllable switch circuit to control the output state of the inverse delayed signal, the magnitude of the pre-emphasis current is adjusted; and a common-mode level adjustment circuit is used to adjust the number of configurable transistors according to the current magnitude and output voltage of the pre-emphasis main circuit to balance the common-mode voltage. Thus, while achieving bidirectional adjustment of the pre-emphasis current and time, the problem of common-mode voltage offset is avoided.

Description

Technical Field

[0001] The present application belongs to the technical field of integrated circuit design, and in particular relates to a pre-emphasis circuit with bidirectional regulation of time and current. Background Art

[0002] LVDS (Low-Voltage Differential Signaling) technology is a level standard for high-speed data transmission. It uses extremely low voltage swings for high-speed differential data transmission, supporting both point-to-point and point-to-multipoint connections. Its significant advantages include low power consumption, low bit error rate, low crosstalk, and low radiation, making it widely used in high-speed serial data communications, such as in high-speed backplanes, cables, and internal PCB communication links. Pre-emphasis is a signal processing technique that compensates for high-frequency components in the input signal at the transmitter.

[0003] In the related art of LVDS driver circuits, when the load capacitance is large, the current pre-emphasis circuit provides a high current during the initial charging phase to ensure sufficient driving capability when facing large capacitive loads. However, adjusting the pre-emphasis capability requires adjusting the number of bias transistors and the bias voltage shared by the main bias circuit, which leads to several problems: The VDS voltage left for the current source and current drain in the pre-emphasis circuit is small due to the presence of the intermediate PMOS and NMOS transistors. To increase VDS, the size of the intermediate PMOS and NMOS transistors must be increased, which results in a large area overhead, making it unsuitable for operation in low-voltage environments or with large load capacitance. Adjusting the driving capability requires changing the number of current sources. To ensure sufficient driving current, a larger area must be reserved for the current source and current drain, resulting in increased circuit area overhead.

[0004] Therefore, developing a pre-emphasis circuit that is suitable for low-voltage environments, has small area overhead, and is adjustable has become a technical problem that urgently needs to be solved. Summary of the Invention

[0005] The present application discloses a pre-emphasis circuit with bidirectional adjustment of time and current, which can balance the common-mode voltage while achieving bidirectional adjustment of pre-emphasis current and time, improves the accuracy and flexibility of pre-emphasis circuit control, meets higher pre-emphasis requirements with a smaller circuit area, and improves the applicability of the pre-emphasis circuit.

[0006] Other purposes and advantages of this application can be further understood from the technical features disclosed in this application.

[0007] To achieve one, part, or all of the above objectives or other objectives, in a first aspect, the present application provides a pre-emphasis circuit with time and current bidirectional adjustment, the pre-emphasis circuit being applicable to a driving circuit, the pre-emphasis circuit comprising:

[0008] The pre-emphasis main circuit includes a plurality of transistors and is used to provide a pre-emphasis current to the driving circuit to enhance the high frequency component of the differential signal;

[0009] A bidirectional regulation circuit includes a configurable transistor, a controllable switch circuit, and an inverter chain. The configurable transistor includes a first configuration transistor and a second configuration transistor. By adjusting the number of the first configuration transistors, the delay time of the differential signal passing through the inverter chain is adjusted to adjust the magnitude of the pre-emphasis time. The inverter chain is used to convert the differential signal into an inverse delayed signal. By adjusting the number of the second configuration transistors and combining the controllable switch circuit to control the output state of the inverse delayed signal, the magnitude of the pre-emphasis current is adjusted.

[0010] The common-mode level adjustment circuit is used to adjust the number of the configurable transistors according to the current size and output voltage of the pre-emphasis main circuit to balance the common-mode voltage.

[0011] In one embodiment, the controllable switch circuit is a CMOS transmission gate, which includes an input terminal, an output terminal and a control terminal. The input terminal of the CMOS transmission gate is connected to the first configuration transistor, one side control terminal of the CMOS transmission gate is connected to the gate of the second configuration transistor, and the output terminal of the CMOS transmission gate is connected to the drain of the same second configuration transistor. The control terminals on both sides of the CMOS transmission gate are used to receive control signals that are differential signals to adjust the number of the second configuration transistors.

[0012] In one embodiment, the common-mode level adjustment circuit includes a comparator, which includes a first input terminal, a second input terminal, and a comparison output terminal; the first input terminal is connected between two load resistors to obtain an output voltage, the second input terminal is connected to a reference circuit to obtain a reference voltage, and the comparison output terminal is used to output a comparison result between the output voltage and the reference voltage; the common-mode level adjustment circuit adjusts the number of the configurable transistors according to the comparison result until the output voltage is equal to half of the reference voltage.

[0013] In one embodiment, the first configuration transistor includes a first configuration PMOS transistor and a first configuration NMOS transistor, and the pre-emphasis main circuit includes an adjustable PMOS transistor and an adjustable NMOS transistor controlled by the bidirectional regulation circuit;

[0014] When the bidirectional regulation circuit controls an adjustable PMOS transistor, the second configuration transistors are PMOS transistors of which the number is configurable; when the bidirectional regulation circuit controls an adjustable NMOS transistor, the second configuration transistors are NMOS transistors of which the number is configurable.

[0015] In one embodiment, when the branch current of the adjustable PMOS tube is greater than the branch current of the adjustable NMOS tube, the number of connected adjustable NMOS tubes is increased through the second configuration transistor; and / or, when the branch current of the adjustable PMOS tube is greater than the branch current of the adjustable NMOS tube, the number of connected adjustable PMOS tubes is reduced through the second configuration transistor.

[0016] In one embodiment, when the output result of the comparison output terminal is high, the number of the second configuration transistors is controlled to decrease in sequence until the output result becomes low, the decreasing number is recorded as a first reference number, and the number of the adjustable PMOS transistors is controlled to be at most lower than the number of the adjustable NMOS transistors by the first reference number; or, when the output result of the comparison output terminal is low, the number of the second configuration transistors is controlled to decrease in sequence until the output result becomes high, the decreasing number is recorded as a second reference number, and the number of the adjustable NMOS transistors is controlled to be at most lower than the number of the adjustable PMOS transistors by the second reference number.

[0017] In one embodiment, the more the first configuration transistors are connected to the circuit, the smaller the delay time and the smaller the pre-emphasis capability; the fewer the first configuration transistors are connected to the circuit, the longer the delay time and the greater the pre-emphasis capability.

[0018] In one embodiment, the differential signal includes a first differential signal and a second differential signal, and the driving circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, wherein the source of the first PMOS transistor is connected to a current source, the source of the first NMOS transistor is grounded, the drain of the second PMOS transistor and the drain of the second NMOS transistor are connected to a first node, and the drain of the third PMOS transistor and the drain of the third NMOS transistor are connected to a second node;

[0019] The pre-emphasis main circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor. The sources of the fourth PMOS transistor and the fifth PMOS transistor are connected to a current source, and the sources of the sixth NMOS transistor and the seventh NMOS transistor are grounded. The sixth PMOS transistor, the seventh PMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor are transistors with adjustable numbers. The drains of the sixth PMOS transistor and the fourth NMOS transistor are connected to the first node for pre-emphasis of the first differential signal. The drains of the seventh PMOS transistor and the fifth NMOS transistor are connected to the second node for pre-emphasis of the second differential signal.

[0020] The bidirectional regulation circuit includes a first regulation circuit connected to the gate of the sixth PMOS transistor, a second regulation circuit connected to the gate of the fourth NMOS transistor, a third regulation circuit connected to the gate of the seventh PMOS transistor, and a fourth regulation circuit connected to the gate of the fifth NMOS transistor. The first regulation circuit and the third regulation circuit are used to control the pre-emphasis current of the first differential signal; the second regulation circuit and the fourth regulation circuit are used to control the pre-emphasis current of the two differential signals.

[0021] In one embodiment, when the first differential signal passes through the inverter chain, after the delay time and when the controllable switch circuit is turned on, a first reverse delayed signal is output as high, thereby controlling at least one transistor of a ninth PMOS transistor in the pre-emphasis main circuit to turn on and output a pre-emphasis current; and / or, when the first differential signal passes through the inverter chain, after the delay time and when the controllable switch circuit is turned on, a first reverse delayed signal is output as high, thereby controlling at least one transistor of a tenth PMOS transistor in the pre-emphasis main circuit to output a pre-emphasis current.

[0022] In one embodiment, when the second differential signal passes through the inverter chain, after the delay time and when the controllable switch circuit is turned on, a second reverse delayed signal is output as low, thereby controlling at least one transistor of the seventh NMOS transistor of the pre-emphasis main circuit to output a pre-emphasis current; and / or, when the second differential signal passes through the inverter chain, after the delay time and when the controllable switch circuit is turned on, a second reverse delayed signal is output as low, thereby controlling at least one transistor of the eighth NMOS transistor of the pre-emphasis main circuit to output a pre-emphasis current.

[0023] The above-mentioned pre-emphasis circuit with bidirectional time and current adjustment adjusts the delay time by adjusting the number of configurable transistors, and adjusts the magnitude of the pre-emphasis current by adjusting the number of configurable transistors and the output state of the controllable switch circuit. Moreover, while achieving bidirectional adjustment, the common-mode level adjustment module addresses the common-mode voltage offset that may be generated by the configurable transistors during the adjustment process. Thus, a smaller circuit area combined with sophisticated circuit control logic can meet higher pre-emphasis requirements, achieving precise and flexible control of the pre-emphasis circuit, improving applicability to low-voltage circuits, and enhancing the driving capability of the LVDS driver circuit under large capacitive loads.

[0024] In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application, the following is a brief introduction to the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0026] Figure 1 A schematic diagram of a low-voltage differential drive circuit provided in this application.

[0027] Figure 2 This is a schematic diagram of a current pre-emphasis circuit in a related technology provided by this application.

[0028] Figure 3 This is a schematic diagram of a pre-emphasis circuit with time and current bidirectional adjustment provided by the present application.

[0029] Figure 4 A timing diagram of a differential signal provided in this application.

[0030] Figure 5 This is a circuit control logic diagram of a pre-emphasis circuit provided in this application. DETAILED DESCRIPTION

[0031] The aforementioned and other technical contents, features, and functions of the present application will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The terms "first," "second," and the like in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, and this is merely a way of distinguishing objects of the same attributes when describing them in the embodiments of the present application.

[0032] refer to Figure 1 , a schematic diagram of the structure of an LVDS driver circuit, in which the first differential signal out_pre_p and the second differential signal out_pre_n form a pair of differential signals, i.e., when one is high, the other is low. Specifically, the first PMOS transistor PM1 acts as a current source, and the first NMOS transistor NM1 acts as a current sink, responsible for providing a stable current. When the first differential signal out_pre_p transitions from high to low, the second differential signal out_pre_n transitions from low to high. At this time, the second PMOS transistor PM2 and the third NMOS transistor NM3 turn on, while the third PMOS transistor PM3 and the second NMOS transistor NM2 turn off. Current flows from PM1, then through PM2, to the first node OUT_N in the middle, then through the first resistor R1 and the second resistor R2, back to the second node OUT_P, through PM3 and NM1, and to ground, forming a complete loop. The typical magnitude of current I1 is 3.5 mA, and R1 = R2, with a resistance of 50 ohms, resulting in a total voltage drop Vod across the first resistor R1 and the second resistor R2 of 350 mV. When the load capacitance is large (usually due to large capacitance loads caused by package pins or multiple interfaces), the 3.5mA current cannot guarantee the signal's tr / tf (rise and fall time, the time it takes for Vod to go from 20% (80%) of the final voltage to 80% (20%) of the final voltage). This is because the larger the capacitance, the slower the charging and the slower the voltage rises (falls).

[0033] It should be noted that, for ease of presentation, the various components of the circuit diagrams in the accompanying drawings of this application are connected by the same names, i.e., signal terminals with the same names have a connection relationship. The xth PMOS transistor in this application is referred to as PMx, and the xth NMOS transistor is referred to as NMx.

[0034] In order to optimize the signal rise / fall time, many designs use current pre-emphasis circuits to provide large currents in the initial stage of charging and optimize the signal rise / fall time. Figure 2, a current pre-emphasis circuit in the related art. Transistors PM5', PM6', NM5', and NM6' are connected to PM2, PM3, NM2, and NM3 in the driver circuit, respectively. The first differential signal out_pre_p and the second differential signal out_pre_n are delayed by a delay time Δt, resulting in a first inverse delayed signal out_pre_p_delay_inv and a second inverse delayed signal out_pre_n_delay_inv, respectively. When the first differential signal out_pre_p transitions from high to low, out_pre_p_delay_inv, previously low, transitions to high after a delay of Δt. This causes PM5' and PM7' to conduct along with PM2 (with a delay of Δt, equivalent to the pre-emphasis circuit on the right applying an additional current for Δt, increasing charging speed and tr). Similarly, NM6', NM8', and NM3 are simultaneously turned on (NM6' and NM8' also conduct for Δt). Current pre-emphasis can ensure that there is sufficient driving capability when a large capacitive load is present, and both tr / tf meet the requirements.

[0035] During research, the inventors of the present application discovered that in order to adjust the pre-emphasis capability of the current pre-emphasis circuit in the related art, the number of bias transistors must be adjusted, and the bias voltages vb1 and vbias used by the main bias circuit must be the same. This leads to the following defects: the current source PM4' and current drain NM4' in the pre-emphasis circuit consume a lot of voltage because the transistors PM5' to NM8' in the middle consume a lot of voltage, leaving a very small VDS voltage for the current source PM4' and current drain NM4'. To increase VDS, the size of the transistors PM5' to NM8' can only be increased. (If the VDS is very small, the current source PM4' and current drain NM4' cannot operate in the saturation region), resulting in a large area overhead, making it unsuitable for low-voltage operation. This structure requires large current source PM4' and current drain NM4' as well as the transistors PM5' to NM8' in the middle, making it unsuitable for large load capacitance. Adjusting the driving capability changes the number of current sources PM4' and current drain NM4'. To ensure sufficient driving current, a large area needs to be reserved for these parts.

[0036] In order to solve the above technical problems, the embodiment of the present application provides a pre-emphasis circuit with time and current bidirectional adjustment, referring to Figure 3The pre-emphasis circuit includes a pre-emphasis main circuit, a bidirectional adjustment circuit, and a common-mode level adjustment circuit. The pre-emphasis circuit is applied to a drive circuit, particularly a low-voltage differential drive circuit. The pre-emphasis main circuit is used to provide a pre-emphasis current to the drive circuit to enhance the high-frequency component of the differential signal, thereby compensating for high-frequency losses during transmission and improving signal quality. The bidirectional adjustment circuit includes a configurable transistor, a controllable switch circuit, and an inverter chain. The configurable transistor includes a first configuration transistor and a second configuration transistor. By adjusting the number of the first configuration transistors, the delay time of the differential signal passing through the inverter chain is adjusted to adjust the pre-emphasis time. The inverter chain is used to convert the differential signal into an inverse delayed signal. By adjusting the number of the second configuration transistors and combining the controllable switch circuit to control the output state of the inverse delayed signal, the pre-emphasis current is adjusted. The common-mode level adjustment circuit is used to adjust the number of configurable transistors according to the current size and output voltage of the pre-emphasis main circuit to balance the common-mode voltage.

[0037] The pre-emphasis circuit of this embodiment adjusts the delay time by adjusting the number of configurable transistors, and adjusts the pre-emphasis current by adjusting the number of configurable transistors and the output state of the controllable switch circuit. Furthermore, while achieving bidirectional regulation, the common-mode level adjustment module addresses the common-mode voltage offset that may be generated by the configurable transistors during the regulation process. This allows for meeting higher pre-emphasis requirements with a smaller circuit area combined with sophisticated circuit control logic, achieving precise and flexible control of the pre-emphasis circuit, improving its applicability to low-voltage circuits, and enhancing the driving capability of the LVDS driver circuit under large capacitive loads.

[0038] In one embodiment, the controllable switch circuit is a CMOS transmission gate, which includes an input, an output, and a control terminal. The input of the CMOS transmission gate is connected to a first configuration transistor, a control terminal on one side of the CMOS transmission gate is connected to the gate of a second configuration transistor, and the output of the CMOS transmission gate is connected to the drain of the same second configuration transistor. The control terminals on both sides of the CMOS transmission gate are used to receive control signals that are differential signals to adjust the number of second configuration transistors. By designing the circuit connection between the CMOS transmission gate and the configurable transistor and combining the circuit control logic, precise control and flexible adjustment of the pre-emphasis current can be achieved to adapt to different operating conditions and changes in data rate, better compensate for high-frequency loss of the differential signal during transmission, and make the rising and falling edges of the signal steeper, thereby reducing the bit error rate and improving the accuracy and reliability of data transmission.

[0039] In one embodiment, reference Figure 3The common-mode level adjustment circuit includes a comparator, which includes a first input terminal, a second input terminal, and a comparison output terminal; the first input terminal is connected between two load resistors to obtain an output voltage, the second input terminal is connected to a reference circuit to obtain a reference voltage, and the comparison output terminal is used to output a comparison result between the output voltage and the reference voltage; the common-mode level adjustment circuit adjusts the number of configurable transistors according to the comparison result until the output voltage is equal to half of the reference voltage. The reference voltage here is the power supply voltage. In this way, the adaptive adjustment capability of the circuit is improved, so that the circuit can automatically adjust the number of configurable transistors according to the actual pre-emphasis voltage change, avoid the adverse effect of the offset between the pull-up current of the PMOS tube and the pull-down current of the NMOS tube on the signal transmission, maintain the stability of the common-mode level, and further improve the stability and reliability of the signal transmission.

[0040] In one embodiment, the first configuration transistor includes a first configuration PMOS transistor and a first configuration NMOS transistor, and the pre-emphasis main circuit includes an adjustable PMOS transistor and an adjustable NMOS transistor controlled by a bidirectional regulation circuit; when the bidirectional regulation circuit controls the adjustable PMOS transistor, the second configuration transistor is a configurable number of PMOS transistors, and when the bidirectional regulation circuit controls the adjustable NMOS transistor, the second configuration transistor is a configurable number of NMOS transistors.

[0041] When the branch current of the adjustable PMOS tube is greater than the branch current of the adjustable NMOS tube, the number of connected adjustable NMOS tubes is increased through the second configuration transistor; and / or, when the branch current of the adjustable PMOS tube is greater than the branch current of the adjustable NMOS tube, the number of connected adjustable PMOS tubes is reduced through the second configuration transistor.

[0042] Similarly, when the branch current of the adjustable PMOS tube is less than the branch current of the adjustable NMOS tube, the number of connected adjustable NMOS tubes is reduced through the second configuration transistor, and / or, when the branch current of the adjustable PMOS tube is less than the branch current of the adjustable NMOS tube, the number of connected adjustable PMOS tubes is increased through the second configuration transistor.

[0043] Furthermore, when the output result of the comparison output terminal is high, the number of the second configuration transistors is controlled to decrease in sequence until the output result becomes low, the decreasing number is recorded as the first reference number, and the number of adjustable PMOS transistors is controlled to be at most lower than the number of adjustable NMOS transistors by the first reference number; or, when the output result of the comparison output terminal is low, the number of the second configuration transistors is controlled to decrease in sequence until the output result becomes high, the decreasing number is recorded as the second reference number, and the number of adjustable NMOS transistors is controlled to be at most lower than the number of adjustable PMOS transistors by the second reference number.

[0044] In this embodiment, a bidirectional adjustment circuit precisely regulates the pre-emphasis circuit. Specifically, for a given pre-emphasis time, adding transistors increases the pre-emphasis current, resulting in stronger pre-emphasis. Similarly, reducing the number of transistors reduces the pre-emphasis current, weakening the pre-emphasis. This allows for better common-mode voltage balance, improved common-mode point offset, and enhanced pre-emphasis circuit stability through detection and comparison by the common-mode level adjustment circuit, combined with regulation by the bidirectional adjustment circuit.

[0045] In one embodiment, the more first-configuration transistors connected to the circuit, the shorter the delay time and the lower the pre-emphasis capability; the fewer first-configuration transistors connected to the circuit, the longer the delay time and the greater the pre-emphasis capability. By adjusting the number of first-configuration transistors, the pre-emphasis time can be precisely adjusted while maintaining a constant pre-emphasis current, thereby achieving flexible and precise control of the pre-emphasis circuit.

[0046] refer to Figure 3 In one embodiment, the differential signal includes a first differential signal and a second differential signal, and the LVDS driving circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor. The source of the first PMOS transistor is connected to a current source, the source of the first NMOS transistor is grounded, the drain of the second PMOS transistor and the drain of the second NMOS transistor are connected to a first node, and the drain of the third PMOS transistor and the drain of the third NMOS transistor are connected to a second node.

[0047] The pre-emphasis main circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor. The sources of the fourth PMOS transistor and the fifth PMOS transistor are connected to a current source, and the sources of the sixth NMOS transistor and the seventh NMOS transistor are grounded. The sixth PMOS transistor, the seventh PMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor are transistors of adjustable quantity. The drains of the sixth PMOS transistor and the fourth NMOS transistor are connected to a first node for pre-emphasis of a first differential signal. The drains of the seventh PMOS transistor and the fifth NMOS transistor are connected to a second node for pre-emphasis of a second differential signal. Thus, by directly connecting the pre-emphasis main circuit to a power supply and omitting the transistors for the current source and the current drain, the pre-emphasis main circuit is simplified, making it suitable for pre-emphasis of low-voltage drive circuits, and achieving a smaller area to meet higher pre-emphasis requirements.

[0048] The bidirectional regulation circuit includes a first regulation circuit connected to the gate of the sixth PMOS transistor, a second regulation circuit connected to the gate of the fourth NMOS transistor, a third regulation circuit connected to the gate of the seventh PMOS transistor, and a fourth regulation circuit connected to the gate of the fifth NMOS transistor. The first regulation circuit and the third regulation circuit are used to control the pre-emphasis current of the first differential signal; the second regulation circuit and the fourth regulation circuit are used to control the pre-emphasis current of the second differential signal.

[0049] Furthermore, the first regulating circuit includes an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor. The eighth PMOS transistor and the ninth NMOS transistor are first configuration transistors, and the tenth PMOS transistor is a second configuration transistor.

[0050] The second regulating circuit includes an eleventh PMOS transistor, a twelfth PMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor. The eleventh PMOS transistor and the twelfth NMOS transistor are first configuration transistors, and the tenth NMOS transistor is a second configuration transistor.

[0051] The third regulating circuit includes a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a thirteenth NMOS transistor, and a fourteenth NMOS transistor. The thirteenth PMOS transistor and the fourteenth NMOS transistor are first configuration transistors, and the fifteenth PMOS transistor is a second configuration transistor.

[0052] The fourth regulating circuit includes a sixteenth PMOS transistor, a seventeenth PMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, and a seventeenth NMOS transistor. The sixteenth PMOS transistor and the seventeenth NMOS transistor are first configuration transistors, and the fifteenth NMOS transistor is a second configuration transistor.

[0053] The first regulating circuit and the second regulating circuit share the same inverter chain; the third regulating circuit and the fourth regulating circuit share the same inverter chain, so as to save circuit area.

[0054] Furthermore, after the first differential signal passes through the inverter chain, a first reverse delayed signal is output as high when the delay time elapses and the controllable switch circuit is turned on, thereby controlling at least one transistor of a ninth PMOS transistor in the pre-emphasis main circuit to turn on and output a pre-emphasis current; and / or, after the first differential signal passes through the inverter chain, a first reverse delayed signal is output as high when the delay time elapses and the controllable switch circuit is turned on, thereby controlling at least one transistor of a tenth PMOS transistor in the pre-emphasis main circuit to output a pre-emphasis current.

[0055] Furthermore, when the second differential signal passes through the inverter chain, after a delay time and when the controllable switch circuit is turned on, a second reverse delayed signal is output as low, thereby controlling at least one transistor of the seventh NMOS transistor of the pre-emphasis main circuit to output a pre-emphasis current; and / or, when the second differential signal passes through the inverter chain, after a delay time and when the controllable switch circuit is turned on, a second reverse delayed signal is output as low, thereby controlling at least one transistor of the eighth NMOS transistor of the pre-emphasis main circuit to output a pre-emphasis current.

[0056] refer to Figure 4 , is a signal timing diagram based on the pre-emphasis circuit of this application, and the following is Figure 4 As an example, combining Figure 3 The upper left circuit diagram and the lower right circuit diagram of the present invention describe in detail the adjustment control process of the pre-emphasis circuit. Among them, the <1:0> behind the transistor represents two transistors, and the <3:0> behind the transistor represents four transistors, indicating that this is a configurable or adjustable transistor. For example, only select <0> , then it represents <1> No participation is required, so <1> The corresponding transistor is turned off. The gate of the PMOS transistor is turned off when it is high and turned on when it is low; the gate of the NMOS transistor is turned off when it is low and turned on when it is high.

[0057] Specifically, out_pre_p_delay_invp1<3:0> is an inverse signal of out_pre_p with a delay of △t. Therefore, when out_pre_p changes from high to low, out_pre_p_delay_invp1<3:0> is high after △t time. During the △t time, PM4 and PM6<3:0> are turned on, and current flows from the power supply through PM4 and PM6<3:0> to the OUT_N point to participate in pre-emphasis, and then flows back to ground through NM5<3:0> and NM7, forming a complete loop.

[0058] NM7 is controlled by out_pre_n. Its gate transitions from low to high at time ①, turning NM7 on. NM5<3:0> is controlled by out_pre_n_delay_inv_n2<3:0>, which is the inverse delayed signal of out_pre_n, with a delay of △t. Therefore, when out_pre_n transitions from low to high at time ①, NM7 immediately turns on. After a delay of △t, out_pre_n_delay_inv_n2<3:0> transitions from high to low. Therefore, the time between NM5<3:0> and NM7 turning on for △t contributes to pre-emphasis, completing the loop.

[0059] Taking the first regulation circuit as an example, we will explain how to implement the delay time △t and how to control the pre-emphasis current: out_pre_p is delayed through several stages to A1, A1 passes through the inverter (PM8, PM9, NM8, NM9), and then passes through the input terminal TG1 of the CMOS transmission gate to the output of out_pre_p_delay_invp1<3:0>. <3> and <0> When choosing, choose <0> ,closure <3> For example, emp_ItrimN<3:0>=0001, emp_ItrimP<3:0>=1110, then TG <3> TG <2> TG <1> All closed, TG <0> Open, PM10 <3> 、PM10 <2> 、PM10 <1> Open, out_pre_p_delay_invp1 <3> 、out_pre_p_delay_invp1 <2> 、out_pre_p_delay_invp1 <1> Output is high, control PM6 <3> 、PM6 <2> 、PM6 <1> Closed; PM10 <0> Close, out_pre_p_delay_invp1 <0> The output has pre-stage control, the output is low, and controls PM6 <0> The rest of the regulation circuit is the same, the difference is that the NMOS tube is controlled by turning off the NMOS tube by outputting a normally low signal.

[0060] Taking the first adjustment circuit as an example, the scheme for adjusting the pre-emphasis delay size to adjust the pre-emphasis capability is explained: by controlling the switching of PM8<3:0> and NM9<3:0> (controlled by emp_TtrimP<3:0> and emn_TtrimN<3:0> respectively), the pull-up and pull-down currents are controlled. The more transistors connected to the circuit, the greater the pull-up and pull-down capabilities, the lower the delay △t, and the weaker the pre-emphasis capability. Similarly, the fewer transistors connected to the circuit, the smaller the pull-up and pull-down capabilities, the longer the delay △t, and the stronger the pre-emphasis capability.

[0061] It should be noted that the specific working processes of the remaining regulating circuits refer to the above description of the first regulating circuit and will not be repeated here.

[0062] Taking the current calibration of the PMOS and NMOS transistors in the upper left and lower right as an example, Atrim1 and Atrim1_n are a pair of differential control signals. When the current matching of the PMOS and NMOS branches (upper left and lower right) needs to be calibrated, Atrim1 is pulled high and out_pre_p is pulled low to open the branch. The current flows from the power supply to PM4 and PM6 through resistors to NM5 and NM7 and then to ground. Ideally, the Vcom voltage should be equal to half the power supply voltage, that is, the vref voltage. Based on the comparator result, the matching degree of the PMOS and NMOS currents can be determined and adjusted, and the common mode point of the pre-emphasis circuit can be optimized.

[0063] Specifically, refer to Figure 5 , the adjustment process includes the following steps:

[0064] Step 1: Initially, turn off the driver circuit, pull out_pre_p low, pull Atrim1 high, and turn on the upper left PMOS and lower right NMOS of the pre-emphasis circuit.

[0065] Step 2: Get and determine the level of the output result comp_out.

[0066] Step 3: If the comp_out output is high, the emp_ItrimN1<3:0> signal is reduced by 1 starting from all 1s (i.e., 1111) until the output comp_out is low. The amount of reduction at this time is recorded as the reference number n1.

[0067] Step 4: When adjusting the pre-emphasis capability, set the PMOS gear to n1 gears lower than the NMOS gear. Repeat the above process according to the actual gear setting of the NMOS to obtain the most accurate n1* for the current gear.

[0068] Step 5: If the comp_out output is low, emp_ItrimN4<3:0> starts with all 1s and decreases by 1 in sequence until the output ends at low; the amount of decrease at this time is recorded as the reference number n4.

[0069] Step 6: When adjusting the pre-emphasis capability, set the NMOS gear to n4 gears lower than the PMOS. Repeat the above process according to the actual gear setting of the PMOS to obtain the most accurate n4* for the current gear.

[0070] In this embodiment, a common-mode level adjustment circuit is used to obtain a reference quantity for transistor adjustment at the initial stage, so that when adjusting the pre-emphasis capability, the adjustment gear is set according to the reference quantity, thereby solving the problem of common-mode voltage offset caused by the mismatch between the pull-up current of the pmos tube and the pull-down current of the nmos tube due to process and other reasons, and improving the stability of the pre-emphasis circuit adjustment process.

[0071] In summary, the pre-emphasis circuit with bidirectional adjustment of time and current in the embodiment of the present application simplifies the pre-emphasis main circuit, making it also suitable for low-voltage pre-emphasis, and a smaller area can achieve greater pre-emphasis capability; the pre-emphasis capability can also be adjusted from two dimensions of pre-emphasis time and pre-emphasis current size, which is more flexible and adaptable; the common-mode voltage of the PMOS branch and NMOS branch current of the pre-emphasis circuit can be improved, avoiding the problem of LVDS common-mode point offset caused by current mismatch between the two branches, further improving the stability and applicability of the pre-emphasis circuit.

[0072] It should be noted that, for those skilled in the art, various improvements and modifications may be made to the present invention without departing from the principles of the present invention, and such improvements and modifications also fall within the scope of protection of the claims of the present invention. It should be understood that certain features of the present invention described in the context of separate embodiments for the sake of clarity may also be provided in combination in a single embodiment. Conversely, various features of the present invention described in the context of a single embodiment for the sake of clarity may also be provided individually or in any suitable combination or as any other described embodiment of the present invention.

Claims

1. A pre-emphasis circuit with bidirectional adjustment of time and current, characterized in that: The pre-emphasis circuit is applicable to a driving circuit, and the pre-emphasis circuit includes: The pre-emphasis main circuit includes a plurality of transistors and is used to provide a pre-emphasis current to the driving circuit to enhance the high frequency component of the differential signal; A bidirectional regulation circuit includes a configurable transistor, a controllable switch circuit, and an inverter chain. The configurable transistor includes a first configuration transistor and a second configuration transistor. By adjusting the number of the first configuration transistors, the delay time of the differential signal passing through the inverter chain is adjusted to adjust the magnitude of the pre-emphasis time. The inverter chain is used to convert the differential signal into an inverse delayed signal. The controllable switch circuit includes an input terminal, an output terminal, and a control terminal. The input terminal of the controllable switch circuit is connected to the first configuration transistor, a control terminal on one side of the controllable switch circuit is connected to the gate of the second configuration transistor, and an output terminal of the controllable switch circuit is connected to the drain of the same second configuration transistor. The control terminals on both sides of the controllable switch circuit are used to receive control signals that are differential signals. The number of the second configuration transistors is adjusted to adjust the magnitude of the pre-emphasis current. A common-mode level adjustment circuit includes a comparator, the comparator including a first input terminal, a second input terminal, and a comparison output terminal; the first input terminal is connected between two load resistors of a driving circuit to obtain an output voltage, the second input terminal is connected to a reference circuit to obtain a reference voltage, and the comparison output terminal is used to output a comparison result between the output voltage and the reference voltage; the common-mode level adjustment circuit adjusts the number of the configurable transistors according to the comparison result until the output voltage is equal to half of the reference voltage, thereby balancing the common-mode voltage.

2. The pre-emphasis circuit with time and current bidirectional regulation according to claim 1, characterized in that: The controllable switch circuit is a CMOS transmission gate.

3. The pre-emphasis circuit with time and current bidirectional regulation according to claim 1, characterized in that: The first configuration transistor includes a first configuration PMOS transistor and a first configuration NMOS transistor, and the pre-emphasis main circuit includes an adjustable PMOS transistor and an adjustable NMOS transistor controlled by the bidirectional regulation circuit; When the bidirectional regulation circuit controls an adjustable PMOS transistor, the second configuration transistors are PMOS transistors of which the number is configurable; when the bidirectional regulation circuit controls an adjustable NMOS transistor, the second configuration transistors are NMOS transistors of which the number is configurable.

4. The pre-emphasis circuit with time and current bidirectional regulation according to claim 3, characterized in that: When the branch current of the adjustable PMOS tube is greater than the branch current of the adjustable NMOS tube, increasing the number of connected adjustable NMOS tubes through the second configuration transistor; and / or, When the branch current of the adjustable PMOS tube is greater than the branch current of the adjustable NMOS tube, the number of connected adjustable PMOS tubes is reduced through the second configuration transistor.

5. The pre-emphasis circuit with time and current bidirectional regulation according to claim 4, characterized in that: When the output result of the comparison output terminal is high, controlling the number of the second configuration transistors to decrease in sequence until the output result becomes low, recording the decreasing number as a first reference number, and controlling the number of the adjustable PMOS transistors to be lower than the number of the adjustable NMOS transistors by at most the first reference number; or, When the output result of the comparison output terminal is low, the number of the second configuration transistors is controlled to decrease in sequence until the output result becomes high, the decreasing number is recorded as the second reference number, and the number of the adjustable NMOS tubes is controlled to be at most lower than the second reference number than the number of the adjustable PMOS tubes.

6. The pre-emphasis circuit with time and current bidirectional regulation according to claim 1, characterized in that: The more the first configuration transistors are connected to the circuit, the smaller the delay time is and the smaller the pre-emphasis capability is; the fewer the first configuration transistors are connected to the circuit, the longer the delay time is and the larger the pre-emphasis capability is.

7. The pre-emphasis circuit with time and current bidirectional regulation according to claim 1, characterized in that: The differential signal includes a first differential signal and a second differential signal, and the driving circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, wherein the source of the first PMOS transistor is connected to a current source, the source of the first NMOS transistor is grounded, the drain of the second PMOS transistor and the drain of the second NMOS transistor are connected to a first node, and the drain of the third PMOS transistor and the drain of the third NMOS transistor are connected to a second node; The pre-emphasis main circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor. The sources of the fourth PMOS transistor and the fifth PMOS transistor are connected to a current source, and the sources of the sixth NMOS transistor and the seventh NMOS transistor are grounded. The sixth PMOS transistor, the seventh PMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor are transistors with adjustable numbers. The drains of the sixth PMOS transistor and the fourth NMOS transistor are connected to the first node for pre-emphasis of the first differential signal. The drains of the seventh PMOS transistor and the fifth NMOS transistor are connected to the second node for pre-emphasis of the second differential signal. The bidirectional regulation circuit includes a first regulation circuit connected to the gate of the sixth PMOS transistor, a second regulation circuit connected to the gate of the fourth NMOS transistor, a third regulation circuit connected to the gate of the seventh PMOS transistor, and a fourth regulation circuit connected to the gate of the fifth NMOS transistor. The first regulation circuit and the third regulation circuit are used to control the pre-emphasis current of the first differential signal; the second regulation circuit and the fourth regulation circuit are used to control the pre-emphasis current of the two differential signals.

8. The pre-emphasis circuit with time and current bidirectional regulation according to claim 7, characterized in that: The first differential signal passes through the inverter chain, and after the delay time and when the controllable switch circuit is turned on, a first reverse delay signal is output as high, thereby controlling at least one transistor of the ninth PMOS tube of the pre-emphasis main circuit to turn on and output a pre-emphasis current; and / or, The first differential signal passes through the inverter chain, and after the delay time and when the controllable switch circuit is turned on, a first reverse delay signal is output as high, thereby controlling at least one transistor of the tenth PMOS tube of the pre-emphasis main circuit to output a pre-emphasis current.

9. The pre-emphasis circuit with time and current bidirectional regulation according to claim 7, characterized in that: The second differential signal passes through the inverter chain, and after the delay time and when the controllable switch circuit is turned on, a second reverse delay signal is output as low, thereby controlling at least one transistor of the seventh NMOS tube of the pre-emphasis main circuit to output a pre-emphasis current; and / or, The second differential signal passes through the inverter chain, and after the delay time and when the controllable switch circuit is turned on, a second reverse delay signal is output as low, controlling at least one transistor of the eighth NMOS tube of the pre-emphasis main circuit to output a pre-emphasis current.

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