Timing verification method, apparatus, device, medium, and product

Abstract

The application discloses a timing verification method, device, equipment, medium and product, and belongs to the technical field of chip design. The method is executed by a computer device deployed with a verification environment, and the verification environment is used for timing verification of at least one DUT. The at least one DUT is used for outputting a timing signal according to image configuration information. The method comprises the following steps: acquiring at least one video frame from a data source; in the case that a first DUT accesses the verification environment, inputting the at least one video frame into the verification environment in response to a verification operation for the first DUT, and obtaining a timing verification result of the first DUT output by the verification environment; wherein the timing verification result comprises at least one of an input verification result and an output verification result, the input verification result is used for indicating a verification result of an input of the first DUT, and the output verification result is used for indicating a verification result of an output of the first DUT. The timing verification is supported to be automated, and the verification efficiency of the timing verification is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip design, and in particular to a timing verification method, device, equipment, medium and product. BACKGROUND

[0002] The timing control module is used for generating timing signals corresponding to video frames or images. Timing signals are a series of precisely defined pulses or trigger signals used for synchronization and control operations in digital circuits and computer systems. The display needs to correctly receive and parse the image data sent by the computer device according to the timing signal, so as to realize the display of video or image.

[0003] When designing the timing control module, the timing signal generation capability of the timing control module needs to be verified. However, for the timing control module, different configurations of video frames or images usually correspond to different timing signals. In the related art, the verification personnel needs to calculate the legal timing signal in advance for the video frames or images under different configurations.

[0004] However, this verification method is too cumbersome and has low verification efficiency. SUMMARY

[0005] The present application provides a timing verification method, device, equipment, medium and product, and the technical solution is as follows:

[0006] According to an aspect of the present application, a timing verification method is provided, which is executed by a computer device deploying a verification environment, the verification environment being used for timing verification of at least one DUT (Device Under Test), the at least one DUT being used for outputting timing signals according to image configuration information; the method comprises:

[0007] obtaining at least one video frame from a data source;

[0008] In the case that a first DUT accesses the verification environment, in response to a verification operation for the first DUT, inputting the at least one video frame to the verification environment to obtain timing verification results of the first DUT output by the verification environment.

[0009] According to an aspect of the present application, a timing verification device is provided, which comprises a verification environment, the verification environment being used for timing verification of at least one DUT (Device Under Test), the at least one DUT being used for outputting timing signals according to image configuration information; the device comprises:

[0010] an obtaining module, configured to obtain at least one video frame from a data source;

[0011] The verification module is configured to input the at least one video frame into the verification environment to obtain a timing verification result of the first DUT output by the verification environment in response to a verification operation on the first DUT when the first DUT accesses the verification environment.

[0012] According to an aspect of the present application, a computer device is provided, comprising a processor and a memory, the memory storing at least one program; the processor is configured to execute the at least one program in the memory to implement the timing verification method.

[0013] According to an aspect of the present application, a computer readable storage medium is provided, the computer readable storage medium storing executable instructions, the executable instructions being loaded and executed by a processor to implement the timing verification method.

[0014] According to an aspect of the present application, a computer program product is provided, the computer program product comprising computer instructions stored in a computer readable storage medium, the computer instructions being read and executed by a processor from the computer readable storage medium to implement the timing verification method.

[0015] The technical scheme provided by the present application has at least the following beneficial effects:

[0016] A verification method for a first DUT is designed, the first DUT being configured to generate a legal timing signal according to image configuration information. By building a verification environment and connecting the first DUT to the verification environment, a timing verification result of at least one DUT is obtained. On the one hand, the verification environment supports timing verification of different DUTs, without the need for users to make additional verification designs for different DUTs, which improves the verification efficiency for DUTs and facilitates users to quickly start the verification for DUTs. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0018] Figure 1 A schematic diagram of a display principle of an analog video provided by an exemplary embodiment of the present application is shown;

[0019] Figure 2 An architecture diagram of a computer system provided by an exemplary embodiment of the present application is shown;

[0020] Figure 3 A flow chart of a timing verification method provided by one example embodiment of the present application is shown;

[0021] Figure 4 A schematic diagram of a timing verification method provided by one example embodiment of the present application is shown;

[0022] Figure 5 A schematic diagram of a timing verification method provided by another example embodiment of the present application is shown;

[0023] Figure 6 A schematic diagram of input and output of a configuration model provided by one example embodiment of the present application is shown;

[0024] Figure 7 A schematic diagram of a timing verification method provided by yet another example embodiment of the present application is shown;

[0025] Figure 8 A schematic diagram of input and output of a timing model provided by one example embodiment of the present application is shown;

[0026] Figure 9 A schematic diagram of input and output of a timing model provided by another example embodiment of the present application is shown;

[0027] Figure 10 A structural block diagram of a timing verification apparatus provided by one example embodiment of the present application is shown;

[0028] Figure 11 A structural schematic diagram of a computer device provided by one example embodiment of the present application is shown. DETAILED DESCRIPTION

[0029] In order to make the objects, technical solutions and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the accompanying drawings.

[0030] The example embodiments will be described in detail herein with reference to the accompanying drawings. The following description is with reference to the drawings, in which like numerals indicate like elements, unless otherwise described in the following description. The embodiments described in the following example embodiments are not meant to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the present application as detailed in the appended claims.

[0031] The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used in the present disclosure and the appended claims, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0032] It should be noted that the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of related data need to comply with relevant laws, regulations and standards of relevant countries and regions. For example, the setting operation and other information involved in the present application are obtained under sufficient authorization.

[0033] It should be understood that although the terms first, second, etc. can be employed in this disclosure to describe various information, the information should not be limited to these terms. These terms are only used to distinguish one type of information from another type of information. For example, a first parameter can also be referred to as a second parameter, and similarly, a second parameter can also be referred to as a first parameter, without departing from the scope of the present disclosure. Depending on the context, the word "if" as used herein can be interpreted as "when" or "upon" or "in response to determining".

[0034] Firstly, the related terms involved in the present application are introduced.

[0035] Timing signal: a series of precisely defined pulses or trigger signals used for synchronization and control operations in digital circuits and computer systems. In the video field and image field shown in the embodiments of the present application, the timing signal includes at least one of the following: field synchronization signal; field front shoulder signal; field rear shoulder signal; field active signal; horizontal synchronization signal; horizontal front shoulder signal; horizontal active signal; horizontal rear shoulder signal; data packet; pixel clock. Next, these timing signals are introduced respectively.

[0036] Field synchronization (Vertical Synchronization, VSYNC) signal: used to identify the start of transmission of a video frame.

[0037] Horizontal synchronization (Horizontal Synchronization, HSYNC) signal: used to identify the start of transmission of a line of pixel data.

[0038] Vertical active (Vertical Active, VActive) signal: used to identify the number of active lines in a video frame, such as the number of corresponding active lines in a video frame with a resolution of 1920x1080 is 1080.

[0039] Horizontal active (Horizontal Active, HActive) signal: used to identify the number of active pixels in a line of pixel data, such as the number of corresponding active pixels in a video frame with a resolution of 1920x1080 is 1920.

[0040] Vertical Front Porch (VFP) signal: used to identify the interval of invalid lines from the end of the field sync signal to the beginning of the valid image data.

[0041] Vertical Back Porch (VBP) signal: used to identify the interval of invalid lines from the end of the valid image data to the beginning of the field sync signal.

[0042] Horizontal Front Porch (HFP) signal: used to identify the interval of invalid pixels from the end of the horizontal sync signal to the beginning of the valid pixel data.

[0043] Horizontal Back Porch (HBP) signal: used to identify the interval of invalid pixels from the end of the valid pixel data to the beginning of the horizontal sync signal.

[0044] Data Enable signal: the pixel data transmitted during the valid level of the Data Enable signal is valid data; the pixel data transmitted during the invalid level of the Data Enable signal is invalid data (e.g. corresponding to displaying black).

[0045] Pixel Clock signal: used to identify the transmission rate of the pixel data. It defines how many pixel data points are transmitted per second (the unit is usually MHz or GHz). For example, a pixel clock of 148.5 MHz means that 148 500000 pixel data points can be transmitted per second.

[0046] The basic concept of digital video originates from analog video. For analog video, it can be understood as follows: video can be decomposed into a plurality of basic viewpoints (pixels), each pixel has independent color information, and these viewpoints are sequentially printed on the screen by an electron gun according to rows and columns, thereby forming a complete picture. By continuously printing pictures and using the delay characteristics of the human eye, dynamic images can be displayed. In this process, there are horizontal blanking and vertical blanking.

[0047] Horizontal Blank (HBlank): the electron gun draws pixels from left to right, and it can only draw one scanning line at a time. Before drawing the next scanning line, it needs to return to the left and prepare for drawing the next scanning line. The time interval between the two is called horizontal blanking, as shown in Figure 1 . That is, the horizontal blanking refers to the time interval between the transmission of the valid data of adjacent two rows of pixels, and the length of the horizontal blanking usually includes the horizontal sync signal and the front porch and back porch of the horizontal scanning. The horizontal blanking can also be referred to as a horizontal blank signal.

[0048] Vertical Blank (VBlank): After all the scan lines in the screen are drawn, it returns to the top left corner of the screen to prepare for the next screen (frame) drawing. The time between the two is the vertical blanking, as shown in Figure 1 . That is, the vertical blanking refers to the time interval between the transmission of the effective data of two adjacent video frames. The length of the vertical blanking usually includes the field synchronization signal and the front and rear shoulders of the field scanning. Among them, the vertical blanking can also be called the field blanking signal.

[0049] In some embodiments, the concept of "field" is the same or similar to the concept of "frame", both of which describe parameters related to a video frame. That is, the above-mentioned field synchronization signal, field effective signal, field front shoulder signal, field rear shoulder signal and field blanking signal can also be called frame synchronization signal, frame effective signal, frame front shoulder signal, frame rear shoulder signal and frame blanking signal.

[0050] It should be understood that in digital video, although the concept of electron gun no longer exists, the display principle of digital video still refers to the display principle of analog video, and the concepts of horizontal blanking and vertical blanking are retained. At this time, it can be selected to enter a low-power state to wait for the end of the time to draw the next round of pixels, or to transmit some other signals such as audio signals.

[0051] Image configuration information: used to indicate the configuration parameters of a video frame. The image configuration information includes at least one of the following: color encoding mode, color depth, refresh rate, image width, image height, image boundary clipping, image format. Among them, the color encoding mode is a way to represent color, and color encoding is to convert the color information perceived by humans into a form of data that computers or other devices can recognize and process. Common color encoding modes such as RGB mode, YUV mode, etc. Image bit depth, also known as color depth or bit depth or color depth, defines the number of colors used by each pixel in an image, and is an important indicator of the richness of image colors. For example, 1-bit bit depth can represent two colors, usually black and white; 4-bit bit depth can represent 16 colors; 8-bit bit depth can represent 256 colors, etc. Image width and image height can be collectively referred to as image resolution. Image format refers to the storage method and encoding rules of pixel data in a video frame. The refresh rate refers to the number of times the screen can be refreshed per second, and the unit is hertz (Hz). For example, a display with a refresh rate of 60Hz means it can refresh the screen 60 times per second. The refresh rate is mainly determined by the hardware performance of the display.

[0052] Frame rate (FPS): the number of video frames displayed per second.

[0053] Vertical Sync Mode: A graphics card setting designed to address the issue of screen tearing in computer games. Screen tearing occurs when the frame rate of a game exceeds the refresh rate of a monitor, causing the monitor to display only a portion of each frame, resulting in a discontinuity in the vertical direction, making the image appear "torn". Vertical Sync is designed to solve this problem. When enabled, the graphics card limits the frame rate of the game based on the refresh rate of the monitor. For example, if the monitor has a refresh rate of 60Hz, the graphics card will limit the frame rate of the game to no more than 60 frames per second. In this way, the graphics card outputs a complete frame each time the monitor refreshes, preventing screen tearing.

[0054] Variable Refresh Rate (VRR) Mode: A technology used in display devices that allows televisions or monitors to automatically adjust their refresh rate in real time to match the frame rate output by compatible computer devices.

[0055] Display Stream Compression (DSC) Mode: A specification for the compression and decompression of image display streams. It contains the syntax and semantics required for compressed video bitstreams. DSC is designed for real-time systems, with real-time compression, transmission, decompression, and display.

[0056] YUV: A color encoding method that represents color as a luminance parameter (Y: Luminance or Luma) and a chrominance parameter (U, V: Chrominance or Chroma). U and V are used to describe the color and saturation of an image, specifying the color of a pixel.

[0057] Figure 2 An architecture diagram of a computer system according to an example embodiment of the present application is shown. The computer system includes a computer device 110.

[0058] Optionally, the computer device 110 can be a terminal or a server.

[0059] Optionally, the terminal includes but is not limited to a mobile phone, a tablet computer, a smart voice interactive device, a game console, a wearable device, a multimedia playback device, a PC (Personal Computer), a vehicle-mounted terminal, a smart home appliance, and the like. Optionally, the terminal can have a verification tool installed and running therein, and the verification tool can have a verification environment built-in or can support user self-deployment of a verification environment.

[0060] It should be noted that the implementation form of the UI (User Interface) design tool and the code generation program described above is not limited, for example, it can be an application program that needs to be downloaded and installed, a small program that does not need to be installed, a web application, a browser plug-in, etc.

[0061] Optionally, the server can be a standalone physical server, or a server cluster, a distributed system, or an artificial intelligence (AI) computing cluster, a cloud computing cluster, etc. composed of multiple physical servers. Among them, the AI computing cluster can also be referred to as an intelligent computing cluster or a smart computing cluster. It can also be a cloud server that provides cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN (Content Delivery Network), and basic cloud computing services such as big data and artificial intelligence platforms, but not limited to this.

[0062] Optionally, the server can be a server that provides background services for the verification tool in the terminal.

[0063] Optionally, the terminal can communicate with the server through a network, such as a wireless or wired network.

[0064] The display engine module is an important part of the graphics processor, which is usually composed of an image processing module, an image timing control module, and a physical signal output module. Among them, the image timing control module is responsible for outputting correct timing signals according to the current configuration, including field synchronization, field front shoulder, field rear shoulder, field effective, line synchronization, line front shoulder, line effective, line rear shoulder, and data packet signals. These signals may have up to 6 different output versions under different clock frequencies, image resolutions, output rates, and display formats, and the verification work is complex and tedious.

[0065] The verification method used in the related art is usually as follows. One verification method is to collect signals through a monitor component and compare them with expected values. This method requires engineers to calculate the correct values of all signals in advance, which is difficult to implement, has low reusability, and needs to be repeated multiple times to complete signal comparison, which is low in efficiency. Another verification method is to implement signal comparison through assertions, which can accurately handle cycle-level errors. However, this verification method has the following disadvantages: ① It relies on manual signal sorting, which is time-consuming and needs to be aligned with the designer, which is low in efficiency. ② The assertion coverage is not complete, and the review of the assertion is time-consuming. ③ A large amount of rewriting is required when the module code changes, which is high in maintenance cost. ④ When a new employee takes over the project, the understanding cost is high, and misunderstandings are easy to occur.

[0066] To overcome the above problems, an embodiment of the present application provides a general, high scalability and high multiplexing image timing model verification method, which can adapt to different versions and different types of image timing control modules, and significantly improve the verification efficiency and accuracy.

[0067] An embodiment of the present application constructs two modules in a verification environment: a timing model and a configuration model, and through the interaction of the two modules with a device under test (DUT), efficient signal comparison and error detection are realized, wherein the DUT is the image timing control module to be tested mentioned above. As shown in Figure 2

[0068] The verification environment 300 includes a configuration model 310 and a timing model 320. The timing model is used to simulate the working process of the DUT. The configuration model 310 is used to determine configuration information, which is used to indicate at least one of the input and output of the timing model.

[0069] The verification environment 300 is used to perform timing verification on the DUT 330 connected to the verification environment 300.

[0070] The verification environment 300 further includes a data source 340, which is used to provide data signals and configuration signals to the DUT 330, and to provide configuration signals to the configuration model 310. The DUT 330 can generate timing signals and second data signals according to the first data signals and configuration signals provided by the data source 340. Generally, the second data signals are signals that are adjusted in timing according to the image configuration information and the generated timing signals. The DUT 330 sends at least one of the timing signals and the first data signals and the second data signals to the timing model 320 in the configuration model 310, so that the timing model 320 generates corresponding timing signals according to the video timing protocol to verify the DUT 330 and obtain timing verification results.

[0071] Figure 3 A flowchart of a timing verification method provided by an exemplary embodiment of the present application is shown. The method is executed by a computer device deployed with a verification environment, which is used for timing verification of at least one DUT, and the at least one DUT is used to output timing signals according to image configuration information; the method includes the following steps.

[0072] Step 210: Obtain at least one video frame from a data source.

[0073] ​Optionally, the at least one video frame comprises at least one of data signals corresponding to respective video frames and configuration signals corresponding to the at least one video frame. Alternatively, the at least one video frame comprises at least one of pixel data (or image data, video data, etc.) corresponding to respective video frames and image configuration information corresponding to the at least one video frame.

[0074] It should be understood that the pixel data, image configuration information, etc. involved in the verification environment all exist in the form of signals, that is, obtaining the at least one video frame from the data source can be understood as obtaining at least one of data signals and configuration signals corresponding to the at least one video frame from the data source. The data signals are used to indicate the pixel data of the at least one video frame, the at least one video frame comprises a plurality of pixel points, each pixel point can be represented by n bits, wherein n is usually a power of 2, such as 8, 16, 32, etc., and the number of bits corresponding to each pixel point is related to the color encoding mode, image bit depth (also referred to as color depth), etc. used by the at least one video frame. The data signals represent the pixel data of the at least one video frame by high and low levels. The configuration signals are the same.

[0075] Optionally, the data signals can also be referred to as image signals, video signals, etc.

[0076] Optionally, the configuration signals are used to indicate image configuration information related to the at least one video frame. The image configuration information includes but is not limited to the color encoding mode, color depth, refresh rate, image width, image height, image boundary clipping, image format, etc. The configuration signals are associated with the data signals of the at least one video frame, and the configuration signals are used to indicate that the computer device confirms the data signals of the at least one video frame.

[0077] Step 220: In the case that the first DUT accesses the verification environment, in response to the verification operation for the first DUT, input at least one video frame to the verification environment to obtain a timing verification result of the first DUT output by the verification environment.

[0078] The timing verification result comprises at least one of an input verification result and an output verification result, the input verification result is used to indicate the verification result of the input of the first DUT, and the output verification result is used to indicate the verification result of the output of the first DUT.

[0079] Optionally, the first DUT is a hardware unit, or the first DUT is an emulation unit. If the first DUT is a hardware unit, the first DUT is connected to the computer device through a hardware interface, so as to realize the access of the first DUT to the verification environment; if the first DUT is an emulation unit, that is, the first DUT is stored in the computer device in the form of a netlist, the first DUT can be connected to the verification environment through a virtual interface by using an emulation application program.

[0080] Optionally, the computer device supports a user to trigger the start of the verification for the first DUT, such as the computer device displaying a control for triggering the verification operation of the first DUT, and the user can click the control through the touch screen or other external devices (such as a keyboard, a mouse, etc.) to trigger the verification operation of the first DUT. Or, the verification environment supports the user to input various operation instructions to trigger different functions of the verification environment, such as modifying the verification environment, starting the verification function of the verification environment, etc., and the user can input the operation instruction of the verification operation of the first DUT through the touch screen or other external devices (such as a keyboard, a mouse, etc.) to trigger the verification operation of the first DUT. The embodiments of the present application do not show all the triggering modes of the verification operation of the first DUT, but the protection scope of the embodiments of the present application is not limited thereto.

[0081] Optionally, the timing verification result of the first DUT is used to indicate the similarity between the first timing signal generated by the first DUT and the second timing signal (i.e., the expected timing signal); or, the timing verification result of the first DUT includes the first timing signal generated by the first DUT and the second timing signal generated by the verification environment; or, the timing verification result of the first DUT includes at least one of the first timing signal generated by the first DUT, the second timing signal generated by the verification environment, the similarity between the first timing signal and the second timing signal, the performance parameter of the first DUT, and the error log of the first DUT.

[0082] In summary, the method shown in the embodiments of the present application designs a verification method for the first DUT, which is used to generate a legal timing signal according to image configuration information. By building a verification environment and connecting the first DUT to the verification environment, the timing verification result of at least one DUT is realized. On the one hand, the verification environment supports the timing verification of different DUTs, without the user making additional verification design for different DUTs, which improves the verification efficiency for DUTs and facilitates the user to quickly start the verification for DUTs.

[0083] Among them, the verification environment needs to be used for timing verification of at least one DUT, and generally, different DUTs should generate different legal timing signals according to different image configuration information. Whether the timing signal is legal depends on whether the relationship between the timing signal and the image configuration information meets the relationship agreed by the video timing protocol. In order to enable the verification environment shown in the embodiments of the present application to realize the timing verification of at least one DUT, the verification environment should include a timing model and a configuration model. Among them, the timing model is used to verify the DUT according to the video timing protocol. The configuration model is used to adjust at least one of the input and output of the timing model according to the characteristics of the DUT. Next, the timing model and the configuration model are introduced respectively.

[0084] 1. Timing model.

[0085] The timing model is used to simulate the working process of the DUT. However, the timing model is to calculate the input as the output according to the video timing protocol.

[0086] Optionally, the step 220 can be implemented as: in the case that the first DUT accesses the verification environment, inputting at least one video frame to the verification environment in response to the verification operation for the first DUT, to generate a first input stimulus; inputting the first input stimulus to the first DUT to obtain a first timing signal output by the first DUT; and inputting at least one of the first input stimulus and the first timing signal to the timing model to obtain a timing verification result.

[0087] Optionally, the verification environment comprises a generation module of the input stimulus, and at least one video frame is inputted to the generation module in the verification environment in response to the verification operation for the first DUT, to generate a first input stimulus.

[0088] Optionally, the first input stimulus is test data or test signal used to drive the first DUT. The first input stimulus is related to image configuration information. For example, the first input stimulus is generated according to the image configuration information.

[0089] Optionally, the first input stimulus further comprises at least one video frame, or in other words, the first input stimulus further comprises data signals and configuration signals of the at least one video frame.

[0090] Optionally, the first DUT is used to generate first timing signals corresponding to the data signals of the at least one video frame according to the data signals and the configuration signals (i.e. image configuration information) of the at least one video frame, and the first timing signals are used to indicate the specific state of the data signals of the at least one video frame, such as using a field synchronization signal to indicate the start of the data signals of a video frame, using a field valid signal to indicate the number of valid lines in a video frame, using a line synchronization signal to indicate the start of transmission of a line of pixel data, using a line valid signal to indicate the number of valid pixels in a line of pixel data, using a data enable signal to indicate the validity of pixel data, and the like, so that the display engine can correctly parse the valid pixel signals in the data signals according to the timing signals, and then display the at least one video frame.

[0091] In some embodiments, the first DUT outputs at least one data signal of a video frame according to the first timing signal generated by the first DUT in addition to outputting the first timing signal. The timing signal output by the first DUT strictly satisfies the timing rules of the display engine or the display, while the data signal of the at least one video frame input into the first DUT does not necessarily satisfy the timing rules of the display engine or the display, and thus the first DUT needs to generate a first timing signal satisfying the video timing protocol according to the image configuration information of the at least one video frame, and output the data signal of the at least one video frame according to the first timing signal, so that the display engine or the display can correctly display the at least one video frame. That is, the timing verification of the first DUT refers to verifying whether the timing signal generated by the first DUT according to the image configuration information satisfies the video timing protocol.

[0092] In some embodiments, at least one of the first input stimulus and the first timing signal is input into the timing model to obtain a timing verification result, including at least one of: inputting the first input stimulus into the timing model to obtain a second timing signal; comparing the second timing signal and the first timing signal to obtain an output verification result; inputting the first timing signal into the timing model to obtain image configuration information; comparing the image configuration information and the first input stimulus to obtain an input verification result.

[0093] Optionally, inputting the first input stimulus into the timing model to obtain a second timing signal can also be implemented by inputting the image configuration information into the timing model to obtain a second timing signal.

[0094] Optionally, the second timing signal is calculated by the timing model according to the image configuration information and the video timing protocol. For example, for the case of image configuration information corresponding to 1920x1080@60Hz, i.e., the resolution is 1920x1080 and the refresh rate is 60Hz, the corresponding lengths of various signals are regulated according to the video timing protocol 11 as follows: the duration of the line synchronization signal is 112; the duration of the line trailing signal is 248; the duration of the line active signal is 1280; the duration of the line leading signal is 48; the duration of the field synchronization signal is 3; the duration of the field trailing signal is 38; the duration of the field active signal is 1024; and the duration of the field leading signal is 1.

[0095] Optionally, the timing model is calculated based on the video timing protocol. That is, the timing model converts the input into the output based on the video timing protocol. For example, the timing model converts the image configuration information into the timing signal based on the video timing protocol, or the timing model converts the timing signal into the image configuration information based on the video timing protocol.

[0096] For the timing model, the reason why the timing signal needs to be converted into image configuration information is that there are some video output modes, such as the variable refresh rate mode, the vertical synchronization mode, the DSC mode and the like, which will change the image configuration information. The timing model determines the image configuration information corresponding to the first DUT according to the first timing signal output by the first DUT according to the video timing protocol, compares the image configuration information with the first input stimulus input into the first DUT, and obtains an input verification result. According to the input verification result, it can be verified whether the first DUT can meet the processing mode for the above modes.

[0097] For example, at least one video frame supports the variable refresh rate mode. After the first input stimulus generated according to the original image configuration information is input into the first DUT, if the first input stimulus further includes update information of the refresh rate and the original refresh rate, the first DUT should generate the first timing signal according to the updated refresh rate, rather than generating the first timing signal according to the original refresh rate. After the first timing signal is input into the timing model, the timing model can obtain the real image configuration information used by the first DUT according to the first timing signal, compare the real image configuration information with the first input stimulus (or the original image configuration information), and determine whether the first DUT supports adjusting the output of the timing signal for the variable refresh rate mode.

[0098] Optionally, the input of the timing model further includes at least one of the following: a synchronization clock; a start signal; and the output of the timing model further includes image data. The image data is the data signal corresponding to at least one video frame.

[0099] Optionally, the synchronization clock is used to ensure the synchronization of the clock inside the computer device. The various components of the entire computer device provide a unified time reference, ensuring that each part can work together. In some embodiments, different systems (such as processors) inside the computer device also use different synchronization clocks, which are not limited by the embodiments of the present application. The synchronization clock is usually generated by a clock generator, which can be a crystal oscillator of the motherboard or other special clock chips. In some complex display systems, a phase-locked loop (PLL) technology can be used to generate a stable and frequency-adjustable synchronization clock signal.

[0100] Optionally, the start signal is used to trigger the timing control model to start working. Or in other words, the start signal is used to trigger the verification environment to start working. That is, in response to the verification operation for the first DUT, the start signal is sent to the timing model.

[0101] In summary, the method provided by the embodiments of the present application shows adding a timing model in a verification environment, which is used to simulate the working process of the first DUT. In the verification environment, first, the first input stimulus is generated according to at least one video frame, and then the first input stimulus is input into the first DUT to obtain the first timing signal. Then, at least one of the input and output corresponding to the first DUT, i.e., at least one of the first input stimulus and the first timing signal, is input into the timing model to simulate the working process of the first DUT, and the timing verification result of the first DUT is obtained, so as to realize the automatic verification for the first DUT and improve the verification efficiency.

[0102] In addition, the timing model supports obtaining the second timing signal according to the first input stimulus, so as to realize the comparison with the first timing signal, i.e., to verify the ability of the first DUT to generate the timing signal. The timing model also supports deducing the image configuration information according to the first timing signal, so as to verify the adjustment ability of the first DUT to generate the timing signal according to some special mode. That is, the ability of the first DUT is verified from multiple aspects, which simplifies the verification process and improves the comprehensiveness and reliability of the verification.

[0103] Further, the timing model is calculated according to the video timing protocol, i.e., it is ensured that the DUT verified by the timing model meets the video timing protocol, and the reliability of the timing verification for the DUT is ensured.

[0104] 2. The configuration model.

[0105] The verification environment includes the configuration model, which is used to determine the configuration information, and the configuration information is used to indicate at least one of the input and output of the timing model.

[0106] In some embodiments, the method further includes: in the case that the first DUT accesses the verification environment, in response to the verification operation for the first DUT, the configuration model obtains the configuration signal from the data source to generate the configuration information. The above-mentioned inputting at least one of the first input stimulus and the first timing signal into the timing model to obtain the timing verification result includes: inputting at least one of the first input stimulus and the first timing signal and the configuration information into the timing model to obtain the timing verification result.

[0107] Optionally, the input of the timing model includes the configuration information output by the configuration model in addition to at least one of the input (i.e., the first input stimulus) and the output (i.e., the first timing signal) of the first DUT. The configuration information is used to indicate how the timing model should process the input and how to adjust the output, so that the processing process of the timing model can accurately simulate the processing process of the first DUT.

[0108] In some embodiments, the configuration information comprises at least one of: a working mode, the working mode being used to indicate that the output of the timing model is image configuration information or a timing signal; a timing strobe signal, the timing strobe signal being used to indicate the timing signal output by the timing model; a vertical synchronization mode; a variable refresh rate mode; a display stream compression mode; a YUV mode.

[0109] The working mode is used to indicate that the output of the timing model is image configuration information or a timing signal, i.e., the working mode is used to indicate whether the timing model generates a timing signal according to image configuration information or generates image configuration information according to a timing signal.

[0110] For example, the configuration information comprises a working mode, the working mode being used to indicate that the output of the timing model is image configuration information or a timing signal; in a case where the configuration information indicates a first working mode, the first input stimulus and the configuration information are input into the timing model to obtain an output verification result, the first working mode being used to indicate that the output of the timing model is a timing signal; in a case where the configuration information indicates a second working mode, the first timing signal and the configuration information are input into the timing model to obtain an input verification result, the second working mode being used to indicate that the output of the timing model is image configuration information. For example, the configuration model performs input verification and output verification for a group of video frames according to the design and verification of the first DUT.

[0111] For example, in a case where the configuration information indicates the first working mode, the first input stimulus and the configuration information are input into the timing model to obtain a second timing signal; the second timing signal and the first timing signal are compared to obtain an output verification result. In a case where the configuration information indicates the second working mode, the first timing signal and the configuration information are input into the timing model to obtain image configuration information; the image configuration information and the first input stimulus are compared to obtain an input verification result.

[0112] The working mode of the timing model is used to indicate that the timing model can support input verification and output verification. The input and output of the first DUT are verified respectively, which helps to comprehensively verify the function of the first DUT, and when the first DUT fails, it can be determined whether the failure is caused by the input stimulus in the verification environment or the failure inside the first DUT based on the input verification result and the output verification result. Since the failure may be caused by abnormal input data, timing problems or design logic defects, if only the output is verified, it can only be found that a failure has occurred, but it cannot be determined where the failure occurs. By checking the input, it can be quickly determined whether the problem is external excitation or internal DUT problem.

[0113] The timing selection signal is used to indicate the timing signal that the timing model needs to output when outputting the timing signal, or the timing selection signal is used to indicate the timing signal input to the timing model. For example, the timing selection signal corresponds to 12 bits, which is used to control whether the timing model samples a specific timing signal (such as field blanking, field front porch, field back porch, etc.). For example, at the beginning of the development of the first DUT, the first DUT does not need to be able to directly output all timing signals, but only needs to output part of the timing signals according to the current design function. At this time, the timing model should also output part of the timing signals of the same type as the first DUT. At this time, the configuration information containing the timing selection signal can be determined by the configuration signal indicating the configuration model, and the timing selection signal is used to indicate the part of the timing signal that should be output. For example, each bit of the timing selection signal corresponds to a timing signal, such as the first bit corresponding to the field sync signal, the second bit corresponding to the field front porch signal, the third bit corresponding to the field back porch signal, the fourth bit corresponding to the field active signal, the fifth bit corresponding to the line sync signal, the sixth bit corresponding to the line front porch signal, the seventh bit corresponding to the line active signal, the eighth bit corresponding to the line back porch signal, the ninth bit corresponding to the data packet, and the tenth to twelfth bits are reserved and do not indicate the timing signal. If the corresponding bit of the timing selection signal is 1, it indicates that the timing model should output the timing signal corresponding to the bit, and if the corresponding bit of the timing selection signal is 0, it indicates that the timing signal corresponding to the bit does not need to be output. For example, if the first bit is 1, it indicates that the timing model should output the field sync signal. It should be noted that the above specific meaning of the value of the bit is only illustrative, and in some embodiments, the corresponding bit of the timing selection signal can be 0 to indicate that the timing signal corresponding to the bit needs to be output, and the corresponding bit of the timing selection signal can be 1 to indicate that the timing signal corresponding to the bit does not need to be output.

[0114] For example, the configuration information includes a timing selection signal, and the timing selection signal is used to indicate the timing signal output by the timing model. The first input stimulus and the configuration information are input to the timing model to obtain a second timing signal, and the second timing signal includes the timing signal indicated by the configuration information; the second timing signal and the first timing signal are compared to obtain an output verification result. Assuming that the first DUT only needs to output the field sync signal, the field front porch signal, the field active signal, and the field back porch signal under the current verification requirement, the timing selection signal in the configuration information can set the first bit to the fourth bit to 1 and set the remaining fifth bit to the twelfth bit to 0, and at this time the timing model will output the field sync signal, the field front porch signal, the field active signal, and the field back porch signal according to the timing selection signal. In addition, the timing selection signal can also be used to indicate the input timing signal to the timing model, that is, when the timing model generates image configuration information according to the timing signal, the input timing signal can be indicated by the timing selection signal.

[0115] For example, the configuration information includes a timing selection signal, and the timing selection signal is used to indicate a timing signal of the input timing model. The configuration model determines the timing selection signal in the configuration information based on the first timing signal; and inputs the first timing signal and the configuration information into the timing model to obtain an input verification result. That is, the timing model is informed by the timing selection signal which timing signals are valid and need to be processed, and which timing signals are invalid and do not need to be processed.

[0116] The vertical synchronization mode and the variable refresh rate mode will adjust the frame rate or the refresh rate during the display process, and after the adjustment of the frame rate and the refresh rate, the sampling time of the timing signal should also be adjusted correspondingly to ensure that the timing signal can support the display of at least one video frame after the adjustment of the frame rate or the refresh rate. For example, the relationship between the display time T of a video frame and the frame rate f is T = 1 / f. When the frame rate is 60FPS, the display time of each video frame is 1 / 60 seconds, that is, about 16.67 milliseconds. The timing signal needs to reasonably arrange the horizontal and vertical scanning processes according to the display time of this video frame. The line synchronization signal controls the time of each line scanning, and the field synchronization signal controls the time of each video frame scanning. Within the period of a video frame, the field synchronization signal is triggered once, indicating the beginning of a new frame; and in each line scanning, the line synchronization signal appears periodically, controlling the electron beam to scan a line from left to right and then return to the starting position of the next line. The relationship between the refresh rate and the timing signal is the same.

[0117] For example, the configuration information includes at least one of the vertical synchronization mode and the variable refresh rate mode; the first input stimulus and the configuration information are input into the timing model to obtain a second timing signal, and the sampling time of the second timing signal is determined based on at least one of the vertical synchronization mode and the variable refresh rate mode; and the second timing signal and the first timing signal are compared to obtain an output verification result. The output verification result is used to verify whether the function of the first DUT for at least one of the vertical synchronization mode and the variable refresh rate mode is normal.

[0118] Optionally, the sampling timing of the timing signal refers to the timing at which other circuit units sample the timing signal, for example, if the timing signal represents a rising edge, the other circuit units should trigger sampling at the rising edge of the timing signal, and for the first DUT and the timing model, they are responsible for generating the timing signal, at this time, the sampling timing of the timing signal can be represented as the timing at which the first DUT or the timing model generates a valid timing signal, for example, the timing at which the timing signal is switched from 0 to 1 to generate a rising edge. The sampling timing of the second timing signal is determined based on at least one of the vertical synchronization mode and the variable refresh rate mode. That is, the sampling timing of the second timing signal is determined based on at least one of the first frame rate and the first refresh rate, the first frame rate is determined based on the vertical synchronization mode, for example, when the frame rate indicated in the configuration signal of at least one video frame is higher than the refresh rate, the frame rate is adjusted to correspond to the refresh rate, and the adjusted frame rate is the first frame rate, for example, the refresh rate is 60Hz, and the first frame rate is less than or equal to 60. The first refresh rate is determined based on the variable refresh rate mode.

[0119] Optionally, the sampling timing of the second timing signal mainly refers to the sampling timing of the synchronization signal (field synchronization signal, line synchronization signal, etc.), and the sampling timing of the remaining timing signals will also change accordingly. For example, the sampling frequency of the line synchronization signal is increased, and the sampling frequencies of the corresponding line valid signal, line front shoulder signal, line rear shoulder signal, etc. should also be increased accordingly, so as to ensure that the scanning and display of a line of a video frame are accelerated.

[0120] Among them, by indicating at least one of the vertical synchronization mode and the variable refresh rate mode in the configuration information, the timing model can assist in verifying whether the first DUT can correctly process and respond to these modes, rather than only verifying some general scenarios, thereby increasing the applicability of the verification environment and the comprehensiveness of the verification.

[0121] The DSC mode and the YUV mode affect the transmission of image data, and thus affect the processing of the at least one video frame by the first DUT. The configuration model controls the processing of the at least one video frame by the timing model by indicating whether to enable at least one of the DSC mode and the YUV mode. DSC is an image compression technology. After the DSC mode is enabled, the amount of data of the image data to be transmitted can be reduced, which requires the first DUT or the timing model to adjust the timing signals such as the row valid signal, the field valid signal, the data enable signal, and the like, for example, to shorten these timing signals. Accordingly, the front shoulder signal (row front shoulder signal and field front shoulder signal), the back shoulder signal (row back shoulder signal and field back shoulder signal), and the like are also adjusted accordingly. The YUV mode is a color encoding mode. The YUV mode and the commonly used RGB mode have some differences in the processing of image data. The YUV mode can cause changes in the pixel clock signal, the data bandwidth, and the like corresponding to the image data. For example, in the RGB mode, each pixel can be represented as a red color component (R), a green color component (G), and a blue color component (B). In the YUV mode, each pixel can be represented as a luminance component (Y) and two color components (U and V), such as color component U being B-Y (blue color difference) and color component V being R-Y (red color difference). However, for the YUV mode, compared with the RGB mode, one step of compression is usually performed, and part of the color accuracy is sacrificed to compress the image data. For example, YUV420 uses 1 set of U and V to share 2 luminance (Y) in the horizontal direction, and 1 set of U and V to share 2 rows of luminance (Y) in the vertical direction, so that the entire image is represented as only 1.25 bytes per pixel after averaging, which is less than the 3 bytes per pixel in the RGB mode. Naturally, the reduction in data volume requires updating the pixel clock signal and the like.

[0122] For example, the configuration information includes at least one of a display stream compression mode and a YUV mode; and the outputs of the first DUT and the timing model further include image data. The image data output by the first DUT is aligned with the first timing signal output by the first DUT, such as being output at a time corresponding to the row valid signal or the field valid signal. Similarly, the image data output by the timing model is aligned with the second timing signal output by the timing model. Therefore, the comparison of the output results can be performed on the image signals in addition to the timing signals. For example, the at least one video frame and the configuration information are input to the timing model to obtain first image data, the first image data being processed based on the at least one video frame, and the processing of the first image data being determined based on at least one of the display stream compression mode and the YUV mode.

[0123] The configuration information indicates at least one of the display stream compression mode and the YUV mode, so that the timing model can assist in verifying whether the first DUT can correctly process and respond to these modes, rather than only verifying some general scenes, thereby increasing the scope of application of the verification environment and the comprehensiveness of the verification.

[0124] Optionally, the timing signal includes at least one of the following: a field synchronization signal; a field front porch signal; a field back porch signal; a field valid signal; a line synchronization signal; a line front porch signal; a line valid signal; a line back porch signal; a data packet; and a pixel clock signal. Details of the timing signal can be referred to the above description of the term "timing signal", and will not be repeated here.

[0125] In some embodiments, the configuration model is configured to drive the verification process for the first DUT in addition to configuring at least one of the input and the output of the timing signal, i.e., the configuration model is also configured to generate an interrupt signal of the first DUT; and the method further includes: in response to an interrupt verification operation for the first DUT, inputting the interrupt signal to the first DUT in the process of inputting the first input stimulus to the first DUT, and obtaining interrupt reporting information of the first DUT, the interrupt reporting information being used to verify the interrupt reporting behavior of the first DUT, when the first DUT is connected to the verification environment.

[0126] For example, the interrupt signal is a specific level or pulse. The interrupt reporting information is used to indicate at least one of the following: that the first DUT has an interrupt, a cause of the interrupt, and a processing method for the interrupt. The cause of the interrupt is, for example, that an abnormal interrupt signal is received from the display panel. The processing method for the interrupt is, for example, saving a scene so as to restore the scene according to the saved information after the interrupt is over.

[0127] In summary, the method provided by the embodiments of the present application shows that a configuration model is added to the verification environment to make the verification environment applicable to timing verification of different DUTs, so that the timing verification method shown by the embodiments of the present application is more universal. The configuration model outputs configuration information to the timing model to adjust at least one of the input and the output of the timing model in the verification process, so that the granularity of the output generated by the timing model can be aligned with the granularity of the timing signal output by the first DUT, avoiding comparison errors due to misalignment of the granularity when comparing the timing signal or the image configuration information, and ensuring the reliability of the timing verification process.

[0128] Further, the configuration model also supports generating an interrupt signal to test the interrupt reporting behavior of the first DUT, thereby expanding the comprehensiveness of the timing verification of the first DUT.

[0129] The verification method used in the related art is generally as follows. One verification method is to collect signals by writing a monitor component and compare them with expected values. This method requires engineers to calculate the correct values of all signals in advance, which is difficult to implement, has low reusability, and needs to be repeated multiple times to complete signal comparison, which is low in efficiency. Another verification method is to implement signal comparison through assertions, which can accurately handle cycle-level errors. However, this verification method has the following disadvantages: a. It relies on manual signal grooming, which is time-consuming and needs to be aligned with the design personnel, and is low in efficiency. b. The assertion coverage is not complete, and the review of the assertion is time-consuming. c. A large amount of rewriting is required when the module code changes, which is high in maintenance cost. d. When a new employee takes over the project, it is high in understanding cost and easy to cause misunderstanding.

[0130] To overcome the above problems, the embodiments of the present application propose a general, high scalability and high reusability image timing model verification method, which can adapt to different versions and different types of image timing control modules, and significantly improve the verification efficiency and accuracy.

[0131] The embodiments of the present application construct two modules in the verification environment: a timing model and a configuration model, and through the interaction of the two modules with the DUT, efficient signal comparison and error detection are realized. As shown in Figure 4

[0132] The verification environment 300 includes a configuration model 310 and a timing model 320. The timing model is used to simulate the working process of the DUT. The configuration model 310 is used to determine the configuration information, which is used to indicate at least one of the input and output of the timing model.

[0133] The verification environment 300 is used to perform timing verification on the DUT 330 connected to the verification environment 300.

[0134] The verification environment 300 further includes a data source 340, which is used to provide data signals and configuration signals to the DUT 330, and to provide configuration signals to the configuration model 310. The DUT 330 can generate timing signals and second data signals according to the first data signals and configuration signals provided by the data source 340. Generally, the second data signals are signals adjusted in timing according to image configuration information. The DUT 330 sends at least one of the timing signals and the first data signals and the second data signals to the timing model 320 in the configuration model 310, so that the timing model 320 generates corresponding timing signals according to the video timing protocol to verify the DUT 330.

[0135] ​The verification environment 300 also includes a monitor 350, which is configured to output at least one of the second data signal and the third data signal from the configuration model 310 or the timing model 320, the third data signal being a data signal shown by the timing model 320 according to the processing process of the DUT. The monitor 350 is configured to capture the timing behavior (such as clock edges, timing relationships) of at least one of the input second data signal and the third data signal, and to complete timing checking or data comparison.

[0136] The specific process of performing timing verification on the DUT 330 using the verification environment 300 is shown as follows.

[0137] 1. Configuration model 310 completion: complete the configuration model 310 according to the design document to ensure that it can cover all configuration scenarios of the DUT.

[0138] 2. Model integration: integrate the configuration model 310 and the timing model 320 into the initial verification environment. The configuration model 310 supports two verification frameworks.

[0139] a. For the first verification framework, the interface of the configuration model is instantiated as a virtual interface, and the monitor (Monitor) and driver (Driver) in the first verification framework are transmitted for signal sampling and driving.

[0140] b. For the second verification framework, the Monitor samples the output of the configuration model and compares it with the input stimulus of the DUT.

[0141] 3. Run the verification simulation: run at least a complete frame of image each time. During the simulation, the configuration model will report error signals in real time, and the verification personnel can locate the error cause by sampling the signals of the Monitor.

[0142] 4. Configuration model modification: when the version of the DUT changes, quickly adapt to new functions by modifying the configuration model to ensure the comprehensiveness and accuracy of the verification.

[0143] And for the configuration model 310 and the timing model 320 shown above, the construction process is as follows Figure 5As shown. First, for the construction process of the two modules, the joint participation of the designer and the verifier is needed. The designer provides the design document 10, which is used to indicate the function of the DUT to be verified, so that the verifier can determine from the design document how the configuration model 310 should output the configuration information to indicate the work of the timing model 320. In addition, the verifier also needs to extract the timing standard information 12 for the timing model 320 calculation process according to the video timing protocol 11, such as different image configuration corresponding timing signal. For example, for the case of image configuration information corresponding to 1920x1080@60Hz, that is, the resolution is 1920x1080 and the refresh rate is 60Hz, the length of each signal corresponding to it is 112 according to the provisions of the video timing protocol 11: line synchronization signal; 248; line after shoulder signal; 1280; line effective signal; 48; line front shoulder signal; 3; field synchronization signal; 38; field after shoulder signal; 1024; field effective signal; 1; field front shoulder signal. After determining the timing standard information 12, the verifier can generate the timing model 320 according to the timing standard information 12, that is, according to the timing standard information 12, the timing model is designed to output the timing signal under different image configuration information, and the corresponding image configuration information is determined for different timing signals. After generating the configuration model 310 and the timing model 320, the configuration model 310 and the timing model 320 can be mounted in the verification environment, which is an initial verification environment, and after mounting the timing model 320 and the configuration model 310, the complete verification environment 300 in the embodiment of the application is obtained. Then, the DUT to be verified can be connected to the verification environment 300 to obtain the simulation and alignment result 13. The simulation and alignment result 13 is used to determine whether the current DUT meets the design requirements and whether further adjustment is needed before re-performing timing verification.

[0144] Next, the configuration model 310 and the timing model 320 are further introduced respectively.

[0145] The main function of the configuration model 310 is to configure the timing model according to the specific characteristics of the DUT, and supplement the input and output signals for the special scene of the DUT. The input and output of the configuration model are as shown in the figure. Figure 6

[0146] The typical application of the configuration model includes one or more of the following.

[0147] 1. Mode selection: By setting the mode selection signal, the output mode of the timing model (outputting image configuration information or timing signal) is controlled.

[0148] ​2. Output selection: through a 12-bit wide timing selection signal, control whether the timing model samples a specific timing signal (such as the field blanking signal, the field pre-shoulder signal, the field post-shoulder signal, etc.) to adapt to the partial signal output of the DUT in the early stage of development.

[0149] 3. VRR mode, VSync mode: in the variable refresh rate (VRR) and vertical synchronization (VSync) modes, adjust the output of the timing model to match the behavior of the DUT. The vertical synchronization mode and the variable refresh rate mode will adjust the frame rate or the refresh rate during display, and after the adjustment of the frame rate and the refresh rate, the timing signal should also be adjusted accordingly to ensure that the timing signal can support the display of at least one video frame after the adjustment of the frame rate or the refresh rate. For example, the relationship between the display time T of a video frame and the frame rate f is T = 1 / f. When the frame rate is 60 FPS, the display time of each video frame is 1 / 60 seconds, i.e. about 16.67 milliseconds. The timing signal needs to reasonably arrange the horizontal and vertical scanning process according to the display time of this video frame. The horizontal synchronization signal controls the time of each line scanning, and the vertical synchronization signal controls the time of each video frame scanning. Within the period of a video frame, the vertical synchronization signal is triggered once, indicating the start of a new frame; and in each line scanning, the horizontal synchronization signal appears periodically, controlling the electron beam to scan a line from left to right and then return to the starting position of the next line. The relationship between the refresh rate and the timing signal is the same.

[0150] 4. DSC mode, YUV input mode: in the DSC and YUV input modes, adjust the output of the timing model to match the data processing method of the DUT. The DSC mode and the YUV mode will affect the transmission method of image data, and thus affect the processing method of the first DUT for at least one video frame. Therefore, the configuration model controls the processing method of the timing model for at least one video frame by indicating whether to enable at least one of the DSC mode and the YUV mode to the timing model. DSC is an image compression technology, and after the DSC mode is enabled, the data amount of the image data required for transmission may be reduced, which makes the first DUT or the timing model need to adjust the timing signals such as the line valid signal, the field valid signal, and the data enable signal, such as shortening these timing signals, and the corresponding pre-shoulder signals (line pre-shoulder signal and field pre-shoulder signal), post-shoulder signals (line post-shoulder signal and field post-shoulder signal) will also be adjusted accordingly. The YUV mode is a color encoding method, and there is a certain difference between the YUV mode and the commonly used RGB mode in the processing method of image data. The YUV mode may cause changes in the pixel clock signal, data bandwidth, etc. corresponding to the image data.

[0151] 5. Interrupt mode: through the interrupt mode, the model can output an interrupt signal (level or pulse), and verify whether the interrupt reporting behavior of the DUT is legal.

[0152] When the DUT version changes, the configuration model can quickly adapt to new functions through a reserved interface, significantly improving verification efficiency. The process of modifying the configuration model is as shown in Figure 7 .

[0153] Step 1: The designer provides a document.

[0154] The scope of change and technical details need to be clearly defined according to the document, laying the foundation for subsequent analysis. For example, whether it involves upgrading the video timing protocol, whether the clock frequency and constraints change, etc.

[0155] Step 2: The verification personnel analyze the document and learn new features.

[0156] Step 3: The verification personnel organize a lecture and list the modification points according to the features.

[0157] Step 4: Modify the configuration module and align the waveforms with the designer.

[0158] After determining the modification points, the verification personnel can modify some input and output information in the configuration model, so that the configuration model matches the content of the document, and then perform timing verification according to the modified configuration model to confirm whether the output data signal meets the designer's requirements.

[0159] Step 5: Run simulation and extract results.

[0160] The main function of the timing model 320 is to output corresponding timing parameter information according to the timing signal input of the DUT. The input and output of the timing model 320 are calculated based on the video timing protocol and can directly adapt to multiple different versions of the DUT. The input and output of the timing model are as shown in Figure 8 and Figure 9 .

[0161] The input signals include at least one of the following signals.

[0162] 1. Mode selection signal: selects the working mode of the timing model.

[0163] 2. Output signal of the DUT: including line synchronization, field synchronization, valid signal, front shoulder signal, rear shoulder signal, and blank signal, etc.

[0164] 3. Synchronization signal, pixel clock, and start signal: used to control the sampling and analysis behavior of the timing model.

[0165] The output signals include at least one of the following signals.

[0166] 1. Image configuration information: such as image width, image height, image refresh rate, etc., used to compare with the input stimulus of the DUT.

[0167] 2. Timing signal: such as horizontal synchronization, field synchronization, active signal, etc., used for comparison with the output signal of the DUT.

[0168] 3. Raw image data: the raw image data is the data signal shown above, the raw image data output by the timing model is the raw image data output according to the image configuration information or according to the timing signal, that is, the raw image data can be used to extract the timing signal characteristics output by the timing model.

[0169] In some embodiments, as shown in Figure 8 The input signals of the timing model 320 include a synchronization clock, a start signal, YUV data input, DSC data input, mode selection signal, timing selection signal, and first timing signal output by the DUT. At this time, the timing model 320 outputs raw image data according to the related configuration information on one hand, and inversely deduces the image configuration information from the first timing signal output by the DUT on the other hand, so as to be used for comparison with the input stimulus of the DUT.

[0170] In other embodiments, as shown in Figure 9 The input signals of the timing model 320 include a synchronization clock, a start signal, YUV data input, DSC data input, mode selection signal, timing selection signal, and image configuration information corresponding to the DUT. For the DUT, the image configuration information is used to generate the input stimulus of the DUT. At this time, the timing model 320 outputs raw image data according to the related configuration information on one hand, and outputs a second timing signal according to the image configuration information of the DUT on the other hand, which is used for comparison with the first timing signal output by the DUT.

[0171] Please refer to Figure 10 , which shows the structure block diagram of the timing verification device provided by an exemplary embodiment of the present application. The device has the functions of implementing the timing verification method examples described above, and the functions can be implemented by hardware or corresponding software executed by hardware. The device can be the computer device introduced above, or can be arranged in the computer device. The device includes a verification environment, which is used for timing verification of at least one DUT. The at least one DUT is used to output a timing signal according to image configuration information. As shown in Figure 11 , the device can include an acquisition module 410 and a verification module 420.

[0172] The acquisition module 410 is used to acquire at least one video frame from a data source.

[0173] The verification module 420 is configured to, in response to a verification operation on the first DUT, input the at least one video frame into the verification environment to obtain a timing verification result of the first DUT output by the verification environment, in a case where the first DUT accesses the verification environment.

[0174] The timing verification result includes at least one of an input verification result and an output verification result, the input verification result is used to indicate a verification result of an input of the first DUT, and the output verification result is used to indicate a verification result of an output of the first DUT.

[0175] In some embodiments, the verification environment includes a timing model configured to simulate a working process of the first DUT, and the verification module 420 includes a sending sub-module, a receiving sub-module, and a verification sub-module.

[0176] The sending sub-module is configured to, in response to the verification operation on the first DUT, input the at least one video frame into the verification environment to generate a first input stimulus, in a case where the first DUT accesses the verification environment.

[0177] The receiving sub-module is configured to input the first input stimulus into the first DUT to obtain a first timing signal output by the first DUT.

[0178] The verification sub-module is configured to input at least one of the first input stimulus and the first timing signal into the timing model to obtain the timing verification result.

[0179] In some embodiments, the verification sub-module is configured to input the first input stimulus into the timing model to obtain a second timing signal, compare the second timing signal with the first timing signal to obtain the output verification result, input the first timing signal into the timing model to obtain image configuration information, and compare the image configuration information with the first input stimulus to obtain the input verification result.

[0180] In some embodiments, the timing model is calculated based on a video timing protocol.

[0181] In some embodiments, the input of the timing model further includes at least one of a synchronization clock and a start signal, and the output of the timing model further includes image data.

[0182] In some embodiments, the verification environment includes a configuration model configured to determine configuration information, the configuration information being used to indicate at least one of an input and an output of the timing model, and the apparatus further includes a configuration module.

[0183] The configuration module is configured to, in response to a verification operation on the first DUT, acquire configuration signals from the data source to generate the configuration information when the first DUT accesses the verification environment.

[0184] The verification submodule is further configured to input at least one of the first input stimulus and the first timing signal and the configuration information into the timing model to obtain the timing verification result.

[0185] In some embodiments, the configuration information includes at least one of: a working mode, the working mode being used to indicate that an output of the timing model is image configuration information or timing signals; a timing strobe signal, the timing strobe signal being used to indicate the timing signals output by the timing model; a vertical synchronization mode; a variable refresh rate mode; a display stream compression mode; a YUV mode.

[0186] In some embodiments, the configuration information includes a working mode, the working mode being used to indicate that an output of the timing model is image configuration information or timing signals; the verification submodule is further configured to, when the configuration information indicates a first working mode, input the first input stimulus and the configuration information into the timing model to obtain the output verification result, the first working mode being used to indicate that the output of the timing model is the timing signals; and when the configuration information indicates a second working mode, input the first timing signal and the configuration information into the timing model to obtain the input verification result, the second working mode being used to indicate that the output of the timing model is the image configuration information.

[0187] In some embodiments, the configuration information includes a timing strobe signal, the timing strobe signal being used to indicate timing signals input into the timing model or timing signals output by the timing model; the verification submodule is further configured to input the first input stimulus and the configuration information into the timing model to obtain second timing signals, the second timing signals including the timing signals indicated by the configuration information; compare the second timing signals and the first timing signals to obtain the output verification result; or, determine the timing strobe signal in the configuration information based on the first timing signal; input the first timing signal and the configuration information into the timing model to obtain the input verification result.

[0188] In some embodiments, the configuration information comprises at least one of a vertical synchronization mode and a variable refresh rate mode; the first verification submodule is further configured to input the first input stimulus and the configuration information into the timing model to obtain a second timing signal, a sampling time of the second timing signal being determined based on at least one of the vertical synchronization mode and the variable refresh rate mode; and compare the second timing signal with the first timing signal to obtain the output verification result.

[0189] In some embodiments, the configuration information comprises at least one of a display stream compression mode and a YUV mode; the output of the first DUT and the timing model further comprises image data; and the apparatus further comprises a data processing module. The data processing module is further configured to input the at least one video frame and the configuration information into the timing model to obtain the first image data, the first image data being obtained based on processing of the at least one video frame, and a processing manner of the first image data being determined based on at least one of the display stream compression mode and the YUV mode.

[0190] In some embodiments, the timing signal comprises at least one of: a field synchronization signal; a field front porch signal; a field back porch signal; a field active signal; a line synchronization signal; a line front porch signal; a line active signal; a line back porch signal; and a data packet.

[0191] In some embodiments, the configuration model is further configured to generate an interrupt signal of the first DUT.

[0192] The configuration module is further configured to, in response to an interrupt verification operation on the first DUT, input the interrupt signal to the first DUT in a process of inputting the first input stimulus to the first DUT, and obtain interrupt reporting information of the first DUT, the interrupt reporting information being used to verify an interrupt reporting behavior of the first DUT.

[0193] It should be noted that the apparatus provided in the above embodiments is only used as an example to illustrate the division of the above functional modules, and in actual applications, the above functions can be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the above described functions. In addition, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process is described in detail in the method embodiments, which will not be repeated here.

[0194] Figure 11 A structural schematic diagram of a computer device provided in an example embodiment of the present application is shown.

[0195] The computer device 800 includes a central processing unit (CPU) 801, a system memory 804, including a random access memory (RAM) 802 and a read-only memory (ROM) 803, and a system bus 805 that couples the system memory 804 to the central processing unit 801. The computer device 800 also includes an input / output system 806 that helps transfer information between the various devices within the computer device, and a mass storage device 807 for storing an operating system 813, application programs 814, and other program modules 815.

[0196] The input / output system 806 includes a display 808 for displaying information and an input device 809, such as a mouse, keyboard, or the like, for inputting information into the computer device. Both the display 808 and the input device 809 are connected to the central processing unit 801 through an input / output controller 810 that is connected to the system bus 805. The input / output system 806 can also include the input / output controller 810 for receiving and processing input from a number of other devices, such as a keyboard, mouse, or electronic stylus. Similarly, the input / output controller 810 provides output to a display screen, printer, or other type of output device.

[0197] The mass storage device 807 is connected to the central processing unit 801 through a mass storage controller (not shown) that is connected to the system bus 805. The mass storage device 807 and its associated computer-readable storage media provide non-volatile storage for the computer device 800. That is, the mass storage device 807 can include a computer- readable storage medium (not shown) such as a hard disk or a compact disc read-only memory (CD-ROM) drive.

[0198] Without loss of generality, the computer readable storage medium can include computer storage medium and communication medium. The computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable storage instructions, data structures, program modules or other data. The computer storage medium includes RAM, ROM, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other solid state storage technology, CD-ROM, digital versatile disc (DVD) or other optical storage, magnetic cassette, magnetic tape, disk storage or other magnetic storage device. Of course, those skilled in the art can know that the computer storage medium is not limited to the above several. The system memory 804 and the mass storage device 807 described above can be collectively referred to as memory.

[0199] The memory stores one or more programs configured to be executed by the one or more central processing units 801, and the one or more programs contain instructions for implementing the above method embodiments, and the central processing unit 801 executes the one or more programs to implement the method provided by each of the above method embodiments.

[0200] According to various embodiments of the present application, the computer device 800 can also be connected to a remote computer device on a network through a network such as the Internet. That is, the computer device 800 can be connected to a network 812 through a network interface unit 811 connected to the system bus 805, or can be connected to other types of networks or remote computer device systems (not shown) using the network interface unit 811.

[0201] The memory also includes one or more programs stored in the memory, and the one or more programs contain steps performed by the computer device in the method provided by the embodiments of the present application.

[0202] In exemplary embodiments, the present application provides a chip including at least one of programmable logic circuit and program instructions, when the chip is running on a computer device, for implementing the timing verification method provided by the above method embodiments.

[0203] In an exemplary embodiment, a non-transitory computer readable storage medium is also provided, having stored thereon a computer program which, when executed by a processor, implements the timing verification method described above.

[0204] In an exemplary embodiment, a computer program product is also provided which, when executed by a processor, implements the timing verification method described above.

[0205] It should be understood that "a plurality of" as referred herein means two or more. The character " / " generally represents a "or" relationship between the objects before and after it. In addition, the step numbers described herein only exemplarily show a possible execution order between the steps, in some other embodiments, the steps described above can also be executed in a different order from the numbers, such as two different numbered steps are executed simultaneously, or two different numbered steps are executed in an order opposite to the illustration, which is not limited by the embodiments of the present application.

[0206] The above only describes optional embodiments of the present application, and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method of timing verification, characterized by, The method is executed by a computer device deployed with a verification environment, the verification environment is used for timing verification of at least one DUT to be tested, the at least one DUT is used for outputting a timing signal according to image configuration information, the verification environment includes a timing model and a configuration model, the timing model is used for simulating a working process of a first DUT, the configuration model is used for determining configuration information, the configuration information is used for indicating at least one of an input and an output of the timing model, the configuration information includes a working mode, the working mode is used for indicating that the output of the timing model is image configuration information or a timing signal; the method comprises: Obtaining at least one video frame from a data source; In the case that the first DUT accesses the verification environment, inputting the at least one video frame into the verification environment in response to a verification operation for the first DUT, obtaining a timing verification result of the first DUT output by the verification environment; Wherein, the timing verification result includes an input verification result and an output verification result, the input verification result is determined in the case that the configuration information indicates a second working mode, the second working mode is used for indicating that the output of the timing model is the image configuration information, the output verification result is determined in the case that the configuration information indicates a first working mode, the first working mode is used for indicating that the output of the timing model is the timing signal.

2. The method of claim 1, wherein, The method further comprises: In the case that the first DUT accesses the verification environment, inputting the at least one video frame into the verification environment in response to a verification operation for the first DUT, obtaining a timing verification result of the first DUT output by the verification environment; In the case that the first DUT accesses the verification environment, inputting the at least one video frame into the verification environment in response to a verification operation for the first DUT, generating a first input stimulus; Inputting the first input stimulus into the first DUT, obtaining a first timing signal output by the first DUT; 3. The method of claim 2, wherein, Inputting at least one of the first input stimulus and the first timing signal into the timing model, obtaining the timing verification result. The method further comprises: Inputting the first input stimulus into the timing model, obtaining a second timing signal; comparing the second timing signal with the first timing signal, obtaining the output verification result; 4. The method of claim 3, wherein, Inputting the first timing signal into the timing model, obtaining image configuration information; comparing the image configuration information with the first input stimulus, obtaining the input verification result.

5. The method of claim 2, wherein, The timing model is calculated based on a video timing protocol. The input of the timing model further includes at least one of the following: a synchronization clock; a start signal; 6. The method according to any one of claims 2 to 5, characterized in that, The output of the timing model further includes image data. The method further comprises: In a case that the first DUT accesses the verification environment, the configuration model acquires a configuration signal from the data source in response to a verification operation for the first DUT, and generates the configuration information; The inputting of the at least one of the first input stimulus and the first timing signal and the configuration information into the timing model to obtain the timing verification result comprises: The inputting of the at least one of the first input stimulus and the first timing signal and the configuration information into the timing model to obtain the timing verification result comprises:

7. The method of claim 6, wherein, The inputting of the at least one of the first input stimulus and the first timing signal and the configuration information into the timing model to obtain the timing verification result comprises: In a case that the configuration information indicates a first working mode, the first input stimulus and the configuration information are input into the timing model to obtain the output verification result, the first working mode being used to indicate that an output of the timing model is the timing signal; In a case that the configuration information indicates a second working mode, the first timing signal and the configuration information are input into the timing model to obtain the input verification result, the second working mode being used to indicate that the output of the timing model is the image configuration information.

8. The method of claim 6, wherein, The configuration information comprises a timing selection signal, the timing selection signal being used to indicate a timing signal input into or output from the timing model; The inputting of the at least one of the first input stimulus and the first timing signal and the configuration information into the timing model to obtain the timing verification result comprises: The first input stimulus and the configuration information are input into the timing model to obtain a second timing signal, the second timing signal comprising a timing signal indicated by the configuration information; the second timing signal and the first timing signal are compared to obtain the output verification result; Or, a timing selection signal in the configuration information is determined based on the first timing signal; the first timing signal and the configuration information are input into the timing model to obtain the input verification result.

9. The method of claim 6, wherein, The configuration information comprises at least one of a vertical synchronization mode and a variable refresh rate mode; The inputting of the at least one of the first input stimulus and the first timing signal and the configuration information into the timing model to obtain the timing verification result comprises: The first input stimulus and the configuration information are input into the timing model to obtain a second timing signal, a sampling time of the second timing signal being determined based on at least one of the vertical synchronization mode and the variable refresh rate mode; the second timing signal and the first timing signal are compared to obtain the output verification result.

10. The method of claim 6, wherein, The configuration information comprises at least one of a display stream compression mode and a YUV mode; the output of the first DUT and the timing model further comprises image data; The method further comprises: inputting the at least one video frame and the configuration information into the timing model to obtain first image data, the first image data being processed based on the at least one video frame, and a processing manner of the first image data being determined based on at least one of the display stream compression mode and the YUV mode.

11. The method of claim 6, wherein, The configuration model is further configured to generate an interrupt signal of the first DUT. The method further comprises: In a case where the first DUT accesses the verification environment, in response to an interrupt verification operation for the first DUT, the interrupt signal is input to the first DUT in a process of inputting the first input stimulus to the first DUT, and interrupt reporting information of the first DUT is acquired, the interrupt reporting information being used to verify an interrupt reporting behavior of the first DUT.

12. The method according to any one of claims 1 to 5, characterized in that, The timing signal comprises at least one of: a field synchronization signal, a field front porch signal, a field back porch signal, a field valid signal, a line synchronization signal, a line front porch signal, a line valid signal, a line back porch signal, and a data packet.

13. A timing verification apparatus, characterized by comprising: The device comprises a verification environment configured to perform timing verification on at least one DUT (DUT: Device Under Test), the at least one DUT being configured to output a timing signal according to image configuration information, the verification environment comprising a timing model and a configuration model, the timing model being configured to simulate a working process of a first DUT, and the configuration model being configured to determine configuration information, the configuration information being configured to indicate at least one of input and output of the timing model, the configuration information comprising a working mode, the working mode being configured to indicate that the output of the timing model is image configuration information or a timing signal; and the device comprises: an acquisition module configured to acquire at least one video frame from a data source; a verification module configured to, in a case where the first DUT accesses the verification environment, in response to a verification operation for the first DUT, input the at least one video frame to the verification environment to obtain a timing verification result of the first DUT output by the verification environment; wherein the timing verification result comprises an input verification result and an output verification result, the input verification result being determined in a case where the configuration information indicates a second working mode, the second working mode being configured to indicate that the output of the timing model is the image configuration information, and the output verification result being determined in a case where the configuration information indicates a first working mode, the first working mode being configured to indicate that the output of the timing model is the timing signal.

14. A computer device, comprising: The computer device comprises a processor and a memory, the memory storing at least one program; and the processor is configured to execute the at least one program in the memory to implement the timing verification method according to any one of claims 1 to 12.

15. A computer readable storage medium, characterized in that, The computer-readable storage medium stores executable instructions, the executable instructions being loaded and executed by a processor to implement the timing verification method according to any one of claims 1 to 12.

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