A current model and parameter extraction method for field effect transistors

Abstract

The application discloses a current model and a parameter extraction method of a field effect transistor, and comprises the following steps: constructing a current model of the field effect transistor; and extracting parameters based on the current model of the field effect transistor. DS The application can represent linear or super-linear (non-linear) behaviors that may occur at low V DS The application can also represent channel length modulation effects that may occur at high V The application can also represent different gate-source voltage power law parameter behaviors of the current of the transistor in the above two cases.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, and particularly relates to a current model and parameter extraction method for a field-effect transistor. Background Technology

[0002] In the integrated circuit design process, calling up the transistor device model is the first step in circuit simulation. Establishing an accurate transistor model helps in the functional evaluation and optimization of the overall performance of the integrated circuit and its system.

[0003] Thin-film transistors (TFTs) are a type of field-effect transistor. Currently, the RPI model [Silvaco, SPICE Models Manual; Cadence, Virtuoso Simulator Components and Device Models Reference] is widely used in commercial EDA software for TFT current models. The RPI model combines the current models in the linear and saturation regions and accounts for the effect of junction resistance. The RPI model can characterize the transistor's output characteristics at high voltages. DS The channel length modulation effect that may occur at low V can also characterize the transistor output characteristics at low V. DS It may exhibit linear behavior at low V, but cannot characterize it at low V. DS The superlinear (nonlinear) behavior that may occur at low V cannot be characterized. DS and high V DS These two scenarios may exhibit different gate-source voltage power-law parameter characteristics. To characterize the transistor output characteristics at low V... DS The superlinear (nonlinear) behavior that may occur during this process, and the successor to the RPI model, B. The research group introduced V DS The relevant junction resistance R C0 exp(-ηV DS A modified RPI model was proposed [H. Cortes-Ordonez, et al. IEEE TED 2020, 67(12): 5685-5692, DOI: 10.1109 / TED.2020.3032082]. To a certain extent, this modified RPI model can characterize the transistor output characteristics at high V... DS The channel length modulation effect that may occur at low V can also characterize the transistor output characteristics at low V. DS The linear or superlinear (nonlinear) behavior that may occur at low V values. However, there are still three limitations: (1) In order to characterize the transistor output characteristics at low V values. DS The linear or superlinear (nonlinear) behavior that may occur at time is introduced with respect to V. DS The relevant junction resistance RC0 exp(-ηV DS This is reasonable. However, as is well known, in high V... DS If the channel length modulation effect is ignored (i.e., λ = 0), the transistor current has reached saturation, and the transistor current should be in line with V. DS Irrelevant. Therefore, in high V DS At that time, the introduction of V DS The relevant junction resistance R C0 exp(-ηV DS (1) This is unreasonable. (2) In order to characterize the transistor output characteristics at high V DS The channel length modulation effect that may occur at this time is introduced by introducing the channel length modulation term 1+λV. DS That's reasonable. However, as we all know, in low V... DS At this time, there is no channel length modulation effect in the transistor. Therefore, at low V DS At that time, the channel length modulation effect term 1+λV is introduced. DS This is unreasonable. (3) Corresponding to low V DS and high V DS In both cases, the model uses the same gate-source voltage power-law parameter γ. However, the transistor current may exhibit different gate-source voltage power-law parameter behaviors in the two cases, and the model cannot characterize this behavior of the transistor current. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention proposes a current model and parameter extraction method for field-effect transistors. The proposed model can characterize the transistor's output characteristics at low V... DS The linear or superlinear (nonlinear) behavior that may occur at high V values ​​can also characterize the transistor output characteristics at high V values. DS The channel length modulation effect that may occur can also characterize the different gate-source voltage power-law parameter characteristics of the transistor current in the two cases mentioned above.

[0005] To achieve the above objectives, the present invention provides a current model and parameter extraction method for a field-effect transistor, comprising:

[0006] Construct a current model for a field-effect transistor;

[0007] Parameters are extracted based on the current model of the field-effect transistor.

[0008] Optionally, the current model for constructing a field-effect transistor includes:

[0009] First, the transistor is at a low V DS and high V DSIn these two cases, separate current models are established, and then they are merged to form a unified current model.

[0010] In low V DS When introducing the power-law parameter γ L And β, the current model is

[0011]

[0012] and

[0013]

[0014] Where μ 0L For low V DS Carrier mobility pre-factor at time γ L For low V DS Power-law parameters of gate-source voltage at time;

[0015] Substituting equation (2) into equation (1), we get

[0016]

[0017] In high V DS When introducing the power-law parameter γ S And the channel length modulation parameter λ, the current model is as follows

[0018] I DS-S =f S ×(1+λV DS (4)

[0019] and

[0020]

[0021] Where μ 0S For high V DS Carrier mobility pre-factor at time γ S For high V DS Power-law parameters of gate-source voltage at time;

[0022] Substituting equation (5) into equation (4), we get

[0023]

[0024] Applying the function that takes the minimum value to equations (3) and (6), we obtain the result for high V. DS and low V DS Simultaneously effective current model,

[0025]

[0026] Where m is the connection I DS-L and I DS-SParameters;

[0027] Substituting equations (3) and (6) into equation (7), equation (7) is rearranged as follows:

[0028]

[0029] or

[0030]

[0031] Technical advantages of this invention: This invention discloses a current model and parameter extraction method for a field-effect transistor, which can characterize the transistor's output characteristics at low V... DS The linear or superlinear (nonlinear) behavior that may occur at high V values ​​can also characterize the transistor output characteristics at high V values. DS The channel length modulation effect that may occur can also characterize the different gate-source voltage power-law parameter characteristics of the transistor current in the two cases mentioned above. Attached Figure Description

[0032] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0033] Figure 1 In this embodiment of the invention, the channel length L is 50 μm, and the offset length L between the drain and source ends is... offset The output characteristics of amorphous InGaZnO thin-film transistors with diameters of (a) 10 μm and (b) 2 μm are shown respectively. The experimental data are compared with the calculation results of Equation (17), where (a) the offset length L offset (b) Offset length L is 10 μm. offset It is 2μm;

[0034] Figure 2 In this embodiment of the invention, the channel length L is 5 μm, and the offset length L between the drain and source ends is... offset The output characteristics of amorphous InGaZnO thin-film transistors with diameters of (a) 10 μm and (b) 2 μm are shown respectively. The experimental data are compared with the calculation results of Equation (17), where (a) the offset length L offset (b) Offset length L is 10 μm. offset It is 2μm;

[0035] Figure 3 In this embodiment of the invention, the channel length L is 200 μm and the drain offset length L offset The output characteristics of a 100μm amorphous InGaZnO thin film transistor are compared with experimental data and the calculation results of Equation (17);

[0036] Figure 4 For the embodiment f of the present invention S and f L With V GS The change, where (a) is f S (b) is f L ;

[0037] Figure 5 In this embodiment of the invention, the channel length L is 200 μm and the drain offset length L offset The output characteristics of a 100μm amorphous InGaZnO thin film transistor are compared with experimental data and the calculation results of Equation (8);

[0038] Figure 6 This is a flowchart illustrating a current model and parameter extraction method for a field-effect transistor according to an embodiment of the present invention. Detailed Implementation

[0039] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0040] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0041] In the integrated circuit design process, calling up the transistor device model is the first step in circuit simulation. Establishing an accurate transistor model helps in the functional evaluation and optimization of the overall performance of the integrated circuit and its system.

[0042] The typical current model applicable to general field-effect transistors (taking N-channel field-effect transistors as an example) is shown below:

[0043] When V DS <V GS -V TH When the transistor operates in the linear region, the transistor current (the current flowing from the drain to the source) is modeled as follows:

[0044]

[0045] When V DS <<V GS -V TH When the transistor operates in the deep linear region, we can obtain from equation (1) that...

[0046]

[0047] When VDS ≥V GS -V TH When the transistor operates in the saturation region, the current model of the transistor is:

[0048]

[0049] Where μ is the carrier mobility, which is a constant; C i V is the gate insulation capacitance per unit area; W and L are the channel width and channel length of the transistor, respectively; V TH V is the threshold voltage of the transistor. GS V is the voltage applied between the gate and source terminals of a transistor, i.e., the gate-source voltage; DS This is the voltage applied between the drain and source terminals of the transistor, i.e., the drain-source voltage.

[0050] Thin-film transistors (TFTs) are a type of field-effect transistor. In terms of device modeling, TFTs differ from conventional field-effect transistors in that their carrier mobility is typically not constant.

[0051] A typical current model for a thin-film transistor (taking an N-channel thin-film transistor as an example) is shown below:

[0052] When V DS <V GS -V TH When the transistor operates in the linear region, the current model of the transistor is:

[0053]

[0054] When V DS <<V GS -V TH When the transistor operates in the deep linear region, we can obtain from equation (4) that...

[0055]

[0056] When V DS ≥V GS -V TH When the transistor operates in the saturation region, the current model of the transistor is:

[0057]

[0058] Where μ0 is the pre-factor of carrier mobility; γ is the power-law parameter of gate-source voltage.

[0059] If μ0 = μ and γ = 0, equations (4), (5), and (6) will be simplified to equations (1), (2), and (3).

[0060] Currently, the current model for thin-film transistors widely used in commercial EDA software is the RPI model [Silvaco, SPICE Models Manual; Cadence, Virtuoso Simulator Components and DeviceModels Reference]:

[0061]

[0062] Where λ is the channel length modulation coefficient; R C α is the junction resistance, which is a constant; α is the saturation drain-source voltage V. DSSAT The parameter, V DSSAT =α(V GS -V TH ); m is the connection to V DS and α(V GS -V TH The parameters of ).

[0063] As can be seen from equation (7), the RPI model combines the current model (5) in the deep linear region and the current model (6) in the saturation region, and takes into account the effect of junction resistance. Equation (7) can characterize the transistor output characteristics at high V. DS The channel length modulation effect that may occur at low V can also characterize the transistor output characteristics at low V. DS It may exhibit linear behavior at low V, but cannot characterize it at low V. DS Superlinear (nonlinear) behavior may occur.

[0064] To characterize the transistor output characteristics at low V DS The superlinear (nonlinear) behavior that may occur can be reported in the literature [H. Cortes-Ordonez, et al. IEEE TED 2020, 67(12): 5685-5692, DOI: 10.1109 / TED.2020.3032082], which is the successor of the RPI model B. The research group introduced V DS The relevant junction resistance R C0 exp(-ηV DS An improved RPI model was proposed.

[0065]

[0066] Where R C0 And η are respectively related to V DS The relevant junction resistance preconditions and exponential parameters.

[0067] If R C0 =RC, η=0, and VDS The relevant junction resistance R C0 exp(-ηV DS The junction resistance R will become a constant. C Equation (8) will become equation (7).

[0068] In low V DS When the transistor operates in the deep linear region, we can obtain from equation (8) that...

[0069]

[0070] In high V DS When the transistor is in the saturation region, we can obtain from equation (8) that...

[0071]

[0072] If R C0 =0, λ=0, Equations (9) and (10) will become equations (5) and (6).

[0073] As reported in the literature [H. Cortes-Ordonez, et al. IEEE TED 2020, 67(12): 5685-5692, DOI: 10.1109 / TED.2020.3032082], to a certain extent, equation (8) can characterize the transistor output characteristics at high V. DS The channel length modulation effect that may occur at low V can also characterize the transistor output characteristics at low V. DS The linear or superlinear (nonlinear) behavior that may occur.

[0074] However, by analyzing equations (9) and (10), it can be found that equation (8) still has three limitations:

[0075] 1. In equation (9), in order to characterize the transistor output characteristics at low V DS The linear or superlinear (nonlinear) behavior that may occur at time is introduced with respect to V. DS The relevant junction resistance R C0 exp(-ηV DS This is reasonable. However, as is well known, in high V... DS If the channel length modulation effect is ignored (i.e., λ = 0), the transistor current has reached saturation. At this point, the transistor current should be equal to V. DS It is irrelevant. Therefore, in equation (10), we introduce a relationship with V. DS The relevant junction resistance R C0 exp(-ηV DS This is unreasonable.

[0076] 2. In equation (10), in order to characterize the transistor output characteristics at high V DS The channel length modulation effect that may occur at this time is introduced by introducing the channel length modulation term 1+λV. DS That's reasonable. However, as we all know, in low V... DS At this time, there is no channel length modulation effect in the transistor. Therefore, in equation (9), the channel length modulation effect term 1+λV is introduced. DS That is unreasonable.

[0077] 3. Corresponding to low V DS and high V DS In both cases, equations (9) and (10) use the same gate-source voltage power-law parameter γ. However, the transistor current may exhibit different gate-source voltage power-law parameter behaviors in the two cases mentioned above, and equation (8) cannot characterize this behavior of the transistor current.

[0078] like Figure 6 As shown, this embodiment provides a current model and parameter extraction method for a field-effect transistor, including:

[0079] First, the transistor is at a low V DS and high V DS In these two cases, separate current models are established, and then they are merged to form a unified current model.

[0080] In low V DS When introducing the power-law parameter γ L And β, the current model is

[0081]

[0082] and

[0083]

[0084] Where μ 0L For low V DS Carrier mobility pre-factor at time γ L For low V DS The power-law parameters of the gate-source voltage at that time.

[0085] Substituting equation (12) into equation (11), we get

[0086]

[0087] 2. In high V DS When introducing the power-law parameter γ S And the channel length modulation parameter λ, the current model is as follows

[0088] I DS-S =f S ×(1+λVDS (14)

[0089] and

[0090]

[0091] Where μ 0S For high V DS Carrier mobility pre-factor at time γ S For high V DS The power-law parameters of the gate-source voltage at that time.

[0092] Substituting equation (15) into equation (14), we get

[0093]

[0094] Applying the function that takes the minimum value to equations (13) and (16), we obtain the result for high V. DS and low V DS Simultaneously effective current model,

[0095]

[0096] Where m is the connection I DS-L and I DS-S The parameters.

[0097] Substituting equations (13) and (16) into equation (17), equation (17) is rearranged as follows:

[0098]

[0099] or

[0100]

[0101] Comparing equation (18) with equation (8), it can be seen that equation (18) and equation (8) are different.

[0102] In the current model (17) proposed in this invention, for high V DS Valid formula (13)I DS-L and for low V DS Valid formula (16)I DS-S They are given separately. Equation (17) can overcome the limitations of equation (8). The advantages of equation (17) are reflected in three aspects.

[0103] 1. In equation (13), in order to characterize the transistor output characteristics at low V DS The linear or superlinear (nonlinear) behavior that may occur at time is introduced with respect to V. DS Related The option is reasonable. It is well known that in high V... DSIf the channel length modulation effect is ignored (i.e., λ = 0), after the drain-source current reaches saturation, the transistor current should be related to V. DS It is irrelevant. Therefore, in equation (16), no relation to V is introduced. DS Related This is also reasonable.

[0104] 2. In equation (16), in order to characterize the transistor output characteristics at high V DS The channel length modulation effect that may occur at this time is introduced by introducing the channel length modulation term 1+λV. DS That's reasonable. However, as we all know, in low V... DS At this time, there is no channel length modulation effect in the transistor. Therefore, in equation (13), the channel length modulation term 1+λV is not introduced. DS This is also reasonable.

[0105] 3. In equations (13) and (16), two gate-source voltage power-law parameters γ are introduced respectively. L and γ S The transistor current may exhibit different power-law parameter characteristics of the gate-source voltage in the two cases mentioned above, and Equation (17) can characterize this behavior of the transistor current.

[0106] Next, experimental data from thin-film transistors reported in [J. Jeong et al. Semicond. Sci. Technol. 2013 28(2): 025015, DOI: 10.1088 / 0268-1242 / 28 / 2 / 025015] and [X. Li et al. IEEE EDL. 2020 41(3): 405-408, DOI: 10.1109 / LED. 2020.2970434] were used to verify Equation (17). The thin-film transistors reported in these two papers are high-voltage amorphous InGaZnO thin-film transistors, which have a drain-source offset structure, and the output characteristics of the transistor are at low V DS It exhibits linear or superlinear (nonlinear) behavior at high V. DS This exhibits a channel length modulation effect. For example... Figure 1 The channel length L shown is 50 μm, and the offset length L between the drain and source ends is... offset The output characteristics of amorphous InGaZnO thin-film transistors (a) with a diameter of 10 μm and (b) with a diameter of 2 μm are shown, and the experimental data are compared with the results calculated by equation (17). Figure 2 The channel length L shown is 5 μm, and the offset length L between the drain and source ends is... offset The output characteristics of amorphous InGaZnO thin film transistors with diameters of (a) 10 μm and (b) 2 μm are shown respectively. The experimental data are compared with the calculation results of Equation (17). Figure 1 The parameter values ​​used for calculation are shown in Table 1. Figure 2 The parameter values ​​used for calculation are shown in Table 2.

[0107] Table 1

[0108]

[0109] Table 2

[0110]

[0111] like Figure 1 and Figure 2 As shown, the current model (17) proposed in this invention can not only characterize the transistor output characteristics at low V DS The linear or superlinear (nonlinear) behavior that occurs at high V values ​​can characterize the transistor output characteristics at high V values. DS The channel length modulation effect that occurs at that time. For example, Figure 3 The channel length L shown is 200 μm, and the drain offset length L is... offset The output characteristics of a 100μm amorphous InGaZnO thin film transistor are compared with experimental data and the calculation results of equation (17). Figure 3 The parameter values ​​used for calculation are shown in Table 3. Figure 3 As shown, the current model (17) proposed in this invention can not only characterize the transistor output characteristics at low V DS The superlinear (nonlinear) behavior that occurs at high V values ​​can characterize the transistor output characteristics at high V values. DS The channel length modulation effect that occurs at that time.

[0112] Table 3

[0113]

[0114] by Figure 3 For example, in the current model (17) proposed in this invention, the process for determining the parameter values ​​is as follows:

[0115] 1. Use equation (14) to fit the data. Figure 3 Chinese V GS =30V at high V DS Experimental data at that time were used to determine the value of λ and extract f. S In V GS The value at 30V.

[0116] 2. Use equation (14) to fit the equation. Figure 3 Chinese V GS From 26V to 6V at high V DS Experimental data at time, extract f S In the above different V GSThe value at time. Extract f. S The values ​​from 30V to 6V are plotted on Figure 4 In (a), a hollow circle symbol is used. Equation (15) is used for fitting. Figure 4 The hollow circle symbol in (a) is used to determine V. TH μ S and γ S The value of .

[0117] 3. Use equation (11) to fit the data. Figure 3 Chinese V GS =30V at low V DS Experimental data at that time were used to determine the value of β, and f was extracted simultaneously. L In V GS The value at 30V.

[0118] 4. Use equation (11) to fit the data. Figure 3 Chinese V GS From 26V to 6V at low V DS Experimental data at time, extract f L In the above different V GS The value at time. Extract f. L The values ​​from 30V to 6V are plotted on Figure 4 In (b), a hollow circle symbol is used. Equation (12) is used for fitting. Figure 4 The hollow circle symbol in (b) is used to determine μ. L and γ L The value of .

[0119] 5. Use equation (17) to fit the equation. Figure 3 Chinese V GS =30V at medium V DS The experimental data at that time were used to determine the value of m.

[0120] like Figure 5 The channel length L shown is 200 μm, and the drain offset length L is... offset The output characteristics of a 100μm amorphous InGaZnO thin film transistor are compared with experimental data and the calculation results of equation (8). Figure 5 The parameter values ​​used for calculation are shown in Table 5.

[0121] Table 5

[0122] parameter value( Figure 4 ) unit W 60 μm L 200 μm <![CDATA[C i ]]> 10.3 <![CDATA[nF / cm 2 ]]> <![CDATA[V TH ]]> -0.5 V <![CDATA[μ0]]> <![CDATA[1.12×10 -1 ]]> <![CDATA[cm 2 V -(1+γ) s -1 ]]> α 16.5 - <![CDATA[R C0 ]]> <![CDATA[1.5×10 9 ]]> Ω η <![CDATA[1.3×10 -2 ]]> <![CDATA[V -1 ]]> γ 0.2 - λ <![CDATA[7×10 -5 ]]> <![CDATA[V -1 ]]> m 30 -

[0123] Bundle Figure 5 and Figure 3 By comparison, the advantages of the model (17) proposed in this invention can be seen: such as Figure 3 As shown, equation (17) can characterize the transistor at low V. DS and high V DSAt different times, in different V GS Experimental data for the period (30V to 6V); such as Figure 5 As shown, equation (8) cannot characterize the transistor at low V. DS At different times, in different V GS The experimental data (from 26V to 6V) is due to... Figure 3 As shown in Table 3, in equation (17) for low V DS and high V DS In these two cases, two gate-source voltage power-law parameters γ are introduced respectively. L =0.55 and γ S =0.2; for Figure 5 As shown in Table 5, in equation (8) for low V DS and high V DS Only one gate-source voltage power-law parameter γ = 0.2 was introduced.

[0124] The above are merely preferred embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A current model and parameter extraction method for a field-effect transistor, characterized in that, include: Construct a current model for a field-effect transistor; Parameters are extracted based on the current model of the field-effect transistor; The current model for constructing a field-effect transistor includes: First, the transistor is at a low V DS and high V DS In these two cases, separate current models are established, and then they are merged to form a unified current model. In low V DS When introducing the power-law parameter γ L And β, the current model is and Where μ 0L For low V DS Carrier mobility pre-factor at time γ L For low V DS Power-law parameters of gate-source voltage at time; Substituting equation (2) into equation (1), we get In high V DS When introducing the power-law parameter γ S And the channel length modulation parameter λ, the current model is as follows I DS-S =f S ×(1+λV DS ) (4) and Where μ 0S For high V DS Carrier mobility pre-factor at time γ S For high V DS Power-law parameters of gate-source voltage at time; Substituting equation (5) into equation (4), we get Applying the function that takes the minimum value to equations (3) and (6), we obtain the result for high V. DS and low V DS Simultaneously effective current model, Where m is the connection I DS-L and I DS-S Parameters; Substituting equations (3) and (6) into equation (7), equation (7) is rearranged as follows: or

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