Display device and driving method thereof

Abstract

There is provided a display device including a first pixel connected to a first gate line and a first reference line, a second pixel connected to the first gate line and a second reference line, a third pixel connected to the second gate line and the second reference line, and a fourth pixel connected to the second gate line and the first reference line, the first pixel and the third pixel each include four sub-pixels, and the second pixel and the fourth pixel each include three sub-pixels.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2023-0192932, filed on December 27, 2023, which is incorporated herein by reference in its entirety as if fully set forth herein. Technical Field

[0002] The present disclosure relates to a display device and a driving method thereof. Background Art

[0003] With the development of information technology, the market for display devices as a communication medium between users and information is growing. Accordingly, display devices such as light-emitting display (LED) devices, quantum dot display (QDD) devices, and liquid crystal display (LCD) devices are increasingly used.

[0004] The above display device includes a display panel having sub-pixels, a driver that outputs a driving signal for driving the display panel, and a power supply that generates power to be provided to the display panel or the driver.

[0005] In a display device, when driving signals such as a scan signal and a data signal are provided to sub-pixels formed in a display panel, the selected sub-pixels transmit light or emit light directly, thereby displaying an image. Summary of the Invention

[0006] Accordingly, the present disclosure relates to a display device and a driving method thereof that substantially eliminate one or more problems caused by limitations and disadvantages of the related art.

[0007] An object of the present disclosure is to improve (offset) a deviation problem that may occur on a display panel, enhance display quality by minimizing flicker or image interference, and implement a display panel having a high aperture ratio and a high PPI (pixels per inch) to improve lifespan without burn-in.

[0008] Additional advantages, objects, and features of the present disclosure will be partially set forth in the description below, and will partially become apparent to those of ordinary skill in the art upon examination of the following, or may be learned from practice of the present disclosure. The objects and other advantages of the present disclosure may be realized and obtained by the structures particularly pointed out in the specification and claims and the drawings.

[0009] To achieve these objects and other advantages and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, a display device includes a first pixel connected to a first gate line and a first reference line, a second pixel connected to the first gate line and a second reference line, a third pixel connected to a second gate line and the second reference line, and a fourth pixel connected to the second gate line and the first reference line, wherein the first pixel and the third pixel each include four sub-pixels, and the second pixel and the fourth pixel each include three sub-pixels.

[0010] The first pixel may include a first connection line connecting the four sub-pixels to the first reference line, the second pixel may include a second connection line connecting the three sub-pixels to the second reference line, the third pixel may include a first connection line connecting the four sub-pixels to the second reference line, and the fourth pixel may include a second connection line connecting the three sub-pixels to the first reference line.

[0011] The second connection line may have a length less than that of the first connection line.

[0012] The first pixel and the third pixel may each include a white sub-pixel that emits white light, and the second pixel and the fourth pixel may not include a white sub-pixel.

[0013] The first pixel and the third pixel may each include a first sub-pixel that emits light of a first color, a second sub-pixel that emits light of a second color, a third sub-pixel that emits light of a third color, and a white sub-pixel that emits white light, and the second pixel and the fourth pixel may each include a first sub-pixel that emits light of a first color, a second sub-pixel that emits light of a second color, and a third sub-pixel that emits light of a third color.

[0014] The first sub-pixels of the first pixel and the third pixel and the first sub-pixels of the second pixel and the fourth pixel may emit red light, the second sub-pixels of the first pixel and the third pixel and the second sub-pixels of the second pixel and the fourth pixel may emit green light, and the third sub-pixels of the first pixel and the third pixel and the third sub-pixels of the second pixel and the fourth pixel may emit blue light.

[0015] In another aspect of the present disclosure, a display device includes: a first pixel including a first connection line connecting four sub-pixels on a first gate line to a first reference line; a second pixel including a second connection line connecting three sub-pixels on the first gate line to a second reference line; a third pixel including a first connection line connecting four sub-pixels on a second gate line to the second reference line; and a fourth pixel including a second connection line connecting three sub-pixels on the second gate line to the first reference line.

[0016] The first pixel and the third pixel may each include a first sub-pixel that emits light of a first color, a second sub-pixel that emits light of a second color, a third sub-pixel that emits light of a third color, and a white sub-pixel that emits white light. The second pixel and the fourth pixel may each include a first sub-pixel that emits light of a first color, a second sub-pixel that emits light of a second color, and a third sub-pixel that emits light of a third color.

[0017] In another aspect of the present disclosure, a display device includes a display panel for displaying an image and a driver for driving the display panel. Wherein, the display panel includes a first pixel connected to a first gate line and a first reference line, a second pixel connected to the first gate line and a second reference line, a third pixel connected to a second gate line and the second reference line, and a fourth pixel connected to the second gate line and the first reference line. Wherein, the first pixel and the third pixel each include four sub-pixels, and the second pixel and the fourth pixel each include three sub-pixels.

[0018] In another aspect of the present disclosure, a driving method of a display device is provided. The display device includes a display panel, and the display panel includes a first pixel, a second pixel, a third pixel, and a fourth pixel. The first pixel includes a first connection line connecting four sub-pixels on the first gate line to the first reference line. The second pixel includes a second connection line connecting three sub-pixels on the first gate line to the second reference line. The third pixel includes a first connection line connecting four sub-pixels on the second gate line to the second reference line. The fourth pixel includes a second connection line connecting three sub-pixels on the second gate line to the first reference line. The method includes applying a gate-on voltage overlapping for a certain period of time to the first gate line and the second gate line, obtaining a first sensed value from the first pixel connected to the first reference line and obtaining a second sensed value from the third pixel connected to the second reference line, and compensating the display panel based on the first sensed value and the second sensed value.

[0019] It should be understood that the foregoing summary and the following detailed description of the present disclosure are both exemplary and explanatory, and are intended to provide further explanation of the claimed present disclosure. Description of the Drawings

[0020] The drawings that provide a further understanding of the present disclosure and are incorporated into and constitute a part of this application illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure. In the drawings:

[0021] Figure 1 is a block diagram schematically showing a light-emitting display device;

[0022] Figure 2 is schematically showing Figure 1Configuration diagram of sub-pixels shown in;

[0023] Figure 3 Is a diagram showing a pixel composed of sub-pixels;

[0024] Figure 4 And Figure 5 Is a diagram showing the configuration of a gate-type gate driver in a panel;

[0025] Figure 6 Is a diagram showing an example of the arrangement of a gate-type gate driver in a panel;

[0026] Figure 7 Is a diagram schematically showing sub-pixels and a data driver according to a first example of an embodiment;

[0027] Figure 8 Is a diagram schematically showing sub-pixels and a data driver according to a second example of an embodiment;

[0028] Figure 9 Is a waveform diagram showing a sensing period and a display period according to an embodiment;

[0029] Figure 10 Is a diagram showing in more detail some components included in a data driver according to an embodiment;

[0030] Figure 11 And Figure 12 Is a diagram showing a method of sensing a display panel according to an embodiment;

[0031] Figure 13 Is a diagram showing a display panel of a light-emitting display device and some pixel groups formed therein according to an embodiment;

[0032] Figure 14 Is a diagram showing Figure 13 A diagram of a specific pixel group shown in;

[0033] Figure 15 Is a diagram showing pixels located on one gate line according to an embodiment;

[0034] Figure 16 Is a diagram showing Figure 15 Deviations that may occur between the pixels shown in;

[0035] Figure 17 Is a diagram showing pixels located on two adjacent gate lines according to an embodiment;

[0036] Figure 18 Is a diagram showing Figure 17 Deviations that may occur between the pixels shown in;

[0037] Figure 19It is a diagram showing a display panel implemented according to an experimental example;

[0038] Figure 20 It is a diagram showing the layout of pixels provided in the display panel according to the experimental example;

[0039] Figure 21 It is a diagram showing a display panel implemented according to an embodiment;

[0040] Figure 22 It is a diagram showing the layout of pixels provided in the display panel according to the embodiment;

[0041] Figure 23 and Figure 24 It is a diagram for comparing between the experimental example and the embodiment;

[0042] Figure 25 It is a diagram showing the waveform of a gate signal for driving the display panel according to the experimental example;

[0043] Figure 26 It is a diagram showing Figure 25 the first problem that may occur in the experimental example during the operation based on the gate signal shown;

[0044] Figure 27 It is a diagram showing the second problem that may occur in the experimental example;

[0045] Figure 28 It is a diagram showing the waveform of a gate signal for driving the display panel according to the embodiment;

[0046] Figure 29 It is a diagram showing Figure 28 the embodiment that improves the first problem presented in the experimental example during the operation based on the gate signal shown;

[0047] Figure 30 It is a diagram showing the embodiment that improves the second problem presented in the experimental example;

[0048] Figure 31 It is a diagram showing the first example that can be referred to when implementing pixels according to the embodiment;

[0049] Figure 32 It is a diagram showing the second example that can be referred to when implementing pixels according to the embodiment. Detailed Description

[0050] The display device according to the present disclosure can be implemented as a television system, an image player, a personal computer (PC), a home theater, automotive electronics, a smart phone, etc., but is not limited thereto. The display device according to the present disclosure can be implemented as a light-emitting display (LED) device, a quantum dot display (QDD) device, a liquid crystal display (LCD) device, etc. However, for ease of description, as an example, a light-emitting display device that directly emits light based on an inorganic light-emitting diode or an organic light-emitting diode will be described below.

[0051] Figure 1 is a block diagram schematically showing a light-emitting display device, Figure 2 is schematically showing Figure 1 the configuration diagram of the sub-pixels shown in Figure 3 is a diagram showing a pixel composed of sub-pixels.

[0052] As Figure 1 , Figure 2 and Figure 3 shown, the light-emitting display device may include an image provider 110, a timing controller 120, a gate driver 130, a data driver 140, a display panel 150, a power supply 180, etc.

[0053] The image provider 110 (set-top box or host system) may output various driving signals and an image data signal provided externally or an image data signal stored in an internal memory. The image provider 110 may provide a data signal and various driving signals to the timing controller 120.

[0054] The timing controller 120 may output a gate timing control signal GDC for controlling the operation timing of the gate driver 130, a data timing control signal DDC for controlling the operation timing of the data driver 140, and various synchronization signals. The timing controller 120 may provide the data signal DATA provided from the image provider 110 to the data driver 140 together with the data timing control signal DDC. The timing controller 120 may be implemented in the form of an integrated circuit (IC) and installed on a printed circuit board, but is not limited thereto.

[0055] The gate driver 130 may output a gate signal (or gate voltage) in response to the gate timing control signal GDC provided from the timing controller 120. The gate driver 130 may provide the gate signal to the sub-pixels included in the display panel 150 through gate lines GL1 to GLm. The gate driver 130 may be implemented in the form of an IC, or a gate structure in the panel may be directly formed on the display panel 150, but is not limited thereto.

[0056] The data driver 140 may sample and latch the data signal DATA in response to a data timing control signal DDC provided from the timing controller 120, convert the digital data signal into an analog data voltage based on a gamma reference voltage, and output the analog data voltage. The data driver 140 may provide the data voltage to sub-pixels included in the display panel 150 through data lines DL1 to DLn. The data driver 140 may be implemented in the form of an integrated circuit (IC) and mounted on the display panel 150 or on a printed circuit board, but is not limited thereto.

[0057] The power supply 180 may generate a first power at a high level and a second power at a low level based on an external input voltage provided from the outside. The power supply 180 may output the first power through a first power supply line EVDD and output the second power through a second power supply line EVSS. The power supply 180 may generate and output voltages required to drive the gate driver 130 (e.g., a scan high voltage and a scan low voltage) and voltages required to drive the data driver 140 (e.g., a drain voltage and a semi-drain voltage), as well as the first power and the second power.

[0058] In one embodiment, the display panel 150 includes a plurality of pixels PX, that is, pixels arranged in multiple rows and multiple columns. The display panel 150 may display an image in response to drive signals including a scan signal and a data voltage, a first power, and a second power. Sub-pixels of the display panel 150 may emit light directly. The display panel 150 may be manufactured based on a substrate having rigidity or flexibility (such as glass, silicon, polyimide, etc.). For example, one sub-pixel SP may be connected to a first data line DL1, a first gate line GL1, a first power supply line EVDD, and a second power supply line EVSS and may include a pixel circuit including a switching transistor, a driving transistor, a capacitor, an organic light emitting diode, etc.

[0059] Since the sub-pixel SP in the light-emitting display device emits light directly, its circuit structure is complex. In addition, there are various compensation circuits that compensate not only for the deterioration of the light-emitting organic light emitting diode but also for the deterioration of the driving transistor that provides the driving current required to drive the organic light emitting diode. Therefore, the sub-pixel SP is simply shown in the form of a block.

[0060] The light-emitting pixel may be composed of a red sub-pixel, a green sub-pixel, and a blue sub-pixel, or may be composed of a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. For example, a pixel PX may include a red sub-pixel SP1 connected to a first data line DL1, a white sub-pixel SP2 connected to a second data line DL2, a green sub-pixel SP3 connected to a third data line DL3, and a blue sub-pixel SP4 connected to a fourth data line DL4. Additionally, the red sub-pixel SP1, the white sub-pixel SP2, the green sub-pixel SP3, and the blue sub-pixel SP4 may be commonly connected to a first reference line REF1. The first reference line REF1 may be used to sense the degradation of an element included in one of the red sub-pixel SP1, the white sub-pixel SP2, the green sub-pixel SP3, and the blue sub-pixel SP4, which will be described below.

[0061] Meanwhile, the timing controller 120, the gate driver 130, and the data driver 140 have been described as separate components. However, depending on the implementation method of the light-emitting display device, one or more of the timing controller 120, the gate driver 130, and the data driver 140 may be integrated into a single IC. Additionally, the timing controller 120, the gate driver 130, the data driver 140, the power supply 180, and the display panel 150 are components for displaying an image and may be defined as a display module.

[0062] Additionally, as an example, a pixel PX in which a red sub-pixel SP1, a white sub-pixel SP2, a green sub-pixel SP3, and a blue sub-pixel SP4 are arranged in sequence is shown. However, the arrangement order and direction of the sub-pixels may vary according to the implementation method of the light-emitting display device.

[0063] Figure 4 and Figure 5 is a diagram showing the configuration of a gate-type gate driver in a panel, Figure 6 is a diagram showing an example of the arrangement of a gate-type gate driver in a panel.

[0064] As Figure 4 shown, the gate-type gate driver in the panel may include a shift register 131 and a level shifter 135. The level shifter 135 may generate driving clock signals Clks and a start signal Vst based on signals and voltages output from the timing controller 120 and the power supply 180.

[0065] The shift register 131 operates based on the signals Clks and Vst output from the level shifter 135 and may output gate signals Scan[1] to Scan[m] for turning on or off transistors formed in the display panel. The shift register 131 may be in the form of a thin film on the display panel in the gate structure of the panel.

[0066] As Figure 4 and Figure 5 shown, unlike the shift register 131, the level shifter 135 can be independently formed in the form of an IC, or can be included in the power supply 180. However, this is merely an example and is not limited thereto.

[0067] As Figure 6 shown, in the panel, the shift registers 131a and 131b of the gate-type gate driver in the output gate signals can be disposed in the non-display area NA of the display panel 150. As an example, the shift registers 131a and 131b are disposed in the left and right non-display areas NA of the display panel 150, but the shift registers 131a and 131b can also be disposed in the upper and lower non-display areas NA of the display panel 150, or can be disposed in the display area AA of the display panel 150.

[0068] Figure 7 is a diagram schematically showing a sub-pixel and a data driver according to a first example of an embodiment, Figure 8 is a diagram schematically showing a sub-pixel and a data driver according to a second example of an embodiment, Figure 9 is a waveform diagram showing a sensing period and a display period

[0069] As Figure 7 shown, according to the first example, one sub-pixel SP may include a switching transistor SW, a driving transistor DT, a sensing transistor ST, a capacitor CST, and an organic light-emitting diode OLED.

[0070] The driving transistor DT may include a gate electrode connected to the first electrode of the capacitor CST, a first electrode connected to the first power supply line EVDD, and a second electrode connected to the anode of the organic light-emitting diode OLED. The capacitor CST may have a first electrode connected to the gate electrode of the driving transistor DT and a second electrode connected to the anode of the organic light-emitting diode OLED. The organic light-emitting diode OLED may have an anode connected to the second electrode of the driving transistor DT and a cathode connected to the second power supply line EVSS.

[0071] The switching transistor SW may include a gate electrode connected to the first scan line GL1a included in the first gate line GL1, a first electrode connected to the first data line DL1, and a second electrode connected to the gate electrode of the driving transistor DT. The sensing transistor ST may include a gate electrode connected to the second scan line GL1b included in the first gate line GL1, a first electrode connected to the first reference line VREF1, and a second electrode connected to the anode of the organic light-emitting diode OLED.

[0072] The sensing transistor ST is a compensation circuit that is added to compensate for the degradation (such as threshold voltage degradation, mobility degradation, etc.) of the driving transistor DT or the organic light-emitting diode OLED. The sensing transistor ST can implement physical threshold voltage sensing based on the source follower operation of the driving transistor DT. The sensing transistor ST can operate to obtain a sensing voltage through a sensing node defined between the driving transistor DT and the organic light-emitting diode OLED.

[0073] According to an embodiment, the data driver 140 may include a driving circuit 141 for driving the sub-pixel SP and a sensing circuit 145 for sensing the sub-pixel SP. The driving circuit 141 may be connected to the first data line DL1 through the first data channel DCH1. The driving circuit 141 may output a data voltage Vdata for driving the sub-pixel SP through the first data channel DCH1.

[0074] The sensing circuit 145 may be connected to the first reference line VREF1 through the first sensing channel SCH1. The sensing circuit 145 may obtain a sensing voltage Vsen sensed from the sub-pixel SP through the first sensing channel SCH1. The sensing circuit 145 may obtain the sensing voltage Vsen based on a current sensing method or a voltage sensing method. The sensing circuit 145 may send (transmit) the obtained sensing voltage Vsen to the timing controller so that the degradation of the elements included in the sub-pixel SP can be determined, and degradation compensation can be performed based on the sensing voltage Vsen.

[0075] As Figure 8 shown, according to a second example, the first gate line GL1 may be integrated into one scan line. That is, different from the first example, the first gate line GL1 may not be divided into a first scan line and a second scan line. In this case, the switching transistor SW and the sensing transistor ST are commonly connected to the first gate line GL1, so they can be turned on or off simultaneously.

[0076] As Figure 9 shown, when the light-emitting display device according to an embodiment operates to drive the display panel, it may adopt driving modes corresponding to a first driving period PWR_ON, a second driving period DISPLAY, and a third driving period PWR_OFF, respectively.

[0077] The first driving period PWR_ON may correspond to a driving start period during which power is applied to the display panel. The second driving period DISPLAY may correspond to a panel driving period during which operations such as displaying an image are performed after power is applied to the display panel. The third driving period PWR_OFF may correspond to a driving end period during which the power applied to the display panel is cut off. At the same time, the third driving period PWR_OFF is a period during which the display panel is driven for a specific period while displaying a black image so that a sensing operation of the display panel can be performed. That is, note that during the third driving period PWR_OFF, the power applied to the display panel and the like is not completely cut off to perform the sensing of the display panel.

[0078] The light-emitting display device according to an embodiment may sense the display panel in at least one of the first driving period PWR_ON, the second driving period DISPLAY, and the third driving period PWR_OFF. As an example, in the second driving period DISPLAY, a blanking period BLK included in the vertical synchronization signal Vsync may be defined as a sensing period PSP, and an active period ACT included in the vertical synchronization signal Vsync may be defined as a display period DSP.

[0079] Figure 10 FIG. is a diagram showing in more detail some components included in a data driver according to an embodiment, Figure 11 and Figure 12 FIG. is a diagram showing a method of sensing a display panel according to an embodiment. Hereinafter, as an example, Figure 7 the structure of the sub-pixel SP shown will be described.

[0080] As in the Figure 10 embodiment shown, the driving circuit 141 may include a digital-to-analog converter DAC to output a sensing data voltage, a black data voltage, or a display data voltage through a first data line DL1. The sensing circuit 145 may include a first voltage circuit SPRE, a second voltage circuit RPRE, a sampling circuit SAM, and an analog-to-digital converter ADC to output and sense a voltage through a first reference line VREF1.

[0081] The first voltage circuit SPRE and the second voltage circuit RPRE may perform a voltage output operation to initialize or charge a node or a circuit included in the sub-pixel SP to a specific voltage level. The first voltage circuit SPRE and the second voltage circuit RPRE may respectively include a first reference voltage source VPRES and a second reference voltage source VPRER. The first voltage circuit SPRE may output a first reference voltage based on the first reference voltage source VPRES, and the second voltage circuit RPRE may output a second reference voltage based on the second reference voltage source VPRER. The first reference voltage may be set to a voltage lower than the second reference voltage.

[0082] The sampling circuit SAM may perform a sampling operation to obtain a sense voltage through the first reference line VREF1. For example, the sampling circuit SAM may obtain the sense voltage based on the sense capacitor SCAP from the sense capacitor PCAP formed on the first reference line VREF1.

[0083] The analog-to-digital converter ADC may convert the analog sense voltage obtained by the sampling circuit SAM into a digital sense voltage and output the digital sense voltage. For example, the analog-to-digital converter ADC may convert the analog sense voltage charged in the sense capacitor SCAP into a digital sense voltage and output the digital sense voltage.

[0084] The timing controller 120 may receive a sense voltage (sense data value) from the sensing circuit 145. The timing controller 120 may determine whether the driving transistor DT or the organic light-emitting diode OLED included in the sub-pixel SP has deteriorated based on the sense voltage, and perform an operation for compensating the deterioration.

[0085] As Figure 11 shown, according to the first example, the light-emitting display device may perform a sequential sensing method of performing sensing from the first gate line GL1 to the M-th gate line GLm of the display panel 150. Although Figure 11 an example of sequentially performing sensing starting from the first gate line GL1 which is the top of the display panel 150 is shown, sensing may be performed starting from the M-th gate line GLm which is the bottom of the display panel 150.

[0086] As Figure 12 shown, according to the second example, the light-emitting display device may perform a random sensing method of sensing only the I-th gate line GLi of the display panel 150. Although Figure 12 an example of sensing only the I-th gate line GLi which is one of the specific gate lines is shown, the sensing target may be two or more gate lines.

[0087] Figure 13 is a diagram showing a display panel of a light-emitting display device according to an embodiment and some pixel groups formed therein, Figure 14 is a diagram showing Figure 13 the specific pixel group shown in

[0088] As Figure 13 shown, in the display panel 150 that emits light in a light-emitting display device according to an embodiment, there may be included a first pixel group PX1 and PX3 having four sub-pixels and a second pixel group PX2 and PX4 having three sub-pixels. The first pixel PX1 and the second pixel PX2 are arranged as a first row of pixels, and the third pixel PX3 and the fourth pixel PX4 are arranged as a second row of pixels after the first row of pixels.

[0089] The first pixel groups PX1 and PX3 may include a first pixel PX1 located on one side (e.g., the first side) of the J-th gate line GLj and a third pixel PX3 located on the other side (e.g., the second side) of the K-th gate line GLk. Each of the first pixel PX1 and the third pixel PX3 may include a first sub-pixel SP1 that emits light of a first color, a second sub-pixel SP2 that emits light of a second color, a third sub-pixel SP3 that emits light of a third color, and a white sub-pixel SPW that emits white light. As Figure 13 shown, the white sub-pixels SPW of the first pixel PX1 and the third pixel PX3 are located in the same column of the pixels.

[0090] Although both the first pixel PX1 and the third pixel PX3 include three sub-pixels SP1 to SP3 and one white sub-pixel SPW, they differ in that the first pixel PX1 is connected to a first reference line REF1 and the third pixel PX3 is connected to a second reference line REF2 different from the first reference line REF1. Additionally, the first pixel PX1 may include a first connection line CNT1 for connecting the three sub-pixels SP1 to SP3 and one white sub-pixel SPW to the first reference line REF1, and the third pixel PX3 may also include a first connection line CNT1 for connecting the three sub-pixels SP1 to SP3 and one white sub-pixel SPW to the second reference line REF2. In one embodiment, the length of the first connection line CNT1 of the first pixel PX1 is the same as the length of the first connection line CNT1 of the third pixel PX3.

[0091] The second pixel groups PX2 and PX4 may include a second pixel PX2 located on the other side of the J-th gate line GLj and a fourth pixel PX4 located on one side of the K-th gate line GLk. Each of the second pixel PX2 and the fourth pixel PX4 may include a first sub-pixel SP1′ that emits light of a first color, a second sub-pixel SP2′ that emits light of a second color, and a third sub-pixel SP3′ that emits light of a third color. As Figure 13 shown, the sub-pixels of the second pixel PX2 are in the same row as the sub-pixels of the first pixel PX1, and the sub-pixels of the third pixel PX3 are in the same row as the sub-pixels of the fourth pixel PX4. Thus, the third pixel PX3 and the first pixel PX1 are in different pixel rows, and the second pixel PX2 and the fourth pixel PX4 are in different pixel rows.

[0092] Although both the second pixel PX2 and the fourth pixel PX4 include three sub-pixels SP1' to SP3', they differ from each other in that the second pixel PX2 is connected to the second reference line REF2 and the fourth pixel PX4 is connected to the first reference line REF1. Additionally, the second pixel PX2 may include a second connection line CNT2 for connecting the three sub-pixels SP1' to SP3' to the second reference line REF2, and the fourth pixel PX4 may also include a second connection line CNT2 for connecting the three sub-pixels SP1' to SP3' to the first reference line REF1. In one embodiment, the length of the second connection line CNT2 of the second pixel PX2 is the same as the length of the second connection line CNT2 of the fourth pixel PX4.

[0093] Referring to the above description and Figure 13 , a pixel including four sub-pixels and a pixel including three sub-pixels may be connected to the J-th gate line GLj (the left and right pixels are asymmetrically arranged). Additionally, for the K-th gate line GLk adjacent to the J-th gate line GLj, the pixel positions may be changed (asymmetric arrangement alternating for each gate line). That is, the first pixel PX1 and the third pixel PX3, as well as the second pixel PX2 and the fourth pixel PX4, are alternately arranged on one side and the other side for each gate line (or the pixel positions including the white sub-pixel are changed to one side and the other side in a zigzag pattern for each gate line).

[0094] Additionally, the white sub-pixel SPW may be located between the first to third sub-pixels SP1 - SP3 and the first to third sub-pixels SP1' - SP3'. That is, the first to third sub-pixels SP1 - SP3 and the first to third sub-pixels SP1' - SP3' may share the white sub-pixel SPW in a zigzag pattern. The structure of sharing the white sub-pixel SPW can achieve a display panel with a high aperture ratio and high PPI (pixels per inch), which can improve the service life without aging.

[0095] Referring to Figure 13 and Figure 14 , the first sub-pixel SP1 and the first sub-pixel SP1' may be selected as the red sub-pixels SPR and SPR' that emit red light. The second sub-pixel SP2 and the second sub-pixel SP2' may be selected as the green sub-pixels SPG and SPG' that emit green light. The third sub-pixel SP3 and the third sub-pixel SP3' may be selected as the blue sub-pixels SPB and SPB' that emit blue light. However, this is merely an example, and the arrangement order of the sub-pixels is not limited thereto.

[0096] Figure 15 is a diagram showing pixels located on one gate line according to an embodiment, Figure 16 is a diagram showing the deviation that may occur between the pixels shown in Figure 15 , Figure 17FIG. is a diagram showing pixels located on two adjacent gate lines according to an embodiment. Figure 18 FIG. is a diagram showing Figure 17 the deviation that may occur between the pixels shown in

[0097] As Figure 15 shown, when viewed from the J-th gate line GLj corresponding to one gate line, the first pixel PX1 and the second pixel PX2 may be asymmetric because the first pixel PX1 has a structure in which four sub-pixels are commonly connected to the first reference line REF1, while the second pixel PX2 has a structure in which three sub-pixels are commonly connected to the second reference line REF2.

[0098] As Figure 15 shown, if the first pixel PX1 and the second pixel PX2 are arranged asymmetrically with respect to the J-th gate line GLj, deviations such as parasitic capacitance difference or line load difference may occur between the first pixel PX1 and the second pixel PX2. For example, as Figure 16 shown, a relationship corresponding to PX1 > PX2 can be established between the first pixel PX1 and the second pixel PX2. Due to process variations or different driving modes and driving voltages, the above deviation problem may become more serious, and thus the display quality may deteriorate.

[0099] As Figure 17 shown, when viewed from the J-th gate line GLj corresponding to one gate line, the first pixel PX1 and the second pixel PX2 may be asymmetric. However, when viewed from the J-th gate line GLj and the K-th gate line GLk corresponding to two gate lines, the first pixel PX1 and the second pixel PX2 may be symmetric with the third pixel PX3 and the fourth pixel PX4 arranged in the opposite manner.

[0100] As Figure 17 shown, when the first pixel PX1 and the second pixel PX2 located on the J-th gate line GLj are asymmetrically set, and the third pixel PX3 and the fourth pixel PX4 located on the K-th gate line GLk are asymmetrically set in the opposite manner, deviations such as parasitic capacitance difference or line load difference existing between the first pixel PX1 to the fourth pixel PX4 can be eliminated. For example, as Figure 18 shown, a relationship corresponding to PX1 & PX4 = PX2 & PX3 can be established between the first pixel PX1, the fourth pixel PX4 and the second pixel PX2, the third pixel PX3 (the same load can be applied between the upper, lower, left, and right pixels).

[0101] In this way, by using a hybrid structure in which the first pixel groups PX1 and PX3 each including four sub-pixels and the second pixel groups PX2 and PX4 each including three sub-pixels are alternately arranged as in this embodiment, the deviation that may occur on the display panel can be improved (offset), and the flicker or image interference can be minimized, thereby improving the display quality.

[0102] Meanwhile, in Figure 15 and Figure 17 , R1 represents the first red data line, G1 represents the first green data line, B1 represents the first blue data line, W1 represents the first white data line, R2 represents the second red data line, G2 represents the second green data line, and B2 represents the second blue data line. In Figure 16 and Figure 18 , R1, G1, B1, and W1 represent parasitic capacitor components that cause deviations in the first red data line, the first green data line, the first blue data line, and the first white data line, and R2, G2, and B2 represent parasitic capacitor components that cause deviations in the second red data line, the second green data line, and the second blue data line.

[0103] In Figure 16 and Figure 18 , W1 indicated in gray represents an actually existing parasitic capacitor component or a relatively small parasitic capacitor component.

[0104] Hereinafter, the experimental examples and the embodiments will be compared, and the advantages of the embodiments will be described.

[0105] Figure 19 is a diagram showing a display panel implemented according to an experimental example, Figure 20 is a diagram showing the layout of pixels provided in the display panel according to the experimental example, Figure 21 is a diagram showing a display panel implemented according to an embodiment, Figure 22 is a diagram showing the layout of pixels provided in the display panel according to the embodiment, Figure 23 and Figure 24 are diagrams for comparing between the experimental example and the embodiment.

[0106] As Figure 19 and Figure 20 shown, in the experimental example, the display panel 150 can be implemented based on the first pixel PX1 including four sub-pixels and the second pixel PX2 including three sub-pixels. In the experimental example, when observed from the J-th gate line GLj and the K-th gate line GLk, the display panel 150 is implemented based on the pixels PX1 and PX2 asymmetrically arranged on one side and the other side. The display panel 150 according to the experimental example may have a layout in which a set of four sub-pixels and a set of three sub-pixels are repeatedly arranged in the direction of all gate lines (or the horizontal direction).

[0107] As Figure 21 and Figure 22 shown, in an embodiment, the display panel 150 may be implemented based on a first pixel PX1 and a third pixel PX3 each including four sub-pixels and a second pixel PX2 and a fourth pixel PX4 each including three sub-pixels. In the embodiment, the display panel 150 is implemented based on the pixels PX1 to PX4. When viewed from one gate line, the pixels PX1 to PX4 are asymmetrically arranged on one side and the other side, but when viewed from two gate lines, as can be seen from the J-th gate line GLj and the K-th gate line GLk, the pixels PX1 to PX4 are symmetrically arranged.

[0108] In the layout of the display panel 150 according to the embodiment, a set of four sub-pixels and a set of three sub-pixels are repeatedly arranged not only in the gate line direction but also in the data line direction (or vertical direction).

[0109] When Figure 19 and Figure 20 shown, when the display panel 150 is alternately driven frame by frame in the experimental example, a pattern PAT1 of brightness reduction in the vertical direction of the display panel 150 may appear in the form of a long vertical line, as Figure 23 shown.

[0110] When Figure 21 and Figure 22 shown, when the display panel 150 is alternately driven frame by frame in the embodiment, a pattern PAT2 of brightness reduction in the vertical direction of the display panel 150 may appear in the form of dots, as Figure 24 shown. When the pattern PAT2 appears in the form of dots in this way, there is no problem from the perspectives of recognition and image quality compared with when the pattern PAT1 appears in the form of a vertical line.

[0111] Figure 23 and Figure 24 show images that can be displayed on the display panel 150 when alternately driving the first driving condition and the second driving condition frame by frame. In the first driving condition, the red, green, and blue sub-pixels are driven 100%, and in the second driving condition, the white sub-pixel is driven and the red, green, and blue sub-pixels are driven less than 5%. For example, Figure 23 and Figure 24 shown, the pattern PAT1 and the pattern PAT2 may be caused by the green sub-pixel, but are not limited thereto.

[0112] From Figure 23 and Figure 24 the comparison between them, it can be determined that when the display panel is implemented and driven based on the pixels arranged as in the embodiment, the problem of deterioration in display quality that may occur in the display panel implemented based on the pixels arranged as in the experimental example can be improved.

[0113] In the following, experimental examples and embodiments will be compared, and other advantages of the embodiments will be described.

[0114] Figure 25 is a diagram showing the waveform of a gate signal for driving a display panel according to an experimental example, Figure 26 is shown in Figure 25 is a diagram showing a first problem that may occur in an experimental example during the operation based on the gate signal shown. Figure 27 is a diagram showing a second problem that may occur in an experimental example.

[0115] As Figure 19 , Figure 20 and Figures 25 to 27 shown, the display panel 150 according to the experimental example can be driven based on gate signals that overlap each other for a certain period of time. Figure 25 shows an example in which the high voltages (or gate-on voltages) of the J-th gate signal Gate[j] and the K-th gate signal Gate[k] applied to adjacent J-th gate line GLj and K-th gate line GLk overlap each other for a certain period of time (e.g., 1 / 2 time).

[0116] Meanwhile, when the gate signals Gate[j] and Gate[k] that overlap each other for a certain period of time are applied to the display panel 150 according to the experimental example and the white sub-pixel SPW connected to the first reference line REF1 is sensed, a problem of sensing value mixing may occur.

[0117] For example, Figure 26 shows that when a sensing operation is performed during the overlap of the J-th gate signal Gate[j] and the K-th gate signal Gate[k], the first sensing value Vsen1 sensed from the white sub-pixel SPW of the J-th gate line GLj and the second sensing value Vsen2 sensed from the white sub-pixel SPW of the K-th gate line GLk may be mixed when obtained through the first reference line REF1.

[0118] In addition, in the display panel 150 according to the experimental example, two sub-pixels adjacent to each other in the vertical direction share a reference line, so if there is a problem in one sub-pixel, the other sub-pixel may be affected.

[0119] Figure 27 shows an example in which a bright spot (abnormal brightness) that appears in one of two sub-pixels adjacent to each other in the vertical direction may affect the other sub-pixel when an operation using the overlapping J-th gate signal Gate[j] and K-th gate signal Gate[k] is performed.

[0120] Figure 28FIG. 0 is a diagram showing waveforms of gate signals for driving a display panel according to an embodiment. Figure 29 FIG. Figure 28 is a diagram showing an embodiment that improves the first problem presented in the experimental example during the operation based on the gate signal shown in FIG. Figure 30 FIG.

[0121] As Figure 21 , Figure 22 and Figures 28 to 30 shown, the display panel 150 according to an embodiment may be driven based on gate signals that overlap each other for a certain period of time. Figure 28 FIG. shows an example in which the high voltages (or gate-on voltages) of the J-th gate signal Gate[j] and the K-th gate signal Gate[k] applied to adjacent J-th gate line GLj and K-th gate line GLk overlap each other for a certain period of time (e.g., 1 / 2 time).

[0122] Meanwhile, when the gate signals Gate[j] and Gate[k] that overlap each other for a certain period of time are applied to the display panel 150 according to an embodiment and the white sub-pixel SPW connected to the first reference line REF1 is sensed, the problem of sensing value mixing may not occur.

[0123] For example, Figure 29 FIG. shows that when the sensing operation is performed during the overlap period of the J-th gate signal Gate[j] and the K-th gate signal Gate[k], the first sensing value Vsen1 sensed from the white sub-pixel SPW of the J-th gate line GLj is obtained through the first reference line REF1, and the second sensing value Vsen2 sensed from the white sub-pixel SPW of the K-th gate line GLk is obtained through the second reference line REF2, so that the problem of mixing of these sensing values does not occur. In one embodiment, the data voltages of at least one of the first pixel PX1 including the white sub-pixel SPW or the third pixel PX3 including the white sub-pixel SPW are compensated based on the first sensing value Vsen1 and the second sensing value Vsen2, respectively.

[0124] In addition, in the display panel 150 according to an embodiment, two sub-pixels adjacent to each other in the vertical direction are connected to different reference lines instead of sharing one reference line, so that even if there is a problem in one sub-pixel, the other sub-pixel may not be affected.

[0125] Figure 30 FIG. shows an example in which a bright spot (abnormal brightness) that appears in one of two sub-pixels adjacent to each other in the vertical direction does not affect other sub-pixels even when the operation using the overlapping J-th gate signal Gate[j] and K-th gate signal Gate[k] is performed.

[0126] It can be determined by comparing the experimental examples with the embodiments that, even when an operation is performed in a case where two gate signals overlapping for a certain period of time are applied to gate lines adjacent to each other in the vertical direction, the embodiments do not cause a problem of mixing of sensed values obtained from two sub-pixels. In addition, in the embodiments, a bright spot (abnormal brightness) occurring in one of two sub-pixels adjacent to each other in the vertical direction does not affect the other sub-pixel. Therefore, the embodiments can improve (offset) a deviation problem that may occur on the display panel and minimize flicker or image interference.

[0127] In addition, the light-emitting display device according to an embodiment may compensate for deterioration of at least one sub-pixel included in each of the first pixel and the second pixel based on the first sensed value Vsen1 and the second sensed value Vsen2, and accordingly compensate for deterioration of at least one sub-pixel included in the display panel.

[0128] Hereinafter, examples that can be referred to when implementing a pixel according to an embodiment will be described.

[0129] Figure 31 is a diagram showing a first example that can be referred to when implementing a pixel according to an embodiment, Figure 32 is a diagram showing a second example that can be referred to when implementing a pixel according to an embodiment.

[0130] As Figure 31 and Figure 32 shown, pixels PX1 to PX4 according to an embodiment may include a plurality of sub-pixels. The plurality of sub-pixels may include a light-emitting region EA and a circuit region DA. The light-emitting region EA is a region where light is emitted, and may be defined as the region where the organic light-emitting diode OLED shown in Figure 7 or Figure 8 is located. The circuit region DA is a region where a circuit for driving the organic light-emitting diode OLED is located, and may be defined as the region where the switching transistor SW, the driving transistor DT, the sensing transistor ST, and the capacitor CST shown in Figure 7 or Figure 8 are located.

[0131] Pixels PX1 to PX4 according to an embodiment may include red sub-pixels SPR and SPR', green sub-pixels SPG and SPG', blue sub-pixels SPB and SPB', and white sub-pixels SPW, and the red sub-pixels SPR and SPR' and the white sub-pixels SPW may have the largest light-emitting region EA.

[0132] The pixels PX1 to PX4 according to an embodiment may be located in a region between a first power supply line EVDD provided on one side and a first power supply line EVDD provided on the other side. The pixels PX1 to PX4 according to an embodiment may include a first reference line VREF1 and a second reference line VREF2 located between a first power supply line EVDD provided on one side and a first power supply line EVDD provided on the other side. The pixels PX1 to PX4 according to an embodiment may include first data lines DL1 to seventh data lines DL7.

[0133] The pixels PX1 to PX4 according to an embodiment may include a first gate line GL1 connected to the first pixel PX1 and the second pixel PX2 and a second gate line GL2 connected to the third pixel PX3 and the fourth pixel PX4. The pixels PX1 to PX4 according to an embodiment may include a first connection line CNT1 having a first length for connecting four sub-pixels to one reference line and a second connection line CNT2 having a second length less than the first length for connecting three sub-pixels to one reference line.

[0134] The first power supply line EVDD, the first data lines DL1 to seventh data lines DL7, the first reference line VREF1, and the second reference line VREF2 may be arranged to be spaced apart at regular intervals in the vertical direction of the substrate. The first gate line GL1 and the second gate line GL2 may be arranged to be spaced apart from each other at regular intervals in the horizontal direction of the substrate. The first connection line CNT1 and the second connection line CNT2 may be arranged to be spaced apart at regular intervals in the horizontal direction of the substrate.

[0135] As in Figure 31 In the first example shown in, the first power supply line EVDD, the first data lines DL1 to seventh data lines DL7, the first reference line VREF1, and the second reference line VREF2 may be formed using a shielding metal layer located at the bottommost layer of the substrate or a source / drain metal layer located above the shielding metal layer. At least one of the first power supply line EVDD, the first data lines DL1 to seventh data lines DL7, the first reference line VREF1, and the second reference line VREF2 may be formed as a single layer or multiple layers.

[0136] The first gate line GL1 and the second gate line GL2 may be formed using a gate metal layer located between the shielding metal layer and the source / drain metal layer. The first connection line CNT1 and the second connection line CNT2 may be formed using a semiconductor layer (active layer) located between the shielding metal layer and the gate metal layer.

[0137] As in Figure 32In the second example shown, the first power supply line EVDD, the first data lines DL1 to DL7, the first reference line VREF1, and the second reference line VREF2 may be formed using a shielding metal layer located at the bottommost layer of the substrate or a source / drain metal layer located above the shielding metal layer. At least one of the first power supply line EVDD, the first data lines DL1 to DL7, the first reference line VREF1, and the second reference line VREF2 may be formed as a single layer or multiple layers.

[0138] The first gate line GL1, the second gate line GL2, the first connection line CNT1, and the second connection line CNT2 may be formed using a gate metal layer located between the shielding metal layer and the source / drain metal layer.

[0139] From Figure 31 the first example shown and Figure 32 the second example shown, it can be determined that due to the connection structure of the first connection line CNT1 and the second connection line CNT2, the asymmetric relationship between a pixel including four sub-pixels and a pixel including three sub-pixels can be regarded as a symmetric relationship when viewed from the entire display panel 150. In addition, in addition to the first connection line CNT1 and the second connection line CNT2, any conductive layer located on a layer different from the layer where the data lines DL1 to DL7 are located can make the asymmetric relationship of the pixels symmetric in the entire display panel 150. Additionally, as Figure 31 and Figure 32 shown, since in the embodiment, one white sub-pixel can be omitted for every two adjacent pixels in the horizontal direction, the aperture ratio can be increased and the number of pad pins can be reduced, so a structure of a display panel capable of achieving a high aperture ratio and a high PPI can be provided.

[0140] When implementing the display panel based on Figure 31 and Figure 32 , pixels may be set for the third gate line in the same layout as that for the first gate line GL1, and pixels may be set for the fourth gate line in the same layout as that for the second gate line GL2. Additionally, pixels may be set to repeat the pixel structure set for a total of four gate lines in the same manner for the remaining gate lines.

[0141] However, the embodiment is not limited thereto. Pixels may be set for the third gate line in the same layout as that for the second gate line GL2, and pixels may be set for the fourth gate line in the same layout as that for the first gate line GL1. Additionally, pixels may be set to repeat the pixel structure set for a total of four gate lines in the same manner for the remaining gate lines.

[0142] As described above, the present disclosure has the effect of improving (offsetting) the deviation problems that may occur on the display panel and enhancing the display quality by minimizing or at least reducing flicker or image interference. In addition, the present disclosure can implement a display panel with a high aperture ratio and a high PPI, and has the effect of improving the lifespan without aging.

[0143] It will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the spirit or scope of the present disclosure. Accordingly, the present disclosure is intended to cover modifications and variations of the present disclosure as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: a first pixel connected to a first gate line and a first reference line; a second pixel connected to the first gate line and a second reference line; a third pixel connected to the second gate line and the second reference line; as well as a fourth pixel, the fourth pixel being connected to the second gate line and the first reference line, The first pixel and the third pixel each include four sub-pixels. The second pixel and the fourth pixel each include three sub-pixels.

2. The display device according to claim 1, wherein: The first pixel includes a first connection line connecting four sub-pixels to the first reference line, The second pixel includes a second connection line connecting three sub-pixels to the second reference line, The third pixel includes a first connection line connecting four sub-pixels to the second reference line, The fourth pixel includes a second connection line connecting three sub-pixels to the first reference line.

3. The display device according to claim 2, wherein: The second connection line has a length smaller than that of the first connection line.

4. The display device according to claim 2, wherein: The first pixel and the third pixel each include a white sub-pixel that emits white light, The second pixel and the fourth pixel do not include a white sub-pixel.

5. The display device according to claim 2, wherein: The first pixel and the third pixel each include a first sub-pixel emitting light of a first color, a second sub-pixel emitting light of a second color, a third sub-pixel emitting light of a third color, and a white sub-pixel emitting white light, The second pixel and the fourth pixel each include a first sub-pixel emitting light of a first color, a second sub-pixel emitting light of a second color, and a third sub-pixel emitting light of a third color.

6. The display device according to claim 5, wherein: The first sub-pixels of the first pixel and the third pixel and the first sub-pixels of the second pixel and the fourth pixel emit red light, The second sub-pixels of the first pixel and the third pixel and the second sub-pixels of the second pixel and the fourth pixel emit green light, The third sub-pixels of the first pixel and the third pixel and the third sub-pixels of the second pixel and the fourth pixel emit blue light.

7. The display device according to claim 2, wherein: The first connection line and the second connection line are formed by a semiconductor layer located between a shielding metal layer and a gate metal layer.

8. A display device, comprising: a first pixel including a first connection line connecting four sub-pixels on a first gate line to a first reference line; a second pixel, the second pixel comprising a second connection line connecting three sub-pixels on the first gate line to a second reference line; a third pixel, the third pixel comprising a first connection line connecting four sub-pixels on the second gate line to the second reference line; A fourth pixel includes a second connection line connecting three sub-pixels on the second gate line to the first reference line.

9. The display device according to claim 8, wherein: The first pixel and the third pixel each include a first sub-pixel emitting light of a first color, a second sub-pixel emitting light of a second color, a third sub-pixel emitting light of a third color, and a white sub-pixel emitting white light, The second pixel and the fourth pixel each include a first sub-pixel emitting light of a first color, a second sub-pixel emitting light of a second color, and a third sub-pixel emitting light of a third color.

10. The display device according to claim 9, wherein: The first sub-pixels of the first pixel and the third pixel and the first sub-pixels of the second pixel and the fourth pixel emit red light, The second sub-pixels of the first pixel and the third pixel and the second sub-pixels of the second pixel and the fourth pixel emit green light, The third sub-pixels of the first pixel and the third pixel and the third sub-pixels of the second pixel and the fourth pixel emit blue light.

11. The display device according to claim 8, wherein: The first connection line and the second connection line are formed by a semiconductor layer located between a shielding metal layer and a gate metal layer.

12. A display device, comprising: a display panel for displaying images; as well as a driver for driving the display panel, Wherein, the display panel comprises: a first pixel connected to a first gate line and a first reference line; a second pixel connected to the first gate line and a second reference line; a third pixel connected to the second gate line and the second reference line; and a fourth pixel, the fourth pixel being connected to the second gate line and the first reference line, The first pixel and the third pixel each include four sub-pixels. The second pixel and the fourth pixel each include three sub-pixels.

13. A method for driving a display device, the display device comprising a display panel, the display panel comprising a first pixel, a second pixel, a third pixel and a fourth pixel, the first pixel comprising a first connection line connecting four sub-pixels on a first gate line to a first reference line, the second pixel comprising a second connection line connecting three sub-pixels on the first gate line to a second reference line, the third pixel comprising a first connection line connecting four sub-pixels on a second gate line to the second reference line, the fourth pixel comprising a second connection line connecting three sub-pixels on the second gate line to the first reference line, the driving method comprising: applying a gate-on voltage overlapping for a certain period of time to the first gate line and the second gate line; acquiring a first sensing value from the first pixel connected to the first reference line and acquiring a second sensing value from the third pixel connected to the second reference line; as well as The display panel is compensated based on the first sensing value and the second sensing value.

14. The driving method according to claim 13, wherein: The first pixel and the third pixel each include a white sub-pixel that emits white light, The second pixel and the fourth pixel do not include a white sub-pixel.

15. The driving method according to claim 13, wherein: The first connection line and the second connection line are formed by a semiconductor layer located between a shielding metal layer and a gate metal layer.

Images