Display device and driving method thereof

Abstract

The invention relates to a display device and a driving method thereof. The display device includes: a first sub-pixel configured to receive a first data voltage and drive a first light emitting element included in the first sub-pixel; a second sub-pixel configured to receive a second data voltage and drive a second light emitting element included in the second sub-pixel; and a third sub-pixel configured to receive a third data voltage and drive a third light emitting element included in the third sub-pixel. At least one of a dynamic range, a maximum voltage, and a minimum voltage of the first data voltage, the second data voltage, and the third data voltage is different from each other. The emission time of the first light-emitting element, the emission time of the second light-emitting element, and the emission time of the third light-emitting element are different from each other.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0192152, filed on December 27, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to a display device and a driving method thereof. Background art

[0004] Various flat - panel display devices are known, such as liquid - crystal display devices and electroluminescent display devices. An electroluminescent display device can use light - emitting elements arranged in each pixel to emit light by itself without a backlight, thereby displaying an input image. The light - emitting elements of an electroluminescent display device can be classified into organic light - emitting elements and inorganic light - emitting elements according to the material of the light - emitting layer.

[0005] Recently, a display device using an inorganic light - emitting element, namely a light - emitting diode (LED), as a light - emitting element of a pixel has attracted attention as a next - generation display device. Since an LED is made of an inorganic material, it does not require a separate encapsulation layer to protect organic materials from moisture, and it has excellent reliability and a long lifespan compared to an organic light - emitting diode (OLED). In addition, an LED has the advantages of a fast lighting speed, excellent luminous efficiency, and impact resistance.

[0006] Light - emitting elements such as micro - LEDs and OLEDs emit light through current, but the current is difficult to control. A pixel circuit for driving a light - emitting element applies a data voltage to a driving transistor to supply current to the light - emitting element by using the driving transistor as a constant - current source. As the data voltage increases, the gate - source voltage of the driving transistor increases, and the amount of current flowing through the light - emitting element increases, thereby increasing the brightness of the light - emitting element.

[0007] In the case of an inorganic light - emitting element such as a micro - LED, due to the material properties of the light - emitting layer, the luminous efficiency is relatively high in a specific current region. The luminous efficiency is an efficiency representing the ratio of brightness to the current applied to the light - emitting element. Although the effect of reducing the current consumption of the light - emitting element can be achieved within a high - efficiency range, a higher data voltage is required to achieve high luminous efficiency. Due to the material properties of the light - emitting layer, in the case of an inorganic light - emitting element of a specific color, a higher data voltage is required to improve the luminous efficiency. As the data voltage increases, the brightness of the inorganic light - emitting element may become too high. This causes the color coordinates and white balance to deviate from the target values, resulting in deterioration of image quality. Summary of the invention

[0008] To solve the above difficulties and / or disadvantages, the present disclosure is proposed.

[0009] The present disclosure provides a display device and a driving method thereof, which can drive a light-emitting element with the maximum luminous efficiency of each color and improve image quality.

[0010] The problems or defects to be solved by the present disclosure are not limited to those described above, and those skilled in the art will clearly understand other problems or defects not mentioned from the following description.

[0011] In one embodiment, a display device includes: a first sub-pixel including a first light-emitting element, the first sub-pixel being configured to receive a first data voltage and drive the first light-emitting element using the first data voltage; a second sub-pixel including a second light-emitting element, the second sub-pixel being configured to receive a second data voltage and drive the second light-emitting element using the second data voltage; a third sub-pixel including a third light-emitting element, the third sub-pixel being configured to receive a third data voltage and drive the third light-emitting element using the third data voltage; and a brightness regulator circuit configured to reduce the brightness of at least one of the first sub-pixel, the second sub-pixel, or the third sub-pixel, wherein a first emission time of the first light-emitting element that emits light, a second emission time of the second light-emitting element that emits light, and a third emission time of the third light-emitting element that emits light are different from each other.

[0012] In one embodiment, a display device includes: a first sub-pixel including a first light-emitting element, a first driving element configured to control a current flowing through the first light-emitting element based on a gate-source voltage of the first driving element, a first switching element configured to switch a current path of the first light-emitting element between a pixel driving voltage and a pixel reference voltage in response to a first emission signal, and a first compensation circuit configured to receive a first data voltage and a scan signal and apply the first data voltage to a gate electrode of the first driving element; a second sub-pixel including a second light-emitting element, a second driving element configured to control a current flowing through the second light-emitting element based on a gate-source voltage of the second driving element, a second switching element configured to switch a current path of the second light-emitting element between a pixel driving voltage and a pixel reference voltage in response to a second emission signal, and a second compensation circuit configured to receive a second data voltage and a scan signal and apply the second data voltage to a gate electrode of the second driving element; a third sub-pixel including a third light-emitting element, a third driving element configured to control a current flowing through the third light-emitting element based on a gate-source voltage of the third driving element, a third switching element configured to switch a current path of the third light-emitting element between a pixel driving voltage and a pixel reference voltage in response to a third emission signal, and a third compensation circuit configured to receive a third data voltage and a scan signal and apply the third data voltage to a gate electrode of the third driving element; and a brightness regulator circuit configured to independently control a pixel driving voltage in each of the first sub-pixel, the second sub-pixel, and the third sub-pixel or one of the first emission signal, the second emission signal, and the third emission signal such that the brightness of at least one of the first sub-pixel, the second sub-pixel, and the third sub-pixel is reduced.

[0013] In one embodiment, a method of driving a display device includes: providing a first data voltage to a first sub-pixel that drives a first light-emitting element with the first data voltage, providing a second data voltage to a second sub-pixel that drives a second light-emitting element with the second data voltage, and providing a third data voltage to a third sub-pixel that drives a third light-emitting element with the third data voltage; and controlling a first emission time of the first light-emitting element, a second emission time of the second light-emitting element, and a third emission time of the third light-emitting element to be different from each other such that the brightness of at least one of the first sub-pixel, the second sub-pixel, and the third sub-pixel is reduced.

[0014] In one embodiment, a display device includes: a display panel including a plurality of pixels, the plurality of pixels having at least one pixel including a first sub-pixel configured to emit first color light, a second sub-pixel configured to emit second color light, and a third sub-pixel configured to emit third color light; a gate driver configured to provide scan signals to the plurality of pixels; a data driver configured to provide data voltages to the plurality of pixels, the data voltages including a first data voltage having a first possible voltage range applied to the first sub-pixel, a second data voltage having a second possible voltage range applied to the second sub-pixel, and a third data voltage having a third possible voltage range applied to the second sub-pixel, wherein the first possible voltage range, the second possible voltage range, and the third possible voltage range are different from each other; and a brightness regulator circuit configured to adjust a first emission time of the first sub-pixel that emits light of the first sub-pixel, a second emission time of the second sub-pixel that emits light of the second sub-pixel, and a third emission time of the third sub-pixel that emits light of the third sub-pixel to be different from each other.

[0015] According to an embodiment of the present disclosure, data voltages for driving light-emitting elements of each color at their maximum luminous efficiency can be set independently for each color to reduce power consumption.

[0016] The present disclosure can appropriately reduce the excessive brightness of each color by using color-specific emission signals and / or color-specific pixel driving voltages, thereby achieving ideal color coordinates and white balance. Therefore, the present disclosure can improve the image quality of the display device.

[0017] The effects of the present disclosure are not limited to the above effects, and other effects not mentioned will be clearly understood by those skilled in the art from the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] By referring to the accompanying drawings and describing the exemplary embodiments of the present disclosure in detail, the above and other objects, features, and advantages of the present disclosure will become more apparent to those of ordinary skill in the art, wherein:

[0019] Figure 1 is a block diagram showing a display device according to an embodiment of the present disclosure;

[0020] Figure 2A 、 2B and 2C are circuit diagrams schematically showing a pixel circuit according to an embodiment of the present disclosure;

[0021] Figure 3 is a schematic diagram schematically showing a sub-pixel structure of a transparent display device;

[0022] Figure 4is a graph showing an example of the current density - to - efficiency ratio characteristics of light - emitting elements of each color;

[0023] Figure 5 is a schematic diagram showing an example of data voltages of each color according to an embodiment of the present disclosure;

[0024] Figure 6 is a detailed circuit diagram showing a pixel circuit according to an embodiment of the present disclosure;

[0025] Figure 7 is a waveform diagram showing signals applied to a pixel circuit according to an embodiment of the present disclosure;

[0026] Figure 8 is a schematic diagram showing a transmission signal output circuit according to an embodiment of the present disclosure;

[0027] Figure 9 is a schematic diagram showing a transmission signal output circuit according to another embodiment of the present disclosure;

[0028] Figure 10 is a schematic diagram showing an example of emission times of sub - pixels of each color;

[0029] Figure 11 is a schematic diagram showing a transmission signal output circuit according to another embodiment of the present disclosure;

[0030] Figure 12 is a diagram showing, according to an embodiment of the present disclosure, from Figure 11 is a waveform diagram showing an example of emission signals of each color output from the shown transmission signal output circuit;

[0031] Figure 13 is a circuit diagram showing a pixel circuit according to another embodiment of the present disclosure;

[0032] Figure 14 is a waveform diagram showing an example of pixel drive voltages of each color;

[0033] Figure 15 is a schematic diagram showing a pixel drive voltage output circuit according to an embodiment of the present disclosure;

[0034] Figure 16 is a schematic diagram showing a pixel drive voltage output circuit according to another embodiment of the present disclosure; and

[0035] Figure 17 is a diagram showing an embodiment of a method for controlling emission times of each color of sub - pixels.

[0036] Figure 18It is a diagram showing another embodiment of a method for controlling the emission time of each color of sub-pixels.

[0037] Figure 19 It is a diagram showing another embodiment of a method for controlling the emission time of each color of sub-pixels. Detailed Description

[0038] Advantages and features of the present disclosure and methods for realizing them will be more clearly understood according to the embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments and can be implemented in various different forms. On the contrary, these embodiments will make the disclosure of the present disclosure complete and allow those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is only limited within the scope of the appended claims.

[0039] The shapes, sizes, ratios, angles, quantities, etc. shown in the drawings for describing the embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally denote the same elements. In addition, when describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0040] Terms such as "comprising", "having", and "including" used herein generally intend to allow the addition of other components, unless these terms are used together with the term "only". Any reference to the singular may include the plural unless otherwise clearly stated.

[0041] Even if not explicitly stated, components are interpreted to include a normal error range.

[0042] When describing the positional or interconnect relationship between two components, such as "on", "above", "below", "adjacent to", "connected or coupled to", "crossing", "intersecting", etc., one or more other components may be inserted between them unless the terms "immediately" or "directly" are used.

[0043] When describing the time precedence relationship, such as "after", "after...", "next", "before...", etc., it may not be continuous on the time base unless the terms "immediately" or "directly" are used.

[0044] Terms such as "first", "second", etc. may be used to distinguish elements from each other, but the functions or structures of the components are not limited by the ordinal numbers or component names in front of the components.

[0045] The following embodiments may be partially or completely combined or combined with each other and may be connected and operated in various technical ways. The embodiments may be performed independently of each other or in relation to each other.

[0046] The pixel circuit of a display device may include a plurality of transistors. A transistor is a three - electrode element including a gate, a source, and a drain. The source is an electrode that supplies carriers to the transistor. In a transistor, carriers flow starting from the source. The drain is an electrode from which carriers leave the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n - channel transistor, since the carriers are electrons, the source voltage is a voltage lower than the drain voltage, such that electrons can flow from the source to the drain. The n - channel transistor has a current direction from the drain to the source. In the case of a p - channel transistor (p - channel metal - oxide semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, such that holes can flow from the source to the drain. In a p - channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. Note that the source and drain of a transistor are not fixed. For example, the source and drain can change according to the applied voltage. Therefore, the present disclosure is not limited to the source and drain of a transistor. In the following description, the source and drain of the transistor are referred to as the first electrode and the second electrode.

[0047] The gate signal swings between a gate - on voltage and a gate - off voltage. The transistor turns on in response to the gate - on voltage and turns off in response to the gate - off voltage. In the case of an n - channel transistor, the gate - on voltage can be a gate - high voltage VGH, and the gate - off voltage can be a gate - low voltage VGL. In the case of a p - channel transistor, the gate - on voltage can be a gate - low voltage VGL, and the gate - off voltage can be a gate - high voltage VGH.

[0048] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0049] Refer to Figure 1 , a display device according to an embodiment of the present disclosure includes a display panel 100, a display panel driving circuit for writing pixel data to pixels 101 of the display panel 100, and a power supply 140 that generates power required to drive the pixels 101 and the display panel driving circuit.

[0050] The substrate of the display panel 100 can be a plastic substrate, a thin glass substrate, or a metal substrate, but is not limited thereto. The display panel 100 can be a rectangular panel having a length in the X - axis direction (or the first direction), a width in the Y - axis direction (or the second direction), and a thickness in the Z - axis direction (or the third direction), but is not limited thereto. For example, at least a part of the display panel 100 can have a curved perimeter.

[0051] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel can be applied to a transparent display device, where an image is displayed on the screen and real objects outside the display panel can be seen. The display panel 100 can be manufactured as a flexible display panel. Additionally, the display panel 100 can be manufactured as a stretchable panel capable of being extended.

[0052] The display area AA of the display panel 100 includes a pixel array for displaying an input image. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels 101 arranged in a matrix form. The display panel 100 may further include a power line commonly connected to the pixels 101. The power line is commonly connected to the pixels 101 to supply a constant voltage required to drive the pixels 101. The power line can be implemented as a long strip line in the first direction or the second direction, or as a mesh line in which the lines in the first direction and the lines in the second direction are electrically connected.

[0053] Each pixel 101 can be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for implementing colors. Each pixel may further include a white sub-pixel. Each sub-pixel includes a pixel circuit for driving a light-emitting element. The pixel circuit is connected to the data line, the gate line, and the power line. Hereinafter, "pixel" can be interpreted as "sub-pixel".

[0054] The pixel array includes a plurality of pixel lines L1 to Ln. Each of the pixel lines L1 to Ln includes a pixel line arranged along the gate line direction (X-axis direction) in the pixel array of the display panel 100. The pixels arranged in one pixel line can share the gate line 103. The pixels arranged in the column direction (Y-axis direction) along the data line direction can share the same data line 102. One horizontal period is the time obtained by dividing one frame period by the total number of the pixel lines L1 to Ln.

[0055] The power supply 140 uses a DC-DC converter to generate a constant voltage (or direct current (DC) voltage) required to drive the pixel array of the display panel 100 and the display panel driving circuit. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply 140 can adjust the level of the input voltage input from the host system 200 to output a constant voltage, such as a gamma reference voltage, a gate low voltage, a gate high voltage, a pixel driving voltage, and a pixel reference voltage. The gamma reference voltage is supplied to the data driver 110. The dynamic range of the data voltage output from the data driver 110 is determined by the voltage range of the gamma reference voltage. The dynamic range of the data voltage is the voltage range between the highest gray scale voltage and the lowest gray scale voltage.

[0056] A high gate voltage and a low gate voltage are supplied to a level shifter 150 and a gate driver 120. Constant voltages such as a pixel driving voltage and a pixel reference voltage are supplied to a pixel 101 through a power line commonly connected to the pixel 101. The pixel driving voltage can be supplied from a main power supply of a host system 200 to the display panel 100. In this case, the power supply 140 does not need to output the pixel driving voltage.

[0057] The display panel driving circuit writes pixel data of an input image into the pixels of the display panel 100 under the control of a timing controller 130. The display panel driving circuit includes a data driver 110 and a gate driver 120.

[0058] The display panel driving circuit may further include a touch sensor driver for driving a touch sensor. The touch sensor driver is omitted in Figure 1 The data driver 110 and the touch sensor driver may be integrated into a single driving integrated circuit (IC). The timing controller 130, the power supply 140, the level shifter 150, the data driver 110, the touch sensor driver, etc. may be further integrated into the driving IC.

[0059] The data driver 110 receives pixel data of an input image received as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 converts the pixel data of the input image into a gamma-compensated voltage using a digital-to-analog converter (DAC) and outputs the data voltage. The gamma reference voltage is divided by a voltage divider circuit of the data driver 110 into gamma-compensated voltages corresponding to each gray level and supplied to the DAC. The DAC generates a data voltage having a gamma-compensated voltage corresponding to the gray level value of the pixel data. The data voltage output from the DAC is output to a data line 102 through an output buffer in each data output channel of the data driver 110.

[0060] Within the maximum luminous efficiency range of each of a red light-emitting element, a green light-emitting element, and a blue light-emitting element, the data voltage may be different. The data driver 110 may differently set at least one of a dynamic range, a maximum voltage, and a minimum voltage of a red data voltage supplied to a red sub-pixel, a green data voltage supplied to a green sub-pixel, and a blue data voltage supplied to a blue sub-pixel so as to drive each of the red light-emitting element, the green light-emitting element, and the blue light-emitting element within the maximum luminous efficiency range.

[0061] The gate driver 120 may be formed on the display panel 100 together with a thin film transistor (TFT) array and wirings of a pixel array. The gate driver 120 may be disposed in a non-display area NA outside a display area AA in the display panel 100, or may be at least partially disposed in the display area AA.

[0062] The gate driver 120 may be disposed in any one of a left non-display area NA and a right non-display area NA outside the display area AA in the display panel 100, and may supply a gate signal to the gate line 103 in a single-feed manner. In the single-feed manner, the gate signal is applied through one end of the gate line 103. The gate driver 120 may be disposed in the left non-display area NA and the right non-display area NA of the display panel 100, and may apply the gate signal to the gate line 103 in a dual-feed manner. In the dual-feed manner, the gate signal is applied simultaneously through both ends of the gate line 103. At least some circuits of the gate driver 120 may be disposed in the display area AA.

[0063] The gate driver 120 may include edge triggers and / or shift registers that output and shift pulses of the gate signal under the control of the timing controller 130. The gate signal may include a scan signal and an emission signal (hereinafter, an EM signal). In this case, the gate driver 120 may include a gate driver that outputs pulses of the scan signal and a gate driver that outputs pulses of the EM signal.

[0064] The timing controller 130 receives pixel data of an input image and a timing signal synchronized with the pixel data from the host system 200. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, etc. The vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted because the vertical period and the horizontal period can be known by counting the data enable signal DE. The data enable signal DE has a period of one horizontal period 1H.

[0065] The timing controller 130 may control the operation timings of the data driver 110 and the gate driver 120 based on the timing signals Vsync, Hsync, and DE received from the host system 200. In addition, the timing controller 130 may control the output timing of the power supply 140. For example, the timing controller 130 may separately control the application time of the pixel driving voltage VDD applied to the sub-pixels for each color sub-pixel by using a power supply enable signal.

[0066] The gate timing control signal output from the timing controller 130 can be input to the shift register of the gate driver 120 through the level shifter 150. The level shifter 150 can receive the gate timing control signal, generate a clock, and output it to the gate driver 120. The input signal of the level shifter 150 is a signal with a digital signal voltage level. The clock output from the level shifter 150 can swing between the gate high voltage and the gate low voltage. The data timing control signal generated from the timing controller 130 is sent to the data driver 110. The power enable signal output from the timing controller 130 can adjust the application time of the pixel driving voltage VDD applied to the sub-pixels of each color.

[0067] The EM signal and / or the power enable signal generated for the sub-pixels of each color can independently control the power application time or the emission time of the sub-pixels of each color to optimize the color coordinates and white balance of the pixel 101.

[0068] The host system 200 can scale the image signal from the video source to match the resolution of the display panel 100 and send it to the timing controller 130 together with the timing signal.

[0069] As Figure 2A 、 Figure 2B and Figure 2C shown, the display panel driving circuit may further include an over-brightness regulator 20 for independently controlling the emission time of the light-emitting elements for the sub-pixels of each color. The over-brightness regulator 20 can output a color-specific EM signal and / or a color-specific pixel driving voltage under the control of the timing controller 130 to reduce the excessive brightness of each color that deteriorates the color coordinates and brightness balance characteristics, thereby adjusting the color coordinates and brightness balance of the display device to an ideal target value.

[0070] In the display device of the present disclosure, each pixel may include a first sub-pixel that receives a first data voltage to drive a first light-emitting element, a second sub-pixel that receives a second data voltage to drive a second light-emitting element, and a third sub-pixel that receives a third data voltage to drive a third light-emitting element. At least one of the dynamic range, the maximum voltage, and the minimum voltage of the first data voltage, the second data voltage, and the third data voltage may be different from each other, and within one frame period, the emission time of the first light-emitting element, the emission time of the second light-emitting element, and the emission time of the third light-emitting element may be different from each other. Here, the first sub-pixel, the second sub-pixel, and the third sub-pixel may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively, but are not limited thereto. Each of the first sub-pixel, the second sub-pixel, and the third sub-pixel may use Figure 2A 、 Figure 2B and Figure 2C shown pixel circuit to drive the light-emitting element.

[0071] Figure 2A , Figure 2B and Figure 2C is a circuit diagram schematically showing a pixel circuit according to an embodiment of the present disclosure.

[0072] Reference Figure 2A , Figure 2B and Figure 2C , the pixel circuits of the first sub-pixel SP_R, the second sub-pixel SP_G and the third sub-pixel SP_B respectively include light emitting elements LD1, LD2 and LD3, driving elements DT1, DT2 and DT3, switching elements M11, M12 and M13 and a compensation circuit 10. Figure 2A , Figure 2B and Figure 2C In the embodiment of the present invention, the driving elements DT1, DT2, and DT3 and the switching elements M11, M12, and M13 are implemented as p-channel transistors, but are not limited thereto.

[0073] The light emitting elements LD1, LD2, and LD3 may be light emitting elements such as OLED or micro LED, but are not limited thereto. In the case of micro LED, it may have a vertical structure in which electrodes are provided at the top and bottom of the semiconductor chip in which the light emitting elements LD1, LD2, and LD3 are integrated, but is not limited thereto. The semiconductor chip in which the light emitting elements LD1, LD2, and LD3 are integrated may be implemented in a lateral structure or a flip chip structure.

[0074] The light emitting elements LD1, LD2 and LD3 may include an anode electrode and a cathode electrode. Figure 2A As shown, the anode electrodes of the light emitting elements LD1, LD2 and LD3 may be connected to a VDD node to which a pixel driving voltage VDD is applied, and the cathode electrodes thereof may be connected to the first electrodes of the switching elements M11, M12 and M13. Figure 2B As shown, the anode electrodes of the light emitting elements LD1, LD2 and LD3 may be connected to the VDD node to which the pixel driving voltage VDD is applied, and the cathode electrodes thereof may be connected to the first electrodes of the driving elements DT1, DT2 and DT3. Figure 2C As shown, anode electrodes of the light emitting elements LD1 , LD2 , and LD3 may be connected to the second electrodes of the driving elements DT1 , DT2 , and DT3 , and cathode electrodes thereof may be connected to a VSS node to which a pixel reference voltage VSS is applied.

[0075] The light emitting elements LD1 , LD2 , and LD3 , the driving elements DT1 , DT2 , and DT3 , and the switching elements M11 , M12 , and M13 may be connected in series between a VDD node and a VSS node.

[0076] The driving elements DT1, DT2, and DT3 regulate the current flowing through the light-emitting elements LD1, LD2, and LD3 based on their gate-source voltages, thereby driving the light-emitting elements LD1, LD2, and LD3. The gate-source voltages of the driving elements DT1, DT2, and DT3 vary according to the data voltage Vdata of the pixel data applied to the gate electrodes of the driving elements DT1, DT2, and DT3. The light-emitting elements LD1, LD2, and LD3 can be driven by the current from the driving elements DT1, DT2, and DT3 to emit light. The driving elements DT1, DT2, and DT3 include gate electrodes, first electrodes, and second electrodes. The gate electrodes and the first electrodes of the driving elements DT1, DT2, and DT3 can be connected to the compensation circuit 10. The first electrodes of the driving elements DT1, DT2, and DT3 can be connected to the second electrodes of the switching elements M11, M12, and M13 as shown in Figure 2A and 2C shown, or can be connected to the cathode electrodes of the light-emitting elements LD1, LD2, and LD3 as shown in Figure 2B shown. The second electrodes of the driving elements DT1, DT2, and DT3 can be connected to the VSS node as shown in Figure 2A shown, or can be connected to the first electrodes of the switching elements M11, M12, and M13 as shown in Figure 2B shown, or can be connected to the anode electrodes of the light-emitting elements LD1, LD2, and LD3 as shown in Figure 2C shown.

[0077] The switching elements M11, M12, and M13 switch the current paths of the light-emitting elements LD1, LD2, and LD3 between the pixel driving voltage VDD and the pixel reference voltage VSS in response to the EM signal EM. Each of the switching elements M11, M12, and M13 includes a gate electrode, a first electrode, and a second electrode. The EM signal EM is applied to the gate electrodes of the switching elements M11, M12, and M13. The EM signal EM can be output from the gate driver 120, or can be output through a separate switching circuit. The first electrodes of the switching elements M11, M12, and M13 can be connected to the cathode electrodes of the light-emitting elements LD1, LD2, and LD3 as shown in Figure 2A shown, or can be connected to the second electrodes of the driving elements DT1, DT2, and DT3 as shown in Figure 2B shown, or can be connected to the VDD node as shown in Figure 2C shown. The second electrodes of the switching elements M11, M12, and M13 can be connected to the first electrodes of the driving elements DT1, DT2, and DT3 as shown in Figure 2A and 2C shown, or can be connected to the VSS node as shown in Figure 2B shown.

[0078] The compensation circuit 10 may include a plurality of switching elements and capacitors. The compensation circuit 10 receives the data voltage Vdata of the pixel data and the scan signal SCAN, and applies the data voltage Vdata to the gate electrodes of the driving elements DT1, DT2, and DT3. The compensation circuit 10 may include an internal compensation circuit or an external compensation circuit. The internal compensation circuit samples the threshold voltages of the driving elements DT1, DT2, and DT3, and uses the threshold voltages to compensate the gate voltages of the driving elements DT1, DT2, and DT3. The external compensation circuit may modulate the pixel data of the input image in the timing controller 130 based on the result of sensing the first electrode voltages of the driving elements DT1, DT2, and DT3, thereby compensating for the deviation or change of the threshold voltages of the driving elements DT1, DT2, and DT3.

[0079] The red light-emitting element, the green light-emitting element, and the blue light-emitting element may emit light of different wavelengths and may have different maximum efficiency ranges. Under the control of the timing controller 130, the over-brightness regulator 20 may output color-specific EM signals and / or color-specific pixel driving voltages to reduce one or more excessive brightnesses of each color. The over-brightness regulator 20 may include a signal output circuit for emission and / or a pixel driving voltage output circuit.

[0080] Figure 3 is a schematic diagram schematically showing the sub-pixel structure of the transparent display device.

[0081] Referring to Figure 3 , the sub-pixel SP of the transparent display device includes a pixel circuit, and a light-emitting portion CIR and a transmissive portion TA.

[0082] The pixel circuit and the light-emitting portion CIR include a circuit region provided with the pixel circuit and the light-emitting element, and an emission region of the light-emitting element. The pixel circuit may be connected to a data line to which the data voltage Vdata is applied, a gate line to which the scan signal SCAN is applied, an EM line to which the EM signal EM is applied, and power supply lines to which the pixel driving voltage VDD and the pixel reference voltage VSS are separately applied.

[0083] The transmissive portion TA is a transparent region through which light passes without metal wirings blocking the light. The transmissive portion TA may be about 50% to 80% of the total area of the sub-pixel SP, but is not limited thereto. The real object outside the display panel 100 can be seen through the transmissive portion TA.

[0084] Figure 4 is a graph showing the current density and efficiency ratio characteristics of the light-emitting elements of each color. In Figure 4 , the horizontal axis represents the current density (A / cm 2 ), and the vertical axis represents the efficiency ratio of the light-emitting elements of each color relative to the reference efficiency when the reference efficiency is 1.Figure 4 The current density to efficiency ratio of the light-emitting elements of each color shown is a normalized value. As Figure 4 shown, the red light-emitting element R, the green light-emitting element G, and the blue light-emitting element B may have different maximum luminous efficiency ranges. It is possible to set the data voltage Vdata as Figure 5 shown such that the driving current regions of the light-emitting elements R, G, and B of each color include the maximum luminous efficiency range.

[0085] Figure 5 is a schematic diagram showing an example of the data voltage of each color according to an embodiment of the present disclosure.

[0086] Referring to Figure 5 , the data voltage Vdata of each color has a dynamic range between a minimum voltage Vmin (e.g., the minimum possible voltage within the dynamic range) and a maximum voltage Vmax (e.g., the maximum possible voltage within the dynamic range). Within the dynamic range of each data voltage Vdata, a data voltage corresponding to the gray scale value of the pixel data is output from the data driver 110 and applied to the gate electrode of the driving element. In the case of the pixel circuit based on a p-channel transistor shown in Figure 2A , 2B and 2C, the minimum voltage Vmin of the data voltage Vdata is the white gray scale voltage when the luminance of the sub-pixel is the highest, and the maximum voltage Vmax of the data voltage Vdata is the black gray scale voltage when the light-emitting element does not emit light.

[0087] The maximum voltage Vmax of the red data voltage Vdata(R) may be higher than the maximum voltage Vmax of each of the green data voltage Vdata(G) and the blue data voltage Vdata(B). The maximum voltage Vmax of the green data voltage Vdata(G) may be higher than the maximum voltage Vmax of the blue data voltage Vdata(B). The minimum voltage Vmin of the red data voltage Vdata(R) may be equal to or similar to the minimum voltage Vmin of the green data voltage Vdata(G) and may be higher than the minimum voltage Vmin of the blue data voltage Vdata(B). The minimum voltage Vmin of the blue data voltage Vdata(B) may be lower than the minimum voltage Vmin of each of the red data voltage Vdata(R) and the green data voltage Vdata(G).

[0088] The data voltage of each color of the present disclosure is not limited to Figure 5 . For example, depending on the material characteristics or chip characteristics of the light-emitting element, the maximum luminous efficiency range of the light-emitting element may be the same as Figure 4The maximum luminous efficiency ranges are different. In the following, the description will focus on multiple embodiments in which color-specific EM signals and / or color-specific pixel driving voltages are used to reduce the excessive luminance values of each color caused by the increase in the data voltage when the data voltage is set as shown in Figure 5 so that the light-emitting elements can operate within the maximum luminous efficiency range of the sub-pixels of each color, but the present disclosure is not limited thereto. In the following embodiments, the red sub-pixel, the green sub-pixel, and the blue sub-pixel may be interpreted as the first sub-pixel, the second sub-pixel, and the third sub-pixel, respectively.

[0089] When the data voltage Vdata is increased to use the maximum luminous efficiency range of the light-emitting elements LD of each color, the luminance of a specific color may increase excessively, resulting in the color coordinates and white balance deviating from the target values. In the present disclosure, the emission time can be independently controlled for each color so that the light-emitting elements LD operate within the maximum luminous efficiency range of each color, and the color coordinates and white balance satisfy the target values.

[0090] Figure 6 is a circuit diagram showing a pixel circuit according to an embodiment of the present disclosure. As shown in Figure 2A , Figure 2B and Figure 2C shown, the pixel circuit of the present disclosure is not limited to Figure 6 .

[0091] Referring to Figure 6 , each of the red sub-pixel, the green sub-pixel, and the blue sub-pixel includes a pixel circuit. The pixel circuit includes a light-emitting element LD, a driving element DT for driving the light-emitting element LD, and a compensation circuit 10. The driving element DT and the switching elements M1, M2, and M3 may be implemented as p-channel transistors, but are not limited thereto.

[0092] The pixel circuit is connected to a data line to which a data voltage Vdata is applied, a gate line to which a scan signal SCAN is applied, and a constant voltage node to which a direct current voltage (or a constant voltage) is applied, such as a VDD node (e.g., a first node) to which a pixel driving voltage VDD is applied, a VSS node (e.g., a second node) to which a pixel reference voltage VSS is applied, and a REF node to which a reference voltage Vref is applied. The constant voltage node is connected to a power supply line provided on the display panel 100, and the power supply line may be commonly connected to all pixels.

[0093] The data voltage Vdata can be selected in the voltage range from 0V to 16V. For each color sub-pixel, at least one of the maximum voltage, minimum voltage, and dynamic range of the data voltage Vdata can be set to be different from each other, so that the light-emitting element of the corresponding color can be driven with the maximum luminous efficiency. The reference voltage Vref can be a voltage selected in the voltage range from 7V to 11V. The pixel driving voltage VDD can be a voltage selected in the voltage range from 6V to 12V, and the pixel reference voltage VSS can be 0V, but the present disclosure is not limited thereto. The gate high voltage VGH of the scan signal SCAN and the EM signal EM can be a voltage selected from 12V to 20V, and its gate low voltage VGL can be a voltage selected from -19V to -12V, but it is not limited thereto. Hereinafter, "VGL" will be referred to as the gate conduction voltage, and "VGH" will be referred to as the gate cut-off voltage. However, in some embodiments, the gate high voltage VGH can be used as the gate conduction voltage, and the gate low voltage VGL can be used as the gate cut-off voltage.

[0094] The driving element DT includes a first electrode connected to the first node S, a gate electrode connected to the second node G, and a second electrode connected to the VSS node. The light-emitting element LD includes an anode electrode connected to the VDD node and a cathode electrode connected to the first electrode of the first switching element M1. The storage capacitor Cst is connected between the first node S and the second node G to charge the gate-source voltage of the driving element DT.

[0095] The first switching element M1 is turned on in response to the gate conduction voltage VGL of the EM signal EM. When the first switching element M1 is turned on, a current path can be electrically connected between the light-emitting element LD and the driving element DT, so that a current flows through the light-emitting element LD, thereby allowing the light-emitting element LD to emit light. The first switching element M1 includes a first electrode connected to the cathode electrode of the light-emitting element LD, a gate electrode connected to the EM line to which the EM signal EM is applied, and a second electrode connected to the first node S.

[0096] The second switching element M2 is connected between the data line to which the data voltage Vdata is applied and the second node G, and is turned on in response to the gate conduction voltage VGL of the scan signal SCAN. When the second switching element M2 is turned on, the data voltage Vdata is applied to the second node G. The second switching element M2 includes a first electrode connected to the data line, a second electrode connected to the second node G, and a gate electrode connected to the gate line to which the scan signal SCAN is applied. The second switching element M2 can be implemented in a double-gate structure, in which two transistors are connected in series to reduce leakage current, but it is not limited thereto.

[0097] The third switching element M3 is connected between the REF node to which a reference voltage Vref is applied and the first node S, and is turned on in response to the gate-on voltage VGL of the scan signal SCAN. When the third switching element M3 is turned on, the reference voltage Vref is applied to the first node S. The third switching element M3 includes a first electrode connected to the REF node, a second electrode connected to the first node S, and a gate electrode connected to the gate line to which the scan signal SCAN is applied.

[0098] Figure 7 is a waveform diagram showing signals applied to a pixel circuit according to an embodiment of the present disclosure.

[0099] Referring to Figure 7 , the scan signals SCAN(n) to SCAN(n + 2) include pulses of scan signals sequentially applied to the nth (where n is a natural number) to the (n + 1)th pixel lines. The pulses of the scan signals SCAN(n) to SCAN(n + 2) swing between the gate-on voltage VGL and the gate-off voltage VGH, and are synchronized with the data voltages Vdata(n) to Vdata(n + 2). When the pulses of the data voltages Vdata(n) to Vdata(n + 2) and the scan signals SCAN(n) to SCAN(n + 2) are applied simultaneously, the data voltage Vdata of the pixel data is applied to the sub-pixels of the corresponding pixel line, thereby programming the sub-pixels. Programming can be interpreted as scanning or data addressing. During one horizontal period, all the sub-pixels of one pixel line are programmed, and during one frame period, the sub-pixels of all the pixel lines L1 to Ln in the display area can be programmed sequentially on a line-by-line basis.

[0100] The EM signal EM includes a first EM signal EM_R, a second EM signal EM_G, and a third EM signal EM_B. Each of the first EM signal EM_R, the second EM signal EM_G, and the third EM signal EM_B includes a pulse of the gate-on voltage VGL applied to the sub-pixels after programming all the sub-pixels of all the pixel lines L1 to Ln in the display area AA.

[0101] Pulses of the first EM signal EM_R are applied to the first switching element M1 of the red sub-pixel to control the emission time of the red sub-pixel. Pulses of the second EM signal EM_G are applied to the first switching element M1 of the green sub-pixel to control the emission time of the green sub-pixel. Pulses of the third EM signal EM_B are applied to the first switching element M1 of the blue sub-pixel to control the emission time of the blue sub-pixel. The pulse widths of the second EM signal EM_G and the third EM signal EM_B are different from each other. The pulse width can be interpreted as the duration of the gate-on voltage. For example, within one frame period, the pulse width W1 of the first EM signal EM_R can be less than the pulse widths W2 and W3 of the second EM signal EM_G and the third EM signal EM_B. The pulse width W2 of the second EM signal EM_G can be greater than the pulse widths W1 and W3 of the first EM signal EM_R and the third EM signal EM_B. The pulse width W3 of the third EM signal EM_B can be greater than the pulse width W1 of the first EM signal EM_R and less than the pulse width W2 of the second EM signal EM_G. In this case, within each frame period, among the red sub-pixel, the green sub-pixel, and the blue sub-pixel, the emission time of the red sub-pixel can be the shortest, and the emission time of the green sub-pixel can be the longest.

[0102] Figure 8 is a schematic diagram showing an emission signal output circuit according to an embodiment of the present disclosure.

[0103] Referring to Figure 8 , the gate driver 120 may include a first EM driver 122R that outputs the first EM signal EM_R, a second EM driver 122G that outputs the second EM signal EM_G, and a third EM driver 122B that outputs the third EM signal EM_G.

[0104] The first EM driver 122R can output the first EM signal EM_R to the first EM line 81 connected to the red sub-pixel SP_R while shifting the pulses of the first EM signal EM_R. The first EM line 81 (one of each of the pixel lines L1 to Ln) may be arranged in a direction (X-axis direction) parallel to the gate line. The second EM driver 122G can output the second EM signal EM_G to the second EM line 82 connected to the green sub-pixel SP_G while shifting the pulses of the second EM signal EM_G. The second EM line 82 (one of each of the pixel lines L1 to Ln) may be arranged in a direction parallel to the gate line. The third EM driver 122B can output the third EM signal EM_B to the third EM line 83 connected to the blue sub-pixel SP_B while shifting the pulses of the third EM signal EM_B. The third EM line 83 (one of each of the pixel lines L1 to Ln) may be arranged in a direction parallel to the gate line.

[0105] Figure 9 is a schematic diagram showing a transmission signal output circuit according to another embodiment of the present disclosure. In this embodiment, compared with Figure 8 the embodiment shown, the number of wirings for applying the EM signal in the display area AA can be reduced, thereby improving the aperture ratio of the pixels and further increasing the transparency in the transparent display device. In Figure 9 , components substantially the same as those in the embodiment shown in the above Figure 8 are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0106] Referring to Figure 9 , the first EM line 81 includes branch lines 81a. One or more branch lines 81a branch from each of the first EM lines 81 and are arranged in a direction parallel to the data lines (Y-axis direction). Each of the first EM lines 81 can be connected to the red sub-pixels SP_R arranged on a plurality of pixel lines (e.g., three pixel lines L1, L2, and L3) through the branch lines 81a to simultaneously supply the first EM signal EM_R to the red sub-pixels SP_R in the pixel lines L1, L2, and L3. That is, the first EM driver 122R simultaneously applies the first EM signal EM_R to the red sub-pixels SPR_R located on different pixel lines. Therefore, the number of channels of the first EM driver 122R and the number of the first EM lines 81 can be reduced.

[0107] The second EM line 82 includes branch lines 82a. One or more branch lines 82a branch from each of the second EM lines 82 and are arranged in a direction parallel to the data lines (Y-axis direction). Each of the second EM lines 82 can be connected to the green sub-pixels SP_G provided on a plurality of pixel lines (e.g., three pixel lines L1, L2, and L3) through the branch lines 82a. Therefore, the second EM driver 122G simultaneously applies the second EM signal EM_G to the green sub-pixels SPR_G located on different pixel lines. Therefore, the number of channels of the second EM driver 122G and the number of the second EM lines 82 can be reduced.

[0108] The third EM line 83 includes branch lines 83a. One or more branch lines 83a branch from each of the third EM lines 83 and are arranged in a direction parallel to the data lines (Y-axis direction). Each of the third EM lines 83 can be connected to the blue sub-pixels SP_B provided on a plurality of pixel lines (e.g., three pixel lines L1, L2, and L3) through the branch lines 83a. Therefore, the third EM driver 122B simultaneously applies the third EM signal EM_B to the blue sub-pixels SPR_B located on different pixel lines. Therefore, the number of channels of the third EM driver 122B and the number of the third EM lines 83 can be reduced.

[0109] Figure 10 It is a schematic diagram showing an example of the emission time of sub-pixels of each color.

[0110] Reference Figure 10 , for the EM signals EM_R, EM_G, and EM_B of each color, the emission times of the sub-pixels SP_R, SP_G, and SP_B of each color can be independently controlled.

[0111] When increasing the data voltage to drive each of the red light-emitting element, green light-emitting element, and blue light-emitting element with maximum driving efficiency, the EM signals EM_R, EM_G, and EM_B can use the emission time to reduce the excessive brightness value of each color, so as to adjust the color coordinates and white balance of the display device to the ideal target values. For example, in the red sub-pixel SP_R, when as Figure 5 shown, the data voltage Vdata is increased to drive the red light-emitting element with maximum luminous efficiency, the brightness of the red sub-pixel may become too high. In this case, the pulse width of the first EM signal EM_R can be set to be less than the pulse widths of the other EM signals EM_G and EM_B, so that the emission time of the red light-emitting element can be reduced compared with the emission times of the light-emitting elements of other colors.

[0112] Figure 11 It is a schematic diagram showing an emission signal output circuit according to another embodiment of the present disclosure.

[0113] Referring to Figure 11 , the display device of the present disclosure may further include a switching circuit 160 that outputs EM signals of each color.

[0114] The switching circuit 160 outputs the EM signals EM_R, EM_G, and EM_B under the control of the timing controller 130 for independently adjusting the emission times of the sub-pixels SP_R, SP_G, and SP_B of each color. The switching circuit 160 includes a first switching element SW1 that outputs the first EM signal EM_R through the output terminal of the first channel, a second switching element SW2 that outputs the second EM signal EM_G through the output terminal of the second channel, and a third switching element SW3 that outputs the third EM signal EM_B through the output terminal of the third channel. Each of the switching elements SW1, SW2, and SW3 can be turned on / off under the control of the timing controller 130 to supply the gate-on voltage VGL and gate-off voltage VGH to the corresponding EM lines 91, 92, and 93, thereby outputting the EM signals EM_R, EM_G, and EM_B. The switching elements SW1, SW2, and SW3 can each be implemented as one or more transistors or multiplexers.

[0115] In the non-display area NA of the display panel 100, EM lines 91, 92, and 93 can be set in a direction parallel to the gate lines (X-axis direction). The EM lines 91, 92, and 93 can respectively include branch lines 91a, 92a, and 93a. One or more first branch lines 91a branch from the first EM line 91 and extend in a direction parallel to the data lines (Y-axis direction) to connect to the red sub-pixels SP_R in the display area AA. One or more second branch lines 92a branch from the second EM line 92 and extend in a direction parallel to the data lines (Y-axis direction) to connect to the green sub-pixels SP_G in the display area AA. One or more third branch lines 93a branch from the third EM line 93 and extend in a direction parallel to the data lines (Y-axis direction) to connect to the blue sub-pixels SP_B in the display area AA.

[0116] The first switching element SW1 outputs a pulse of the first EM signal EM_R to the first EM line 91 connected to the red sub-pixel SP_R. The first EM signal EM_R can be applied to the red sub-pixels SP_R on different pixel lines through the first branch line 91a to adjust the emission time of the red light-emitting element according to its pulse width. The second switching element SW2 outputs a pulse of the second EM signal EM_G to the second EM line 92 connected to the green sub-pixel SP_G. The second EM signal EM_G can be applied to the green sub-pixels SP_G on different pixel lines through the second branch line 92a to adjust the emission time of the green light-emitting element according to its pulse width. The third switching element SW3 outputs a pulse of the third EM signal EM_B to the third EM line 93 connected to the blue sub-pixel SP_B. The third EM signal EM_B can be applied to the blue sub-pixels SP_B on different pixel lines through the third branch line 93a to adjust the emission time of the blue light-emitting element according to its pulse width.

[0117] Figure 12 is a waveform diagram showing an example of each color of EM signal output from Figure 11 the emission signal output circuit shown.

[0118] Reference Figure 12 , when increasing the data voltage so as to drive each of the red light-emitting element, the green light-emitting element, and the blue light-emitting element with maximum driving efficiency, each color of EM signals EM_R, EM_G, and EM_B can reduce the excessive brightness value of each color to adjust the color coordinates and white balance of the display device to an ideal target value. For example, the pulse width of the first EM signal EM_R can be set to be smaller than the pulse widths of the other EM signals EM_G and EM_B, such that the emission time of the red light-emitting element can be reduced compared to the emission times of the light-emitting elements of other colors.

[0119] In another embodiment of the present disclosure, the data voltage is increased to drive each of the red light-emitting element, the green light-emitting element, and the blue light-emitting element with maximum driving efficiency, but the excessive brightness value of each color can be reduced by using the pixel driving voltage of each color. The pixel driving voltage of each color can be applied together with the EM signals EM_R, EM_G, and EM_B of each color.

[0120] Figure 13 is a circuit diagram showing a pixel circuit according to another embodiment of the present disclosure. In this embodiment, components substantially the same as those in the Figure 6 shown pixel circuit are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0121] Referring to Figure 13 , the pixel circuit includes a light-emitting element LD, a driving element DT for driving the light-emitting element LD, and a compensation circuit 10. The compensation circuit 10 is substantially the same as the compensation circuit shown in Figure 6 . The driving element DT and the switching elements M2 and M3 can be implemented as p-channel transistors, but are not limited thereto. In this embodiment, the first switching element that turns on / off in response to the EM signal can be omitted, but the present disclosure is not limited thereto.

[0122] The pixel driving voltage VDD is separated by color. The first pixel driving voltage VDD_R is applied to the VDD node of the red sub-pixel SP_R, and the second pixel driving voltage VDD_G is applied to the VDD node of the green sub-pixel SP_G. The third pixel driving voltage VDD_B is applied to the VDD node of the blue sub-pixel SP_B. The light-emitting element LD includes an anode electrode connected to the VDD node and a cathode electrode connected to the first node S. The second and third switching elements M2 and M3 are turned on in response to the gate conduction voltage VGL of the scan signal SCAN and are turned off in response to the gate cut-off voltage VGH of the scan signal SCAN.

[0123] Figure 14 is a waveform diagram showing an example of the pixel driving voltage of each color.

[0124] Referring to Figure 14 , the pixel driving voltages VDD_R, VDD_G, and VDD_B of each color are applied to the VDD node of the pixel circuit corresponding to the emission time set for each color of the sub-pixels SP_R, SP_G, and SP_B. When the pixel driving voltages VDD_R, VDD_G, and VDD_B of each color are applied to the corresponding VDD nodes of the pixel circuit, a current can be applied to the light-emitting element LD so that the light-emitting element LD emits light. When the pixel driving voltages VDD_R, VDD_G, and VDD_B of each color are not applied, no current flows through the light-emitting element LD, so that the light-emitting element LD does not emit light.

[0125] The pixel driving voltages VDD_R, VDD_G, and VDD_B for each color can reduce the excessive luminance values for each color. For example, in each frame period, the application time (e.g., the first duration) of the first pixel driving voltage VDD_R within a frame period can be set to be less than the application time (e.g., the second duration) of the second pixel driving voltage VDD_G and the application time of the third pixel driving voltage VDD_B, such that the emission time of the red light-emitting elements can be reduced compared to the emission times of the light-emitting elements of other colors. In each frame period, the application time of the third pixel driving voltage VDD_B can be set to be greater than the application time of the first pixel driving voltage VDD_R and less than the application time of the second pixel driving voltage VDD_G.

[0126] Figure 15 is a schematic diagram showing a pixel driving voltage output circuit according to an embodiment of the present disclosure.

[0127] Referring to Figure 15 , the pixel driving voltage output circuit switches the pixel driving voltage VDD output from the power supply 140 under the control of the timing controller 130 to output the pixel driving voltages VDD_R, VDD_G, and VDD_B for each color. The pixel driving voltage output circuit includes a first switching element TR_R, a second switching element TR_G, and a third switching element TR_B. Each of the switching elements TR_R, TR_G, and TR_B can be implemented as a p-channel transistor, but is not limited thereto.

[0128] The timing controller 130 can control the pixel driving voltage output circuit by generating a power supply enable signal for separately controlling the on / off timing of each of the switching elements TR_R, TR_G, and TR_B. The power supply enable signal output from the timing controller 130 is converted by a level shifter 150 into a first power supply enable signal EN_R, a second power supply enable signal EN_G, and a third power supply enable signal EN_B that swing between a gate conduction voltage VGL and a gate cutoff voltage VGH.

[0129] The first switching element TR_R is turned on in response to the gate conduction voltage VGL of the first power enable signal EN_R to supply the pixel driving voltage VDD to the first VDD power line 151. The first VDD power line 151 is connected to the VDD node of the red sub-pixel SP_R. The second switching element TR_G is turned on in response to the gate conduction voltage VGL of the second power enable signal EN_G to supply the pixel driving voltage VDD to the second VDD power line 152. The second VDD power line 152 is connected to the VDD node of the green sub-pixel SP_G. The third switching element TR_B is turned on in response to the gate conduction voltage VGL of the third power enable signal EN_B to supply the pixel driving voltage VDD to the third VDD power line 153. The third VDD power line 153 is connected to the VDD node of the blue sub-pixel SP_B.

[0130] Figure 16 is a schematic diagram showing a pixel driving voltage output circuit according to another embodiment of the present disclosure. In this embodiment, components substantially the same as those in the Figure 15 circuit shown are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0131] Referring to Figure 16 , the pixel driving voltage output circuit includes a first VDD output unit 141 (e.g., a first circuit), a second VDD output unit 142 (e.g., a second circuit), and a third VDD output unit 143 (e.g., a third circuit) that output pixel driving voltages under the control of the timing controller 130. The output timings of the first VDD output unit 141, the second VDD output unit 142, and the third VDD output unit 143 can be independently controlled by the timing controller 130. The first VDD output unit 141, the second VDD output unit 142, and the third VDD output unit 143 can output pixel driving voltages at the same voltage level, or can output pixel driving voltages at different voltage levels for each color sub-pixel.

[0132] The timing controller 130 can control the pixel driving voltage output circuit by generating power enable signals EN_R, EN_G, and EN_B that independently control the output timings of the VDD output units 141, 142, and 143. The first VDD output unit 141 supplies the first pixel driving voltage VDD_R to the first VDD power line 151 in response to the first power enable signal EN_R. The second VDD output unit 142 supplies the second pixel driving voltage VDD_G to the second VDD power line 152 in response to the second power enable signal EN_G. The third VDD output unit 143 supplies the third pixel driving voltage VDD_B to the third VDD power line 153 in response to the third power enable signal EN_B.

[0133] In each frame period, after programming of all sub-pixels in the display area AA is completed, the sub-pixels SP_R, SP_G, and SP_B can emit light. The emission times of the sub-pixels SP_R, SP_G, and SP_B can be controlled to be different from each other by using the EM signals EM_R, EM_G, and EM_B of each color and / or by using the pixel driving voltages VDD_R, VDD_G, and VDD_B of each color. For example, the emission time of the red sub-pixel SP_R can be less than the emission times of the green sub-pixel SP_G and the blue sub-pixel SP_B. The emission time of the blue sub-pixel SP_B can be greater than the emission time of the red sub-pixel SP_R and less than the emission time of the green sub-pixel SP_B.

[0134] Figures 17 to 19 is a diagram showing various embodiments of a method for controlling the emission times of sub-pixels of each color.

[0135] Referring to Figure 17 , the emission times of the sub-pixels SP_R, SP_G, and SP_B can overlap on the time axis. At least two of the emission time of the first sub-pixel SP_R, the emission time of the second sub-pixel SP_G, and the emission time of the third sub-pixel SP_B can overlap on the time axis. For example, after the green sub-pixel SP_G starts to emit light, the blue sub-pixel SP_B can start to emit light while the green sub-pixel SP_G is emitting light. Subsequently, when the green and blue sub-pixels SP_G and SP_B are emitting light, the red sub-pixel SP_R can start to emit light. Before the emission times of the green sub-pixel SP_G and the blue sub-pixel SP_B end, the emission time of the red sub-pixel SP_R can end. After the emission time of the red sub-pixel SP_R ends, the emission time of the blue sub-pixel SP_B can end, and then the emission time of the green sub-pixel SP_G can end.

[0136] Referring to Figure 18 and Figure 19 , the emission times of the sub-pixels SP_R, SP_G, and SP_B can be separated on the time axis. For example, after the emission time of the red sub-pixel SP_R ends, the emission time of the blue sub-pixel SP_B can start. Subsequently, after the emission time of the blue sub-pixel SP_B ends, the emission time of the green sub-pixel SP_G can start. Therefore, the emission times of the red, green, and blue sub-pixels do not overlap in time. As Figure 19 shown, the emission time of each color can be repeated two or more times within one frame period. In these embodiments, compared with the embodiments shown in Figure 17 , since the current flowing through the light-emitting element LD is separated in time (e.g., does not overlap in time), the heat generation of the display panel 100 can be further reduced.

[0137] Depending on the efficiency of the light-emitting elements of each color or the operating environment of the display device, the emission times of the sub-pixels SP_R, SP_G, and SP_B can be controlled by any one of the methods shown in Figure 17 , Figure 18 and Figure 19 or a combination of two or more of the methods. For example, during the Nth frame period, the emission times of the sub-pixels SP_R, SP_G, and SP_B can be controlled by the emission time control method of any one of Figure 17 , 18 and 19, and during the (N + 1)th frame period, the emission time can be controlled by another emission time control method.

[0138] According to one or more embodiments of the present disclosure, the display device can be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved surface devices, sliding devices, variable devices, electronic notepads, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbook computers, workstations, navigators, vehicle navigations, vehicle display devices, vehicle devices, theater devices, theater display devices, TVs, wallpaper devices, billboard devices, game devices, laptop computers, monitors, cameras, video cameras, and household appliances, etc. The display device according to one or more embodiments of the present disclosure can be applied to an organic light-emitting lighting device or an inorganic light-emitting lighting device.

[0139] The objects to be achieved by the present disclosure, the means for achieving the above objects of the present disclosure, and the effects are not essential features for defining the claims. Therefore, the scope of the claims is not limited to the disclosure of the present disclosure.

[0140] Although the embodiments of the present disclosure have been described in more detail with reference to the drawings, the present disclosure is not limited thereto and can be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all aspects and do not limit the present disclosure.

Claims

1. A display device, comprising: a first sub-pixel including a first light emitting element, the first sub-pixel being configured to receive a first data voltage and drive the first light emitting element using the first data voltage; a second sub-pixel including a second light emitting element, the second sub-pixel being configured to receive a second data voltage and drive the second light emitting element using the second data voltage; a third sub-pixel including a third light emitting element, the third sub-pixel being configured to receive a third data voltage and drive the third light emitting element using the third data voltage; as well as a brightness adjuster circuit configured to reduce the brightness of at least one of the first sub-pixel, the second sub-pixel, or the third sub-pixel, wherein a first emission time of the first light emitting element at which the first light emitting element emits light, a second emission time of the second light emitting element at which the second light emitting element emits light, and a third emission time of the third light emitting element at which the third light emitting element emits light are different from each other.

2. The display device of claim 1 , wherein a maximum possible voltage of the first data voltage is higher than a maximum possible voltage of each of the second data voltage and the third data voltage, and a minimum possible voltage of the first data voltage is equal to a minimum possible voltage of the second data voltage and higher than a minimum possible voltage of the third data voltage.

3. The display device of claim 2, wherein a maximum possible voltage of the second data voltage is higher than a maximum possible voltage of the third data voltage, and a minimum possible voltage of the third data voltage is lower than a minimum possible voltage of each of the first data voltage and the second data voltage.

4. The display device according to claim 1, wherein at least one of the dynamic ranges of the first data voltage, the second data voltage, and the third data voltage, the maximum voltages of the first data voltage, the second data voltage, and the third data voltage, and the minimum voltages of the first data voltage, the second data voltage, and the third data voltage are different from each other.

5. The display device according to claim 1, wherein: The first sub-pixel includes a first driving transistor and a first switching transistor connected in series with the first light emitting element between a first node to which a pixel driving voltage is applied and a second node to which a pixel reference voltage is applied. wherein the second sub-pixel includes a second driving transistor and a second switching transistor connected in series with the second light emitting element between the first node and the second node, and The third sub-pixel includes a third driving transistor and a third switching transistor which are connected in series with the third light emitting element between the first node and the second node.

6. The display device according to claim 5, wherein: The brightness adjuster circuit is configured to output a first emission signal to the first switch transistor, a second emission signal to the second switch transistor, and a third emission signal to the third switch transistor, wherein the first switch transistor is turned on in response to the gate-on voltage of the first emission signal and electrically connects a current path between the first light-emitting element and the first driving transistor, wherein the second switch transistor is turned on in response to the gate-on voltage of the second emission signal and electrically connects a current path between the second light emitting element and the second driving transistor, and The third switch transistor is turned on in response to the gate-on voltage of the third emission signal, and electrically connects a current path between the third light-emitting element and the third driving transistor.

7. The display device according to claim 6, wherein: The duration of the gate-on voltage of the first emission signal is shorter than the duration of the gate-on voltage of the second emission signal and the duration of the gate-on voltage of the third emission signal, wherein the duration of the gate-on voltage of the second emission signal is greater than the duration of the gate-on voltage of the first emission signal and the duration of the gate-on voltage of the third emission signal, The duration of the gate-on voltage of the third emission signal is greater than the duration of the gate-on voltage of the first emission signal and less than the duration of the gate-on voltage of the second emission signal.

8. The display device according to claim 7, wherein: Each of the first sub-pixel, the second sub-pixel and the third sub-pixel further comprises: a second switching transistor configured to apply a corresponding one of a first data voltage, a second data voltage, or a third data voltage applied through the data line to a gate electrode of a corresponding one of the first driving transistor, the second driving transistor, or the third driving transistor in response to a gate-on voltage of a scan signal applied through the gate line; and A third switching transistor is configured to apply a reference voltage to a first electrode of a corresponding one of the first driving transistor, the second driving transistor, or the third driving transistor in response to the gate-on voltage of the scan signal.

9. The display device according to claim 8, further comprising: a first gate driver configured to output the scanning signal; a first transmit driver configured to output the first transmit signal; a second transmit driver configured to output the second transmit signal; as well as The third transmit driver is configured to output the third transmit signal.

10. The display device according to claim 9, wherein: The first emission driver provides the first emission signal to a plurality of first sub-pixels including the first sub-pixels through a first emission signal line that is parallel to the gate and provided for each pixel line, wherein the second emission driver provides the second emission signal to a plurality of second sub-pixels including the second sub-pixels through a second emission signal line that is parallel to the gate line and is provided for each pixel line, The third emission driver provides the third emission signal to a plurality of third sub-pixels including the third sub-pixel through a third emission signal line that is parallel to the gate line and is provided for each pixel line.

11. The display device according to claim 9, wherein: The first emission signal output from the first emission driver is simultaneously provided to first sub-pixels located on different pixel lines among a plurality of first sub-pixels, wherein the second emission signal outputted from the second emission driver is simultaneously provided to second sub-pixels located on different pixel lines among a plurality of second sub-pixels, wherein the third emission signal outputted from the third emission driver is simultaneously provided to third sub-pixels located on different pixel lines among a plurality of third sub-pixels, One channel of the first emission driver is connected to a first sub-pixel arranged on a different pixel line through a first emission signal line parallel to the gate line and a first branch line branched from the first emission signal line in a direction parallel to the data line, one channel of the second emission driver is connected to a second sub-pixel arranged on a different pixel line through a second emission signal line parallel to the gate line and a second branch line branched from the second emission signal line in a direction parallel to the data line, and One channel of the third emission driver is connected to third subpixels arranged on different pixel lines through a third emission signal line parallel to the gate line and a third branch line branched from the third emission signal line in a direction parallel to the data line.

12. The display device according to claim 8, further comprising: a switch circuit configured to output the first transmit signal via a first channel of the switch circuit, output the second transmit signal via a second channel of the switch circuit, and output the third transmit signal via a third channel of the switch circuit, wherein the first emission signal output from the first channel of the switch circuit is applied to a first sub-pixel among a plurality of first sub-pixels arranged in different pixel lines among a plurality of pixel lines through a first emission signal line parallel to a gate line in a non-display area of ​​the display device and a first branch line branched from the first emission signal line in a direction parallel to a data line, wherein the second emission signal output from the second channel of the switch circuit is applied to second sub-pixels among a plurality of second sub-pixels arranged on different pixel lines through a second emission signal line parallel to a gate line in a non-display area of ​​the display device and a second branch line branched from the second emission signal line in a direction parallel to a data line, and In which, the third emission signal output from the third channel of the switching circuit is applied to the third sub-pixels of multiple third sub-pixels arranged in different pixel lines through a third emission signal line parallel to the gate line in the non-display area of ​​the display device and a third branch line branched from the third emission signal line in a direction parallel to the data line.

13. The display device according to claim 1, wherein: The first sub-pixel is connected to a first VDD node to which a first pixel driving voltage is applied, the second sub-pixel is connected to a second VDD node to which a second pixel driving voltage is applied, and the third sub-pixel is connected to a third VDD node to which a third pixel driving voltage is applied, and The brightness adjuster circuit is configured to individually control the first pixel driving voltage applied to the first sub-pixel, the second pixel driving voltage applied to the second sub-pixel, and the third pixel driving voltage applied to the third sub-pixel, so that the first emission time of the first light-emitting element, the second emission time of the second light-emitting element, and the third emission time of the third light-emitting element are different from each other.

14. The display device according to claim 13, wherein: A first duration of applying the first pixel driving voltage to the first VDD node of the first sub-pixel in one frame period is shorter than a second duration of applying the second pixel driving voltage to the second VDD node of the second sub-pixel and a third duration of applying the three pixel driving voltages to the third VDD node of the third sub-pixel, wherein the third duration of applying the third pixel driving voltage to the third VDD node of the third sub-pixel within one frame period is greater than the first duration of applying the first pixel driving voltage to the first VDD node of the first sub-pixel, and is less than the second duration of applying the second pixel driving voltage to the second VDD node of the second sub-pixel.

15. The display device according to claim 13, further comprising: a power supply configured to output the first pixel driving voltage, the second pixel driving voltage and the third pixel driving voltage; and a level shifter configured to output a first power enable signal, a second power enable signal, and a third power enable signal, Wherein, the brightness adjuster circuit comprises: a first switch transistor configured to provide the first pixel driving voltage to a first VDD power line in response to the first power enable signal; a second switching transistor configured to provide the second pixel driving voltage to a second VDD power line in response to the second power enable signal; and a third switch transistor configured to provide the third pixel driving voltage to a third VDD power line in response to the third power enable signal, wherein the first VDD power line is connected to the first VDD nodes of a plurality of first sub-pixels including the first sub-pixel, The second VDD power line is connected to the second VDD nodes of a plurality of second sub-pixels including the second sub-pixel, and The third VDD power line is connected to the third VDD nodes of the plurality of third sub-pixels of the third sub-pixels.

16. The display device according to claim 13, wherein the brightness adjuster circuit comprises: a first VDD output section configured to provide the first pixel driving voltage to a first VDD power line in response to a first power enable signal; a second VDD output section configured to provide the second pixel driving voltage to a second VDD power line in response to a second power enable signal; and a third VDD output part configured to provide the third pixel driving voltage to a third VDD power line in response to a third power enable signal, wherein the first VDD power line is connected to the first VDD node of a plurality of first sub-pixels including the first sub-pixel, the second VDD power line is connected to the second VDD node of a plurality of second sub-pixels including the second sub-pixel, and the third VDD power line is connected to the third VDD node of a plurality of third sub-pixels including the third sub-pixel.

17. The display device according to claim 4, wherein in one frame period, the first emission time of the first light emitting element is shorter than the second emission time of the second light emitting element and the third emission time of the third light emitting element, the third emission time of the third light emitting element is longer than the first emission time of the first light emitting element and shorter than the second emission time of the second light emitting element, and At least two of the first emission time of the first light emitting element, the second emission time of the second light emitting element, and the third emission time of the third light emitting element overlap in time.

18. The display device according to claim 4, wherein in one frame period, the first emission time of the first light emitting element is shorter than the second emission time of the second light emitting element and the third emission time of the third light emitting element, the third emission time of the third light emitting element is longer than the first emission time of the first light emitting element and shorter than the second emission time of the second light emitting element, and At least two of the first emission time of the first light emitting element, the second emission time of the second light emitting element, and the third emission time of the third light emitting element do not overlap in time. 19 . The display device according to claim 1 , wherein the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.

20. A display device, comprising: a first sub-pixel including a first light emitting element, a first driving element configured to control a current flowing through the first light emitting element based on a gate-source voltage of the first light emitting element, a first switching element configured to switch a current path of the first light emitting element between a pixel driving voltage and a pixel reference voltage in response to a first emission signal, and a first compensation circuit configured to receive a first data voltage and a scan signal and apply the first data voltage to a gate electrode of the first driving element; a second sub-pixel including a second light emitting element, a second driving element configured to control a current flowing through the second light emitting element based on a gate-source voltage of the second driving element, a second switching element configured to switch a current path of the second light emitting element between a pixel driving voltage and a pixel reference voltage in response to a second emission signal, and a second compensation circuit configured to receive a second data voltage and a scan signal and apply the second data voltage to a gate electrode of the second driving element; a third sub-pixel, comprising a third light emitting element, a third driving element configured to control a current flowing through the third light emitting element based on a gate-source voltage of the third driving element, a third switching element configured to switch a current path of the third light emitting element between a pixel driving voltage and a pixel reference voltage in response to a third emission signal, and a third compensation circuit configured to receive a third data voltage and a scan signal and apply the third data voltage to a gate electrode of the third driving element; and A brightness adjuster circuit is configured to independently control the pixel driving voltage or one of the first emission signal, the second emission signal and the third emission signal in each of the first sub-pixel, the second sub-pixel and the third sub-pixel, so that the brightness of at least one of the first sub-pixel, the second sub-pixel and the third sub-pixel is reduced.

21. A method for driving a display device, comprising: supplying a first data voltage to a first subpixel driving a first light emitting element using a first data voltage, supplying a second data voltage to a second subpixel driving a second light emitting element using a second data voltage, and supplying a third data voltage to a third subpixel driving a third light emitting element using a third data voltage; as well as A first emission time of the first light emitting element, a second emission time of the second light emitting element, and a third emission time of the third light emitting element are controlled to be different from each other so that the brightness of at least one of the first sub-pixel, the second sub-pixel, and the third sub-pixel is reduced.

22. A display device, comprising: A display panel including a plurality of pixels having at least one pixel including a first sub-pixel configured to emit a first color light, a second sub-pixel configured to emit a second color light, and a third sub-pixel configured to emit a third color light; a gate driver configured to provide a scanning signal to the plurality of pixels; a data driver configured to provide data voltages to the plurality of pixels, the data voltages including a first data voltage having a first possible voltage range applied to the first sub-pixel, a second data voltage having a second possible voltage range applied to the second sub-pixel, and a third data voltage having a third possible voltage range applied to the second sub-pixel, wherein the first possible voltage range, the second possible voltage range, and the third possible voltage range are different from each other; as well as A brightness adjuster circuit is configured to adjust a first emission time of the first subpixel at which the first subpixel emits light, a second emission time of the second subpixel at which the second subpixel emits light, and a third emission time of the third subpixel at which the third subpixel emits light to be different from each other.

23. The display device according to claim 22, wherein: a maximum voltage of the first possible voltage range of the first data voltage is greater than a maximum voltage of the second possible voltage range of the second data voltage and a maximum voltage of the third possible voltage range of the third data voltage, and The minimum voltage of the first possible voltage range of the first data voltage is equal to the minimum voltage of the second possible voltage range of the second data voltage and is greater than the minimum voltage of the third possible voltage range of the third data voltage.

24. The display device according to claim 23, wherein: The maximum voltage of the second possible voltage range of the second data voltage is greater than the maximum voltage of the third possible voltage range of the third data voltage, and the minimum voltage of the third possible voltage range of the third data voltage is less than the minimum voltage of the first possible voltage range of the first data voltage and the minimum voltage of the second possible voltage range of the second data voltage.

25. The display device according to claim 22, wherein: The brightness adjuster circuit is configured as follows: providing a first emission signal to a first switching transistor included in the first sub-pixel, the first switching transistor being turned on in response to the first emission signal, and the first switching transistor connecting a current path between a first light emitting element included in the first sub-pixel and a first driving transistor, providing a second emission signal to a second switch transistor included in the second sub-pixel, the second switch transistor being turned on in response to the second emission signal, and the second switch transistor connecting a current path between a second light emitting element included in the second sub-pixel and a second driving transistor, and A third emission signal is provided to a third switch transistor included in the third subpixel, the third switch transistor is turned on in response to the third emission signal, and the third switch transistor connects a current path between a third light emitting element included in the third subpixel and a third driving transistor.

26. The display device according to claim 25, wherein: The duration of the first transmitting signal turning on the first switch transistor is shorter than the duration of the second transmitting signal turning on the second switch transistor and the turn-on time of the third transmitting signal turning on the third switch transistor. The duration of the second transmit signal is greater than the duration of the first transmit signal and the duration of the third transmit signal.

27. The display device according to claim 22, wherein: The first sub-pixel is connected to a first VDD node, a first pixel driving voltage is applied to the first sub-pixel at the first VDD node, the second sub-pixel is connected to a second VDD node, a second pixel driving voltage is applied to the second sub-pixel at the second VDD node, and the third sub-pixel is connected to a third VDD node, a third pixel driving voltage is applied to the third sub-pixel at the third VDD node, and The brightness adjuster circuit is configured to individually control a first duration of applying the first pixel driving voltage to the first sub-pixel, a second duration of applying the second pixel driving voltage to the second sub-pixel, and a third duration of applying the three pixel driving voltages to the third sub-pixel so that they are different from each other.

28. The display device according to claim 27, wherein: The first duration is less than the second duration and the third duration, and the second duration is greater than the first duration and the third duration.

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