Pixel circuit, display panel, display device and driving method of pixel circuit

Abstract

The invention relates to a pixel circuit, a display panel, a display device and a driving method of the pixel circuit, in a first grid reset stage of the pixel circuit, a data writing module is switched on in response to a first scanning signal, and a first reset module is switched on in response to a second scanning signal; in a data writing stage of the pixel circuit, the data writing module is switched on in response to a first scanning signal, and the first reset module is switched off in response to a second scanning signal; in the same driving period of the pixel circuit, the data writing stage is located after the first grid reset stage. By using the pixel circuit, the use performance of an OLED display product can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a pixel circuit, a display panel, a display device, and a driving method for a pixel circuit. Background Art

[0002] Flat panel display devices based on technologies such as Organic Light Emitting Diode (OLED) and Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptop computers, and desktop computers due to advantages such as high picture quality, power saving, thin body, and wide application range, and have become the mainstream in display devices.

[0003] However, the performance of current OLED display products needs to be improved. Summary of the Invention

[0004] Based on this, it is necessary to provide a pixel circuit, a display panel, a display device, and a driving method for a pixel circuit to improve the performance of OLED display products in view of the above technical problems.

[0005] In a first aspect, the present application provides a pixel circuit, which includes:

[0006] A driving module;

[0007] A data writing module, the first end of the data writing module receives a data signal, the second end of the data writing module is connected to the first end of the driving module, and the control end of the data writing module receives a first scan signal;

[0008] A first reset module, the first end of the first reset module receives a first reset signal, the second end of the first reset module is connected to the control end of the driving module, and the control end of the first reset module receives a second scan signal; wherein,

[0009] In the first gate reset stage of the pixel circuit, the data writing module is turned on in response to the first scan signal, and the first reset module is turned on in response to the second scan signal;

[0010] In the data writing stage of the pixel circuit, the data writing module is turned on in response to the first scan signal, and the first reset module is turned off in response to the second scan signal; within the same driving cycle of the pixel circuit, the data writing stage is after the first gate reset stage.

[0011] In one embodiment, during the second gate reset stage of the pixel circuit, the data writing module is turned on in response to the first scan signal, and the first reset module is turned off in response to the second scan signal; wherein, within the same driving cycle of the pixel circuit, the second gate reset stage is before the first gate reset stage.

[0012] In one embodiment, the duration of the first gate reset stage is greater than that of the second gate reset stage.

[0013] In one embodiment, the above pixel circuit further includes:

[0014] A threshold compensation module, the first end of the threshold compensation module is respectively connected to the second end of the first reset module and the control end of the driving module, the second end of the threshold compensation module is connected to the second end of the driving module, and the control end of the threshold compensation module receives the third scan signal;

[0015] Wherein, during the data writing stage of the pixel circuit, the level signal of the first scan signal is an effective level, the level signal of the third scan signal at least includes an effective level, and within the same driving cycle of the pixel circuit, the data writing stage is after the first gate reset stage.

[0016] In one embodiment, the above pixel circuit further includes:

[0017] A second reset module, the first end of the second reset module receives the second reset signal, the second end of the second reset module is connected to the second end of the driving module, and the control end of the second reset module receives the fourth scan signal;

[0018] A storage module, which is respectively connected to the control end and the first end of the driving module;

[0019] A first light emission control module, the first end of the first light emission control module receives the power supply voltage, the second end of the first light emission control module is respectively connected to the second end of the data writing module and the first end of the driving module, and the control end of the first light emission control module receives the light emission control signal;

[0020] A second light emission control module, the first end of the second light emission control module is connected to the second end of the driving module, the second end of the second light emission control module is respectively connected to the second end of the second reset module and the anode of the light emitting element, and the control end of the second light emission control module receives the light emission control signal.

[0021] In one embodiment, the above fourth scan signal and the second scan signal are the same scan signal.

[0022] In a second aspect, the present application provides a display panel, the display panel includes:

[0023] The pixel circuit provided in the above first aspect.

[0024] In one embodiment, the above display panel further includes a light-emitting control driving circuit, and the light-emitting control driving circuit is connected to the control end of the data writing module of the pixel circuit for providing a first scanning signal received by the control end of the data writing module.

[0025] In a third aspect, the present application provides a display device including the display panel provided in the second aspect above.

[0026] In a fourth aspect, the present application provides a driving method for a pixel circuit, which is applied to the pixel circuit provided in the first aspect. The driving period of the pixel circuit at least includes a first gate reset stage;

[0027] In the first gate reset stage, a first scanning signal is provided to the data writing module, and the data signal is written to the first end of the driving module through the data writing module; and a second scanning signal is provided to the first reset module, and the received first reset signal is transmitted to the control end of the driving module through the first reset module.

[0028] In the data writing stage, a first scanning signal is provided to the data writing module, and the data signal is written to the first end of the driving module through the data writing module; wherein, within the same driving period of the pixel circuit, the data writing stage is located after the first gate reset stage.

[0029] In one embodiment, the driving period of the above pixel circuit further includes a second gate reset stage;

[0030] In the second gate reset stage, a first scanning signal is provided to the data writing module, and the data signal is written to the first end of the driving module through the data writing module; wherein, within the same driving period of the pixel circuit, the second gate reset stage is located before the first gate reset stage.

[0031] The pixel circuit, display panel, display device, and driving method of the pixel circuit provided by the embodiments of the present application. The pixel circuit includes: a driving module; a data writing module, the first end of the data writing module receives a data signal, the second end of the data writing module is connected to the first end of the driving module, and the control end of the data writing module receives a first scanning signal; a first reset module, the first end of the first reset module receives a first reset signal, the second end of the first reset module is connected to the control end of the driving module, and the control end of the first reset module receives a second scanning signal; wherein, in the first gate reset stage of the pixel circuit, the data writing module is turned on in response to the first scanning signal, and the first reset module is turned on in response to the second scanning signal; in the data writing stage of the pixel circuit, the data writing module is turned on in response to the first scanning signal, and the first reset module is turned off in response to the second scanning signal; within the same driving cycle of the pixel circuit, the data writing stage is after the first gate reset stage. Before the data signal data is written to the N1 node between the first reset module and the driving module, the potential of the N2 node between the data writing module and the driving module is first reset using the data signal data. Although the falling edge of the data signal data will still make the potential of the N2 node between the data writing module and the driving module relatively low, in the first gate reset stage of the pixel circuit, the data writing module will be turned on in response to the first scanning signal, and the first reset module will be turned on in response to the second scanning signal. At this time, writing a data signal data can play a role in resetting the potential of the N2 node. In this way, overcompensation will not occur in the subsequent compensation stage. After entering the light-emitting stage, since the potential of the N2 node is effectively reset, the voltage difference between the N1 node and the N2 node connected to the first reset module and the driving module can be maintained within a reasonable range, and the threshold voltage of the driving module will not drift abnormally. In this way, the driving module can control the output of the current according to the normal working state, so that the current flowing through the pixel light-emitting element meets the requirements of normal light emission. The pixel light-emitting element can emit light stably and uniformly, and abnormal phenomena such as dark stripes will no longer appear in the picture, thereby effectively improving the use performance of the OLED display product. Description of the Drawings

[0032] Figure 1 It is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application;

[0033] Figure 2 It is a schematic signal timing diagram of a pixel circuit provided by an embodiment of the present application;

[0034] Figure 3 It is a schematic signal timing diagram of another pixel circuit provided by an embodiment of the present application;

[0035] Figure 4 It is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application;

[0036] Figure 5 A schematic structural diagram of another pixel circuit provided by an embodiment of the present application;

[0037] Figure 6 A schematic structural diagram of another pixel circuit provided by an embodiment of the present application;

[0038] Figure 7 A schematic signal timing diagram of another pixel circuit provided by an embodiment of the present application;

[0039] Figure 8 A schematic structural diagram of another pixel circuit provided by an embodiment of the present application;

[0040] Figure 9 A schematic structural diagram of another pixel circuit provided by an embodiment of the present application;

[0041] Figure 10 A schematic structural diagram of a display panel provided by an embodiment of the present application;

[0042] Explanation of reference numerals:

[0043] 10 - driving module, 20 - data writing module, 30 - first reset module, 40 - threshold compensation module, 50 - second reset module, 60 - storage module, 70 - first light emission control module, 80 - second light emission control module, 90 - light emission control driving circuit. Detailed implementation manners

[0044] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs. The terms used in the specification of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0046] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another element, it can be directly on the other element or there can also be intermediate elements. Further, when a layer is referred to as being "under" another layer, it can be directly below or there can be one or more intermediate elements. It can also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or there can also be one or more intermediate elements.

[0047] In cases where "comprising", "having", and "including" as described herein are used, unless an explicit limiting term such as "only", "consisting of", etc. is used, another component can also be added. Unless otherwise mentioned, terms in the singular form can include the plural form and should not be understood as having a quantity of one.

[0048] It should be understood that although terms such as "first", "second", etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present application, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element.

[0049] It should also be understood that when interpreting an element, although not explicitly described, the element is interpreted as including an error range, which should be within the acceptable deviation range of a specific value determined by those skilled in the art. For example, "about", "approximately", or "substantially" can mean within one or more standard deviations, which are not defined herein.

[0050] In addition, in the specification, the phrase "planar distribution schematic diagram" refers to the drawing when observing the target part from above, and the phrase "cross-sectional schematic diagram" refers to the drawing when observing the cross-section intercepted by vertically cutting the target part from the side.

[0051] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the various elements are only drawn by way of example in the drawings and not necessarily to the true scale.

[0052] During the operation of the pixel circuit, in order to accurately present the black areas in an image, such as a night scene, black text, etc., specific pixels need to be displayed as black, so a write black block operation needs to be performed. When performing the write black block operation, in order to achieve the effect of the pixel being displayed as black, the data signal data needs to quickly transition from a high level to a low level. This rapid transition of the level from high to low will form a falling edge.

[0053] The inventor has found through research that during the black block writing operation, when the data signal data has a falling edge and the potential drops rapidly, it will affect the node between the data writing module and the driving module in the pixel circuit, that is, the N2 node. At the moment when the falling edge of the data signal data occurs, due to the capacitive coupling effect, charges will be redistributed under the action of the capacitor, which will cause the potential of the N2 node to be pulled down.

[0054] After the potential of the N2 node decreases, it will directly lead to a decrease in the voltage difference between the N2 node and another N1 node (i.e., the node where the first reset module and the driving module are connected). The threshold voltage is a key parameter that determines the on and off states of the transistor. When the voltage difference between the N1 node and the N2 node decreases, the electric field distribution inside the driving transistor will change. This change in the electric field distribution will cause the threshold voltage of the driving transistor to drift positively, which means that the driving transistor requires a higher voltage to enter the conducting state.

[0055] In the subsequent compensation stage, the pixel circuit will adjust the working state of the driving transistor according to a preset mechanism. However, since the threshold voltage of the driving transistor has drifted positively, the compensation stage will overcompensate based on an incorrect state judgment, causing the potential of the N1 node to exceed the normal working range and be too high.

[0056] After entering the light-emitting stage, when the potential of the N1 node is too high, the current flowing through the pixel light-emitting element will be abnormal and cannot meet the current conditions required for normal light emission, which will lead to abnormal light emission of the pixel. On the display screen, this abnormality appears as dark stripes, seriously damaging the uniformity and visual effect of the screen and reducing the display quality.

[0057] Based on the above technical problems, the inventor has found through research that reasonably adjusting the timing relationship between the first scan signal and the second scan signal can effectively improve the problems that occur during the black block writing operation of the pixel circuit. Specifically, the moment when the first scan signal switches from the invalid level to the valid level is advanced by a specific time interval relative to the moment when the second scan signal switches from the invalid level to the valid level. Exemplarily, taking the data writing transistor as a P-type transistor, the switching time of the first scan signal from the high level to the low level needs to be advanced.

[0058] Based on this discovery, the inventor has further developed the technical solution of the embodiment of the present application.

[0059] Specifically, the pixel circuit provided by the embodiment of the present application includes: a driving module; a data writing module, the first end of the data writing module receives a data signal, the second end of the data writing module is connected to the first end of the driving module, and the control end of the data writing module receives a first scanning signal; a first reset module, the first end of the first reset module receives a first reset signal, the second end of the first reset module is connected to the control end of the driving module, and the control end of the first reset module receives a second scanning signal; wherein, in the first gate reset stage of the pixel circuit, the data writing module is turned on in response to the first scanning signal, and the first reset module is turned on in response to the second scanning signal; in the data writing stage of the pixel circuit, the data writing module is turned on in response to the first scanning signal, and the first reset module is turned off in response to the second scanning signal; within the same driving cycle of the pixel circuit, the data writing stage is after the first gate reset stage.

[0060] With the above technical solution, before the data signal data is written into the N1 node between the first reset module and the driving module, the potential of the N2 node between the data writing module and the driving module is first reset using the data signal data. Although the falling edge of the data signal data will still make the potential of the N2 node between the data writing module and the driving module relatively low, in the first gate reset stage of the pixel circuit, the data writing module will be turned on in response to the first scanning signal, and the first reset module will be turned on in response to the second scanning signal. At this time, writing a data signal data can play a role in resetting the potential of the N2 node. In this way, there will be no over-compensation situation in the subsequent compensation stage. After entering the light-emitting stage, since the potential of the N2 node is effectively reset, the voltage difference between the N1 node and the N2 node connected to the first reset module and the driving module can be maintained within a reasonable range, and the threshold voltage of the driving module will not drift abnormally. In this way, the driving module can control the output of the current according to the normal working state, so that the current flowing through the pixel light-emitting element meets the requirements of normal light emission. The pixel light-emitting element can emit light stably and uniformly, and there will no longer be abnormal phenomena such as dark stripes in the picture, thereby effectively improving the performance of the OLED display product.

[0061] The above is the core idea of the present application. Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the protection scope of the present application.

[0062] Figure 1 It is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application. Refer to Figure 1, the pixel circuit includes a driving module 10, a data writing module 20, and a first reset module 30. Among them, the first end of the data writing module 20 is used to receive a data signal data, the second end of the data writing module 20 is connected to the first end of the driving module 10, and the control end of the data writing module 20 receives a first scanning signal SN; the first reset module 30, the first end of the first reset module 30 receives a first reset signal VREF1, the second end of the first reset module 30 is connected to the control end of the driving module 10, and the control end of the first reset module 30 receives a second scanning signal SP. Among them, in the first gate reset stage of the pixel circuit, the data writing module 20 is turned on in response to the first scanning signal SN, and the first reset module 30 is turned on in response to the second scanning signal SP; in the data writing stage of the pixel circuit, the data writing module 20 is turned on in response to the first scanning signal SN, and the first reset module 30 is turned off in response to the second scanning signal SP; within the same driving cycle of the pixel circuit, the data writing stage is after the first gate reset stage. Before the data signal data is written into the N1 node of the first reset module 30 and the driving module 10, the potential of the N2 node between the data writing module 20 and the driving module 10 is first reset using the data signal data. Without improvement, when performing a black block writing operation, a falling edge of the data signal data will cause the potential of the N2 node between the data writing module and the driving module to be pulled down. After the potential of the N2 node decreases, the voltage difference between the N1 node and the N2 node connected to the first reset module and the driving module will relatively decrease, which will cause the threshold voltage of the driving module to drift positively relatively.

[0063] In the next compensation stage, due to the positive drift of the threshold voltage of the driving module, the potential of the N1 node will exceed the normal range and be too high. When entering the light-emitting stage, this abnormal potential will cause the current flowing through the pixel light-emitting element to not meet the normal light-emitting requirements, thereby causing a light-emitting abnormality problem, which is manifested as a dark stripe on the display screen, seriously affecting the display quality.

[0064] By reasonably adjusting the timing relationship between the first scan signal and the second scan signal, although the falling edge of the data signal data still makes the potential of node N2 relatively low, during the first gate reset stage of the pixel circuit, the data writing module will be turned on in response to the first scan signal, and the first reset module will be turned on in response to the second scan signal. At this time, writing a data signal data can play a role in resetting the potential of node N2. In this way, overcompensation will not occur in the subsequent compensation stage. After entering the light-emitting stage, since the potential of node N2 is effectively reset, the voltage difference between node N1 and node N2 can be maintained within a reasonable range, and the threshold voltage of the driving module 10 will not drift abnormally. In this way, the driving module 10 can control the output of the current according to the normal working state, so that the current flowing through the light-emitting element D meets the requirements of normal light emission. The light-emitting element D can emit light stably and uniformly, and abnormal dark stripes will no longer appear in the picture, thereby effectively improving the performance of the OLED display product.

[0065] Figure 2 FIG. is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application. As Figure 2 shown, the driving module 10 may include a driving transistor T1, the data writing module 20 may include a data writing transistor T2, and the first reset module 30 may include a first reset transistor T3. Among them, the first end of the data writing transistor T2 is used to receive the data signal data, the control end of the data writing transistor T2 is used to receive the first scan signal SN, and the second end of the data writing transistor T2 is connected to the first end of the driving transistor T1. The first end of the first reset transistor T3 is used to receive the first reset signal VERF1, the second end of the first reset transistor is connected to the control end of the driving transistor T1, and the control end of the first reset transistor T3 receives the second scan signal SP.

[0066] Figure 3 FIG. is a schematic signal timing diagram of a pixel circuit provided by an embodiment of the present application. As Figure 3 shown, for the convenience of description, it is assumed that the driving transistor T1, the data writing transistor T2, and the first reset transistor T3 are all P-type transistors. During the first gate reset stage Tm1 of the pixel circuit, the first scan signal SN and the second scan signal SP are both output with effective low levels, and the data writing stage Tm2 is located after the first gate reset stage Tm1. In practical applications, the effective levels output by the first scan signal SN and the second scan signal SP can also be high levels, which can be determined according to the specific device types in the data writing module 20 and the first reset module 30, and no limitation is made here.

[0067] In the above embodiments, before the data signal data is written into the N1 node between the first reset transistor T3 and the driving transistor T1, the potential of the N2 node between the data writing transistor T2 and the driving transistor T1 is first reset by using the data signal data. Although the falling edge of the data signal data will still make the potential of the N2 node too low, during the first gate reset stage of the pixel circuit, the data writing transistor T2 will conduct in response to the first scan signal, and the first reset transistor T3 will conduct in response to the second scan signal. At this time, writing a data signal data can play a role in resetting the potential of the N2 node. In this way, overcompensation will not occur in the subsequent compensation stage. After entering the light-emitting stage, since the potential of the N2 node is effectively reset, the voltage difference between the N1 node and the N2 node can be maintained within a reasonable range, and the threshold voltage of the driving transistor T1 will not drift abnormally. In this way, the driving transistor T1 can control the output of the current according to the normal working state, so that the current flowing through the light-emitting element D meets the requirements of normal light emission. The light-emitting element D can emit light stably and uniformly, and there will no longer be abnormal dark stripes in the picture, thus effectively improving the performance of the OLED display product.

[0068] Figure 4 It is a signal timing diagram of a pixel circuit provided by an embodiment of the present application. As Figure 4 shown, during the second gate reset stage Tm3 of the pixel circuit, the data writing module 20 conducts in response to the first scan signal SN, and the first reset module 30 disconnects in response to the second scan signal SP; wherein, within the same driving cycle of the pixel circuit, the second gate reset stage Tm3 is located before the first gate reset stage Tm1.

[0069] Among them, the level signal of the first scan signal SN is an active low level, and the level signal of the second scan signal SP is an inactive high level. In practical applications, the active levels output by the first scan signal SN and the second scan signal SP can also be high levels, which can be determined according to the specific device types in the data writing module 20 and the first reset module 30, and no limitation is made here.

[0070] In the above embodiments, the coupling effect of the falling edge of the data signal data on the driving module may not be completely offset by the first gate reset stage. Therefore, within the same driving cycle of the pixel circuit and before the first gate reset stage Tm1, a second gate reset stage Tm3 is set. Adding the second gate reset stage Tm3 can further reduce the influence brought by the coupling effect of the falling edge of the data signal data, making the working state of the driving module more stable. Therefore, the current flowing through the pixel light-emitting element more meets the requirements of normal light emission, and the pixel light emission is more stable and uniform, thereby significantly improving the picture quality and performance of the OLED display product.

[0071] Optionally, the duration of the first gate reset stage Tm1 is greater than the duration of the second gate reset stage Tm3.

[0072] The longer duration allows the pixel circuit to have more sufficient time to adjust the internal charge distribution and potential state, enabling the charge redistribution in the capacitive coupling effect to reach stability, making the voltage difference between the N1 node and the N2 node closer to the ideal state, reducing the potential deviation, minimizing the impact on the threshold voltage of the driving module, and making the driving module operate more stably. Moreover, within the relatively long Tm1 time period, the pixel circuit can perform multiple fine-tuning and calibration operations, thereby effectively reducing abnormal light emission phenomena such as dark stripes during the light emission stage.

[0073] Figure 5 It is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application. Refer to Figure 5 As shown, the pixel circuit further includes: a threshold compensation module 40. Among them, the first end of the threshold compensation module 40 is respectively connected to the second end of the first reset module 30 and the control end of the driving module 10, the second end of the threshold compensation module 40 is connected to the second end of the driving module 10, and the control end of the threshold compensation module 40 receives the third scan signal SQ;

[0074] Among them, during the data writing stage Tm2 of the pixel circuit, the level signal of the first scan signal SN is an effective level, and the level signal of the third scan signal SQ at least includes an effective level. Within the same driving cycle of the pixel circuit, the data writing stage is located after the first gate reset stage. The threshold compensation module 40 is used to compensate the threshold voltage of the driving transistor T1 under the control of the third scan signal SQ, so that the driving current generated by the driving transistor T1 is not affected by the threshold voltage of the driving transistor T1, thereby improving the display uniformity of the display panel.

[0075] Specifically, referring to Figure 6 As shown, the threshold compensation module 40 may include a threshold compensation transistor T4. The first end of the threshold compensation transistor T4 is respectively connected to the second end of the first reset transistor T3 and the control end of the driving transistor T1, the second end of the threshold compensation transistor T4 is connected to the second end of the driving transistor T1, and the control end of the threshold compensation transistor T4 receives the third scan signal SQ.

[0076] Figure 7 It is a schematic signal timing diagram of a pixel circuit provided by an embodiment of the present application. As shown in Figure 7As shown, during the data writing stage Tm2 of the pixel circuit, the level signal of the first scan signal SN is an effective level, and the level signal of the third scan signal SQ includes at least the effective level. During the same driving cycle of the pixel circuit, the data writing stage is after the first gate reset stage Tm1. In practical applications, the effective level output by the second scan signal SP and the third scan signal SQ can also be a high level, which can be determined according to the specific device types in the first reset module 30 and the threshold compensation module 40, and no specific limitation is made here.

[0077] During the data writing stage Tm2, the first scan signal SN becomes an effective level. Since the control terminal of the data writing module 20 is connected to the first scan signal SN, the data writing module 20 is turned on, and the data signal data can be transmitted through the data writing module 20 to the first end of the driving module 10, thereby writing the externally input data signal data into the driving module 10. At the same time, the level signal of the third scan signal SQ includes at least the effective level. When the third scan signal SQ is at the effective level, the threshold compensation module 40 is turned on. Since the first end of the threshold compensation module 40 is respectively connected to the second end of the first reset module 30 and the control terminal of the driving module 10, and the second end is connected to the second end of the driving module 10, the turned-on threshold compensation module 40 can compensate the threshold voltage of the driving module 10 to offset the threshold voltage fluctuations caused by factors such as manufacturing process differences and temperature changes, so that the driving module 10 can work stably.

[0078] The first gate reset stage Tm1 provides a stable potential basis for data writing, reducing data writing errors caused by potential deviations. During the data writing stage, the first scan signal SN and the third scan signal SQ cooperate to ensure accurate data writing and effective compensation of the threshold voltage.

[0079] Figure 8 This is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application. As Figure 8 shown, the pixel circuit includes a second reset module 50, a storage module 60, a first light emission control module 70, and a second light emission control module 80.

[0080] Among them, the first end of the second reset module 50 receives the second reset signal VREF2, the second end of the second reset module 50 is connected to the second end of the driving module 10, and the control terminal of the second reset module 50 receives the fourth scan signal SR.

[0081] The storage module 60 is respectively connected to the control terminal and the first end of the driving module 10.

[0082] The first end of the first light-emitting control module 70 receives the power supply voltage PVDD. The second end of the first light-emitting control module 70 is respectively connected to the second end of the data writing module 20 and the first end of the driving module 10. The control end of the first light-emitting control module 70 receives the light-emitting control signal EMIT.

[0083] The first light-emitting control module 70 is used to control the on / off between the power supply voltage PVDD and the driving module 10 under the control of the light-emitting control signal EMIT. Based on this, the first light-emitting control module 70 can be used to effectively control the driving module 10 to improve the display effect.

[0084] The first end of the second light-emitting control module 80 is connected to the second end of the driving module 10. The second end of the second light-emitting control module 80 is respectively connected to the second end of the second reset module 50 and the anode of the light-emitting element D. The control end of the second light-emitting control module 80 receives the light-emitting control signal.

[0085] The second light-emitting control module 80 is used to control the on / off between the driving module 10 and the light-emitting element D under the control of the light-emitting control signal EMIT. Based on this, the second light-emitting control module 80 can be used to effectively control the driving module 10 to drive the light-emitting element D to emit light to improve the display effect.

[0086] Figure 9 It is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application. The second reset module 50 may include a second reset transistor T5. The first end of the second reset transistor T5 receives the second reset signal VREF2. The second end of the second reset transistor T5 is connected to the second end of the driving transistor T1. The control end of the second reset transistor T5 receives the fourth scan signal SR.

[0087] The first light-emitting control module 70 may include a first light-emitting control transistor T6. The first end of the first light-emitting control transistor T6 receives the power supply voltage PVDD. The second end of the first light-emitting control transistor T6 is respectively connected to the second end of the data writing transistor T2 and the first end of the driving transistor T1. The control end of the first light-emitting control transistor T6 receives the light-emitting control signal EMIT.

[0088] The storage module 60 may include a storage capacitor Cst. The storage capacitor Cst is respectively connected to the control end and the first end of the driving transistor T1.

[0089] The second light-emitting control module 80 may include a second light-emitting control transistor T7. The first end of the second light-emitting control transistor T7 is connected to the second end of the driving transistor T1. The second end of the second light-emitting control transistor T7 is respectively connected to the second end of the second reset transistor T5 and the anode of the light-emitting element D. The control end of the second light-emitting control transistor T7 receives the light-emitting control signal EMIT.

[0090] Optionally, the fourth scan signal SR and the second scan signal SP are the same scan signal. The level characteristics and timing characteristics of the fourth scan signal SR are the same as those of the second scan signal SP. When the level characteristics and timing characteristics of the fourth scan signal SR are set to be the same as those of the second scan signal SP, no additional separate driving circuit is required to generate the fourth scan signal SR, saving the border and reducing power consumption.

[0091] The embodiment of the present application also provides a display panel, which includes the pixel circuit provided in any of the above embodiments. The specific structure of the pixel circuit can be referred to Figures 1 - 9 and related content, which will not be elaborated here.

[0092] Figure 10 is a schematic structural diagram of a display panel provided by an embodiment of the present application. As Figure 10 shown, the display panel further includes a light emission control driving circuit 90, which is connected to the control end of the data writing module 20 of the pixel circuit and is used to provide the first scan signal SN received by the control end of the data writing module 20.

[0093] The light emission control driving circuit 90 can provide a stable first scan signal SN. The stable first scan signal SN can ensure that the data writing module 20 conducts and disconnects at the correct time nodes, thereby ensuring that the data signal data can be accurately written into the driving module 10. Compared with the input of an unstable first scan signal SN, the stable first scan signal SN can effectively reduce the occurrence of data writing errors and avoid display problems such as screen flickering and color deviation, improving the accuracy and reliability of the display content of the display panel.

[0094] Based on the display panel provided in the above embodiment, the present application further provides a display device, which is applied to the display panel provided in any of the above embodiments. The display panel includes the pixel circuit and the light emission control driving circuit 90 provided in any of the above embodiments. The specific structure of the pixel circuit can be referred to Figures 1 - 9 and related content, which will not be elaborated here. The light emission control driving circuit 90 can be referred to Figure 10 and related content, which will not be elaborated here.

[0095] Based on the pixel circuit provided in the above embodiments, the present application further provides a driving method for the pixel circuit, which is applied to the pixel circuit provided in any of the above embodiments. The driving cycle of the pixel circuit at least includes a first gate reset stage; in the first gate reset stage, a first scan signal SN is provided to the data writing module 20, and the data signal is written to the first end of the driving module 10 through the data writing module 20; and a second scan signal SP is provided to the first reset module 30, and the received first reset signal is transmitted to the control end of the driving module 10 through the first reset module 30.

[0096] In the data writing stage, a first scan signal SN is provided to the data writing module 20, and the data signal is written to the first end of the driving module 10 through the data writing module 20; wherein, within the same driving cycle of the pixel circuit, the data writing stage is located after the first gate reset stage.

[0097] Refer to Figure 1 , in the first gate reset stage, the data writing module 20 of the pixel circuit receives the data signal data under the control of the first scan signal, and writes the received data signal data to the N2 node to reset the first end of the driving module 10 of the pixel circuit.

[0098] The first reset module 30 of the pixel circuit receives the first reset signal under the control of the second scan signal, and writes the received first reset signal to the N1 node to reset the control end of the driving module 10 of the pixel circuit.

[0099] Wherein, in the first gate reset stage, when the first scan signal SN is at an effective level, the data writing module 20 of the pixel circuit receives the externally input data signal data. The data signal data contains information such as controlling the display color and brightness of the pixel.

[0100] The data writing module 20 transmits the received data signal data to the N2 node. After the data signal data is written to the N2 node, the first end of the driving module 10 of the pixel circuit completes the reset operation, providing conditions for the driving module 10 to control the pixel to emit light according to the data signal data subsequently.

[0101] At the same time, when the second scan signal SP is at an effective level, the first reset module 30 transmits the received first reset signal to the N1 node. After the first reset signal VREF1 is written to the N1 node, the control end of the driving module 10 of the pixel circuit completes the reset operation, and its potential returns to the threshold voltage of the driving module 10, enabling the driving module 10 to control the pixel to emit light in a predetermined manner.

[0102] In the above embodiments, before the data signal data is written to the control terminal of the driving module 10, the data signal data is first used to reset the first terminal of the driving module 10, that is, the node between the data writing module 20 and the driving module 10, and the threshold voltage of the driving module is improved by adjusting the voltage between the N1 node and the N2 node of the driving module, so as to realize the normal display function of the pixel circuit.

[0103] Optionally, the driving cycle of the above pixel circuit further includes a second gate reset stage Tm3; in the second gate reset stage Tm3, a first scan signal SN is provided to the data writing module 20, and the data signal data is written to the first terminal of the driving module 10 through the data writing module 20; wherein, within the same driving cycle of the pixel circuit, the second gate reset stage Tm3 is located before the first gate reset stage Tm1.

[0104] Refer to Figure 1 , in the second gate reset stage Tm3, the data writing module 20 of the pixel circuit receives the data signal data under the control of the first scan signal, and writes the received data signal data to the N2 node to reset the first terminal of the driving module 10 of the pixel circuit.

[0105] Among them, in the second gate reset stage, when the first scan signal SN is at an effective level, the data writing module 20 receives the data signal data input from the outside. The data signal data contains information for controlling pixel display, such as parameters such as color and brightness.

[0106] After receiving the data signal data, the data writing module 20 transmits it to the N2 node. By writing the data signal data to the N2 node, the voltage of the first terminal of the driving module 10 of the pixel circuit can be reset.

[0107] In the above embodiments, by writing the data signal data to the N2 node for reset in the second gate reset stage Tm3, the potential of the first terminal of the driving module 10 can be restored to a stable and predictable initial state. In this way, the driving module 10 can more accurately control the light-emitting state of the pixel according to the requirements of the data signal data, thereby improving the accuracy and stability of pixel display and further optimizing the quality of the entire display screen.

[0108] In the description of this specification, the description with reference to terms such as "some embodiments", "other embodiments", etc. means that the specific features, structures, materials or features described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0109] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0110] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A pixel circuit, characterized in that: The pixel circuit comprises: Driver module; A data writing module, wherein a first end of the data writing module receives a data signal, a second end of the data writing module is connected to the first end of the driving module, and a control end of the data writing module receives a first scanning signal; A first reset module, wherein a first end of the first reset module receives a first reset signal, a second end of the first reset module is connected to a control end of the driving module, and the control end of the first reset module receives a second scanning signal; wherein In a first gate reset phase of the pixel circuit, the data writing module is turned on in response to the first scanning signal, and the first reset module is turned on in response to the second scanning signal; In the data writing phase of the pixel circuit, the data writing module is turned on in response to the first scanning signal, and the first reset module is turned off in response to the second scanning signal; within the same driving cycle of the pixel circuit, the data writing phase is located after the first gate reset phase.

2. The pixel circuit according to claim 1, characterized in that: In the second gate reset phase of the pixel circuit, the data writing module is turned on in response to the first scanning signal, and the first reset module is turned off in response to the second scanning signal; wherein, within the same driving cycle of the pixel circuit, the second gate reset phase is located before the first gate reset phase.

3. The pixel circuit according to claim 2, characterized in that: The duration of the first gate reset phase is longer than the duration of the second gate reset phase.

4. The pixel circuit according to claim 1, characterized in that: The pixel circuit further includes: a threshold compensation module, wherein a first end of the threshold compensation module is respectively connected to the second end of the first reset module and the control end of the driving module, a second end of the threshold compensation module is connected to the second end of the driving module, and the control end of the threshold compensation module receives a third scanning signal; Among them, in the data writing stage of the pixel circuit, the level signal of the first scanning signal is a valid level, the level signal of the third scanning signal at least includes a valid level, and within the same driving cycle of the pixel circuit, the data writing stage is located after the first gate resetting stage.

5. The pixel circuit according to claim 1, characterized in that: The pixel circuit further includes: a second reset module, wherein a first end of the second reset module receives a second reset signal, a second end of the second reset module is connected to a second end of the driving module, and a control end of the second reset module receives a fourth scanning signal; A storage module, connected to the control end of the driving module and the first end of the driving module respectively; a first light-emitting control module, wherein a first end of the first light-emitting control module receives a power supply voltage, a second end of the first light-emitting control module is respectively connected to a second end of the data writing module and a first end of the driving module, and a control end of the first light-emitting control module receives a light-emitting control signal; A second light-emitting control module, wherein the first end of the second light-emitting control module is connected to the second end of the driving module, the second end of the second light-emitting control module is respectively connected to the second end of the second reset module and the anode of the light-emitting element, and the control end of the second light-emitting control module receives a light-emitting control signal.

6. The pixel circuit according to claim 5, characterized in that: The fourth scanning signal and the second scanning signal are the same scanning signal.

7. A display panel, characterized in that: Comprising the pixel circuit as described in any one of claims 1-6.

8. The display panel according to claim 7, characterized in that: The display panel further includes a light emitting control driving circuit, which is connected to a control end of a data writing module of the pixel circuit and is used to provide a first scanning signal received by the control end of the data writing module.

9. A display device, characterized in that: Comprising the display panel as claimed in claim 7 or 8.

10. A method for driving a pixel circuit, characterized in that: Applied to the pixel circuit according to any one of claims 1 to 6, the driving cycle of the pixel circuit at least includes a first gate reset phase; In the first gate reset stage, a first scanning signal is provided to the data writing module, and a data signal is written to the first end of the driving module through the data writing module; and a second scanning signal is provided to the first reset module, and the first reset module transmits the received first reset signal to the control end of the driving module; In the data writing stage, the first scanning signal is provided to the data writing module, and the data signal is written to the first end of the driving module through the data writing module; wherein, in the same driving cycle of the pixel circuit, the data writing stage is located after the first gate resetting stage.

11. The driving method of the pixel circuit according to claim 10, characterized in that: The driving cycle of the pixel circuit also includes a second gate reset phase; In the second gate reset stage, the first scanning signal is provided to the data writing module, and the data signal is written to the first end of the driving module through the data writing module; wherein, within the same driving cycle of the pixel circuit, the second gate reset stage is located before the first gate reset stage.

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