Gate drive circuit, power-on starting method, display panel and display device

Abstract

The invention discloses a gate drive circuit, a power-on starting method, a display panel and a display device. The gate drive circuit comprises a GOA module, a level conversion module and a time sequence control module. The time sequence control module pull-up unit is used for providing a second clock signal of the first frequency for the level conversion module before the level conversion module is powered on and started; and the power supply module is used for providing a second clock signal with a second frequency for the level conversion module after the level conversion module is powered on and started. The first time sequence control module provides the second clock signal of the first frequency for the level conversion module before the level conversion module is powered on and after the level conversion module is powered on and can provide the second clock signal of the second frequency for the level conversion module after the level conversion module is powered on and started. Therefore, the third clock signal and the fourth clock signal which are opposite in phase can be output in a short time according to the second clock signal of the first frequency, and the situation that the third clock signal and the fourth clock signal are both high levels or low levels is avoided.

Description

Technical Field

[0001] This application belongs to the technical field of display devices, and particularly relates to a gate driving circuit, a power-on startup method, a display panel, and a display device. Background Art

[0002] Currently, a liquid crystal panel is one of the important components of a liquid crystal display device. The liquid crystal panel includes pixel units arranged in rows and columns. When the liquid crystal panel is working, the row driving circuit can provide a gate driving signal to the pixel circuit corresponding to the pixel unit in units of one row of pixel units, complete the row scanning of the liquid crystal panel, and realize the function of displaying images on the liquid crystal panel. Common row driving circuits include two types: a gate on array (GOA) driving circuit and a chip on film (COF) driving circuit. Since the GOA driving circuit has the advantages of a narrow border and low cost, it is widely used in display devices.

[0003] However, when the level conversion chip used in the existing GOA driving circuit is powered on and started up, there may be a situation where the output of the level conversion chip is abnormal, resulting in mis-conduction of some switching devices and triggering over-current protection. Summary of the Invention

[0004] The purpose of this application is to provide a gate driving circuit, a power-on startup method, a display panel, and a display device, aiming to solve the problem of mis-triggering over-current protection existing in traditional display panels.

[0005] In the first aspect of the embodiments of this application, a gate driving circuit is provided. The gate driving circuit includes: a GOA module, the GOA module includes an output unit and a pull-down maintenance unit. The output unit is used to generate and output a scan signal based on a first clock signal when the voltage of the charging node of the GOA module is greater than or equal to a preset threshold. The pull-down maintenance unit is connected between the charging node and the low-level trace connection; a timing control module, connected to the level conversion module, is used to provide a second clock signal with a first frequency to the level conversion module from before the level conversion module is powered on and started up to after the level conversion module is powered on and started up; and is used to adjust the frequency of the second clock signal from the first frequency to a second frequency after the level conversion module is powered on and started up; the second frequency is lower than the first frequency; the level conversion module is connected to the pull-down maintenance unit through the half-bridge switch circuit of the GOA module. The level conversion module is used to output an inverted third clock signal and a fourth clock signal to the pull-down maintenance unit according to the second clock signal. The third clock signal and the fourth clock signal are used to control the conduction and cut-off of the pull-down maintenance unit through the half-bridge switch circuit.

[0006] In one embodiment, the half-bridge switching circuit includes a first switching device and a second switching device, and the pull-down maintaining unit includes a third switching device; a first end of the first switching device is connected to a high-level trace, a second end of the first switching device is connected to a control end of the third switching device, a first end of the second switching device is connected to the control end of the third switching device, a second end of the second switching device is connected to a low-level trace, and control ends of the first switching device and the second switching device are both connected to the level conversion module to respectively receive the third clock signal and the fourth clock signal; a first end of the third switching device is connected to the charging node, and a second end of the third switching device is connected to the low-level trace.

[0007] In one embodiment, the output unit includes a fourth switching device and a bootstrap capacitor; a first end of the bootstrap capacitor is connected to the charging node, a first end of the fourth switching device is configured to receive the first clock signal, a second end of the fourth switching device is connected to a second end of the bootstrap capacitor, a control end of the fourth switching device is connected to the charging node, and a second end of the fourth switching device is configured to output the scan signal.

[0008] In one embodiment, the GOA module further includes a pull-up unit, the pull-up unit is connected between the charging node and the high-level trace, and the pull-up unit is configured to pull up the voltage of the charging node to a high level before the output unit generates a high-level pulse of the scan signal according to a high-level pulse of the first clock signal.

[0009] In one embodiment, the gate driving circuit further includes a pull-down unit; the pull-down unit is configured to pull down the voltage of an output end of the output unit to a low level before a next rising edge of the first clock signal after a falling edge of the scan signal.

[0010] In one embodiment, the timing control module is further configured to output a fifth clock signal to the level conversion module after outputting the second clock signal of the second frequency, and the level conversion module is configured to output the first clock signal according to the fifth clock signal.

[0011] In one embodiment, the level conversion module includes a level conversion unit and an enable control unit; the enable control unit is connected to the level conversion unit and the timing control module, and is configured to output an enable signal after the timing control module outputs the second clock signal of the second frequency and an input voltage of the gate driving circuit is greater than a first preset voltage; the level conversion unit is configured to be powered on and started after receiving the enable signal.

[0012] The second aspect of the embodiments of the present application provides a power-on startup method, which is applied to a gate driving circuit. The gate driving circuit includes: a GOA module, which includes an output unit and a pull-down maintenance unit. The output unit is configured to generate and output a scan signal based on a first clock signal when the voltage of the charging node of the GOA module is greater than or equal to a preset threshold. The pull-down maintenance unit is connected to the charging node and a low-level trace; a level conversion module, which is connected to the pull-down maintenance unit through a half-bridge switch circuit. The level conversion module is configured to generate and output an inverted third clock signal and a fourth clock signal to the pull-down maintenance unit according to a second clock signal. The third clock signal and the fourth clock signal are used to control the conduction and cutoff of the pull-down maintenance unit through the half-bridge switch circuit. The power-on startup method includes: before the level conversion module is powered on and started up to after the level conversion module is powered on and started up, providing the second clock signal with a first frequency to the level conversion module; after the level conversion module is powered on and started up, adjusting the frequency of the second clock signal from the first frequency to a second frequency; the second frequency is lower than the first frequency.

[0013] The third aspect of the embodiments of the present application provides a display panel, which includes a plurality of cascaded gate driving circuits as described above. Among them, the nth-level gate driving circuit is configured to generate and output a scan signal applied to the nth-row pixel circuit in the display panel based on a first clock signal during a corresponding scan period.

[0014] In one embodiment, the display panel further includes a power supply circuit, which is configured to generate and output a working voltage and a high-level voltage based on an input voltage; the gate driving circuit further includes a feedback module, which is connected to the timing control module of the gate driving circuit. The feedback module is configured to provide a feedback voltage to the timing control module based on the working voltage. The timing control module is configured to output a second clock signal after the feedback voltage is greater than a second preset voltage; the time node when the feedback voltage reaches the second preset voltage precedes the first rising edge of the high-level voltage.

[0015] The fourth aspect of the embodiments of the present application provides a display device, which includes the display panel as described above.

[0016] The beneficial effects of the embodiments of the present application compared with the prior art are as follows: By first enabling the timing control module to provide a second clock signal with a first frequency to the level conversion module before and after the level conversion module is powered on and started, after the level conversion module is powered on and started, it can output an inverted third clock signal and a fourth clock signal according to the second clock signal with the first frequency in a short time, avoiding the situation where both the third clock signal and the fourth clock signal are high level or both are low level, thereby avoiding the situation where two switching devices of the half-bridge switching circuit are turned on simultaneously, resulting in overcurrent protection of the trigger gate drive circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of a gate drive circuit provided by an embodiment of the present application; Figure 2 Waveform diagrams of high-level voltage, low-level voltage, first clock signal, second clock signal, third clock signal, fourth clock signal, and fifth clock signal provided by an embodiment of the present application; Figure 3 Specific circuit diagram of the GOA module provided by an embodiment of the present application; Figure 4 Specific circuit diagrams of the level conversion module and the feedback module provided by an embodiment of the present application; Figure 5 Flowchart of a power-on startup method provided by an embodiment of the present application; Figure 6 Schematic diagram of a display panel provided by an embodiment of the present application; Figure 7 Schematic diagram of a display device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] In order to make the technical problems, technical solutions, and beneficial effects to be solved by the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0019] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0020] It should be understood that the orientation or positional relationship indicated by terms such as "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.

[0021] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality of" means two or more, unless otherwise specifically defined.

[0022] Currently, a display panel usually includes a plurality of gate driving circuits. One gate driving circuit can be connected to one row of pixel circuits. One gate driving circuit can be used to generate and output a scan signal applied to the corresponding pixel circuit based on a clock signal within a corresponding scan period. The scan period specifically corresponds to the scan signals that each gate driving circuit needs to output. Within the scan period, the corresponding clock signal only includes one high-level pulse. The gate driving circuit usually needs to output a scan signal with the same high-level pulse based on one high-level pulse of the clock signal within the corresponding scan period. There is a phase difference between the scan signals output by different gate driving circuits. When the corresponding pixel circuit receives the scan signal, the pixel circuit will obtain the corresponding part of the Data signal from the continuous Data signals when the voltage of the scan signal is greater than the set threshold, and finally achieve the progressive scanning of the display panel.

[0023] Figure 1 The schematic diagram of the gate driving circuit provided by an embodiment of the present application is shown. For the convenience of description, only the parts related to this embodiment are shown and are described in detail as follows: A gate driving circuit 10 is applied to a display panel, and the display panel includes a plurality of gate driving circuits 10.

[0024] The gate driving circuit 10 includes: a GOA module 100, a level conversion module 200, and a timing control module 300.

[0025] The GOA module 100 includes an output unit 110 and a pull-down maintenance unit 120. The output unit 110 is used to generate and output a scan signal based on the first clock signal when the voltage of the charging node PU of the GOA module 100 is greater than or equal to a preset threshold. The pull-down maintenance unit 120 is connected between the charging node PU and the low-level trace.

[0026] The level conversion module 200 is connected to the pull-down maintenance unit 120 through the half-bridge switch circuit 130. The level conversion module 200 is configured to output the inverted third clock signal LC1 and the fourth clock signal LC2 to the pull-down maintenance unit 120 according to the second clock signal LC_In. The third clock signal LC1 and the fourth clock signal LC2 are used to control the conduction and cut-off of the pull-down maintenance unit 120 through the half-bridge switch circuit 130. When the pull-down maintenance unit 120 is cut off, the charging node PU is disconnected from the low-level trace. When the pull-down maintenance unit 120 is conducting, the charging node PU is connected to the low-level trace, thereby pulling down the voltage of the charging node PU to the low level.

[0027] The timing control module 300 is connected to the level conversion module 200, and is configured to provide the second clock signal LC_In with the first frequency to the level conversion module 200 from before the power-on startup of the level conversion module 200 to after the power-on startup of the level conversion module 200; and is configured to provide the second clock signal LC_In with the second frequency to the level conversion module 200 after the power-on startup of the level conversion module 200; the second frequency is lower than the first frequency.

[0028] Specifically, the timing control module 300 can provide the second clock signal LC_In with the second frequency to the level conversion module 200 after a certain duration of power-on startup of the level conversion module 200.

[0029] In some embodiments, the timing control module 300 can be configured to provide the second clock signal LC_In with the second frequency to the level conversion module 200 after providing the second clock signal LC_In with the first frequency for a preset duration to the level conversion module 200. The frequency switching time node of the second clock signal LC_In can be adaptively set according to the actual situation and requirements of the gate drive circuit 10.

[0030] The specific waveforms of the high-level voltage VGH on the high-level trace, the low-level voltage VGL on the low-level trace, the first clock signal CK, the second clock signal LC_In, the third clock signal LC1, the fourth clock signal LC2, and the fifth clock signal CPV are as Figure 2 shown.

[0031] At the moment T1, the level conversion module 200 is powered on and starts up, and outputs the corresponding third clock signal LC1 and fourth clock signal LC2 according to the second clock signal LC_In with the first frequency.

[0032] At time T2, the frequency of the second clock signal LC_In switches from the first frequency to the second frequency. Correspondingly, the level conversion module 200 outputs the corresponding third clock signal LC1 and fourth clock signal LC2 according to the second clock signal LC_In of the second frequency.

[0033] Among them, the level conversion module 200 may specifically include a level conversion chip. The timing control module 300 may specifically include a logic control unit, such as a microcontroller like a chip or a single-chip microcomputer.

[0034] It should be noted that the third clock signal LC1 and the fourth clock signal LC2 can be used to respectively supply two switching devices of the half-bridge switching circuit 130 connected between the high-level trace and the low-level trace, so as to generate a corresponding square wave signal at the connection point of the two switching devices to further control other switching devices. When the level conversion module 200 is powered on and started, some level conversion chips have a probability of outputting the in-phase third clock signal LC1 and fourth clock signal LC2 when the second clock signal LC_In is not recognized. And if both the third clock signal LC1 and the fourth clock signal LC2 are high level or both are low level, it may cause the two switching devices to conduct simultaneously, resulting in the connection between the high-level trace and the low-level trace and triggering the overcurrent protection of the gate drive circuit 10.

[0035] By first enabling the timing control module 300 to provide the second clock signal LC_In of the first frequency to the level conversion module 200 before the level conversion module 200 is powered on and started until after the level conversion module 200 is powered on and started, it can make the level conversion module 200 output the inverted third clock signal LC1 and fourth clock signal LC2 according to the second clock signal LC_In of the first frequency within a short time after the level conversion module 200 is powered on and started, avoiding the situation where both the third clock signal LC1 and the fourth clock signal LC2 are high level or both are low level, thereby avoiding the situation where the two switching devices of the half-bridge switching circuit 130 conduct simultaneously and triggering the overcurrent protection of the gate drive circuit 10.

[0036] It should be noted that during the process of the gate drive circuit 10 receiving the input voltage and generating the corresponding working voltage, the actual power-on start time node of the level conversion module 200 will be affected by various factors, and it is difficult to determine the actual power-on start time node of the level conversion module 200. It is necessary to continuously output the second clock signal LC_In of the first frequency for a period of time to cover all possible power-on start time nodes of the level conversion module 200. Therefore, the duration of the second clock signal LC_In of the first frequency needs to be determined according to the actual situation.

[0037] Meanwhile, when the device performance permits, the higher the first frequency, the faster the takeover of the level conversion module 200 after the level conversion module 200 is powered on and started, so as to adjust the third clock signal LC1 and the fourth clock signal LC2 to the inverted state in the shortest time. Therefore, in some embodiments, the first frequency is the maximum frequency of the signal that the timing control module 300 can output.

[0038] It can be understood that the second frequency needs to be determined according to the display panel refresh rate, and this embodiment does not limit it.

[0039] In some embodiments, the voltage of the high level of the second clock signal LC_In is equal to the operating voltage of the gate driving circuit 10, and the voltages of the high levels of the third clock signal LC1 and the fourth clock signal LC2 are equal to the voltage of the high-level trace.

[0040] In one embodiment, the structures of the respective gate driving circuits 10 are the same. Figure 3 The GOA module 100 of the nth-stage gate driving circuit 10 is shown. For ease of description, the nth-stage gate driving circuit 10 is taken as an example in the subsequent embodiments. The half-bridge switching circuit 130 includes a first switching device Q1 and a second switching device Q2, and the pull-down maintaining unit 120 includes a third switching device Q3.

[0041] The first end of the first switching device Q1 is connected to the high-level trace, the second end of the first switching device Q1 is connected to the control end of the third switching device Q3 of the GOA module 100, the first end of the second switching device Q2 is connected to the control end of the third switching device Q3, the second end of the second switching device Q2 is connected to the low-level trace, and the control ends of the first switching device Q1 and the second switching device Q2 are both connected to the level conversion module 200 to respectively access the third clock signal LC1 and the fourth clock signal LC2.

[0042] The first end of the third switching device Q3 is connected to the charging node PU, and the second end of the third switching device Q3 is connected to the low-level trace.

[0043] Since the third clock signal LC1 and the fourth clock signal LC2 are inverted with each other under normal operating conditions, only one of the first switching device Q1 and the second switching device Q2 is conducting at the same time. When the first switching device Q1 is conducting and the second switching device Q2 is off, the half-bridge switching circuit 130 can provide a high level to the control end of the third switching device Q3. When the first switching device Q1 is off and the second switching device Q2 is conducting, the half-bridge switching circuit 130 can provide a low level to the control end of the third switching device Q3.

[0044] Specifically, in some embodiments, the first switching device Q1, the second switching device Q2, and the third switching device Q3 can all be N-type transistors.

[0045] In one embodiment, as Figure 3 shown, the output unit 110 includes a fourth switching device Q4 and a bootstrap capacitor C1.

[0046] One end of the bootstrap capacitor C1 is connected to the charging node PU. One end of the fourth switching device Q4 is used to receive the first clock signal CK. The second end of the fourth switching device Q4 is connected to the second end of the bootstrap capacitor C1. The control end of the fourth switching device Q4 is connected to the charging node PU, and the second end of the fourth switching device Q4 is used to output a scanning signal.

[0047] Specifically, the fourth switching device Q4 is configured to conduct when the voltage difference between the voltage at the control end of the fourth switching device Q4 and the voltage at the first end of the fourth switching device Q4 is greater than the conduction threshold.

[0048] It can be understood that in the corresponding scanning period, before the output unit 110 outputs a corresponding scanning signal according to a high-level pulse of the first clock signal CK, it is necessary to charge the charging node PU to make the fourth switching device Q4 conduct.

[0049] In one embodiment, as Figure 3 shown, the GOA module 100 further includes a pull-up unit 140. The pull-up unit 140 is connected between the charging node PU and the high-level trace. The pull-up unit 140 is used to pull up the voltage of the charging node PU to a high level before the output unit 110 generates a high-level pulse of the scanning signal according to the high-level pulse of the first clock signal in the scanning period.

[0050] The pull-up unit 140 can be used to charge the charging node PU within the corresponding scanning period to achieve the output of the scanning signal.

[0051] Specifically, the pull-up unit 140 can include a fifth switching device Q5. One end of the fifth switching device Q5 is connected to the high-level trace. The second end of the fifth switching device Q5 is connected to the charging node PU. The control end of the fifth switching device Q5 can receive the scanning signal or the cascaded control signal output by other gate driving circuits 10. The signal received by the control end of the fifth switching device Q5 can be specifically determined according to the timing and waveform of the scanning signal or the cascaded control signal output by each actual gate driving circuit 10.

[0052] In some embodiments, in a plurality of cascaded gate driving circuits 10, the pull-up unit 140 of the nth stage may be connected to the gate driving circuit 10 of the (n - 1)th stage to control the pull-up unit 140 of the nth stage according to the scan signal G(n - 1) output by the gate driving circuit 10 of the (n - 1)th stage.

[0053] In one embodiment, as Figure 3 shown, the gate driving circuit 10 further includes a pull-down unit 150.

[0054] The pull-down unit 150 is configured to pull down the voltage at the output terminal of the output unit 110 to a low level before the next rising edge of the first clock signal after the falling edge of the scan signal.

[0055] Since the pixel circuit connected to the gate driving circuit 10 usually has a certain capacitance, the pull-down unit 150 is used to quickly release the charge at the output terminal of the output unit 110 to avoid abnormal scan signals.

[0056] Specifically, the pull-down unit 150 includes a sixth switching device Q6. The first end of the sixth switching device Q6 is connected to the output terminal of the output unit 110, the second end of the sixth switching device Q6 is connected to the low-level trace, and the control end of the sixth switching device Q6 may be connected to the scan signal output by other gate driving circuits 10 or the cascaded control signal. The signal connected to the control end of the sixth switching device Q6 may be specifically determined according to the timing and waveform of the scan signal or the cascaded control signal output by each actual gate driving circuit 10.

[0057] In some embodiments, in a plurality of cascaded gate driving circuits 10, the pull-down unit 150 of the nth stage may be connected to the gate driving circuit 10 of the (n + 1)th stage to control the pull-down unit 150 of the nth stage according to the scan signal G(n + 1) output by the gate driving circuit 10 of the (n + 1)th stage.

[0058] In one embodiment, the timing control module 300 is further configured to output a fifth clock signal CPV to the level conversion module 200 after outputting the second clock signal LC_In of the second frequency, and the level conversion module 200 is configured to output a first clock signal CK according to the fifth clock signal CPV.

[0059] As Figure 2 shown, at time T3, the timing control module 300 starts to output the fifth clock signal CPV, and the level conversion module 200 is configured to output a first clock signal CK according to the fifth clock signal CPV.

[0060] After the power-on startup of the level conversion module 200 is completed and the level conversion module 200 starts to work stably, the first clock signal CK can be output through the level conversion module 200 to generate a scan signal.

[0061] Specifically, after the timing control module 300 can control the pull-down holding module to pull down the voltage of the charging node PU to a low level through the corresponding second clock signal LC_In, the fifth clock signal CPV is output to avoid the abnormal voltage of the charging node PU caused by the coupling capacitance between the first end of the fourth switching device Q4 and the charging node PU through the first clock signal CK, resulting in the mis-conduction of the fourth switching device Q4.

[0062] In one embodiment, as Figure 4 shown, the level conversion module 200 includes a level conversion unit 210 and an enable control unit 220. The level conversion unit 210 is used to power on and start after receiving an enable signal. The enable control unit 220 is connected to the level conversion unit 210 and the timing control module 300, and is used to output an enable signal after the timing control module 300 outputs a second clock signal LC_In with a second frequency and the input voltage VIN is greater than a first preset voltage.

[0063] It can be understood that the timing control module 300 can provide a control signal to the enable control unit 220 when outputting the second clock signal LC_In with a second frequency, and the enable control unit 220 can output an enable signal according to the control signal.

[0064] In some embodiments, the enable control unit 220 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a seventh switching device Q7, an eighth switching device Q8, a ninth switching device Q9, and a voltage detection unit 221.

[0065] The first end of the first resistor R1 is used to connect to the input voltage VIN. The second end of the first resistor R1 is respectively connected to the first end of the second resistor R2 and the input end of the voltage detection unit 221. The second end of the second resistor R2 is grounded. The output end of the voltage detection unit 221 is connected to the control end of the seventh switching device Q7. The first end of the seventh switching device Q7 is respectively connected to the first end of the ninth switching device Q9, the first end of the fifth resistor R5, and the first end of the third resistor R3. The second end of the seventh switching device Q7 is grounded. The second end of the fifth resistor R5 is used to connect to the operating voltage VCC. The second end of the third resistor R3 is respectively connected to the control end of the ninth switching device Q9 and the first end of the fourth resistor R4. The second end of the ninth switching device Q9 is connected to the level conversion unit 210. The second end of the fourth resistor R4 is connected to the first end of the eighth switching device Q8. The second end of the eighth switching device Q8 is grounded. The control end of the eighth switching device Q8 is connected to the timing control module 300.

[0066] Both the seventh switching device Q7 and the eighth switching device Q8 are N-type transistors, and the ninth switching device Q9 is a P-type transistor. The voltage detection unit 221 is used to control the seventh switching device Q7 to conduct when the input voltage VIN is less than or equal to the first preset voltage. The eighth switching device Q8 is turned on or off according to the control signal of the timing control module 300.

[0067] When the seventh switching device Q7 is turned off and both the eighth switching device Q8 and the ninth switching device Q9 are turned on, the enable control unit 220 can output a corresponding enable signal.

[0068] In some embodiments, the gate drive circuit 10 further includes a feedback module 400. The feedback module 400 is connected to the timing control module 300 and is used to provide a feedback voltage to the timing control module 300 based on the operating voltage VCC. The timing control module 300 can be used to output a second clock signal after the feedback voltage is greater than the second preset voltage.

[0069] It can be understood that the second preset voltage can be set according to the first preset voltage, or the specific parameters of the feedback module 400 can be configured according to the first preset voltage, so that the timing control module 300 powers on and starts before the level conversion module 200, ensuring that the second clock signal LC_In with the first frequency can be received when the level conversion module 200 powers on and starts.

[0070] In some embodiments, current-limiting resistors are provided on both the high-level trace and the low-level trace to limit the current when the first switching device Q1 and the second switching device Q2 are turned on simultaneously, avoiding triggering overcurrent protection.

[0071] Figure 5The flowchart of the power-on startup method provided by an embodiment of the present application is shown. For the sake of convenience of description, only the parts related to this embodiment are shown and are described in detail as follows: A power-on startup method is applied to the gate driving circuit 10 as described in any of the above embodiments. As Figure 1 shown, the gate driving circuit 10 includes: a GOA module 100 and a level conversion module 200.

[0072] The GOA module 100 includes an output unit 110 and a pull-down maintenance unit 120. The output unit 110 is configured to generate and output a scan signal based on the first clock signal CK when the voltage of the charging node PU of the GOA module 100 is greater than or equal to a preset threshold. The pull-down maintenance unit 120 is connected to the charging node PU and the low-level trace; It is connected to the pull-down maintenance unit 120 through a half-bridge switch circuit 130. The level conversion module 200 is configured to generate and output an inverted third clock signal LC1 and a fourth clock signal LC2 to the pull-down maintenance unit 120 according to the second clock signal LC_In. The third clock signal LC1 and the fourth clock signal LC2 are used to control the on and off of the pull-down maintenance unit 120 through the half-bridge switch circuit 130; The power-on startup method includes: step S100 to step S200.

[0073] Step S100: Before the level conversion module 200 is powered on and started up to after the level conversion module 200 is powered on and started up, a second clock signal LC_In with a first frequency is provided to the level conversion module 200.

[0074] Step S200: After the level conversion module 200 is powered on and started up, a second clock signal LC_In with a second frequency is provided to the level conversion module 200. Wherein, the second frequency is lower than the first frequency.

[0075] Specifically, in step S200, a second clock signal LC_In with a second frequency can be provided to the level conversion module 200 after a certain duration from when the level conversion module 200 is powered on and started up.

[0076] In some embodiments, step S200 can also be set to provide a second clock signal LC_In with a second frequency to the level conversion module 200 after providing a second clock signal LC_In with a first frequency to the level conversion module 200 for a preset duration.

[0077] It can be understood that the power-on startup method can be specifically implemented by the timing control module 300 of the gate driving circuit 10.

[0078] By enabling the shilling timing control module 300 to provide a second clock signal LC_In with a first frequency to the level conversion module 200 before the level conversion module 200 powers on and after it powers on, the level conversion module 200 can output an inverted third clock signal LC1 and a fourth clock signal LC2 according to the second clock signal LC_In with the first frequency within a short time after powering on, avoiding the situation where both the third clock signal LC1 and the fourth clock signal LC2 are at a high level or both are at a low level, thereby avoiding the situation where two switching devices of the half-bridge switching circuit 130 are turned on simultaneously, resulting in overcurrent protection of the trigger gate drive circuit 10.

[0079] Figure 6 The figure shows a schematic diagram of a display panel provided by an embodiment of the present application. For the sake of convenience of description, only the parts related to this embodiment are shown and are described in detail as follows: A display panel 20 includes a plurality of cascaded gate drive circuits 10 as described in any of the above embodiments and a plurality of pixel circuits 21 corresponding to each of the gate drive circuits 10 one by one. The gate drive circuit 10 is connected to the corresponding pixel circuit 21. The nth-stage gate drive circuit 10 is configured to generate and output a scan signal applied to the pixel circuit 21 of the nth row based on the first clock signal during the corresponding scan period.

[0080] Since the display panel 20 includes the gate drive circuit 10 of any of the above embodiments, the display panel 20 has the beneficial effects of the gate drive circuit 10 of any of the above embodiments, which will not be elaborated here.

[0081] In some embodiments, the display panel 20 may specifically be a liquid crystal display panel.

[0082] In one embodiment, the display panel 20 further includes a power supply circuit 22. The power supply circuit 22 is configured to generate and output a working voltage VCC, a high-level voltage VGH, and a low-level voltage VGL based on an input voltage VIN. The high-level voltage VGH and the low-level voltage VGL are respectively provided to the gate drive circuit 10 through a high-level trace and a low-level trace.

[0083] In one embodiment, the time node when the feedback voltage output by the feedback module 400 reaches the second preset voltage precedes the first rising edge of the high-level voltage VGH.

[0084] It can be understood that by configuring the feedback module 400, the conversion coefficient between the working voltage VCC and the feedback voltage can be adjusted, and the time node when the feedback voltage reaches the second preset voltage can be controlled. So that the timing control module 300 can output the second clock signal before other modules (such as the level conversion module 200) that work according to the high-level voltage VGH are powered on.

[0085] Figure 7 The figure shows a schematic diagram of a display device provided by an embodiment of the present application. For the sake of convenience of description, only the parts related to this embodiment are shown and are described in detail as follows: A display device 30 includes a display panel 20 as described in any of the above embodiments.

[0086] Since the display device 30 includes the display panel 20 as described in any of the above embodiments, the display device 30 has the beneficial effects of the display panel 20 as described in any of the above embodiments, which will not be elaborated here.

[0087] In some embodiments, the display device 30 may specifically be a smart device such as a mobile phone or a computer.

[0088] Through the description of the above embodiments, those skilled in the art can understand that for the convenience and conciseness of description, only the above-mentioned division of each functional module is used as an example for illustration. In practical applications, the above functions can be allocated to different functional modules according to needs, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0089] It should be understood that the devices and methods disclosed in several embodiments provided by the present application can be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another device. In addition, some features can be ignored or not executed. In addition, the couplings or direct couplings or communication connections shown or discussed with each other can be through some interfaces. The indirect couplings or communication connections of devices or units can be in electrical, mechanical or other forms.

[0090] The units described as separate components may or may not be physically separated. The components shown as units may be one physical unit or multiple physical units. That is, they can be located in one place or distributed to multiple different places. The parts or all of the units can be selected according to actual needs to achieve the purpose of this solution.

[0091] In addition, each functional unit in various embodiments of the present application can be integrated in a processing unit; can also exist physically separately; can also be that some units are integrated in one unit and some units exist physically separately. The above integrated units can be implemented in the form of hardware or in the form of software functional units.

[0092] It should be noted that all or part of the above-described various embodiments provided in the present application (for example, part or all of any feature) can be arbitrarily combined or used in combination with each other.

[0093] The above content is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes: A GOA module, where the GOA module includes an output unit and a pull-down maintenance unit. The output unit is configured to generate and output a scan signal based on a first clock signal when the voltage of a charging node of the GOA module is greater than or equal to a preset threshold. The pull-down maintenance unit is connected between the charging node and a low-level trace connection; A timing control module, connected to a level conversion module, configured to provide a second clock signal with a first frequency to the level conversion module from before the level conversion module powers on and starts up to after the level conversion module powers on and starts up; and configured to adjust the frequency of the second clock signal from the first frequency to a second frequency after the level conversion module powers on and starts up; the second frequency is lower than the first frequency; The level conversion module is connected to the pull-down maintenance unit through a half-bridge switching circuit of the GOA module. The level conversion module is configured to output an inverted third clock signal and a fourth clock signal to the pull-down maintenance unit according to the second clock signal. The third clock signal and the fourth clock signal are used to control the on and off of the pull-down maintenance unit through the half-bridge switching circuit.

2. The gate driving circuit according to claim 1, wherein The half-bridge switching circuit includes a first switching device and a second switching device, and the pull-down maintenance unit includes a third switching device; A first end of the first switching device is connected to a high-level trace, a second end of the first switching device is connected to a control end of the third switching device, a first end of the second switching device is connected to the control end of the third switching device, a second end of the second switching device is connected to the low-level trace, and control ends of the first switching device and the second switching device are both connected to the level conversion module to respectively access the third clock signal and the fourth clock signal; A first end of the third switching device is connected to the charging node, and a second end of the third switching device is connected to the low-level trace.

3. The gate driving circuit according to claim 1, wherein, The output unit includes a fourth switching device and a bootstrap capacitor; A first end of the bootstrap capacitor is connected to the charging node, a first end of the fourth switching device is configured to access the first clock signal, a second end of the fourth switching device is connected to a second end of the bootstrap capacitor, a control end of the fourth switching device is connected to the charging node, and a second end of the fourth switching device is configured to output the scan signal.

4. The gate driving circuit according to claim 1, wherein The GOA module further includes a pull-up unit, which is connected between the charging node and the high-level trace. The pull-up unit is configured to pull up the voltage of the charging node to a high level before the output unit generates a high-level pulse of the scan signal according to a high-level pulse of the first clock signal.

5. The gate driving circuit according to claim 1, wherein The gate driving circuit further includes a pull-down unit; The pull-down unit is configured to pull down the voltage of an output end of the output unit to a low level before the next rising edge of the first clock signal after the falling edge of the scan signal.

6. The gate driving circuit according to any one of claims 1 to 5, characterized in that, The timing control module is further configured to output a fifth clock signal to the level conversion module after outputting the second clock signal of the second frequency, and the level conversion module is configured to output the first clock signal according to the fifth clock signal.

7. The gate driving circuit according to any one of claims 1 to 5, characterized in that, The level conversion module includes a level conversion unit and an enable control unit; The enable control unit is connected to the level conversion unit and the timing control module, and is configured to output an enable signal after the timing control module outputs the second clock signal of the second frequency and the input voltage of the gate driving circuit is greater than a first preset voltage; The level conversion unit is configured to be powered on and started after receiving the enable signal.

8. Power-on startup method, characterized in that, Applied to a gate driving circuit, the gate driving circuit includes: A GOA module, the GOA module includes an output unit and a pull-down maintenance unit, the output unit is configured to generate and output a scan signal based on the first clock signal when the voltage of the charging node of the GOA module is greater than or equal to a preset threshold, and the pull-down maintenance unit is connected to the charging node and a low-level trace; A level conversion module, connected to the pull-down maintenance unit through a half-bridge switch circuit, the level conversion module is configured to generate and output an inverted third clock signal and a fourth clock signal to the pull-down maintenance unit according to the second clock signal, and the third clock signal and the fourth clock signal are used to control the conduction and cutoff of the pull-down maintenance unit through the half-bridge switch circuit; The power-on startup method includes: Before the level conversion module is powered on and started, and after the level conversion module is powered on and started, providing the second clock signal of the first frequency to the level conversion module; After the level conversion module is powered on and started, adjusting the frequency of the second clock signal from the first frequency to a second frequency; the second frequency is lower than the first frequency.

9. Display panel, characterized in that, Including a plurality of cascaded gate driving circuits as described in any one of claims 1 to 7, wherein the nth-level gate driving circuit is configured to generate and output a scan signal applied to the pixel circuit of the nth row in the display panel based on the first clock signal during a corresponding scan period.

10. The display panel according to claim 9, characterized in that, The display panel further includes a power supply circuit, and the power supply circuit is configured to generate and output a working voltage and a high-level voltage based on an input voltage; The gate driving circuit further includes a feedback module, the feedback module is connected to the timing control module of the gate driving circuit, and the feedback module is configured to provide a feedback voltage to the timing control module based on the working voltage, and the timing control module is configured to output a second clock signal after the feedback voltage is greater than a second preset voltage; The time node when the feedback voltage reaches the second preset voltage precedes the first rising edge of the high-level voltage.

11. Display device, characterized in that, Including a display panel as described in claim 9 or 10.

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