Semiconductor structure

Abstract

The embodiment of the invention relates to the technical field of semiconductors, and provides a semiconductor structure, which comprises a first chip and a second chip which are bonded with each other, the first chip comprises a plurality of storage arrays arranged in an array; the second chip comprises a plurality of logic sections corresponding to the storage array, each logic section comprises at least one pair of word line driving sections and a peripheral circuit section, each pair of word line driving sections comprises two word line driving sections which are arranged at intervals, and each part of the peripheral circuit section is located between the adjacent word line driving sections; or each logic section comprises a word line driving section of which the orthographic projection on the first chip is H-shaped, the word line driving section encircles to form two concave areas which are arranged at intervals along the extension direction of the word lines, and the peripheral circuit sections are respectively positioned in the two concave areas. The embodiment of the invention is at least beneficial to improving the layout diversity of the word line driving section in the second chip so as to reduce the wiring difficulty in the first chip.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure. Background Art

[0002] To save chip area, the memory chip including the memory cell array and the logic chip including the logic circuit including the sense amplifier and the word line driver are manufactured on two different wafers, and the two different wafers are hybrid bonded by direct hybrid bonding process. According to this method, the memory cell array and the logic circuit can be manufactured by separate processes.

[0003] However, the layout of the sense amplifier and the word line driver in the logic chip needs to be optimized to better establish an electrical connection relationship with the memory cell array in the memory chip. Summary of the invention

[0004] The disclosed embodiment provides a semiconductor structure, which is at least conducive to improving the layout diversity of the word line driving block in the second chip, so as to reduce the wiring difficulty in the first chip.

[0005] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a semiconductor structure, including: a first chip and a second chip bonded to each other; the first chip includes a plurality of memory arrays arranged in an array; the second chip includes a plurality of logic blocks corresponding to the memory arrays, each of the logic blocks includes at least a pair of word line drive blocks and a peripheral circuit block, the pair of word line drive blocks includes two word line drive blocks spaced apart, and each part of the peripheral circuit block is located between adjacent word line drive blocks; or, each of the logic blocks includes: a word line drive block whose orthographic projection on the first chip is an H-shape, the word line drive block encloses two recessed areas spaced apart along a word line extension direction, and the peripheral circuit blocks are respectively located in the two recessed areas.

[0006] In some embodiments, the logic block includes two pairs of word line driving blocks spaced apart along a word line extension direction X, and the orthographic projection of the peripheral circuit block in each logic block on the first chip is in a cross shape.

[0007] In some embodiments, in the word line extension direction X, the size of the word line driver block is equal to the size of the logic block, and in the bit line extension direction, the peripheral circuit block is arranged between adjacent word line driver blocks, and the word line extension direction X intersects with the bit line extension direction Y.

[0008] In some embodiments, in the bit line extension direction Y, each of the word line driving sections has a convex portion facing the peripheral circuit section, and the peripheral circuit section has a concave portion corresponding to the convex portion.

[0009] In some embodiments, along the bit line extension direction Y, the minimum value of the width of the peripheral circuit section is greater than the maximum value of the width of the word line driving section.

[0010] In some embodiments, the two convex portions in the pair of word line driving sections face each other in the bit line extension direction Y, and the convex portion is disposed in the middle of the word line driving section.

[0011] In some embodiments, the peripheral circuit sections in two adjacent logic sections along the word line extension direction X are adjacent to each other.

[0012] In some embodiments, the logic section includes a pair of word line driving sections, and the pair of word line driving sections are spaced apart along the word line extension direction X. In the word line extension direction X, the peripheral circuit section is disposed between the adjacent word line driving sections.

[0013] In some embodiments, each logic section further includes: a first sense amplifier section and a second sense amplifier section that are opposite and spaced apart along the bit line extension direction. The word line driving section and the peripheral circuit section are both located between the first sense amplifier section and the second sense amplifier section, and the word line extension direction X and the bit line extension direction Y intersect.

[0014] In some embodiments, the first sense amplifier section of one of two adjacent logic sections along the bit line extension direction Y is adjacent to the second sense amplifier section of the other. The adjacent first sense amplifier section and the second sense amplifier section form a sense amplifier section; the memory array includes a plurality of bit lines spaced apart along the word line extension direction X, and the bit line is electrically connected to one of the two sense amplifier sections corresponding to the memory array.

[0015] In some embodiments, the first chip further includes: a first bit line connection section facing the first sense amplifier section, a second bit line connection section facing the second sense amplifier section, and a word line connection section facing the word line driving section; wherein, the first sense amplifier section and the first bit line connection section are bonded to each other, the second sense amplifier section and the second bit line connection section are bonded to each other, and the word line driving section and the word line connection section are bonded to each other.

[0016] In some embodiments, the first chip further includes: a plurality of word lines arranged at intervals along the bit line extension direction Y, and a first wiring layer having a plurality of first wirings, the first wirings corresponding to the word lines one by one; the bit line extension direction Y and the word line extension direction X form a reference plane, and the word lines whose orthographic projections on the reference plane overlap with the orthographic projection of the word line connection section on the reference plane are first word lines, and the remaining word lines are second word lines, the first wirings corresponding to the first word lines are first sub-wirings, and the first wirings corresponding to the second word lines are second sub-wirings; wherein, the first sub-wiring extends along the word line extension direction X; the second sub-wiring includes a first connection portion and a second connection portion connected in contact, the first connection portion extends along the word line extension direction X, and the second connection portion extends along the bit line extension direction Y; one end of any one of the first wirings is electrically connected to the word line, and the other end is located in the orthographic projection of the word line connection section on the reference plane.

[0017] In some embodiments, the first chip further includes: a plurality of first bonding posts arranged in an array along the bit line extension direction Y and the word line extension direction X, at least part of the first bonding posts located in the word line connection section are electrically connected to one end of the first wiring, and the other end of the first wiring is electrically connected to the word line.

[0018] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0019] The memory array in the first chip and the logic section in the second chip are facing each other, that is, the memory array and the logic section are stacked in the vertical direction, which is beneficial to reducing the layout area of a single chip in the horizontal direction. Wherein, the vertical direction is the direction from the first chip to the second chip, and the horizontal direction is perpendicular to the vertical direction. In some cases, each part of the peripheral circuit section is located between adjacent word line driving sections. In other words, for the peripheral circuit section, all word line driving sections are located in relatively marginal areas, so as to ensure that the peripheral circuit section is centrally arranged in the middle area, and the peripheral circuit section is an integral body that will not be separated by the word line driving sections, so that the layout of the peripheral circuit section in a single logic section is more concentrated; in other cases, the word line driving section whose orthographic projection on the first chip is in the shape of an "H" divides the peripheral circuit section into two parts. For any one of the two parts, the word line driving section is also located in a relatively marginal area, so as to make the layout of any one of the two parts more concentrated, and the peripheral circuit section of one logic section can be connected to the peripheral circuit section of another logic section, which is beneficial to improving the concentration between the peripheral circuit sections of multiple logic sections. Therefore, the various layouts of the word line driving section and the peripheral circuit section provided by the embodiments of the present disclosure are all beneficial to improving the concentration of the layout of the peripheral circuit section. Description of the Drawings

[0020] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, the drawings in the figures do not constitute a scale limitation; In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0021] Figure 1 It is a three-dimensional structure schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0022] Figure 2 It is a top view structure schematic diagram of a logic block in the semiconductor structure provided by an embodiment of the present disclosure;

[0023] Figure 3 It is another three-dimensional structure schematic diagram of the semiconductor structure provided by an embodiment of the present disclosure;

[0024] Figure 4 It is another top view structure schematic diagram of the logic block in the semiconductor structure provided by an embodiment of the present disclosure;

[0025] Figure 5 It is yet another top view structure schematic diagram of the logic block in the semiconductor structure provided by an embodiment of the present disclosure;

[0026] Figure 6 It is Figure 5 a top view structure schematic diagram of a word line driving block and a peripheral circuit block;

[0027] Figure 7 It is yet another top view structure schematic diagram of the logic block in the semiconductor structure provided by an embodiment of the present disclosure;

[0028] Figure 8 It is a top view structure schematic diagram of two Figure 2 adjacent logic blocks shown;

[0029] Figure 9 It is yet another top view structure schematic diagram of the logic block in the semiconductor structure provided by an embodiment of the present disclosure;

[0030] Figure 10 It is a top view structure schematic diagram of two Figure 2 adjacent logic blocks shown in another way;

[0031] Figure 11A top - view structural diagram of multiple bit - lines in the storage array provided by the embodiments of the present disclosure;

[0032] Figure 12 A top - view structural diagram of the first chip in the semiconductor structure provided by the embodiments of the present disclosure;

[0033] Figure 13 A partial top - view structural diagram of the second wiring layer in the first chip provided by the embodiments of the present disclosure;

[0034] Figure 14 A top - view structural diagram of multiple word - lines in the storage array provided by the embodiments of the present disclosure;

[0035] Figure 15 A top - view structural diagram of the first wiring layer in the first chip provided by the embodiments of the present disclosure;

[0036] Figure 16a A partial top - view structural diagram of the first sub - wiring and the first bonding post in the first chip provided by the embodiments of the present disclosure;

[0037] Figure 16b A partial top - view structural diagram of the second sub - wiring and the first bonding post in the first chip corresponding to the word - line opposite to the peripheral region provided by the embodiments of the present disclosure;

[0038] Figure 16c A partial top - view structural diagram of the second sub - wiring and the first bonding post in the first chip corresponding to the word - line opposite to the connection section of the first bit - line provided by the embodiments of the present disclosure;

[0039] Figure 17 A cross - sectional structural diagram of the first chip and the second chip provided by the embodiments of the present disclosure. Detailed implementation manners

[0040] As can be seen from the background art, the layout of sense amplifiers and word - line drivers in logic chips needs to be optimized.

[0041] The present disclosure provides a semiconductor structure. The memory array in the first chip and the logic block in the second chip are facing each other, that is, the memory array and the logic block are stacked in the vertical direction, which is beneficial to reducing the layout area of a single chip in the horizontal direction. Here, the vertical direction is the direction from the first chip to the second chip, and the horizontal direction is perpendicular to the vertical direction. In some cases, each part of the peripheral circuit block is located between adjacent word line driving blocks. In other words, for the peripheral circuit block, all word line driving blocks are located in the relatively marginal areas, which is beneficial to ensuring that the peripheral circuit block is centrally arranged in the middle area, and the peripheral circuit block is an integral whole that will not be separated by the word line driving blocks, so that the layout of the peripheral circuit block in a single logic block is more concentrated. In other cases, the word line driving block in the shape of an "H" in the orthographic projection on the first chip divides the peripheral circuit block into two parts. For either of the two parts, the word line driving block is also located in the relatively marginal area, which is beneficial to making the layout of either of the two parts more concentrated, and the peripheral circuit block of one logic block can be connected to the peripheral circuit block of another logic block, which is beneficial to improving the concentration between the peripheral circuit blocks of multiple logic blocks. Therefore, the various layouts of the word line driving block and the peripheral circuit block provided by the embodiments of the present disclosure are all beneficial to improving the concentration of the layout of the peripheral circuit block.

[0042] The following will elaborate on each embodiment of the present disclosure with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present disclosure, many technical details are proposed for readers to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions required to be protected by the embodiments of the present disclosure can still be implemented.

[0043] The embodiments of the present disclosure provide a semiconductor structure. The following will describe in detail the semiconductor structure provided by the embodiments of the present disclosure with reference to the accompanying drawings.

[0044] Reference Figures 1 to 9 , the layout of the word line driving block and the peripheral circuit block in each logic block in the semiconductor structure includes at least the following two major types of embodiments.

[0045] Among them, Figure 1 is a three-dimensional structure schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure; Figure 2 is a top view structure schematic diagram of a logic block in a semiconductor structure provided by an embodiment of the present disclosure; Figure 3 is another three-dimensional structure schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure; Figure 4 is another top view structure schematic diagram of a logic block in a semiconductor structure provided by an embodiment of the present disclosure; Figure 5Another top - view structure diagram of the logic block in the semiconductor structure provided by the embodiments of the present disclosure; Figure 6 is Figure 5 a top - view structure diagram of the word - line driving block and the peripheral - circuit block; Figure 7 Another top - view structure diagram of the logic block in the semiconductor structure provided by the embodiments of the present disclosure; Figure 8 is Figure 2 a top - view structure diagram of the adjacency of two logic blocks shown; Figure 9 Another top - view structure diagram of the logic block in the semiconductor structure provided by the embodiments of the present disclosure.

[0046] In some embodiments, referring to Figure 1 , Figure 2 , Figure 5 , Figure 7 or Figure 9 , taking the markings in Figure 1 and Figure 2 as an example, the semiconductor structure includes: a first chip 101 and a second chip 102 bonded to each other; the first chip 101 includes a plurality of memory arrays 100 arranged in an array; the second chip 102 includes a plurality of logic blocks 103 corresponding to the memory arrays 100, each logic block 103 includes at least a pair of word - line driving blocks 104 and peripheral - circuit blocks 105, a pair of word - line driving blocks 104 includes two word - line driving blocks 104 arranged at intervals, and each part of the peripheral - circuit block 105 is located between adjacent word - line driving blocks 104. It should be noted that the examples in Figure 2 , Figure 5 , Figure 7 or Figure 9 will be described in detail respectively later.

[0047] In other embodiments, with reference to Figure 3 and Figure 4 , the semiconductor structure includes: a first chip 201 and a second chip 202 bonded to each other; the first chip 201 includes a plurality of memory arrays 200 arranged in an array; the second chip 202 includes a plurality of logic blocks 203 corresponding to the memory arrays 200, each logic block 203 includes: a word - line driving block 204 whose orthographic projection on the first chip 201 is in an H shape, the word - line driving block 204 encloses two recessed areas 214 arranged at intervals along the word - line extension direction X, and the peripheral - circuit blocks 205 are respectively located in the two recessed areas 214.

[0048] It should be noted that Figure 1 only one memory array 100 in the first chip 101 is shown in Figure 3Two memory arrays 200 arranged horizontally in the first chip 201 are shown. In practical applications, the number of memory arrays 100 and 200 in the first chips 101 and 201 is not limited, and multiple memory arrays 100 and 200 can be arranged only along the bit line extension direction Y or only along the word line extension direction X, or multiple memory arrays 100 and 200 can be arranged in an array along the bit line extension direction Y and the word line extension direction X. The array arrangement here includes but is not limited to square arrangement, rectangular arrangement or hexagonal arrangement. It can be understood that, referring to Figure 1 and Figure 2 , the memory array 100 in the first chip 101 is opposite to the logic block 103 in the second chip 102, that is, the memory array 100 and the logic block 103 are stacked along the vertical direction Z, which is beneficial to reducing the layout area of a single chip in the horizontal direction H. Among them, the vertical direction Z is the direction from the first chip 101 to the second chip 102, and the horizontal direction H is perpendicular to the vertical direction Z. It should be noted that, Figure 3 and Figure 4 In the example shown, the correspondence between the memory array 200 in the first chip 201 and the logic block 203 in the second chip 202 is similar to that in the example shown in Figure 1 and Figure 2 , and will not be elaborated here.

[0049] In addition, in some cases, referring to Figure 1 and Figure 2 , each logic block 103 includes at least a pair of word line driving blocks 104, and each part of the peripheral circuit block 105 is located between adjacent word line driving blocks 104. In other words, for the peripheral circuit block 105, all word line driving blocks 104 are located in the relatively marginal areas, which is beneficial to ensuring that the peripheral circuit block 105 is centrally arranged in the middle area, and the peripheral circuit block 105 is an integral whole that will not be separated by the word line driving blocks 104, so that the layout of the peripheral circuit block 105 in a single logic block 103 is more concentrated and more convenient for circuit design; in other cases, referring to Figure 3 and Figure 4, the orthographic projection on the first chip 201 is the word line driving section 204 in the shape of an H. The word line driving section 204 divides the peripheral circuit section 205 into two parts. For either of the two parts, the word line driving section 204 is also in the area at the relative edge, which is beneficial to making the layout of either of the two parts more concentrated. Moreover, the peripheral circuit section 205 of one logic section 203 can be connected to the peripheral circuit section 205 of another logic section 203, which is beneficial to improving the concentration among the peripheral circuit sections 205 of multiple logic sections 203. Therefore, the various layouts of the word line driving sections 104, 204 and the peripheral circuit sections 105, 205 provided by the embodiments of the present disclosure are all beneficial to improving the concentration of the layout of the peripheral circuit sections 105, 205.

[0050] It should be noted that, taking the markings in Figure 1 and Figure 2 as an example, the storage array 100 includes multiple word lines arranged at intervals. The word line extension direction X is the extension direction of the word lines, and the word line extension direction X and the horizontal direction H are in the same horizontal plane.

[0051] In some cases, the storage array 100 includes multiple bit lines arranged at intervals. The bit line extension direction Y is the extension direction of the bit lines, and the bit line extension direction Y, the word line extension direction X, and the horizontal direction H are all in the same horizontal plane. In one example, the bit line extension direction Y is perpendicular to the word line extension direction X.

[0052] In some cases, the second chips 102, 202 including multiple logic sections 103, 203 corresponding to the storage arrays 100, 200 means that: the storage arrays 100, 200 and the logic sections 103, 203 correspond one by one. This correspondence can refer to both the corresponding relationship in electrical connection and the corresponding relationship in physical position. The corresponding relationship in physical position includes: the orthographic projections of the storage arrays 100, 200 on the first chips 101, 201 coincide with the orthographic projections of the logic sections 103, 203 on the first chips 101, 201.

[0053] The following will detail the case where each logic section includes at least a pair of word line driving sections 104 and peripheral circuit sections 105.

[0054] In some embodiments, referring to Figure 2, in the word line extension direction X, the size of the word line driving section 104 is equal to that of the logic section 103. In the bit line extension direction Y, the peripheral circuit section 105 is disposed between adjacent word line driving sections 104, and the word line extension direction X intersects with the bit line extension direction Y. Thus, the logic section 103 only includes a pair of word line driving sections 104, and the pair of word line driving sections 104 are spaced apart along the bit line extension direction Y. In the bit line extension direction Y, the peripheral circuit section 105 is disposed between adjacent word line driving sections 104, which is beneficial to making the layout of the peripheral circuit section 105 concentrated in an entire area, avoiding the peripheral circuit section 105 being partitioned into multiple areas, so as to facilitate subsequent layout of the peripheral circuit sections 105 in multiple logic sections 103 in a mutually connected complete area, facilitating unified design of the wiring in multiple peripheral circuit sections 105 to reduce the wiring difficulty in the peripheral circuit section 105, and thus being beneficial to unified management and control of multiple peripheral circuit sections 105.

[0055] In some embodiments, with continued reference to Figure 2 , the orthographic projection of the word line driving section 104 on the first chip 101 and the orthographic projection of the peripheral circuit section 105 on the first chip 101 are both rectangles.

[0056] In other embodiments, with reference to Figure 5 and Figure 6 , on the basis that in the word line extension direction X, the size of the word line driving section 304 is equal to that of the logic section 303, and in the bit line extension direction Y, the peripheral circuit section 305 is disposed between adjacent word line driving sections 304, in the bit line extension direction Y, each word line driving section 304 has a convex portion 314 facing the peripheral circuit section 305, and the peripheral circuit section 305 has a concave portion 315 corresponding to the convex portion 314.

[0057] It should be noted that the convex portion 314 and the concave portion 315 are located in the same area. To clearly show the convex portion 314 in the word line driving section 304 and the concave portion 315 in the peripheral circuit section 305, Figure 6 in Figure 5 the word line driving section 304 and the peripheral circuit section 305 in the semiconductor structure shown are drawn in a split manner.

[0058] It can be understood that the total layout space occupied by a pair of word line driving sections 304 needs to be used to control all the word lines in a corresponding memory array 100. At the same time, it is also desired to layout the peripheral circuit sections 105 in multiple logic sections 103 in a mutually connected complete area, and the area where adjacent peripheral circuit sections 105 are connected is not too small to cause too small a spacing between adjacent wirings. Based on this, the design Figure 5As shown, for a pair of word line driving sections 304, in the edge region of the logic section 303, the width of the word line driving section 304 in the bit line extending direction Y is designed to be smaller, so as to reserve a larger width in the logic section 303 for laying out the peripheral circuit section 305. That is, the peripheral circuit section 305 located in the edge region of the logic section 303 has a larger width in the bit line extending direction Y, so as to increase the width of the connected region between adjacent peripheral circuit sections 305 in the bit line extending direction Y, facilitating more wirings in adjacent peripheral circuit sections 105 to be shared, that is, enabling more wirings to penetrate through multiple adjacent peripheral circuit sections 305. In addition, each word line driving section 304 is designed to have a convex portion 314 facing the peripheral circuit section 305, which is beneficial to ensuring that while reserving a larger width for the layout of the peripheral circuit section 305 in the edge region, the word line driving section 304 occupies a sufficient large layout space. For example, increasing the width of a part of the word line driving section 304 in the bit line extending direction Y to control all the word lines 108 in a corresponding memory array 100.

[0059] In some embodiments, referring to Figure 6 , Figure 6 For Figure 5 in, along the bit line extending direction Y, the minimum value W1 of the width of the peripheral circuit section 305 is greater than the maximum value W2 of the width of the word line driving section 304.

[0060] It can be understood that, in the bit line extending direction Y, each word line driving section 304 has a convex portion 314 facing the peripheral circuit section 305, and the peripheral circuit section 305 has a concave portion 315 corresponding to the convex portion 314. Based on this, the minimum value W1 of the width of the peripheral circuit section 305 is the width of the peripheral circuit section 305 at the position with the concave portion 315; the maximum value W2 of the width of the word line driving section 304 is the width of the word line driving section 304 at the position with the convex portion 314. In this way, W1 is greater than W2, which is beneficial to making the layout space of the peripheral circuit section 305 more concentrated, further increasing the width of the peripheral circuit section 305 located in the edge region of the logic section 303 in the bit line extending direction Y, so as to further increase the width of the connected region between adjacent peripheral circuit sections 105 in the bit line extending direction Y, facilitating more wirings in adjacent peripheral circuit sections 105 to be shared, that is, enabling more wirings to penetrate through multiple adjacent peripheral circuit sections 105.

[0061] In some embodiments, referring to Figure 5 or Figure 6, two protrusions 314 in a pair of word line driving sections 304 face each other along the bit line extending direction Y, and the protrusions 314 are centrally arranged in the word line driving sections 304; in some embodiments, the two protrusions in a pair of word line driving sections are staggered along the word line extending direction.

[0062] In some cases, that the two protrusions 314 face each other along the bit line extending direction Y means that, with the projection plane perpendicular to the bit line extending direction Y as a reference, the orthographic projections of the two protrusions 314 on this projection plane coincide.

[0063] In still other embodiments, referring to Figure 7 , the logic section 403 includes two pairs of word line driving sections 404 arranged at intervals along the word line extending direction X, and the peripheral circuit sections 405 in each logic section 403 are in a cross shape in the orthographic projection on the first chip 101 (referring to Figure 1 ).

[0064] It can be understood that the two pairs of word line driving sections 404 in total include 4 word line driving sections 404, and the 4 word line driving sections 404 can be described as being combined in pairs to form a pair of word line driving sections 404. Taking two word line driving sections 404 arranged at intervals along the bit line extending direction Y as a pair of word line driving sections 404 as an example, the two pairs of word line driving sections 404 are arranged at intervals along the word line extending direction X. Based on this, the peripheral circuit section 405 is located between any two word line driving sections 404. In this way, it is beneficial to make the layout of the peripheral circuit section 405 concentrated in an entire area, avoiding the peripheral circuit section 405 being divided into multiple areas, so as to facilitate the subsequent layout of the peripheral circuit sections 405 in multiple logic sections 403 in a mutually connected complete area, facilitating the unified design of the wiring in multiple peripheral circuit sections 405 to reduce the wiring difficulty in the peripheral circuit section 405, and thus being beneficial to the unified management and control of multiple peripheral circuit sections 405.

[0065] In some cases, referring to Figure 7 , with the plane formed by the bit line extending direction Y and the word line extending direction X as the projection plane, the orthographic projection shapes of the 4 word line driving sections 404 on this projection plane are the same, which is beneficial to improving the regularity of the wiring in the word line driving section 404 to reduce the wiring difficulty.

[0066] In some cases, two adjacent word line driving sections 404 along the bit line extending direction Y face each other, that is, with the projection plane perpendicular to the bit line extending direction Y as a reference, the orthographic projections of the two word line driving sections 404 on this projection plane coincide; and / or, in some cases, two adjacent word line driving sections 404 along the word line extending direction X face each other, that is, with the projection plane perpendicular to the word line extending direction X as a reference, the orthographic projections of the two word line driving sections 404 on this projection plane coincide.

[0067] In the above various embodiments, taking the logic block 103 in Figure 2 as an example, referring to Figure 8 , the peripheral circuit blocks 105 in two adjacent logic blocks 103 along the word line extending direction X are adjacent. In this way, it is convenient to layout the peripheral circuit blocks 105 in multiple logic blocks 103 arranged along the word line extending direction X in a complete interconnected area, which is convenient for unified design of the wiring in the multiple peripheral circuit blocks 105 to reduce the wiring difficulty in the peripheral circuit blocks 105, and thus is beneficial to the unified management and control of the multiple peripheral circuit blocks 105. It should be noted that, Figure 5 or Figure 7 in the examples shown, the peripheral circuit blocks 305 and 405 in two adjacent logic blocks 303 and 403 along the word line extending direction X can also be adjacent; in addition, it should be noted that two adjacent logic blocks can rely on each other (without a gap) in the word line extending direction, or can be separated by an intermediate gap area.

[0068] In still some other embodiments, referring to Figure 9 , the logic block 503 includes a pair of word line driving blocks 504, the pair of word line driving blocks 504 are arranged at intervals along the word line extending direction X, and in the word line extending direction X, the peripheral circuit block 505 is arranged between adjacent word line driving blocks 504.

[0069] In some cases, continuing to refer to Figure 9 , taking the plane formed by the bit line extending direction Y and the word line extending direction X as the projection plane, the orthographic projection shapes of the two word line driving blocks 504 on this projection plane are the same, which is beneficial to improving the regularity of the wiring in the word line driving blocks 504 to reduce the wiring difficulty.

[0070] In still some other embodiments, referring to Figure 3 and Figure 4 , each logic block 203 includes: a word line driving block 204 whose orthographic projection on the first chip 201 is in an H shape, the word line driving block 204 encloses two recessed areas 214 arranged at intervals along the word line extending direction X, and the peripheral circuit blocks 205 are respectively located in the two recessed areas 214.

[0071] In this way, a logic block 203 can only have one word line driving block 204, and the orthographic projection of the word line driving block 204 on the first chip 201 is in an H shape. It should be noted that along the word line extending direction X, the orthographic projection shape of the word line driving block 204 can be regarded as an H shape; along the word line extending direction X, the orthographic projection shape of the word line driving block 204 can be regarded as an I shape.

[0072] In addition, the peripheral circuit section 205 is respectively arranged in the two recessed areas 214. For a single logic section 203, along the word line extending direction X, the peripheral circuit section 205 is divided into a left section and a right section, such that for three adjacent logic sections 203 along the word line extending direction X, the left section in the middle logic section 203 is adjacent to the right section of one logic section 203, and the right section in the middle logic section 203 is adjacent to the left section of another logic section 203. In this way, it is beneficial to establish the mutual connection of the peripheral circuit sections 205 in adjacent logic sections 203, and it is beneficial to concentrate the layout of the word line driving section 204 in a whole area, avoiding the word line driving section 204 being divided into multiple areas.

[0073] In the above various embodiments, taking the logic section 103 in Figure 2 as an example, each logic section 103 may further include: a first sense amplifier section 116 and a second sense amplifier section 126 that are opposite and spaced apart along the bit line extending direction Y. The word line driving section 104 and the peripheral circuit section 105 are both located between the first sense amplifier section 116 and the second sense amplifier section 126, and the word line extending direction X and the bit line extending direction Y intersect.

[0074] In some cases, taking the plane formed by the bit line extending direction Y and the word line extending direction X as the projection plane, the orthographic projection shapes of the first sense amplifier section 116 and the second sense amplifier section 126 on this projection plane are the same.

[0075] In the above various embodiments, taking the logic section 103 in Figure 2 as an example, referring to Figure 10 , the first sense amplifier section 116 of one of the two adjacent logic sections 103 along the bit line extending direction Y is adjacent to the second sense amplifier section 126 of the other. The adjacent first sense amplifier section 116 and second sense amplifier section 126 form a sense amplifier section 106; in combination with referring to Figure 10 and Figure 11 , the memory array 100 includes a plurality of bit lines 107 that are spaced apart along the word line extending direction X, and the bit line 107 is electrically connected to one of the two sense amplifier sections 106 corresponding to the memory array 100.

[0076] Among them, Figure 10 is another top view structure schematic diagram of the adjacency of the two logic sections shown in Figure 2 ; Figure 11 is a top view structure schematic diagram of a plurality of bit lines in the memory array provided by the present disclosure embodiment.

[0077] It can be understood that the first sense amplifier block 116 and the second sense amplifier block 126 in the same logic block 103 are electrically connected to different bit lines 107 in the same memory array 100, and one sense amplifier block 106 is composed of the first sense amplifier block 116 of one of the adjacent two logic blocks 103 and the second sense amplifier block 126 of the other. Based on this, the bit lines 107 electrically connected to the same sense amplifier block 106 come from two different memory arrays 100, so that the bit lines 107 in the two memory arrays 100 can be used as references for each other in the sense amplifier block 106.

[0078] It should be noted that Figure 4 , Figure 5 , Figure 7 or Figure 9 In the examples shown, the first sense amplifier blocks 216, 316, 416, 516 are similar to the first sense amplifier block 116 shown in Figure 2 , and the second sense amplifier blocks 226, 326, 426, 526 are similar to the second sense amplifier block 126 shown in Figure 2 , and the electrical connection relationship between the first sense amplifier block and the second sense amplifier block and the bit line 107 is similar to the example shown in Figure 2 , which will not be elaborated here. In addition, Figure 2 , Figures 4 to 10 uses SWDlayout to illustrate the word line driving block and Peri layout to illustrate the peripheral circuit block; Figure 2 , Figure 4 , Figure 5 , Figures 7 to 10 uses SA1 layout to illustrate the first sense amplifier block and SA2 layout to illustrate the second sense amplifier block.

[0079] In the above various embodiments, taking the first chip 101 and the second chip 102 shown in Figure 1 as examples, in combination with reference to Figure 2 and Figure 12 , the first chip 101 may further include: a first bit line connection block 117 (BL1 layout) facing the first sense amplifier block 116, a second bit line connection block 127 (BL2 layout) facing the second sense amplifier block 126, and a word line connection block 118 (WL layout) facing the word line driving block 104; wherein, the first sense amplifier block 116 and the first bit line connection block 117 are bonded to each other, the second sense amplifier block 126 and the second bit line connection block 127 are bonded to each other, and the word line driving block 104 and the word line connection block 118 are bonded to each other.

[0080] Wherein, Figure 12A top view structure diagram of the first chip in the semiconductor structure provided by the embodiments of the present disclosure.

[0081] In some cases, taking the plane formed by the bit line extension direction Y and the word line extension direction X as the projection plane, the fact that the first sense amplifier block 116 and the first bit line connection block 117 are facing each other means that the positive projections of the first sense amplifier block 116 and the first bit line connection block 117 on this projection plane coincide; the fact that the second sense amplifier block 126 and the second bit line connection block 127 are facing each other means that the positive projections of the second sense amplifier block 126 and the second bit line connection block 127 on this projection plane coincide; the fact that the word line driving block 104 and the word line connection block 118 are facing each other means that the positive projections of the word line driving block 104 and the word line connection block 118 on this projection plane coincide.

[0082] It can be understood that the first sense amplifier block 116 and the first bit line connection block 117 are bonded to each other, so that some bit lines 107 in the memory array 100 can be electrically connected to the first sense amplifier block 116 through the first bit line connection block 117, thereby realizing cross amplification with the reference bit line; the second sense amplifier block 126 and the second bit line connection block 127 are bonded to each other, so that some bit lines 107 in the memory array 100 can be electrically connected to the second sense amplifier block 126 through the second bit line connection block 127, thereby realizing cross amplification with the reference bit line; the word line driving block 104 and the word line connection block 118 are bonded to each other, so that the word lines 108 in the memory array 100 can be electrically connected to the word line driving block 104 through the word line connection block 118.

[0083] It should be noted that Figure 4 、 Figure 5 、 Figure 7 or Figure 9 In the examples shown, the corresponding relationships between the first bit line connection block, the second bit line connection block, and the word line connection block in the first chip and the respective blocks in the second chip are similar to those in the examples shown in Figure 2 and Figure 12 and will not be elaborated here.

[0084] In the above various embodiments, taking the first chip 101 and the second chip 102 shown in Figure 1 as examples, in combination with reference to Figure 1 and Figure 13 , the first chip 101 may further include: a second wiring layer 147 having a plurality of second wirings 137, the second wirings 137 corresponding to the bit lines 107 one by one, and the lengths of the adjacent second wirings 137 in the bit line extension direction Y are different along the word line extension direction X.

[0085] Among them, Figure 13A partial top view structural schematic diagram of the second wiring layer in the first chip provided by an embodiment of the present disclosure.

[0086] It can be understood that the second wiring layer 147 is located in the first bit line connection section 117 and the second bit line connection section 127, and the second wiring layer 147 is located on the side of the bit line 107 close to the second chip 102.

[0087] In some embodiments, referring to Figure 12 and Figure 13 , the first chip 101 may further include: a plurality of first bonding posts 119 arranged in an array along the bit line extension direction Y and the word line extension direction X. Among the first bonding posts 119 located in the first bit line connection section 117 and the second bit line connection section 127, at least some of the first bonding posts 119 are electrically connected to one end of the second wiring 137, and the other end of the second wiring 137 is electrically connected to the bit line 107 (refer to Figure 11 ).

[0088] It should be noted that Figure 13 draws a dot at both ends of the second wiring 137 to indicate the electrical connection points between the second wiring 137 and the first bonding post 119 and between the second wiring 137 and the bit line 107.

[0089] It can be understood that the plurality of first bonding posts 119 arranged in an array along the bit line extension direction Y and the word line extension direction X are in the same layer, that is, the plurality of first bonding posts 119 are in the same film layer, and adjacent first bonding posts 119 are electrically insulated. Figure 13 only shows the approximate position of each first bonding post 119 in a rectangular area. In addition, the film layer where the plurality of first bonding posts 119 are located is on the side of the second wiring layer 147 close to the second chip 102 (refer to Figure 1 ).

[0090] It should be noted that Figure 13 only shows Figure 12 the second wiring 137 and the first bonding post 119 in the partial area of the first bit line connection section 117 in Figure 13 , and the length layout of the plurality of second wirings 137 in the bit line extension direction Y in Figure 13Two different layout modes are schematically shown, and they will not be enumerated one by one here. Moreover, to show the positional relationship between the second wiring 137 and the first bonding post 119, Figure 13 in Figure 13 , a perspective drawing method is adopted for the rectangle schematically showing the approximate position where the first bonding post 119 is located.

[0091] In some cases, the arrangement modes of multiple second wirings 137 in the first bit line connection section 117 and the second bit line connection section 127 can be axially symmetric along the word line extension direction X, which is beneficial to improving the regularity of the wirings in the first bit line connection section 117 and the second bit line connection section 127, so as to reduce the wiring difficulty.

[0092] In addition, the second wiring 137 corresponds to the bit line 107 one by one, that is, each bit line 107 is equipped with a corresponding second wiring 137, and the bit line 107 realizes electrical connection with the first bonding post 119 through the corresponding second wiring 137.

[0093] It should be noted that taking the plane formed by the bit line extension direction Y and the word line extension direction X as the projection plane, Figure 13 in Figure 13 , the orthographic projection of some second wirings 137 on this projection plane will penetrate the orthographic projection of multiple first bonding posts 119 on this projection plane. However, the second wiring 137 will only realize electrical connection with the first bonding post 119 whose orthographic projection at the end overlaps with it, that is, one first bonding post 119 will only realize electrical connection with one second wiring 137. Based on this, the purpose of the different lengths of adjacent second wirings 137 in the bit line extension direction Y is to enable adjacent second wirings 137 to realize electrical connection with different first bonding posts 119.

[0094] In some cases, with reference to Figure 12 and Figure 13 , there are connecting posts (not shown in the figure) between the second wiring 137 and the bit line 107 to realize the electrical connection between the second wiring 137 and the bit line 107. In addition, one end of the second wiring 137 not electrically connected to the bit line 107 can be in contact connection with the first bonding post 119.

[0095] It should be noted that Figure 4 , Figure 5 , Figure 7 or Figure 9 In the examples shown in Figure 4 , Figure 5 , Figure 7 or Figure 9 , the bit line, the second wiring layer with multiple second wirings, and the first bonding post can also have the above characteristics, which will not be elaborated here. In addition, Figure 12 in Figure 12 , the first bit line connection section 117 is schematically shown by BL1 layout, the second bit line connection section 127 is schematically shown by BL2 layout, and the outer word line connection section 118 is schematically shown by WL layout.

[0096] In the above various embodiments, taking Figure 1 the shown first chip 101 and second chip 102 as examples, with reference to Figures 14 to 1 FIG. 6, the first chip 101 may further include: a plurality of word lines 108 arranged at intervals along the bit line extension direction Y, and a first wiring layer 158 having a plurality of first wirings 148, where the first wirings 148 and the word lines 108 correspond one by one; the bit line extension direction Y and the word line extension direction X form a reference plane, and the word lines 108 whose orthographic projections on the reference plane are within the orthographic projection of the word line connection section 118 on the reference plane are the first word lines 128, and the remaining word lines are the second word lines 138, the first wirings 148 corresponding to the first word lines 128 are the first sub-wirings 168, and the first wirings 148 corresponding to the second word lines 138 are the second sub-wirings 178.

[0097] Among them, Figure 14 FIG. 6 is a top view structural schematic diagram of a plurality of word lines in the memory array provided by the embodiments of the present disclosure; Figure 15 FIG. 7 is a top view structural schematic diagram of the first wiring layer in the first chip provided by the embodiments of the present disclosure; Figure 16a FIG. 8 is a partial top view structural schematic diagram of the first sub-wiring and the first bonding post in the first chip provided by the embodiments of the present disclosure; Figure 16b FIG. 9 is a partial top view structural schematic diagram of the second sub-wiring and the first bonding post corresponding to the word line opposite to the peripheral region and the first chip provided by the embodiments of the present disclosure; Figure 16c FIG. 10 is a partial top view structural schematic diagram of the second sub-wiring and the first bonding post corresponding to the word line opposite to the first bit line connection section and the first chip provided by the embodiments of the present disclosure. It should be noted that Figure 14 different forms of lines are used in FIGS. 6 to 10 to represent the first word line 128 and the second word line 138.

[0098] Among them, with reference to Figure 16a FIG. 7, the first sub-wiring 168 extends along the word line extension direction X; with reference to Figure 16b FIG. 8 Figure 16b and Figure 16a FIG. 9 Figure 16b and Figure 16b FIG. 10, the second sub-wiring 178 includes a first connection portion 188 and a second connection portion 198 connected in contact, the first connection portion 188 extends along the word line extension direction X, and the second connection portion 198 extends along the bit line extension direction Y; with reference to Figure 14 FIG. 6 Figure 14 and

[0099] It can be understood that, along the vertical direction Z, the first wiring layer 158 may be located between the second wiring layer 147 and the bit line 107, or the first wiring layer 158 may be located on the side of the second wiring layer 147 close to the second chip 102.

[0100] In some embodiments, with continued reference to FIG. 16, the lengths of adjacent first sub-wirings 168 in the word line extending direction X are different along the bit line extending direction Y, the lengths of adjacent first connection portions 188 in the word line extending direction X are different along the bit line extending direction Y, and the lengths of adjacent second connection portions 198 in the word line extending direction X are different along the bit line extending direction Y.

[0101] In some embodiments, with continued reference to FIG. 16, the first chip 101 may further include: a plurality of first bonding posts 119 arranged in an array along the bit line extending direction Y and the word line extending direction X, at least some of the first bonding posts 119 located in the word line connection section 118 are electrically connected to one end of the first wiring 148, and the other end of the first wiring 148 is electrically connected to the word line 108.

[0102] It can be understood that the plurality of first bonding posts 119 are in the same film layer, and this film layer is not only located on the side of the second wiring layer 147 close to the second chip 102 (reference Figure 1 ), but also located on the side of the first wiring layer 158 close to the second chip 102 (reference Figure 1 ). In addition, the film layer where the plurality of first bonding posts 119 are located has a plurality of first bonding posts 119 in the area facing the first bit line connection section 117, the second bit line connection section 127, or the word line connection section 118.

[0103] In some embodiments, with combined reference to Figure 14 and Figure 15 , the first wiring layer 158 corresponding to a storage array 100 (reference Figure 1 ) is divided into a plurality of regions. Among them, with combined reference to Figure 12 and Figure 15, the peripheral region 109 is located between two word line connection sections 118. Along the word line extension direction X, first, the first wiring layer 158 facing the first bit line connection section 117 is sequentially divided into a D1 part and a D2 part, and the first wiring layer 158 facing the second bit line connection section 127 is sequentially divided into a D3 part and a D4 part; second, the first wiring layer 158 facing one of the two word line connection sections 118 is sequentially divided into an A1 part, a B1 part, a C1 part, a C2 part, a B2 part, and an A2 part, and the first wiring layer 158 facing the other of the two word line connection sections 118 is sequentially divided into an A3 part, a B3 part, a C3 part, a C4 part, a B4 part, and an A4 part; third, the first wiring layer 158 facing the peripheral region 109 is sequentially divided into an E1 part and an E2 part.

[0104] Reference Figure 16a , the lengths of adjacent first sub-wirings 168 in the word line extension direction X are different along the bit line extension direction Y.

[0105] It should be noted that Figure 16a only shows Figure 15 the first sub-wiring 168 and the first bonding post 119 in the local area located in the A1 part in Figure 16a , and the length layout of multiple first sub-wirings 168 in the word line extension direction X in Figure 16a is only an example. In actual applications, there can be various different situations for the length layout of multiple first sub-wirings 168 in the A1 part in the word line extension direction X, and only the lengths of adjacent first sub-wirings 168 in the word line extension direction X need to be different, which will not be enumerated one by one here. Moreover, to reflect the positional relationship between the first sub-wiring 168 and the first bonding post 119,

[0106] In addition, taking the plane formed by the bit line extension direction Y and the word line extension direction X as the projection plane, Figure 16a the orthographic projections of some first sub-wirings 168 on this projection plane will pass through the orthographic projections of multiple first bonding posts 119 on this projection plane. However, the first sub-wiring 168 will only be electrically connected to the first bonding post 119 whose end orthographic projection overlaps with it, and one first bonding post 119 will only be electrically connected to one first sub-wiring 168. Based on this, the purpose of the different lengths of adjacent first sub-wirings 168 in the word line extension direction X is to enable adjacent first sub-wirings 168 to be electrically connected to different first bonding posts 119.

[0107] In some cases, the arrangement of multiple first sub-wirings 168 in the A1 part and the A2 part may be axially symmetric along the bit line extension direction Y; and / or, the arrangement of multiple first sub-wirings 168 in the A1 part and the A3 part may be axially symmetric along the word line extension direction X; and / or, the arrangement of multiple first sub-wirings 168 in the A2 part and the A4 part may be axially symmetric along the word line extension direction X. Thus, it is beneficial to improve the regularity of the wirings in the word line connection section 118 to reduce the wiring difficulty.

[0108] Reference Figure 16b , the lengths of adjacent first connection parts 188 in the word line extension direction X along the bit line extension direction Y are different, and the lengths of adjacent second connection parts 198 in the bit line extension direction Y along the word line extension direction X are different.

[0109] It should be noted that Figure 16b only shows Figure 15 the second sub-wirings 178 and the first bonding posts 119 in the local areas of the E1 part, the B1 part, and the B3 part in Figure 16b , and the length layout of two parts of multiple second sub-wirings 178 in the word line extension direction X or the bit line extension direction Y in Figure 16b is only an example. In actual applications, there can be various different situations for the length layout of two parts of multiple second sub-wirings 178 in the E1 part in the word line extension direction X or the bit line extension direction Y. It only needs to satisfy that "the lengths of adjacent first connection parts 188 in the word line extension direction X along the bit line extension direction Y are different, and the lengths of adjacent second connection parts 198 in the bit line extension direction Y along the word line extension direction X are different", and they will not be enumerated one by one here. Moreover, to show the positional relationship between the second sub-wirings 178 and the first bonding posts 119,

[0110] In addition, taking the plane formed by the bit line extension direction Y and the word line extension direction X as the projection plane, Figure 16b the orthographic projection of some second sub-wirings 178 in

[0111] on this projection plane will pass through the orthographic projections of multiple first bonding posts 119 on this projection plane. However, the second sub-wirings 178 will only be electrically connected to the first bonding posts 119 whose orthographic projections of the ends overlap with theirs. One first bonding post 119 will only be electrically connected to one second sub-wiring 178. Based on this, the purpose of the lengths of two parts of adjacent second sub-wirings 178 being different in both the word line extension direction X and the bit line extension direction Y is to enable adjacent second sub-wirings 178 to be electrically connected to different first bonding posts 119.In some cases, the multiple second sub-wirings 178 in the E1 part are divided into two groups, where one group of second sub-wirings 178 are all electrically connected to the first bonding post 119 facing the B1 part, and the other group of second sub-wirings 178 are all electrically connected to the first bonding post 119 facing the B3 part.

[0112] In some cases, the arrangement of the multiple second sub-wirings 178 in the E1 part and the E2 part can be axially symmetric along the bit line extension direction Y, and the multiple second sub-wirings 178 in the E2 part are divided into two groups, where one group of second sub-wirings 178 are all electrically connected to the first bonding post 119 facing the B2 part, and the other group of second sub-wirings 178 are all electrically connected to the first bonding post 119 facing the B4 part. In this way, it is beneficial to improve the regularity of the wirings in the word line connection section 118 to reduce the wiring difficulty.

[0113] Reference Figure 16c , the lengths of adjacent first connection parts 188 in the word line extension direction X are different along the bit line extension direction Y, and the lengths of adjacent second connection parts 198 in the bit line extension direction Y are different along the word line extension direction X.

[0114] It should be noted that Figure 16c only shows Figure 15 the second sub-wirings 178 and the first bonding posts 119 in the local areas of the D1 part and the C1 part in Figure 16c , and the length layout of the two parts of the multiple second sub-wirings 178 in the word line extension direction X or the bit line extension direction Y in Figure 16c is only an example. In actual applications, there can be many different situations for the length layout of the two parts of the multiple second sub-wirings 178 in the D1 part in the word line extension direction X or the bit line extension direction Y, and only need to satisfy that "the lengths of adjacent first connection parts 188 in the word line extension direction X are different along the bit line extension direction Y, and the lengths of adjacent second connection parts 198 in the bit line extension direction Y are different along the word line extension direction X", and will not be enumerated one by one here. Moreover, to reflect the positional relationship between the second sub-wirings 178 and the first bonding posts 119, Figure 16c the rectangle indicating the approximate position of the first bonding post 119 is drawn in a perspective manner.

[0115] In addition, taking the plane formed by the bit line extension direction Y and the word line extension direction X as the projection plane, Figure 16cThe orthographic projection of a part of the second sub-wiring 178 on this projection plane will penetrate through the orthographic projections of multiple first bonding posts 119 on this projection plane. However, the second sub-wiring 178 will only make electrical connections with the first bonding posts 119 whose orthographic projections at their ends overlap. One first bonding post 119 will only make an electrical connection with one second sub-wiring 178. Based on this, the purpose that the lengths of two parts in the adjacent second sub-wirings 178 are different in the word line extending direction X and the bit line extending direction Y is to enable the adjacent second sub-wirings 178 to make electrical connections with different first bonding posts 119.

[0116] In some cases, the arrangement of multiple second sub-wirings 178 located in the D1 part and the D2 part can be axisymmetric along the bit line extending direction Y; and / or, the arrangement of multiple second sub-wirings 178 located in the D1 part and the D3 part can be axisymmetric along the word line extending direction X; and / or, the arrangement of multiple second sub-wirings 178 located in the D2 part and the D4 part can be axisymmetric along the word line extending direction X. In this way, it is beneficial to improve the regularity of the wirings in the word line connection section 118 to reduce the wiring difficulty.

[0117] It can be understood that the first wirings 148 and the word lines 108 are in one-to-one correspondence, that is, each word line 108 is equipped with a corresponding first wiring 148, and this word line 108 makes an electrical connection with the first bonding post 119 through the corresponding first wiring 148.

[0118] In some cases, with reference to Figure 14 and FIG. 16, there are connection posts (not shown in the figure) between the first wiring 148 and the word line 108 to achieve the electrical connection between the first wiring 148 and the word line 108. In addition, one end of the first wiring 148 that is not electrically connected to the word line 108 can be in contact connection with the first bonding post 119.

[0119] It should be noted that Figure 4 、 Figure 5 、 Figure 7 or Figure 9 In the examples shown, the word lines, the first wiring layer having multiple first wirings, and the first bonding posts may also have the above characteristics, which will not be elaborated here.

[0120] In some embodiments, with reference to Figure 17 , the second chip 102 may further include: multiple second bonding posts 129 arranged in an array along the bit line extending direction Y and the word line extending direction X, and the first bonding posts 119 and the second bonding posts 129 are in contact connection one by one to achieve the bonding of the first chip 101 and the second chip 102.

[0121] Among them, Figure 17A schematic cross-sectional structure diagram of the first chip and the second chip provided by the embodiments of the present disclosure.

[0122] It can be understood that multiple second bonding posts 129 are in the same film layer, and this film layer is located on the side of the logic block 103 close to the first chip 101 (refer to Figure 1 ). In addition, the film layer where the multiple second bonding posts 129 are located has multiple second bonding posts 129 in the regions facing the word line driving block 104, the peripheral circuit block 105, the first sense amplifier block 116, or the second sense amplifier block 126. Moreover, each bit line 107 is equipped with a corresponding second wiring 137, and this bit line 107 is electrically connected to the first bonding post 119 through the corresponding second wiring 137. Moreover, each word line 108 is equipped with a corresponding first wiring 148, and this word line 108 is electrically connected to the first bonding post 119 through the corresponding first wiring 148. Based on this, the bit line 107 in the first chip 101 can be electrically connected to the first sense amplifier block 116 or the second sense amplifier block 126 by means of the second wiring 137, the first bonding post 119, and the second bonding post 129, and the word line 108 in the first chip 101 can be electrically connected to the word line driving block 104 by means of the first wiring 148, the first bonding post 119, and the second bonding post 129.

[0123] It should be noted that for the convenience of description and to clearly show the characteristics of the semiconductor structure, the Figures 1 to 1 6 in the embodiments of the present disclosure are all partial structure schematic diagrams of the semiconductor structure.

[0124] In summary, the memory array 100 in the first chip 101 faces the logic block 103 in the second chip 102, that is, the memory array 100 and the logic block 103 are stacked along the vertical direction Z, which is beneficial to reducing the layout area of a single chip in the horizontal direction H. In some cases, refer to Figure 1 and Figure 2 , each logic block 103 includes at least a pair of word line driving blocks 104, and each part of the peripheral circuit block 105 is located between adjacent word line driving blocks 104. In other words, for the peripheral circuit block 105, all word line driving blocks 104 are located in the relatively edge regions, which is beneficial to ensuring that the peripheral circuit block 105 is concentratedly arranged in the middle region, and the peripheral circuit block 105 is an integral whole that will not be separated by the word line driving blocks 104, so that the layout of the peripheral circuit block 105 in a single logic block 103 is more concentrated; in other cases, refer to Figure 3 and Figure 4, the orthographic projection on the first chip 201 is the word line driving section 204 in the shape of an H. Then, the word line driving section 204 divides the peripheral circuit section 205 into two parts. For either of the two parts, the word line driving section 204 is also located in the area at the relative edge, which is conducive to making the layout of either of the two parts more concentrated. Moreover, the peripheral circuit section 205 of one logic section 203 can be connected to the peripheral circuit section 205 of another logic section 203, which is conducive to improving the concentration among the peripheral circuit sections 205 of multiple logic sections 203. Therefore, the various layouts of the word line driving sections 104 and 204 and the peripheral circuit sections 105 and 205 provided by the embodiments of the present disclosure are all conducive to improving the concentration of the layout of the peripheral circuit sections 105 and 205.

[0125] Those of ordinary skill in the art can understand that the above-described embodiments are specific examples for implementing the present disclosure. In practical applications, various changes can be made to them in form and details without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the protection scope of the embodiments of the present disclosure should be determined by the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A first chip and a second chip bonded to each other; The first chip includes a plurality of memory arrays arranged in an array; The second chip includes a plurality of logic blocks corresponding to the memory arrays. Each logic block includes at least a pair of word line driving blocks and a peripheral circuit block. The pair of word line driving blocks includes two word line driving blocks arranged at intervals, and each part of the peripheral circuit block is located between the adjacent word line driving blocks; Alternatively, each logic block includes: a word line driving block whose orthographic projection on the first chip is in the shape of an "H". The word line driving block encloses two recessed areas arranged at intervals along the word line extending direction, and the peripheral circuit blocks are respectively located in the two recessed areas.

2. The semiconductor structure according to claim 1, wherein The logic block includes two pairs of the word line driving blocks arranged at intervals along the word line extending direction X. The orthographic projection of the peripheral circuit block in each logic block on the first chip is in the shape of a cross.

3. The semiconductor structure according to claim 1, wherein In the word line extending direction X, the size of the word line driving block is equal to the size of the logic block. In the bit line extending direction, the peripheral circuit block is arranged between the adjacent word line driving blocks. The word line extending direction X intersects with the bit line extending direction Y.

4. The semiconductor structure according to claim 3, wherein In the bit line extending direction Y, each word line driving block has a convex portion facing the peripheral circuit block, and the peripheral circuit block has a concave portion corresponding to the convex portion.

5. The semiconductor structure according to claim 4, characterized in that, In the bit line extending direction Y, the minimum value of the width of the peripheral circuit block is greater than the maximum value of the width of the word line driving block.

6. The semiconductor structure according to claim 4, characterized in that, The two convex portions in the pair of word line driving blocks face each other in the bit line extending direction Y, and the convex portion is centrally arranged in the word line driving block.

7. The semiconductor structure according to any one of claims 3 to 6, characterized in that The peripheral circuit blocks in two adjacent logic blocks along the word line extending direction X are adjacent to each other.

8. The semiconductor structure according to claim 1, wherein The logic block includes a pair of word line driving blocks arranged at intervals along the word line extending direction X. In the word line extending direction X, the peripheral circuit block is arranged between the adjacent word line driving blocks.

9. The semiconductor structure according to claim 1 or 8, characterized in that, Each logic block further includes: a first sense amplifier block and a second sense amplifier block arranged opposite to each other and at intervals along the bit line extending direction. The word line driving block and the peripheral circuit block are both located between the first sense amplifier block and the second sense amplifier block. The word line extending direction X intersects with the bit line extending direction Y.

10. The semiconductor structure according to claim 9, wherein, The first sense amplifier block of one of two adjacent logic blocks along the bit line extending direction Y is adjacent to the second sense amplifier block of the other. The adjacent first sense amplifier block and the second sense amplifier block form a sense amplifier block; The memory array includes a plurality of bit lines arranged at intervals along the word line extending direction X. The bit line is electrically connected to one of the two sense amplifier blocks corresponding to the memory array.

11. The semiconductor structure according to claim 9, wherein The first chip further includes: a first bit line connection block opposite to the first sense amplifier block, a second bit line connection block opposite to the second sense amplifier block, and a word line connection block opposite to the word line driving block; Among them, the first sense amplification section and the first bit line connection section are bonded to each other, the second sense amplification section and the second bit line connection section are bonded to each other, and the word line driving section and the word line connection section are bonded to each other.

12. The semiconductor structure according to claim 11, wherein, The first chip further includes: a plurality of word lines arranged at intervals along the bit line extension direction Y, and a first wiring layer having a plurality of first wirings, and the first wirings and the word lines correspond to each other one by one; The bit line extension direction Y and the word line extension direction X form a reference plane. Among the word lines, the word lines whose orthographic projections on the reference plane overlap with the orthographic projection of the word line connection section on the reference plane are first word lines, and the remaining word lines are second word lines. The first wirings corresponding to the first word lines are first sub-wirings, and the first wirings corresponding to the second word lines are second sub-wirings; Among them, the first sub-wiring extends along the word line extension direction X; the second sub-wiring includes a first connection portion and a second connection portion connected in contact. The first connection portion extends along the word line extension direction X, and the second connection portion extends along the bit line extension direction Y; one end of any one of the first wirings is electrically connected to the word line, and the other end is located in the orthographic projection of the word line connection section on the reference plane in the orthographic projection on the reference plane.

13. The semiconductor structure according to claim 12, wherein The first chip further includes: a plurality of first bonding posts arranged in an array along the bit line extension direction Y and the word line extension direction X. At least part of the first bonding posts located in the word line connection section are electrically connected to one end of the first wiring, and the other end of the first wiring is electrically connected to the word line.

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