Temperature compensation method and device for double-rate synchronous dynamic random access memory

Abstract

The invention provides a temperature compensation method and device for a double-rate synchronous dynamic random access memory. The method comprises the following steps: sending a first parameter and a second parameter to a coprocessor; the first parameter is used for indicating the coprocessor to perform temperature compensation, and the second parameter is used for indicating a time interval of temperature compensation detection; writing the first variable and the second variable into a register of the coprocessor; the first variable is used for instructing the coprocessor to disconnect the connection of the main processor to the DDR, and the second variable is used for instructing the coprocessor to retrain at least one subsystem and perform temperature compensation on the DDR in the retraining process. According to the invention, the flexibility of temperature compensation can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of memories, and particularly to a temperature compensation method and apparatus for a double data rate synchronous dynamic random access memory. Background Art

[0002] Double data rate synchronous dynamic random access memory (DDR) and low power double data rate synchronous dynamic random access memory (LPDDR) memory technologies are widely used in computers, servers, and various electronic devices. Their high-speed data transmission and synchronous clock technologies make them one of the key technologies in the modern electronics industry.

[0003] Especially for LPDDR, its performance changes under different temperature conditions, so temperature compensation technology is needed to adjust and optimize to ensure the stability and accuracy of data transmission. Summary of the Invention

[0004] The present disclosure provides a temperature compensation method and apparatus for a double data rate synchronous dynamic random access memory, which can improve the flexibility of temperature compensation.

[0005] The technical solution of the present disclosure is implemented as follows:

[0006] The present disclosure provides a temperature compensation method for a double data rate synchronous dynamic random access memory (DDR), which is executed by a main processor. The method includes: sending a first parameter and a second parameter to a coprocessor; the first parameter is used to instruct the coprocessor to perform temperature compensation, and the second parameter is used to instruct the time interval for performing temperature compensation detection; writing a first variable and a second variable into the registers of the coprocessor; the first variable is used to instruct the coprocessor to disconnect the connection of the main processor to the DDR, and the second variable is used to instruct the coprocessor to retrain at least one subsystem and perform temperature compensation on the DDR during the retraining process.

[0007] In some possible implementation manners, before sending the first parameter and the second parameter to the coprocessor, the above method further includes: setting a first register parameter of the main processor; the first register parameter is used to instruct the counting rule of the data strobe signal (DQS) timer of the DDR; setting the handshake information between the main processor and the coprocessor to zero; the zeroed handshake information is used to indicate that the DDR has completed the previous temperature compensation request.

[0008] In some possible embodiments, before writing the first variable and the second variable to the coprocessor, the above method further includes: reading the second register parameter and the third register parameter of the main processor; the second register parameter is used to represent the most significant bit of the DQS oscillator counter, and the third register parameter is used to represent the least significant bit of the DQS oscillator counter; determining a first delay time of the DQS oscillator counter based on the most significant bit, the least significant bit, and a preset first mapping relationship; the first mapping relationship is the mapping relationship between the most significant bit, the least significant bit, and the first delay time; the first delay time is the time length that the DQS timer takes from start to stop recorded by the DQS oscillator counter within a first time period; in the case where a first difference between the first delay time and a second delay time of the DQS oscillator counter is greater than a preset threshold, determining that the DDR needs temperature compensation and the direction of temperature compensation; the second delay time is the time length that the DQS timer takes from start to stop recorded by the DQS oscillator counter within a second time period; the second time period occurs before the first time period.

[0009] In some possible embodiments, after determining that the DDR needs temperature compensation and the direction of temperature compensation, the method further includes: determining a target delay time of the DQS oscillator counter after removing the influence of temperature drift based on the first difference between the first delay time and the second delay time and a preset second mapping relationship; the second mapping relationship is the mapping relationship between the first difference and the target delay time; writing the target delay time to the register of the coprocessor.

[0010] In some possible embodiments, before writing the first variable and the second variable to the coprocessor, the above method further includes: reading the minimum value and the maximum value of the receive enable signal of at least one subsystem; determining a starting point and an ending point of retraining based on the minimum value and the maximum value of the receive enable signal; writing the starting point and the ending point of retraining to the register of the coprocessor.

[0011] In some possible embodiments, before writing the first variable and the second variable to the coprocessor, the above method further includes: reading a first initial variable of a first register in the main processor; modifying the first initial variable to obtain the first variable; reading a second initial variable of a second register in the main processor; modifying the second initial variable to obtain the second variable.

[0012] In some possible embodiments, after modifying the second initial variable to obtain the second variable, the above method further includes: modifying the handshake information between the main processor and the coprocessor based on the second variable; the modified handshake information is used to indicate a target subsystem for retraining in at least one subsystem; sending the modified handshake information to the coprocessor.

[0013] The present disclosure provides a temperature compensation method for a double data rate synchronous dynamic random access memory, which is executed by a coprocessor. The method includes: receiving a first parameter and a second parameter sent by a main processor; the first parameter is used to instruct the coprocessor to perform temperature compensation, and the second parameter is used to indicate the time interval of temperature compensation; reading a first variable and a second variable written by the main processor from a register; the first variable is used to instruct the coprocessor to disconnect the access to the DDR, and the second variable is used to instruct the coprocessor to retrain at least one subsystem, and perform temperature compensation on the DDR during the retraining process; disconnecting the connection between the main processor and the DDR based on the first variable; performing temperature compensation on the DDR based on the first parameter, the second parameter, and the second variable.

[0014] In some possible implementation manners, performing temperature compensation on the DDR based on the first parameter, the second parameter, and the second variable includes: receiving modified handshake information sent by the main processor; the modified handshake information is used to indicate a target subsystem for retraining in at least one subsystem; reading a target delay time, a starting point, and an ending point of temperature compensation written by the main processor; retraining the target subsystem based on the modified handshake information, and during the retraining process, performing temperature compensation on the DDR based on the target delay time, the starting point and the ending point of retraining, the first parameter, the second parameter, and the second variable.

[0015] The present disclosure provides a temperature compensation device for a double data rate synchronous dynamic random access memory, which is applied to a main processor. The above-mentioned device includes: a data sending module, configured to send a first parameter and a second parameter to a coprocessor; the first parameter is used to instruct the coprocessor to perform temperature compensation, and the second parameter is used to indicate the time interval for temperature compensation detection; a data writing module, configured to write a first variable and a second variable into a register of the coprocessor; the first variable is used to instruct the coprocessor to disconnect the connection of the main processor to the DDR, and the second variable is used to instruct the coprocessor to retrain at least one subsystem, and perform temperature compensation on the DDR during the retraining process.

[0016] In some possible implementation manners, the above-mentioned device further includes: a data processing module, configured to set a first register parameter of the main processor; the first register parameter is used to instruct the counting rule of a data strobe signal (DQS) timer of the DDR; setting the handshake information between the main processor and the coprocessor to zero; the handshake information after being set to zero is used to indicate that the DDR has completed the previous temperature compensation request.

[0017] In some possible embodiments, the data processing module is further configured to read the second register parameter and the third register parameter of the main processor; the second register parameter is used to represent the most significant bit of the DQS oscillator counter, and the third register parameter is used to represent the least significant bit of the DQS oscillator counter; based on the most significant bit, the least significant bit, and a preset first mapping relationship, determine the first delay time of the DQS oscillator counter; the first mapping relationship is the mapping relationship between the most significant bit, the least significant bit, and the first delay time; the first delay time is the time length of the DQS timer from start to stop recorded by the DQS oscillator counter within a first time period; in the case where the first difference between the first delay time and the second delay time of the DQS oscillator counter is greater than a preset threshold, determine that the DDR needs temperature compensation and the direction of temperature compensation; the second delay time is the time length of the DQS timer from start to stop recorded by the DQS oscillator counter within a second time period; the second time period occurs before the first time period.

[0018] In some possible embodiments, the data processing module is further configured to determine the target delay time of the DQS oscillator counter after removing the influence of temperature drift based on the first difference between the first delay time and the second delay time and a preset second mapping relationship; the second mapping relationship is the mapping relationship between the first difference and the target delay time; write the target delay time into the register of the coprocessor.

[0019] In some possible embodiments, the data processing module is further configured to read the minimum value and the maximum value of the receive enable signals of at least one subsystem; based on the minimum value and the maximum value of the receive enable signals, determine the start point and the end point of retraining; write the start point and the end point of retraining into the register of the coprocessor.

[0020] In some possible embodiments, the data processing module is further configured to read the first initial variable of the first register in the main processor; modify the first initial variable to obtain the first variable; read the second initial variable of the second register in the main processor; modify the second initial variable to obtain the second variable.

[0021] In some possible embodiments, the data processing module is further configured to modify the handshake information between the main processor and the coprocessor based on the second variable; the modified handshake information is used to indicate the target subsystem for retraining in at least one subsystem; send the modified handshake information to the coprocessor.

[0022] The present disclosure provides a temperature compensation device for a double data rate synchronous dynamic random access memory, which is applied to a coprocessor. The device includes: a data receiving module, configured to receive a first parameter and a second parameter sent by a main processor; the first parameter is used to instruct the coprocessor to perform temperature compensation, and the second parameter is used to indicate the time interval of temperature compensation; a data reading module, configured to read a first variable and a second variable written by the main processor from a register; the first variable is used to instruct the coprocessor to disconnect the access to the DDR, and the second variable is used to instruct the coprocessor to perform retraining on at least one subsystem and perform temperature compensation on the DDR during the retraining process; a connection interruption module, configured to disconnect the connection between the main processor and the DDR based on the first variable; a temperature compensation module, configured to perform temperature compensation on the DDR based on the first parameter, the second parameter, and the second variable.

[0023] In some possible implementation manners, the temperature compensation module is configured to receive modified handshake information sent by the main processor; the modified handshake information is used to indicate a target subsystem for retraining in at least one subsystem; read a target delay time, a starting point and an ending point of temperature compensation written by the main processor; perform retraining on the target subsystem based on the modified handshake information, and perform temperature compensation on the DDR based on the target delay time, the starting point and the ending point of retraining, the first parameter, the second parameter, and the second variable during the retraining process.

[0024] The present disclosure provides an electronic device, including: a memory, configured to store executable instructions; a processor, configured to implement the method provided by the present disclosure when executing the executable instructions stored in the memory.

[0025] The present disclosure provides a computer storage medium, storing executable instructions, which are configured to implement the method provided by the present disclosure when the executable instructions are executed by a processor.

[0026] The present disclosure provides a computer program product, including a computer program or instructions, which are configured to implement the method provided by the present disclosure when the computer program or instructions are executed by a processor.

[0027] In the present disclosure, the main processor sends a first parameter and a second parameter for instructing temperature compensation and the time interval of temperature compensation detection to the coprocessor, and writes the first parameter for instructing the coprocessor to disconnect the main processor from accessing the DDR and the second variable for instructing the coprocessor to perform retraining on at least one subsystem into the register of the coprocessor, which can enable the DDR to perform temperature compensation in any state, without restricting the DDR to be in an idle, self-refresh, or refresh state, thereby improving the flexibility of temperature compensation.

[0028] Further, the temperature compensation method described in the embodiments of the present disclosure is implemented in cooperation with the main processor and the coprocessor, without using proprietary hardware resources. Thus, the chip area can be reduced, and the cost can be further reduced. And the time when the main processor disconnects the DDR connection can be shortened as much as possible, further improving the flexibility and portability of the temperature compensation scheme.

[0029] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure and, together with the specification, are used to explain the principles of the present disclosure.

[0031] Figure 1 Schematic flowchart of the first embodiment of the temperature compensation method for a double data rate synchronous dynamic random access memory in the embodiments of the present disclosure;

[0032] Figure 2 Schematic flowchart of the second embodiment of the temperature compensation method for a double data rate synchronous dynamic random access memory in the embodiments of the present disclosure;

[0033] Figure 3 Schematic flowchart of the third embodiment of the temperature compensation method for a double data rate synchronous dynamic random access memory in the embodiments of the present disclosure;

[0034] Figure 4 Schematic flowchart of the fourth embodiment of the temperature compensation method for a double data rate synchronous dynamic random access memory in the embodiments of the present disclosure;

[0035] Figure 5 Schematic flowchart of the fifth embodiment of the temperature compensation method for a double data rate synchronous dynamic random access memory in the embodiments of the present disclosure;

[0036] Figure 6 Schematic flowchart of the sixth embodiment of the temperature compensation method for a double data rate synchronous dynamic random access memory in the embodiments of the present disclosure;

[0037] Figure 7 Schematic flowchart of the seventh embodiment of the temperature compensation method for a double data rate synchronous dynamic random access memory in the embodiments of the present disclosure;

[0038] Figure 8 Schematic diagram of the first structure of the temperature compensation device for a double data rate synchronous dynamic random access memory in the embodiments of the present disclosure;

[0039] Figure 9 Schematic diagram of the second structure of the temperature compensation device for a double data rate synchronous dynamic random access memory in the embodiments of the present disclosure. Detailed implementation manners

[0040] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present disclosure. Instead, they are merely examples of devices consistent with some aspects of the present disclosure as detailed in the appended claims.

[0041] To illustrate the technical solutions described in the present disclosure, the following will be described through specific embodiments.

[0042] Regarding the temperature drift phenomenon during the read and write processes of low power double data rate synchronous dynamic random access memory (LPDDR), there are currently two mainstream temperature compensation methods: 1. Through the phyretrain method, perform RxCLK, RxEN, and TxDqWr retrain; 2. Through the MRR Snoop Control method, read the drift caused by the change of the internal oscillator of the dram with temperature and voltage, and perform compensation for TxDqs and RxDqs.

[0043] However, there are several limitations in using the above two methods for RxCLK, RxEN, and TxDqWr retrain and MRR Snoop Control: (1) Retrain can only be performed when the DRAM is in the idle, self-refresh (without power-down), and refresh conditions; (2) Retrain can only be supported when the data rate ≥ 1600 Mbps; (3) Whether performing RxCLK, RxEN, and TxDqWr retrain through the retrain method or performing temperature compensation through MRR Snoop Control, specific circuits and other hardware need to be placed in the phy for support, but using specific hardware support will occupy a relatively large area.

[0044] The above reasons result in relatively low flexibility in temperature compensation for double data rate synchronous dynamic random access memory.

[0045] To solve the above problems, the embodiments of the present disclosure provide a temperature compensation method and device for double data rate synchronous dynamic random access memory to improve the flexibility of temperature compensation.

[0046] It should be noted that for the convenience of description, the temperature compensation method for the double data rate synchronous dynamic random access memory (doubledatarate SDRAM, DDR) will be simply referred to as the temperature compensation method hereinafter.

[0047] In the embodiments of the present application, both DDR and LPDDR belong to dynamic random access memories. Hereinafter, the above temperature compensation method will be described by taking LPDDR as an example.

[0048] Figure 1 FIG. is a schematic flowchart of the first embodiment of the temperature compensation method for the double data rate synchronous dynamic random access memory in the embodiments of the present disclosure. This method is executed by the main processor. Refer to Figure 1 As shown, the method may include:

[0049] S101, sending a first parameter and a second parameter to the coprocessor. Among them, the first parameter is used to instruct the coprocessor to perform temperature compensation, and the second parameter is used to indicate the time interval for performing temperature compensation detection.

[0050] It can be understood that the main processor sends the first parameter to the coprocessor to determine whether the coprocessor needs to perform retraining, and performs temperature compensation during the retraining process. The second parameter sent by the main processor to the coprocessor determines the time interval for the coprocessor to perform temperature compensation, that is, how often to perform temperature compensation detection.

[0051] In an example, the main processor sends the first parameter to the coprocessor. The first parameter is set to "yes", and the first parameter characterizes that the DDR memory system will perform temperature compensation regularly regardless of temperature changes. Then, the main processor sends the second parameter to the coprocessor. The second parameter is set to "6 seconds (s)", and the second parameter characterizes that the DDR memory system will perform temperature compensation detection every 6 s. If the temperature change reaches the temperature compensation threshold, temperature compensation will be performed; if the temperature change does not reach the temperature compensation threshold, temperature compensation will not be performed.

[0052] In some embodiments, the double data rate synchronous dynamic random access memory described in the embodiments of the present disclosure corresponds to one main processor, one coprocessor, and at least one subsystem. The main processor is the core component of the computer, responsible for executing program instructions and processing data; the coprocessor is an auxiliary processor used to share specific tasks of the main processor to improve overall performance; the subsystem refers to the memory subsystem, which includes a DDR memory controller, a DDR PHY (physical layer), a DDR channel, and a DDR memory.

[0053] In the embodiments of the present disclosure, a case where the DDR corresponds to two subsystems is taken as an example for illustration. It should be noted that the DDR involved in the embodiments of the present disclosure is not limited to two subsystems, and two subsystems are only one of the examples.

[0054] In some embodiments, in a DDR memory system, the main processor communicates with the DDR through a memory controller, sends read / write requests, and processes data from the memory; the main processor sends specific data processing instructions to the coprocessor, and the coprocessor executes these instructions and returns the results; the subsystem is responsible for managing the transfer of data between the host system and the DDR memory device to ensure the efficiency and reliability of data transfer.

[0055] In some possible implementation manners, before the above S101, the above temperature compensation method may further include: setting the first register parameter of the main processor; the first register parameter is used to indicate the counting rule of the data strobe signal (DQS) timer of the DDR; setting the handshake information between the main processor and the coprocessor to zero; the handshake information after being set to zero is used to indicate that the DDR has completed the previous temperature compensation request.

[0056] It can be understood that by setting the parameter of one of the mode registers in the main processor (i.e., the first register parameter), the counting rule of the DQS timer can be controlled. Then, by setting the handshake information of the handshake register between the main processor and the coprocessor to zero, a new round of temperature compensation can be started.

[0057] In some embodiments, the handshake register is located in the main processor and is used to handle the communication between the main processor and the coprocessor to transmit the handshake signal of the temperature compensation request.

[0058] In an example, control the main processor to set the 23rd mode register (mode register 23, MR23) in the DDR = 0x40, and MR23 = 0x40 means that the DQS timer inside the DDR will stop counting after counting 2048 DQS clock signals (CLK).

[0059] In one example, taking two x32 subsystems as an example, each subsystem corresponds to two ranks of different storage units, and the two subsystems altogether include four ranks. The handshake register between the main processor and the coprocessor is denoted as AP2RTC_shakehand[3:0], and a zeroing operation is performed on AP2RTC_shakehand[3:0], that is, AP2RTC_shakehand[3:0] = 0b0000; wherein, 4 bits respectively represent the handshake information of the four ranks, bit[0] represents the temperature compensation request of subsys0rank0, bit[1] represents the temperature compensation request of subsys0 rank1, bit[2] represents the temperature compensation request of subsys1rank0, bit[3] represents the temperature compensation request of subsys1 rank1; setting a bit to 1 indicates that temperature compensation is required, and it will be cleared to 0 after the temperature compensation is completed, that is, the zeroing operation.

[0060] In some embodiments, before zeroing the handshake information of the handshake register between the main processor and the coprocessor, the above temperature compensation method may further include: the main processor controls the update request signal to ensure that the updated delay line can be successfully updated in the physical layer (PHY).

[0061] In one example, enable dfi-ctrlupd, and the function of the dfi-ctrlupd signal is to control the update request signal to ensure that the updated delay line can be successfully updated in the PHY.

[0062] In one example, taking two x32 subsystems as an example for illustration, Figure 2 This is a schematic flowchart of the second embodiment of the temperature compensation method for a double data rate synchronous dynamic random access memory in the embodiments of the present disclosure. Refer to Figure 2 As shown, the above temperature compensation method may include:

[0063] S201, the main processor sets MR23 = 0x40.

[0064] S202, the main processor enables the dfi-ctrlupd signal.

[0065] S203, the main processor zeros the handshake information between the main processor and the coprocessor.

[0066] S204, the main processor sends a first parameter to determine whether to keep performing retrain.

[0067] S205, the main processor sends a second parameter to determine the time interval t for detecting temperature compensation interval .

[0068] S206, The coprocessor performs temperature compensation regularly based on the second parameter and returns the result of the temperature compensation to the main processor.

[0069] S102, Write the first variable and the second variable into the registers of the coprocessor. Wherein, the first variable is used to instruct the coprocessor to disconnect the main processor's connection to the DDR, and the second variable is used to instruct the coprocessor to perform retraining on at least one subsystem and perform temperature compensation on the DDR during the retraining process.

[0070] It can be understood that the main processor writes the variables corresponding to the registers (i.e., the first variable and the second variable) into the registers of the coprocessor, so that the coprocessor can perform retrain on at least one subsystem by reading the first variable and the second variable in the registers, and perform temperature compensation on the DDR during the retrain process.

[0071] In some possible implementation manners, after the above S101 and before S102, the above temperature compensation method may further include: reading the second register parameter and the third register parameter of the main processor; the second register parameter is used to represent the most significant bit (MSB) of the DQS oscillator counter, and the third register parameter is used to represent the least significant bit (LSB) of the DQS oscillator counter; determining the first delay time of the DQS oscillator counter based on the most significant bit, the least significant bit, and a preset first mapping relationship; in the case that the first difference between the first delay time and the second delay time of the DQS oscillator counter is greater than a preset threshold, determining that the DDR needs to perform temperature compensation and the direction of the temperature compensation.

[0072] Wherein, the first mapping relationship is the mapping relationship between the most significant bit, the least significant bit, and the first delay time; the first delay time is the time length from the start to the stop of the DQS timer recorded by the DQS oscillator counter within the first time period; the second delay time is the time length from the start to the stop of the DQS timer recorded by the DQS oscillator counter within the second time period; the second time period occurs before the first time period.

[0073] It can be understood that by reading the values of the registers in the main processor, the first delay time of the DQS oscillator count can be calculated. The first delay time drifts approximately linearly with the temperature. Based on the first delay time, it can be determined whether the DDR has undergone temperature drift and whether temperature compensation is required.

[0074] In one example, the main processor obtains the second register parameter (i.e., the most significant bit) and the third register parameter (i.e., the least significant bit) by reading the values of MR18 and MR19. The value of MR18 can be represented as MR18_value and is used to store the MSB of the DQS oscillator count; the value of MR19 can be represented as MR19_value and is used to store the LSB of the DQS oscillator count.

[0075] In one example, after obtaining MR18_value and MR19_value, the first delay time of the DQS oscillator count can be calculated based on Expression (1).

[0076]

[0077] In Equation (1), tctdelay_init represents the first delay time of the DQS oscillator count. The time for each DQS CLK is 470 picoseconds (ps), and the DQS timer stops counting after counting 2048 DQS clks.

[0078] It can be understood that in Equation (1), MR18_value is the most significant bit, MR19_value is the least significant bit, tctdelay_init is the first delay time, and the first mapping relationship is the expression shown in Equation (1).

[0079] In one example, the first delay times corresponding to the two subsystems can be represented as tctdelay_init0 and tctdelay_init1 respectively.

[0080] In some embodiments, after calculating the current first delay time of the DQS oscillator count, the first delay time can be compared with the second delay time of the DQS oscillator count obtained in the previous calculation, that is, the first difference between the first delay time and the second delay time is calculated; when the absolute value of the first difference is greater than or equal to a preset threshold, temperature compensation is required; when the absolute value of the first difference is less than the preset threshold, the steps of reading the second register parameter and the third register parameter of the main processor are returned.

[0081] In one example, when it is determined that temperature compensation is required, if the first delay time is greater than the second delay time, the delay needs to be increased to compensate for the increased delay caused by the temperature rise; if the first delay time is less than the second delay time, the delay needs to be reduced to compensate for the reduced delay caused by the temperature drop.

[0082] In some embodiments, after obtaining the first delay time, the above temperature compensation method may further include: reading the initial values of four bytes corresponding to each subsystem and nine delaylines of the transmit data write signals (TxDqWr) to perform temperature compensation on TxDqWr.

[0083] In one example, taking two x32 subsystems as an example, the initial values of four bytes and nine delaylines of TxDqWr for the two subsystems are stored in delayline_init_dq_sys0[4][9] and delayline_init_dq_sys1[4][9] respectively.

[0084] In one example, performing temperature compensation on TxDqWr mainly involves adjusting the delayline to ensure the stability and accuracy of data transmission.

[0085] In some possible implementation manners, after determining that the DDR needs temperature compensation and the direction of temperature compensation, the above temperature compensation method may further include: determining the target delay time of the DQS oscillator counter after removing the influence of temperature drift based on the first difference between the first delay time and the second delay time and a preset second mapping relationship; the second mapping relationship is the mapping relationship between the first difference and the target delay time; writing the target delay time into the register of the coprocessor.

[0086] It can be understood that after determining the first difference, the main processor may calculate the delay time of the DQS oscillator count (i.e., the target delay time) after removing the current temperature drift of the DDR based on the preset second mapping relationship; then, write the target delay time into the register of the coprocessor.

[0087] In some embodiments, the expression (2) of the second mapping relationship is as follows:

[0088] wdq_delayline_new = μ × (tctdelay_new - tctdelay_old) + wdq_delayline_old (2)

[0089] In formula (2), μ is a preset DDR coefficient, tctdelay_new is the first delay time, tctdelay_old is the second delay time, wdq_delayline_new is the current target delay time, and wdq_delayline_old is the target delay time calculated during the previous temperature compensation.

[0090] In some embodiments, the value of μ varies according to different brands, part numbers, and batches of DDR. Therefore, the value of μ can be determined by collecting relevant data.

[0091] In one example, Figure 3 FIG. 3 is a schematic flowchart of a third embodiment of the temperature compensation method for a double data rate synchronous dynamic random access memory according to an embodiment of the present disclosure. Refer to Figure 3 As shown, the above temperature compensation method may include:

[0092] S301, the main processor reads MR18_value and MR19_value.

[0093] S302, the main processor calculates tctdelay_init0 and tctdelay_init1 corresponding to two subsystems respectively.

[0094] S303, the main processor calculates delayline_init_dq_sys0[4][9] and delayline_init_dq_sys1[4][9] respectively.

[0095] S304, the main processor calculates the value of tctdelay_new, and determines whether to perform temperature compensation by comparing it with tctdelay_old; if temperature compensation is to be performed, S305 is executed; if temperature compensation is not to be performed, return to S301.

[0096] S305, the main processor calculates wdq_delayline_new.

[0097] S306, the main processor writes wdq_delayline_new into the register of the coprocessor, and cooperates with the coprocessor to implement retrain of the receive enable signal (RxEN).

[0098] S307, the main processor resets the training completion bit of the receive enable signal, and releases the reset (releasereset). After the release is completed, return to S301.

[0099] In some possible implementation manners, before the above S102, the temperature compensation method may further include: reading the minimum value and the maximum value of the receive enable signal of at least one subsystem; determining the start point and the end point of retraining based on the minimum value and the maximum value of the receive enable signal; writing the start point and the end point of retraining into the register of the coprocessor.

[0100] It can be understood that the main processor can determine the start point and end point of retraining by reading the maximum and minimum values of RxEN; after determining the start point and end point of retraining, write the start point and end point into the registers of the coprocessor to cooperate with the coprocessor to complete retraining.

[0101] In one example, the main processor reads the maximum and minimum values of RxEN corresponding to 4 bytes in each subsystem; based on the maximum and minimum values, determine the start point and end point of RxEN retrain, and it is necessary to ensure that the retrain range includes the RxEN of each byte, even if the start point is less than the minimum value of RxEN and the end point is greater than the maximum value of RxEN.

[0102] In some embodiments, after determining the start point and end point of retraining, the above temperature compensation method may further include: the main processor sets the step size of RxEN retrain, where the step size represents the jump value of the delay line during the training process.

[0103] In some possible implementation manners, before the above S102, the above temperature compensation method may further include: reading the first initial variable of the first register in the main processor; modifying the first initial variable to obtain the first variable; reading the second initial variable of the second register in the main processor; modifying the second initial variable to obtain the second variable.

[0104] It can be understood that the first variable and the second variable are obtained by modifying the registers in the main processor.

[0105] In one example, read the first register in the main processor to obtain the value of the first register dataflow (i.e., the first initial variable), modify the first initial variable to obtain the first variable dataflow_mpc. dataflow_mpc is used to set the DDR memory controller to the mpc mode during RxEN retrain, that is, when disconnecting the main processor's access to the DDR memory, dataflow_mpc can be used to adjust the signal timing.

[0106] In one example, the second register in the main processor is read to obtain the value of the second register, that is, the second initial variable. The second initial variable is modified to obtain the second variables rank0_rdglvl_req and rank1_rdglvl_req. rank0_rdglvl_req and rank1_rdglvl_req respectively correspond to two ranks of the subsystem. rank0_rdglvl_req and rank1_rdglvl_req are used to send a single-rank RxENretrain request to the PHY after the coprocessor disconnects the DDR connection of the main processor.

[0107] In some possible implementation manners, after modifying the second initial variable to obtain the second variables, the above temperature compensation method may further include: modifying the handshake information between the main processor and the coprocessor based on the second variables; the modified handshake information is used to indicate the target subsystem for retraining in at least one subsystem; and sending the modified handshake information to the coprocessor.

[0108] It can be understood that after determining that temperature compensation is required, the target subsystem for retraining can be determined in at least one subsystem by modifying the handshake information of the handshake register between the main processor and the coprocessor.

[0109] In some embodiments, after determining that temperature compensation is required, the main processor may read the value of the third register (such as MR13) in the main processor. MR13 contains the settings for controlling various functions of the DDR, including read preamble training. The value of MR13 is denoted as MR13_pre, and MR13_pre refers to the normal value of MR13, that is, the original value before any modification. This value usually contains the standard settings of the DDR memory for normal operation. Then, the value of MR13 is modified to obtain MR13_value. MR13_value is the value after bit [1] is set to 1, which means enabling read preamble training. Only through the operation of setting bit [1] of the above MR13_value can subsequent retraining be performed.

[0110] In one example, Figure 4 is a schematic flowchart of the fourth embodiment of the temperature compensation method for a double data rate synchronous dynamic random access memory in the embodiments of the present disclosure. Refer to Figure 4 As shown, the above temperature compensation method may include:

[0111] S401, the main processor reads the maximum and minimum values of RxEN of four bytes in each subsystem.

[0112] S402, the main processor determines the start point and end point of retrain based on the maximum and minimum values of RxEN.

[0113] S403, the main processor sets the step size of RxEN training.

[0114] S404, the main processor reads and modifies the first initial variable of the first register to obtain the first variable.

[0115] S405, the main processor writes the start point and end point of retrain into the register of the coprocessor.

[0116] S406, the main processor reads and modifies the second initial variable of the second register to obtain the second variable.

[0117] S407, the main processor reads and modifies the value of the third register to obtain MR13_pre and MR13_value.

[0118] S408, the main processor writes the first variable and the second variable into the register of the coprocessor, and cooperates with the coprocessor to complete retrain.

[0119] Thus, the temperature compensation method executed by the main processor is completed.

[0120] The embodiment of the present disclosure also provides a temperature compensation method for a double data rate synchronous dynamic random access memory executed by a coprocessor. Figure 5 It is a schematic flowchart of the fifth embodiment of the temperature compensation method for the double data rate synchronous dynamic random access memory in the embodiment of the present disclosure. This method is executed by the coprocessor. Refer to Figure 5 As shown, this method may include:

[0121] S501, receive the first parameter and the second parameter sent by the main processor. Among them, the first parameter is used to instruct the coprocessor to perform temperature compensation, and the second parameter is used to instruct the time interval of temperature compensation.

[0122] It can be understood that the coprocessor receives the first parameter and the second parameter sent by the main processor.

[0123] S502, read the first variable and the second variable written by the main processor from the register. Among them, the first variable is used to instruct the coprocessor to disconnect the access to the DDR, and the second variable is used to instruct the coprocessor to retrain at least one subsystem and perform temperature compensation on the DDR during the retraining process.

[0124] It can be understood that after the main processor writes the first variable and the second variable into the register of the coprocessor, the coprocessor can obtain the first variable and the second variable by reading the register.

[0125] S503, disconnect the connection between the main processor and the DDR based on the first variable.

[0126] It can be understood that the first variable is used to instruct the coprocessor to disconnect the access to the DDR. Then, the coprocessor can disconnect the main processor's access to the DDR memory based on the first variable, that is, disconnect the DDR connection.

[0127] S504, perform temperature compensation on the DDR based on the first parameter, the second parameter, and the second variable.

[0128] It can be understood that the coprocessor can perform retrain on RxEN based on the first parameter, the second parameter, and the second variable, and perform temperature compensation on the DDR during the retrain process.

[0129] In some possible implementation manners, the above temperature compensation for the DDR based on the first parameter, the second parameter, and the second variable may include: receiving the modified handshake information sent by the main processor; the modified handshake information is used to indicate the target subsystem for retraining in at least one subsystem; reading the target delay time, the start point and the end point of retraining written by the main processor; based on the modified handshake information, performing retraining on the target subsystem, and during the retraining process, performing temperature compensation on the DDR based on the target delay time, the start point and the end point of temperature compensation, the first parameter, the second parameter, and the second variable.

[0130] It can be understood that the coprocessor reads the target delay time, the start point and the end point of retraining written by the main processor, and performs retrain on the target subsystem indicated by the handshake information based on the target delay time and the start point and the end point of retraining.

[0131] In some embodiments Figure 6 is a schematic flowchart of the sixth embodiment of the temperature compensation method for the double data rate synchronous dynamic random access memory in the embodiments of the present disclosure. Refer to Figure 6As shown in the figure, the temperature compensation method for DDR may include: (1) The main processor 62 is controlled by the application software 61. The main processor 62 completes the compensation of the delay line of TxDqWr and the preparatory work before RxEN retrain, prepares the required parameters and variables in advance and writes them into the registers of the coprocessor 63, and then sends a handshake message and an interrupt instruction to the coprocessor 63. (2) After receiving the interrupt instruction, the coprocessor 63 reads out the data filled in the registers of the coprocessor 63 by the main processor 62, disconnects the access of the main processor 62 to the DDR, performs RxEN retrain. After the retrain is completed, the interrupt and handshake messages are cleared and the access of the main processor 62 to the DDR is restored, and the control right is returned to the main processor 62. (3) The application software 61 controls the main processor 62 to enter the sleep state, temporarily releases the control right of the main processor 62, waits for a period of time, and then continues to repeat steps (1) and (2).

[0132] In some embodiments, Figure 7 FIG. 7 is a schematic flowchart of the seventh embodiment of the temperature compensation method for a double data rate synchronous dynamic random access memory in the embodiments of the present disclosure, Figure 7 showing a schematic diagram of the interaction between the main processor and the coprocessor. Refer to Figure 7 As shown in the figure, the method includes:

[0133] S701, the main processor writes all the register configurations required for RxEN retrain into the registers of the coprocessor. And handshake with the coprocessor through the AP2RTC_shakehand[3:0] register and issue an interrupt.

[0134] S702, after receiving the interrupt, the coprocessor determines which subsystem and which rank need to perform RxEN retrain through the AP2RTC_shakehand[3:0] handshake register, reads out the corresponding variables from the registers of the coprocessor, and prepares for RxEN retrain.

[0135] S703, the coprocessor disconnects the DDR connection and writes the above corresponding configuration into the phyd register to perform RxEN retrain. After RxEN retrain is completed, a polling operation (polling done) is performed to clear the interrupt and set the corresponding bit of the AP2RTC_shakehand[3:0] handshake register to zero for the next RxEN retrain.

[0136] Thus, the above temperature compensation method is completed.

[0137] In an embodiment of the present disclosure, the main processor sends a first parameter and a second parameter for indicating a time interval for temperature compensation and temperature compensation detection to the coprocessor, and writes a first parameter for indicating that the coprocessor disconnects the main processor from the DDR and a second variable for indicating that the coprocessor performs retraining on at least one subsystem into the register of the coprocessor, so that temperature compensation can be performed on the DDR in any state, without restricting the DDR to be in an idle, self-refresh, or refresh state, thereby improving the flexibility of temperature compensation.

[0138] Furthermore, the temperature compensation method described in the embodiment of the present disclosure is implemented in cooperation with the main processor and the coprocessor, without using proprietary hardware resources. Thus, the area of the chip can be reduced, and the cost can be further reduced. In addition, the time for the main processor to disconnect from the DDR can be minimized as much as possible, further improving the flexibility and portability of the temperature compensation solution.

[0139] Furthermore, the temperature compensation method described in the embodiment of the present disclosure can perform temperature compensation for any data transfer rate (data rate), without being restricted to the case where data rate ≥ 1600 Mbps, further improving the flexibility of temperature compensation.

[0140] Based on the same inventive concept, the embodiment of the present disclosure further provides a temperature compensation device for a double data rate synchronous dynamic random access memory. The device can be a chip or a system-on-chip of a server, or a functional module for the method described in one or more of the above embodiments in the server. Figure 8 For the first structural schematic diagram of the temperature compensation device for the double data rate synchronous dynamic random access memory in the embodiment of the present disclosure, see Figure 8 As shown, the temperature compensation device 800 for the double data rate synchronous dynamic random access memory may include: a data sending module 801, configured to send a first parameter and a second parameter to the coprocessor; the first parameter is used to indicate that the coprocessor performs temperature compensation, and the second parameter is used to indicate a time interval for temperature compensation detection; a data writing module 802, configured to write a first variable and a second variable into the register of the coprocessor; the first variable is used to indicate that the coprocessor disconnects the main processor from the DDR, and the second variable is used to indicate that the coprocessor performs retraining on at least one subsystem and performs temperature compensation on the DDR during the retraining process.

[0141] In some possible embodiments, the above-mentioned device 800 further includes: a data processing module, configured to set first register parameters of the main processor; the first register parameters are used to indicate the counting rule of the data strobe signal (DQS) timer of the DDR; set the handshake information between the main processor and the coprocessor to zero; the handshake information after being set to zero is used to indicate that the DDR has completed the previous temperature compensation request.

[0142] In some possible embodiments, the data processing module is further configured to read second register parameters and third register parameters of the main processor; the second register parameters are used to represent the most significant bit of the DQS oscillator counter, and the third register parameters are used to represent the least significant bit of the DQS oscillator counter; based on the most significant bit, the least significant bit, and a preset first mapping relationship, determine a first delay time of the DQS oscillator counter; the first mapping relationship is the mapping relationship between the most significant bit, the least significant bit, and the first delay time; the first delay time is the time length recorded by the DQS oscillator counter for the DQS timer from start to stop within a first time period; in the case that a first difference between the first delay time and a second delay time of the DQS oscillator counter is greater than a preset threshold, determine that the DDR needs temperature compensation and the direction of temperature compensation; the second delay time is the time length recorded by the DQS oscillator counter for the DQS timer from start to stop within a second time period; the second time period occurs before the first time period.

[0143] In some possible embodiments, the data processing module is further configured to determine a target delay time of the DQS oscillator counter after removing the influence of temperature drift based on the first difference between the first delay time and the second delay time and a preset second mapping relationship; the second mapping relationship is the mapping relationship between the first difference and the target delay time; write the target delay time into the register of the coprocessor.

[0144] In some possible embodiments, the data processing module is further configured to read the minimum value and the maximum value of the receive enable signal of at least one subsystem; determine a starting point and an ending point of retraining based on the minimum value and the maximum value of the receive enable signal; write the starting point and the ending point of retraining into the register of the coprocessor.

[0145] In some possible embodiments, the data processing module is further configured to read a first initial variable of a first register in the main processor; modify the first initial variable to obtain a first variable; read a second initial variable of a second register in the main processor; modify the second initial variable to obtain a second variable.

[0146] In some possible embodiments, the data processing module is further configured to modify the handshake information between the main processor and the coprocessor based on a second variable; the modified handshake information is used to indicate a target subsystem for retraining in at least one subsystem; and send the modified handshake information to the coprocessor.

[0147] Based on the same inventive concept, an embodiment of the present disclosure further provides a temperature compensation device for a double data rate synchronous dynamic random access memory. The device may be a chip or a system-on-chip of a server, or may also be a functional module in the server for the method described in one or more of the above embodiments. Figure 9 This is a second structural schematic diagram of the temperature compensation device for the double data rate synchronous dynamic random access memory in the embodiment of the present disclosure. Refer to Figure 9 As shown, the temperature compensation device 900 for the double data rate synchronous dynamic random access memory may include: a data receiving module 901, configured to receive a first parameter and a second parameter sent by the main processor; the first parameter is used to instruct the coprocessor to perform temperature compensation, and the second parameter is used to indicate the time interval for temperature compensation; a data reading module 902, configured to read a first variable and a second variable written by the main processor from a register; the first variable is used to instruct the coprocessor to disconnect the access to the DDR, and the second variable is used to instruct the coprocessor to retrain at least one subsystem and perform temperature compensation on the DDR during the retraining process; a connection interruption module 903, configured to disconnect the connection between the main processor and the DDR based on the first variable; and a temperature compensation module 904, configured to perform temperature compensation on the DDR based on the first parameter, the second parameter, and the second variable.

[0148] In some possible embodiments, the temperature compensation module 904 is configured to receive the modified handshake information sent by the main processor; the modified handshake information is used to indicate a target subsystem for retraining in at least one subsystem; read the target delay time, the start point and the end point of temperature compensation written by the main processor; based on the modified handshake information, retrain the target subsystem, and during the retraining process, perform temperature compensation on the DDR based on the target delay time, the start point and the end point of retraining, the first parameter, the second parameter, and the second variable.

[0149] An embodiment of the present disclosure provides a computer program product or a computer program. The computer program product or the computer program includes computer instructions, and the computer instructions are stored in a computer storage medium. A processor of a computer device reads the computer instructions from the computer storage medium, and the processor executes the computer instructions, so that the computer device executes the above temperature compensation method of the embodiment of the present disclosure.

[0150] Embodiments of the present disclosure provide a computer storage medium storing executable instructions, where the executable instructions, when executed by a processor, will cause the processor to execute the temperature compensation method provided by the embodiments of the present disclosure. For example Figure 1 and Figure 5 the temperature compensation method shown.

[0151] In some embodiments, the computer storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disc, or CD-ROM; or may be various devices including one or any combination of the above memories.

[0152] In some embodiments, the executable instructions may be in the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including being deployed as an independent program or being deployed as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0153] As an example, the executable instructions may or may not correspond to a file in the file system, may be stored as part of a file that stores other programs or data. For example, they may be stored in one or more scripts in a hyper text markup language (HTML) document, stored in a single file dedicated to the program in question, or stored in multiple cooperating files (such as files storing one or more modules, subroutines, or portions of code).

[0154] As an example, the executable instructions may be deployed to execute on one computing device, or on multiple computing devices located at one location, or on multiple computing devices distributed at multiple locations and interconnected by a communication network.

[0155] Those skilled in the art will readily conceive of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known common general knowledge or conventional technical means in the technical field not disclosed by the present disclosure. The specification and examples are only to be considered as exemplary, and the true scope and spirit of the present disclosure are pointed out by the following claims.

[0156] It should be understood that the present disclosure is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only limited by the appended claims.

Claims

1. A temperature compensation method for a double data rate synchronous dynamic random access memory DDR, characterized in that: Executed by a main processor, the method includes: Sending a first parameter and a second parameter to the coprocessor; the first parameter is used to instruct the coprocessor to perform temperature compensation, and the second parameter is used to indicate a time interval for performing temperature compensation detection; A first variable and a second variable are written into the register of the coprocessor; the first variable is used to instruct the coprocessor to disconnect the main processor from the DDR, and the second variable is used to instruct the coprocessor to retrain at least one subsystem and perform temperature compensation on the DDR during the retraining process.

2. The method according to claim 1, characterized in that Before sending the first parameter and the second parameter to the coprocessor, the method further includes: Setting a first register parameter of the main processor; the first register parameter is used to indicate a counting rule of a data selection signal DQS timer of the DDR; The handshake information between the main processor and the coprocessor is reset to zero; the handshake information after being reset to zero is used to indicate that the DDR has completed the last temperature compensation request.

3. The method according to claim 2, characterized in that Before writing the first variable and the second variable into the coprocessor, the method further includes: Reading a second register parameter and a third register parameter of the main processor; the second register parameter is used to represent the most significant bit of the DQS oscillator counter, and the third register parameter is used to represent the least significant bit of the DQS oscillator counter; Based on the most significant bit, the least significant bit and a preset first mapping relationship, determining a first delay time of the DQS oscillator counter; the first mapping relationship is a mapping relationship between the most significant bit, the least significant bit and the first delay time; the first delay time is the length of time taken by the DQS timer from start to stop recorded by the DQS oscillator counter in a first time period; When a first difference between the first delay time and the second delay time of the DQS oscillator counter is greater than a preset threshold, it is determined that the DDR needs to be temperature compensated and the direction of the temperature compensation; the second delay time is the length of time taken by the DQS timer from start to stop recorded by the DQS oscillator counter in a second time period; the second time period occurs before the first time period.

4. The method according to claim 3, characterized in that After determining that the DDR needs to be temperature compensated and the direction of the temperature compensation, the method further includes: Determine a target delay time of the DQS oscillator counter after removing the influence of temperature drift based on a first difference between the first delay time and the second delay time and a preset second mapping relationship; the second mapping relationship is a mapping relationship between the first difference and the target delay time; The target delay time is written into a register of the coprocessor.

5. The method according to claim 1, characterized in that Before writing the first variable and the second variable into the coprocessor, the method further includes: Reading a minimum value and a maximum value of a receive enable signal of the at least one subsystem; Determining a starting point and an ending point of retraining based on a minimum value and a maximum value of the reception enable signal; The starting point and the ending point of the retraining are written into the register of the coprocessor.

6. The method according to claim 1, characterized in that Before writing the first variable and the second variable into the coprocessor, the method further includes: Reading a first initial variable of a first register in a main processor; modifying the first initial variable to obtain the first variable; Reading a second initial variable of a second register in the main processor; The second initial variable is modified to obtain the second variable.

7. The method according to claim 6, characterized in that After modifying the second initial variable to obtain the second variable, the method further includes: Modify the handshake information between the main processor and the coprocessor based on the second variable; the modified handshake information is used to indicate the target subsystem to be retrained in the at least one subsystem; The modified handshake information is sent to the coprocessor.

8. A temperature compensation method for a double data rate synchronous dynamic random access memory DDR, characterized in that: Executed by a coprocessor, the method includes: receiving a first parameter and a second parameter sent by a main processor; wherein the first parameter is used to instruct the coprocessor to perform temperature compensation, and the second parameter is used to indicate a time interval of temperature compensation; Reading a first variable and a second variable written by the main processor from a register; the first variable is used to instruct the coprocessor to disconnect access to the DDR, and the second variable is used to instruct the coprocessor to retrain at least one subsystem and perform temperature compensation on the DDR during the retraining process; Based on the first variable, disconnecting the main processor from the DDR; The DDR is temperature compensated based on the first parameter, the second parameter and the second variable.

9. The method according to claim 8, characterized in that The performing temperature compensation on the DDR based on the first parameter, the second parameter and the second variable comprises: receiving modified handshake information sent by the main processor; the modified handshake information is used to indicate a target subsystem to be retrained in the at least one subsystem; Reading the target delay time, the start point and the end point of the temperature compensation written by the main processor; Based on the modified handshake information, the target subsystem is retrained, and during the retraining process, the DDR is temperature compensated based on the target delay time, the start point and end point of the retraining, the first parameter, the second parameter and the second variable.

10. A temperature compensation device for a double data rate synchronous dynamic random access memory DDR, characterized in that: Applied to a main processor, the device comprises: A data sending module, used for sending a first parameter and a second parameter to the coprocessor; the first parameter is used for instructing the coprocessor to perform temperature compensation, and the second parameter is used for indicating a time interval for performing temperature compensation detection; A data writing module is used to write a first variable and a second variable into the register of the coprocessor; the first variable is used to instruct the coprocessor to disconnect the main processor from the DDR, and the second variable is used to instruct the coprocessor to retrain at least one subsystem and perform temperature compensation on the DDR during the retraining process.

11. A temperature compensation device for a double data rate synchronous dynamic random access memory DDR, characterized in that: Applied to a coprocessor, the device comprises: A data receiving module, used for receiving a first parameter and a second parameter sent by a main processor; the first parameter is used for instructing the coprocessor to perform temperature compensation, and the second parameter is used for indicating a time interval of temperature compensation; a data reading module, configured to read from a register a first variable and a second variable written by the main processor; the first variable is used to instruct the coprocessor to disconnect access to the DDR, and the second variable is used to instruct the coprocessor to retrain at least one subsystem and perform temperature compensation on the DDR during the retraining process; A connection interruption module, used for disconnecting the main processor from the DDR based on the first variable; A temperature compensation module is used to perform temperature compensation on the DDR based on the first parameter, the second parameter and the second variable.

12. An electronic device, characterized in that: The electronic device comprises: A memory for storing executable instructions; A processor, configured to implement the method of any one of claims 1 to 7 or claims 8 to 9 when executing the executable instructions or computer programs stored in the memory.

13. A computer-readable storage medium storing executable instructions or a computer program, characterized in that: When the executable instructions are executed by a processor, the method of any one of claims 1 to 7 or claims 8 to 9 is implemented.

14. A computer program product, comprising a computer program or instructions, characterized in that: When the computer program or instruction is executed by a processor, the steps of the method according to any one of claims 1 to 7 or claims 8 to 9 are implemented.

Images