Sensitive amplifier and control method

Abstract

The invention provides a sensitive amplifier and a control method, the sensitive amplifier comprises a seventh transistor, an eighth transistor, a first switch unit, a second switch unit and a first equalization circuit, and the first switch unit and the second switch unit receive an isolation control signal and are switched on or off based on the isolation control signal. The output end of the first equalization circuit is connected with the control end of the seventh transistor and the control end of the eighth transistor, and the first switch unit and the second switch unit are controlled to be switched on or switched off in a combined mode. The first equalization circuit precharges the bit line and the complementary bit line to a second precharge voltage, and forms a compensation voltage on the bit line and the complementary bit line.

Description

Technical Field

[0001] This application relates to, but is not limited to, a sense amplifier and a control method thereof. Background Art

[0002] With the popularization of electronic devices such as mobile phones, tablets, and personal computers, semiconductor memory technology has also developed rapidly.

[0003] In a Dynamic Random Access Memory (DRAM), an amplifier circuit is provided to amplify the voltage difference and realize reading or writing data in a storage unit. The improvement of the amplifier circuit can improve the performance of the memory. Summary of the Invention

[0004] Some embodiments of this application provide a sense amplifier, including: a seventh transistor, an eighth transistor, a first switch unit, a second switch unit, and a first equalization circuit;

[0005] A first end of the seventh transistor is connected to a bit line, a control end of the seventh transistor is connected to a first end of the first switch unit, a second end of the first switch unit is connected to a first end of the eighth transistor, and a second end of the seventh transistor receives a second power signal;

[0006] A first end of the eighth transistor is connected to a complementary bit line, a control end of the eighth transistor is connected to a second end of the second switch unit, a first end of the second switch unit is connected to a first end of the seventh transistor, and a second end of the eighth transistor receives a second power signal;

[0007] The first switch unit and the second switch unit receive an isolation control signal and conduct or cut off based on the isolation control signal;

[0008] An output end of the first equalization circuit is connected to a control end of the seventh transistor and a control end of the eighth transistor, and is configured to output a third power signal based on a first equalization signal.

[0009] In some embodiments, the sense amplifier further includes: a first transistor and a second transistor;

[0010] A first end of the first transistor receives a first power signal, a second end is connected to a first end of the seventh transistor, and a control end is connected to a second end of the second transistor;

[0011] A first end of the second transistor receives a first power signal, a second end is connected to a first end of the eighth transistor, and a control end is connected to a second end of the first transistor.

[0012] In some embodiments, the sense amplifier further includes: a first transistor and a second transistor;

[0013] A first terminal of the first transistor receives a first power signal, a control terminal of the first transistor is connected to a control terminal of a seventh transistor, and a second terminal of the first transistor is connected to a bit line;

[0014] A first terminal of the second transistor receives the first power signal, a control terminal of the second transistor is connected to a control terminal of an eighth transistor, and a second terminal of the second transistor is connected to a complementary bit line.

[0015] In some embodiments, the first equalization circuit includes a fifth transistor and a sixth transistor, and the first equalization signal includes a second equalization signal and a third equalization signal;

[0016] A first terminal of the fifth transistor is configured to receive a third power signal, a second terminal is connected to the control terminal of the seventh transistor or the control terminal of the eighth transistor, and a control terminal is configured to receive the second equalization signal;

[0017] A first terminal of the sixth transistor is connected to the control terminal of the seventh transistor, a second terminal of the sixth transistor is connected to the control terminal of the eighth transistor, and a control terminal of the sixth transistor is configured to receive the third equalization signal.

[0018] In some embodiments, the first transistor and the second transistor are P-type transistors, and the seventh transistor and the eighth transistor are N-type transistors; or,

[0019] The first transistor and the second transistor are N-type transistors, and the seventh transistor and the eighth transistor are P-type transistors.

[0020] Some embodiments of the present application provide a control method for a sense amplifier, and the sense amplifier includes a seventh transistor, an eighth transistor, a first switching unit, a second switching unit, and a first equalization circuit;

[0021] A first terminal of the seventh transistor is connected to the bit line, a control terminal of the seventh transistor is connected to a first terminal of the first switching unit, a second terminal of the first switching unit is connected to a first terminal of the eighth transistor, and a second terminal of the seventh transistor receives a second power signal;

[0022] A first terminal of the eighth transistor is connected to the complementary bit line, a control terminal of the eighth transistor is connected to a second terminal of the second switching unit, a first terminal of the second switching unit is connected to the first terminal of the seventh transistor, and a second terminal of the eighth transistor receives the second power signal;

[0023] Control terminals of the first switching unit and the second switching unit receive an isolation control signal; an output terminal of the first equalization circuit is connected to the control terminals of the seventh transistor and the eighth transistor, and the control method includes:

[0024] In the idle stage, the isolation control signal controls the first switch unit and the second switch unit to conduct, and the first equalization signal controls the first equalization circuit to output a third power signal. The voltage of the second power signal is the first pre-charge voltage, and the third power signal is the second pre-charge voltage;

[0025] In the offset cancellation stage, the isolation control signal controls the first switch unit and the second switch unit to turn off, and the first equalization signal controls the first equalization circuit to output a third power signal. The voltages of the second power signal and the third power signal make the seventh transistor and the eighth transistor operate in the source follower mode.

[0026] In some embodiments, the sense amplifier further includes: a first transistor and a second transistor; a first end of the first transistor receives a first power signal, a second end is connected to a first end of the seventh transistor, and a control end is connected to a second end of the second transistor; a first end of the second transistor receives the first power signal, a second end is connected to a first end of the eighth transistor, and a control end is connected to a second end of the first transistor;

[0027] In the offset cancellation stage, when the first transistor and the second transistor are P-type transistors, the seventh transistor and the eighth transistor are N-type transistors, the voltage of the second power signal is greater than the first pre-charge voltage, the voltage of the third power signal is greater than the second pre-charge voltage, and the voltage of the second power signal is greater than the voltage of the third power signal.

[0028] In some embodiments, the sense amplifier further includes: a first transistor and a second transistor; a first end of the first transistor receives a first power signal, a second end is connected to a first end of the seventh transistor, and a control end is connected to a second end of the second transistor; a first end of the second transistor receives the first power signal, a second end is connected to a first end of the eighth transistor, and a control end is connected to a second end of the first transistor;

[0029] In the offset cancellation stage, when the first transistor and the second transistor are N-type transistors, the seventh transistor and the eighth transistor are P-type transistors, the voltage of the second power signal is less than the first pre-charge voltage, the voltages of the third power signal are both less than the second pre-charge voltage, and the voltage of the second power signal is less than the voltage of the third power signal.

[0030] Some embodiments of the present application provide a control method for a sense amplifier. The sense amplifier includes a first transistor, a second transistor, a seventh transistor, an eighth transistor, a first switch unit, a second switch unit, and a first equalization circuit;

[0031] A first end of the first transistor receives a first power signal. A control end of the first transistor is connected to a control end of a seventh transistor. A second end of the first transistor is connected to a bit line. A first end of a second transistor receives the first power signal. A control end of the second transistor is connected to a control end of an eighth transistor. A second end of the second transistor is connected to a complementary bit line.

[0032] A first end of the seventh transistor is connected to the bit line. A control end of the seventh transistor is connected to a first end of a first switching unit. A second end of the first switching unit is connected to a first end of the eighth transistor. A second end of the seventh transistor receives a second power signal.

[0033] A first end of the eighth transistor is connected to the complementary bit line. A control end of the eighth transistor is connected to a second end of a second switching unit. A first end of the second switching unit is connected to the first end of the seventh transistor. A second end of the eighth transistor receives the second power signal.

[0034] A control end of the first switching unit and a control end of the second switching unit receive an isolation control signal. An output end of a first equalization circuit is connected to the control ends of the seventh transistor and the eighth transistor. The control method includes:

[0035] In an idle stage, the isolation control signal controls the first switching unit and the second switching unit to conduct. The first equalization signal controls the first equalization circuit to output a third power signal. The voltages of the first power signal and the second power signal are a first pre-charge voltage, and the third power signal is a second pre-charge voltage.

[0036] In an offset cancellation stage, the isolation control signal controls the first switching unit and the second switching unit to cut off. The first equalization signal controls the first equalization circuit to output a third power signal. The voltages of the first power signal and the third power signal make the first transistor and the second transistor in a source follower mode. The voltages of the second power signal and the third power signal make the seventh transistor and the eighth transistor in a source follower mode.

[0037] In some embodiments, in the offset cancellation stage, the voltage of the first power signal is less than the first pre-charge voltage, the voltage of the second power signal is greater than the first pre-charge voltage, and the voltage of the third power signal is the second pre-charge voltage.

[0038] In some embodiments, the first equalization circuit includes a fifth transistor and a sixth transistor. The first equalization signal includes a second equalization signal and a third equalization signal.

[0039] A first end of the fifth transistor is configured to receive the third power signal. A second end is connected to the control end of the seventh transistor or the control end of the eighth transistor. A control end is configured to receive the second equalization signal.

[0040] The first end of the sixth transistor is connected to the control end of the seventh transistor, the second end of the sixth transistor is connected to the control end of the eighth transistor, and the control end of the sixth transistor is used to receive a third equalization signal. The method further includes:

[0041] In the pre-charge stage, the third equalization signal is at a high level first, and the sixth transistor is turned on; subsequently, the first power signal and the second power signal are at a first pre-charge voltage, and then the second equalization signal is at a high level, and the fifth transistor is turned on.

[0042] The sense amplifier and control method provided in this application, the sense amplifier includes a seventh transistor, an eighth transistor, a first switch unit, a second switch unit, and a first equalization circuit. The first switch unit and the second switch unit receive an isolation control signal and conduct or cut off based on the isolation control signal, so as to control whether the seventh transistor and the eighth transistor perform voltage difference amplification. By setting the first equalization circuit, the output end of the first equalization circuit is connected to the control ends of the seventh transistor and the eighth transistor, and by combining the conduction or cut-off of the first switch unit and the second switch unit, the first equalization circuit pre-charges the bit line and the complementary bit line to a second pre-charge voltage, and the first equalization circuit also forms a compensation voltage on the bit line and the complementary bit line. In this way, there is no need to additionally set transistors for completely eliminating or partially eliminating signal control, reducing the number of transistors in the sense amplifier and reducing the chip area of the sense amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The drawings herein are incorporated into the specification and form a part of this specification, showing embodiments consistent with this application, and are used together with the specification to explain the principles of this application.

[0044] Figure 1 It is a schematic structural diagram of a sense amplifier;

[0045] Figure 2 For Figure 1 The timing schematic diagram of the sense amplifier shown;

[0046] Figure 3 It is a schematic structural diagram of another sense amplifier;

[0047] Figure 4 It is a schematic structural diagram of a sense amplifier according to some embodiments of this application;

[0048] Figure 5 It is a schematic structural diagram of a sense amplifier according to other embodiments of this application;

[0049] Figure 6 For Figure 4 The timing schematic diagram of the sense amplifier shown;

[0050] Figure 7 ForFigure 5 Timing schematic diagram of the sense amplifier shown

[0051] Figure 8 Structural schematic diagram of a sense amplifier according to some embodiments of the present application

[0052] Figure 9 Structural schematic diagram of a sense amplifier according to other embodiments of the present application

[0053] Figure 10 is Figure 10 Timing schematic diagram of the sense amplifier shown

[0054] 110. First switch unit; 120. Second switch unit; 130. First equalization circuit; BLB. Complementary bit line; BL. Bit line; EQOC. Second equalization signal; EQ. Third equalization signal; VOC. Third power supply signal; CS1. First power supply signal; CS2. Second power supply signal; ISO. Isolation control signal; M1. First transistor; M2. Second transistor; M3. Third transistor; M4. Fourth transistor; M5. Fifth transistor; M6. Sixth transistor; M7. Seventh transistor; M8. Eighth transistor; M11. Eleventh transistor; M12. Twelfth transistor; M13. Thirteenth transistor; M14. Fourteenth transistor; M15. Fifteenth transistor; M16. Sixteenth transistor; M17. Seventeenth transistor; M18. Eighteenth transistor; M21. Twenty - first transistor; M22. Twenty - second transistor; M23. Twenty - third transistor.

[0055] Through the above - mentioned drawings, specific embodiments of the present application have been shown, and there will be more detailed descriptions hereinafter. These drawings and textual descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. Detailed Description of the Embodiments

[0056] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application.

[0057] It should be noted that the high level and low level mentioned below are relative concepts (i.e., the voltage value of the high level is higher than that of the corresponding low level), and the specific voltage value of the high level is not limited, nor is the specific voltage value of the low level limited. Moreover, it is not limited that the high levels applied to different signal lines in this specific embodiment are equal. Those skilled in the art should understand that the values of the corresponding high level and low level can be set by themselves according to process nodes, speed requirements, reliability requirements, etc.

[0058] Figure 1 is a schematic structural diagram of a sense amplifier, as Figure 1 shown, a sense amplifier includes an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a seventeenth transistor M17, and an eighteenth transistor M18.

[0059] The first end of the eleventh transistor M11 receives a fourth power supply signal PCS, the second end of the eleventh transistor M11 is connected to the first end of the seventeenth transistor M17, and the control end of the eleventh transistor M11 is connected to the second end of the twelfth transistor M12. The first end of the twelfth transistor M12 receives a fourth power supply signal PCS, the second end of the twelfth transistor M12 is connected to the first end of the eighteenth transistor M18, and the control end of the twelfth transistor M12 is connected to the second end of the eleventh transistor M11.

[0060] The control end of the seventeenth transistor M17 is connected to the first end of the eighteenth transistor M18 through the thirteenth transistor M13, the second end of the seventeenth transistor M17 receives a fifth power supply signal NCS, and the thirteenth transistor M13 conducts or cuts off according to an isolation control signal ISO. The control end of the eighteenth transistor M18 is connected to the first end of the seventeenth transistor M17 through the fourteenth transistor M14, the second end of the eighteenth transistor M18 receives a fifth power supply signal NCS, and the fourteenth transistor M14 conducts or cuts off according to an isolation control signal ISO. The control end of the seventeenth transistor M17 is connected to a bit line, and the control end of the eighteenth transistor M18 is connected to a complementary bit line.

[0061] The sense amplifier further includes a fifteenth transistor M15 and a sixteenth transistor M16. The first end of the fifteenth transistor M15 is connected to the control end of the seventeenth transistor M17, the second end of the fifteenth transistor M15 is connected to the first end of the seventeenth transistor M17, the first end of the sixteenth transistor M16 is connected to the first end of the eighteenth transistor M18, the second end of the sixteenth transistor M16 is connected to the control end of the eighteenth transistor M18, and the control ends of the fifteenth transistor M15 and the sixteenth transistor M16 both receive an offset control signal OC, and the offset control signal OC is used to control the fifteenth transistor M15 and the sixteenth transistor M16 to conduct or cut off.

[0062] The sense amplifier further includes a second equalization circuit. The output terminal of the second equalization circuit is connected to the first terminal of the seventeenth transistor M17 or the first terminal of the eighteenth transistor M18. The second equalization circuit receives a fourth equalization signal, and outputs a sixth power signal under the control of the fourth equalization signal, and pre-charges the voltages of the bit line BL and the complementary bit line BLB with the sixth power signal.

[0063] As Figure 1 shown, in some embodiments, the second equalization circuit includes a nineteenth transistor M19. The first terminal of the nineteenth transistor M19 is connected to the first terminal of the eighteenth transistor M18. The second terminal of the nineteenth transistor M19 receives the sixth power signal. The control terminal of the nineteenth transistor M19 receives the fourth equalization signal PreEQ. The fourth equalization signal PreEQ is used to control the conduction or cut-off of the nineteenth transistor M19, so as to realize the output of the sixth power signal by the second equalization circuit. Then, in cooperation with the conduction of the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, and the sixteenth transistor M16, the pre-charging of the bit line BL and the complementary bit line BLB is realized.

[0064] Figure 2 As Figure 1 shown, a possible timing control diagram of the sense amplifier is shown. The sense amplifier can also use other timing controls, which are not limited here.

[0065] Here, the eleventh transistor M11 and the twelfth transistor M12 are taken as P-type transistors, and the thirteenth transistor M13 to the nineteenth transistor M19 are taken as N-type transistors for illustration.

[0066] As Figure 2 shown, in the pre-charging stage S1, the fourth equalization signal PreEQ is at a high level, the nineteenth transistor M19 is turned on, the isolation control signal ISO is at a high level, the thirteenth transistor M13 and the fourteenth transistor M14 are turned on, the offset control signal OC is at a high level, the fifteenth transistor M15 and the sixteenth transistor M16 are turned on, the fourth power signal PCS and the fifth power signal NCS are both at a third pre-charging voltage, the word line signal WL is at a low level, the word line is turned off, and the bit line BL and the complementary bit line BLB are pre-charged to the third pre-charging voltage.

[0067] In the offset cancellation stage S2, the fourth equalization signal PreEQ is at a low level, the nineteenth transistor M19 is turned off, the isolation control signal ISO is at a low level, the thirteenth transistor M13 and the fourteenth transistor M14 are turned off, the offset control signal OC is at a high level, the fifteenth transistor M15 and the sixteenth transistor M16 are turned on, the fourth power supply signal PCS is the power supply voltage, the fifth power supply signal NCS is the ground voltage, the word line signal WL is at a low level, the word line is turned off, and a compensation voltage is formed on the bit line BL and the complementary bit line BLB.

[0068] In the charge sharing stage S3, the fourth equalization signal PreEQ is at a low level, the nineteenth transistor M19 is turned off, the isolation control signal ISO is at a low level, the thirteenth transistor M13 and the fourteenth transistor M14 are turned off, the offset control signal OC is at a low level, the fifteenth transistor M15 and the sixteenth transistor M16 are turned off, both the fourth power supply signal PCS and the fifth power supply signal NCS are the third pre-charge voltage, the word line signal WL is at a high level, the word line is turned on, and a shared voltage is formed on the bit line BL and the complementary bit line BLB. In some embodiments, in the charge sharing stage, the isolation control signal ISO is at a high level, or, in the second half of the charge sharing stage, the isolation control signal ISO is at a high level.

[0069] In the sense amplification stage S4, the fourth equalization signal PreEQ is at a low level, the nineteenth transistor M19 is turned off, the isolation control signal ISO is at a high level, the thirteenth transistor M13 and the fourteenth transistor M14 are turned on, the offset control signal OC is at a low level, the fifteenth transistor M15 and the sixteenth transistor M16 are turned off, the fourth power supply signal PCS is the power supply voltage, the fifth power supply signal NCS is the ground voltage, the word line signal WL is at a high level, the word line is turned on, and the voltage difference on the amplified bit line BL and the complementary bit line BLB is amplified.

[0070] It should be noted here that the isolation control signal ISO, the offset control signal OC, and the fourth equalization signal PreEQ are not limited to the above control timings and can also be in other ways, which are not restricted here.

[0071] Such as Figure 3As shown, in some embodiments, the second equalization circuit includes a twenty-second transistor M22 and a twenty-third transistor M23. A first end of the twenty-second transistor M22 is connected to the bit line BL, a second end of the twenty-second transistor M22 receives a sixth power signal, a first end of the twenty-third transistor M23 receives the sixth power signal, a second end of the twenty-third transistor M23 is connected to the complementary bit line BLB, and control ends of the twenty-second transistor M22 and the twenty-third transistor M23 receive a fourth equalization signal PreEQ. The fourth equalization signal PreEQ is used to control conduction or cutoff of the twenty-second transistor M22 and the twenty-third transistor M23, so as to output the sixth power signal by the second equalization circuit, and perform pre-charging on the bit line BL and the complementary bit line BLB.

[0072] However, in the above technical solution, in order to add the function of mismatch compensation, two additional devices, namely a fifteenth transistor M15 and a sixteenth transistor M16, are added, resulting in a relatively large area overhead of the sense amplifier.

[0073] Figure 4 and Figure 5 is a circuit schematic diagram of a sense amplifier provided in some embodiments of the present application. As Figure 4 and Figure 5 shown, some embodiments of the present application provide a sense amplifier, which includes: a seventh transistor M7, an eighth transistor M8, a first switch unit 110, a second switch unit 120, and a first equalization circuit 130.

[0074] A first end of the seventh transistor M7 is connected to the bit line BL, a control end of the seventh transistor M7 is connected to a first end of the first switch unit 110, a second end of the first switch unit 110 is connected to a first end of the eighth transistor M8, and a second end of the seventh transistor M7 receives a second power signal CS2.

[0075] A first end of the eighth transistor M8 is connected to the complementary bit line BLB, a control end of the eighth transistor M8 is connected to a second end of the second switch unit 120, a first end of the second switch unit 120 is connected to the first end of the seventh transistor M7, and a second end of the eighth transistor M8 receives the second power signal CS2.

[0076] The first switch unit 110 and the second switch unit 120 receive an isolation control signal ISO and conduct or cut off based on the isolation control signal ISO. An output end of the first equalization circuit 130 is connected to the control ends of the seventh transistor M7 and the eighth transistor M8, and is configured to output a third power signal VOC based on a first equalization signal.

[0077] Among them, the first switch unit 110 and the second switch unit 120 receive the isolation control signal ISO and turn on or off based on the isolation control signal ISO, so as to control whether the control end of the seventh transistor M7 is connected to the first end of the eighth transistor M8, and control whether the control end of the eighth transistor M8 is connected to the first end of the seventh transistor M7, thereby controlling whether the seventh transistor M7 and the eighth transistor M8 perform voltage difference amplification.

[0078] The output end of the first equalization circuit 130 is connected to the control ends of the seventh transistor M7 and the eighth transistor M8. The first equalization circuit 130 also receives a first equalization signal and is configured to output a third power supply signal VOC based on the first equalization signal. By controlling the voltage of the third power supply signal VOC output by the first equalization circuit 130 and the time when the first equalization circuit 130 outputs the third power supply signal VOC, and controlling the on or off time of the first switch unit 110 and the second switch unit 120, the bit line BL and the complementary bit line BLB are precharged to the second precharge voltage, and it is also used to form a compensation voltage on the bit line BL and the complementary bit line BLB. The compensation voltage is used to completely eliminate or partially eliminate the noise caused by the mismatch between the seventh transistor M7 and the eighth transistor M8.

[0079] In the above technical solution, the first switch unit 110 and the second switch unit 120 receive the isolation control signal ISO and turn on or off based on the isolation control signal ISO, so as to control whether the seventh transistor M7 and the eighth transistor M8 perform voltage difference amplification. By setting the first equalization circuit 130, the output end of the first equalization circuit 130 is connected to the control ends of the seventh transistor M7 and the eighth transistor M8, and by combining the control of the on or off of the first switch unit 110 and the second switch unit 120, the first equalization circuit 130 can precharge the bit line BL and the complementary bit line BLB to the second precharge voltage by controlling the voltage of the output third power supply signal VOC and the voltage of the second power supply signal when the first switch unit 110 and the second switch unit 120 are turned on. The first equalization circuit 130 can also form a compensation voltage on the bit line BL and the complementary bit line BLB by adjusting the voltage of the output third power supply signal VOC and the voltage of the second power supply signal when the first switch unit 110 and the second switch unit 120 are turned off. In this way, there is no need to additionally set transistors for offset to completely eliminate or partially eliminate signal control, reducing the number of transistors in the sense amplifier and reducing the chip area of the sense amplifier.

[0080] In some embodiments, such as Figure 4 and Figure 5As shown, the sense amplifier includes a first transistor M1 and a second transistor M2. The first end of the first transistor M1 receives a first power supply signal CS1. The second end of the first transistor M1 is connected to the first end of a seventh transistor M7. The control end of the first transistor M1 is connected to the second end of the second transistor M2. The first end of the second transistor M2 receives the first power supply signal CS1. The second end of the second transistor M2 is connected to the first end of an eighth transistor M8. The control end of the second transistor M2 is connected to the second end of the first transistor M1.

[0081] The first transistor M1 and the second transistor M2 perform voltage difference amplification under the drive of the first power supply signal CS1.

[0082] In some embodiments, as Figure 4 and Figure 5 shown, the first equalization circuit 130 includes a fifth transistor M5 and a sixth transistor M6. The first equalization signal includes a second equalization signal EQOC and a third equalization signal EQ.

[0083] The first end of the fifth transistor M5 is used to receive a third power supply signal VOC. The second end is connected to the control end of the seventh transistor M7. The control end is used to receive the second equalization signal EQOC. The first end of the sixth transistor M6 is connected to the control end of the seventh transistor M7. The second end of the sixth transistor M6 is connected to the control end of the eighth transistor M8. The control end of the sixth transistor M6 is used to receive the third equalization signal EQ.

[0084] The second equalization signal EQOC controls the fifth transistor M5 to conduct, so that the control end of the seventh transistor M7 receives the third power supply signal VOC. The third equalization signal EQ controls the sixth transistor M6 to conduct, so that the control ends of the seventh transistor M7 and the eighth transistor M8 are connected. The control end of the eighth transistor M8 receives the third power supply signal VOC, and combines to control the conduction or cut-off of the first switch unit 110 and the second switch unit 120. By setting the voltage of the third unit signal VOC and the voltage of the second power supply signal CS2, the bit line BL and the complementary bit line BLB can be pre-charged to a second pre-charge voltage in the pre-charge stage, and a compensation voltage can be formed on the bit line BL and the complementary bit line BLB in the offset cancellation stage. The compensation voltage is used to completely eliminate or partially eliminate the noise caused by the mismatch of the seventh transistor M7 and the eighth transistor M8. In this way, there is no need to additionally set transistors controlled by an offset complete elimination or partial elimination signal, reducing the number of transistors of the sense amplifier and reducing the chip area of the sense amplifier.

[0085] In some embodiments, the second equalization signal and the third equalization signal can be one equalization signal, which is generated by a control circuit. This can save signal lines and reduce the chip area. In another embodiment, the second equalization signal and the third equalization signal can be two equalization signals, which are independently generated but enabled simultaneously, improving control flexibility. In yet another embodiment, the second equalization signal and the third equalization signal can be two equalization signals that are independently generated and enabled at different times. For example, the third equalization signal is enabled after the second equalization signal. Thus, when the gate voltage of the eighth transistor M8 is greater than the gate voltage of the seventh transistor M7, by enabling the third equalization signal first, the voltage difference across the sixth transistor M6 can be reduced first, and then the gate-source voltage Vgs (the voltage difference between the gate and the source) of the fifth transistor M5 can be reduced. Since the driving ability of the fifth transistor M5 is related to the magnitude of the gate-source voltage Vgs, the greater the gate-source voltage Vgs, the stronger the driving ability and the greater the power consumption. Therefore, enabling the third equalization signal EQ first and then enabling the second equalization signal EQOC is beneficial to reducing the power consumption of the equalization circuit and is also beneficial to reducing the power consumption caused by the situation where the control terminal voltage of the seventh transistor M7 is first pulled up to a voltage higher than the pre-charge level and then drops due to the relatively strong driving ability of the fifth transistor M5.

[0086] In some embodiments, as Figure 4 shown, the first transistor M1 and the second transistor M2 are P-type transistors, and the seventh transistor M7 and the eighth transistor M8 are N-type transistors.

[0087] In some embodiments, as Figure 5 shown, the first transistor M1 and the second transistor M2 are N-type transistors, and the seventh transistor M7 and the eighth transistor M8 are P-type transistors.

[0088] In some embodiments, as Figure 4 and Figure 5 shown, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are all N-type transistors.

[0089] Some embodiments of the present application provide a control method for a sense amplifier. The control method includes the following steps:

[0090] S101. In the idle stage, the isolation control signal ISO controls the first switch unit 110 and the second switch unit 120 to conduct. The first equalization signal controls the first equalization circuit 130 to output the third power signal VOC. The voltage of the second power signal CS2 is the first pre-charge voltage, and the third power signal VOC is the second pre-charge voltage.

[0091] Among them, the output terminal of the first equalization circuit 130 is connected to the control terminals of the seventh transistor M7 and the eighth transistor M8. The first equalization signal controls the first equalization circuit 130 to output a third power signal VOC. The isolation control signal ISO controls the first switch unit 110 and the second switch unit 120 to conduct, so that the control terminal of the seventh transistor M7 is connected to the first end of the eighth transistor M8, and the control terminal of the eighth transistor M8 is connected to the first end of the seventh transistor M7, and controls the voltage of the second power signal CS2 to be a first pre-charge voltage, thus realizing pre-charging the voltages on the bit line BL and the complementary bit line BLB to a second pre-charge voltage.

[0092] The first pre-charge voltage and the second pre-charge voltage can be the same or different, and there is no limitation in this regard.

[0093] S102. In the offset cancellation stage, the isolation control signal ISO controls the first switch unit 110 and the second switch unit 120 to cut off. The first equalization signal controls the first equalization circuit 130 to output a third power signal VOC. The voltages of the second power signal CS2 and the third power signal VOC make the seventh transistor M7 and the eighth transistor M8 in a source follower mode.

[0094] Among them, the isolation control signal ISO controls the first switch unit 110 and the second switch unit 120 to cut off, so that the control terminal of the seventh transistor M7 is disconnected from the first end of the eighth transistor M8, and the control terminal of the eighth transistor M8 is disconnected from the first end of the seventh transistor M7. The first equalization signal controls the first equalization circuit 130 to output a third power signal VOC. The voltages of the second power signal CS2 and the third power signal VOC make the seventh transistor M7 and the eighth transistor M8 in a source follower mode, thus forming a compensation voltage on the bit line BL and the complementary bit line BLB (the first end of the seventh transistor M7 and the second end of the eighth transistor M8).

[0095] In the above technical solution, during the idle stage, the isolation control signal ISO controls the first switch unit 110 and the second switch unit 120 to conduct. The first equalization signal controls the first equalization circuit 130 to output the third power supply signal VOC. The voltage of the second power supply signal CS2 is the first pre-charging voltage, and the voltage of the third power supply signal VOC is the second pre-charging voltage, so as to pre-charge the bit line BL and the complementary bit line BLB to the second pre-charging voltage during the idle stage. During the offset cancellation stage, the isolation control signal ISO controls the first switch unit 110 and the second switch unit 120 to cut off. The first equalization signal controls the first equalization circuit 130 to output the third power supply signal VOC. The voltages of the second power supply signal CS2 and the third power supply signal VOC make the seventh transistor M7 and the eighth transistor M8 in the source follower mode, so that a compensation voltage can be formed on the bit line BL and the complementary bit line BLB by controlling the voltages of the third power supply signal VOC and the second power supply signal CS2.

[0096] In some embodiments, during the offset cancellation stage, if the first transistor M1 and the second transistor M2 are P-type transistors, and the seventh transistor M7 and the eighth transistor M8 are N-type transistors, the voltage of the second power supply signal is greater than the first pre-charging voltage, the voltage of the third power supply signal is greater than the second pre-charging voltage, and the voltage of the second power supply signal is greater than the voltage of the third power supply signal. The voltages of the second power supply signal CS2 and the third power supply signal VOC make the seventh transistor M7 and the eighth transistor M8 in the source follower mode, so that a compensation voltage is formed on the bit line BL and the complementary bit line BLB.

[0097] When the seventh transistor M7 and the eighth transistor M8 are N-type transistors and are in the source follower mode, if the control terminal voltage of the seventh transistor M7 and the eighth transistor M8 is Vx, that is, when the voltage of the third power supply signal is Vx, the first terminal of the seventh transistor M7 is Vx - Vt7, where Vt7 is the threshold voltage of the seventh transistor M7, and the first terminal of the eighth transistor M8 is Vx - Vt8, where Vt8 is the threshold voltage of the eighth transistor M8. Since the first terminal of the seventh transistor M7 is connected to the bit line and the first terminal of the eighth transistor M8 is connected to the complementary bit line, a compensation voltage VOS is formed on the bit line BL and the complementary bit line BLB.

[0098] In some embodiments, during the offset cancellation stage, if the first transistor and the second transistor are N-type transistors, the seventh transistor and the eighth transistor are P-type transistors, the voltage of the second power supply signal is less than the first pre-charging voltage, the voltages of the third power supply signal are both less than the first pre-charging voltage, and the voltage of the second power supply signal is less than the voltage of the third power supply signal. The voltages of the second power supply signal CS2 and the third power supply signal VOC make the seventh transistor M7 and the eighth transistor M8 in the source follower mode, and thus a compensation voltage is formed on the bit line BL and the complementary bit line BLB.

[0099] When the seventh transistor M7 and the eighth transistor M8 are P-type transistors and are in the source follower mode, if the control terminal voltages of the seventh transistor M7 and the eighth transistor M8 are Vx, that is, when the voltage of the third power supply signal is Vx, then the first terminal of the seventh transistor M7 is VX+Vt7, where Vt7 is the threshold voltage of the seventh transistor M7, and the first terminal of the eighth transistor M8 is Vx+Vt8, where Vt8 is the threshold voltage of the eighth transistor M8. Since the first terminal of the seventh transistor M7 is connected to the bit line and the first terminal of the eighth transistor M8 is connected to the complementary bit line, a compensation voltage VOS is formed on the bit line BL and the complementary bit line BLB in this way.

[0100] Here, taking the first transistor M1 and the second transistor M2 as P-type transistors and the seventh transistor M7 and the eighth transistor M8 as N-type transistors as an example, some embodiments of the present application provide a control method for a sense amplifier. The control method includes the following steps:

[0101] S201. In the idle stage, the first equalization signal controls the first equalization circuit 130 to output the third power supply signal VOC, the isolation control signal ISO controls the first switch unit 110 and the second switch unit 120 to conduct, the word line signal is at a low level, the voltage of the first power supply signal CS1 and the voltage of the second power supply signal CS2 are the first pre-charge voltage, and the third power supply signal VOC is the second pre-charge voltage. With such a setting, the voltages on the bit line BL and the complementary bit line BLB are maintained at the second pre-charge voltage.

[0102] S202. In the offset cancellation stage, the first equalization signal controls the first equalization circuit 130 to output the third power supply signal VOC, the isolation control signal ISO controls the first switch unit 110 and the second switch unit 120 to cut off, and the word line signal is at a low level. The voltage of the third power supply signal VOC is greater than the second pre-charge voltage, the voltage of the second power supply signal CS2 is greater than the first pre-charge voltage, and the voltage of the second power supply signal CS2 is greater than the voltage of the third power supply signal VOC. The voltages of the second power supply signal CS2 and the third power supply signal VOC make the seventh transistor M7 and the eighth transistor M8 in the source follower mode, and the seventh transistor M7 and the eighth transistor M8 are controlled to conduct through the third power supply signal VOC, so that the second power supply signal CS2 can charge the bit line BL or the complementary bit line BLB to form a compensation voltage on the bit line BL and the complementary bit line BLB. The charging process continues until the gate-source voltage Vgs of the seventh transistor M7 or the eighth transistor M8 is less than its corresponding threshold voltage. Among them, the voltage of the first power supply signal CS1 can be the first pre-charge voltage.

[0103] S203. During the charge sharing phase, the equalization signal controls the equalization circuit to stop providing the third power supply signal VOC, the isolation control signal ISO controls the first switch unit 110 and the second switch unit 120 to conduct, the voltages of the first power supply signal CS1 and the second power supply signal CS2 are the first pre-charge voltage, and the control word line signal is at a high level. With such settings, charge sharing occurs between the storage unit and the bit line BL, and a charge sharing voltage is formed on the bit line BL and the complementary bit line BLB.

[0104] Among them, during the charge sharing phase, the voltage of the third power supply signal VOC can continue to remain unchanged, that is, the voltage of the third power supply signal VOC is the same in the offset cancellation phase and the charge sharing phase. In other embodiments, the voltage of the third power supply signal VOC can also be restored to the second pre-charge voltage during the charge sharing phase.

[0105] S204. During the sense amplification phase, the first equalization signal controls the first equalization circuit 130 to stop providing the third power supply signal VOC, the isolation control signal ISO controls the first switch unit 110 and the second switch unit 120 to conduct, and the word line signal is at a high level. The voltage of the first power supply signal CS1 is the power supply voltage, and the voltage of the second power supply signal CS2 is the ground voltage. With such settings, the voltage difference between the bit line BL and the complementary bit line BLB is amplified.

[0106] Among them, during the sense amplification phase, the voltage of the third power supply signal VOC can continue to remain unchanged, that is, the voltage of the third power supply signal VOC is the same in the sense amplification phase, the offset cancellation phase, and the charge sharing phase. In other embodiments, the voltage of the third power supply signal VOC can be restored to the second pre-charge voltage during the sense amplification phase.

[0107] S205. During the pre-charge phase, the first equalization signal controls the first equalization circuit 130 to provide the third power supply signal VOC, the isolation control signal ISO controls the first switch unit 110 and the second switch unit 120 to conduct, the word line signal is at a low level, the voltages of the first power supply signal CS1 and the second power supply signal CS2 are the first pre-charge voltage, and the third power supply signal VOC is the second pre-charge voltage. With such settings, the voltages on the bit line BL and the complementary bit line BLB are pre-charged to the second pre-charge voltage.

[0108] In the above technical solution, through the above timing control method, the mismatch noise on the seventh transistor M7 and the eighth transistor M8 is completely eliminated or partially eliminated, and the data on the storage unit is accurately amplified. It should be noted that the above control method is also applicable to the case where there are only the seventh transistor M7 and the eighth transistor M8, and only the control parts corresponding to the first transistor M1, the second transistor M2, and the first power supply signal need to be ignored.

[0109] Here, taking the Figure 4 shown circuit structure as an example, the first transistor M1 and the second transistor M2 are P-type transistors, and the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are N-type transistors.

[0110] Figure 6 For Figure 4 the timing schematic diagram of the sense amplifier shown, as Figure 6 shown, some embodiments of the present application provide a control method for a sense amplifier. The control method includes the following steps:

[0111] S301. In the idle stage S1, the second equalization signal EQOC and the third equalization signal EQ are at a high level, and the fifth transistor M5 and the sixth transistor M6 are turned on. The isolation control signal ISO is at a high level, and the third transistor M3 and the fourth transistor M4 are turned on. The third power supply signal VOC is the second pre-charge voltage V2, the voltages of the first power supply signal CS1 and the second power supply signal CS2 are the first pre-charge voltage V1, and the word line signal WL is at a low level. In this way, the voltages on the bit line BL and the complementary bit line BLB are maintained at the second pre-charge voltage V2.

[0112] Among them, the first pre-charge voltage V1 and the second pre-charge voltage V2 may be the same or different.

[0113] S302. In the offset cancellation stage S2, the second equalization signal EQOC and the third equalization signal EQ are at a high level, and the fifth transistor M5 and the sixth transistor M6 are turned on. The isolation control signal ISO is at a low level, and the third transistor M3 and the fourth transistor M4 are turned off. The voltage of the third power supply signal VOC is greater than the second pre-charge voltage V2, the voltage of the second power supply signal CS2 is greater than the first pre-charge voltage V1, and the voltage of the second power supply signal CS2 is greater than the voltage of the third power supply signal VOC. The voltages of the second power supply signal CS2 and the third power supply signal VOC make the seventh transistor M7 and the eighth transistor M8 in a source follower mode. In this way, a compensation voltage is formed on the bit line BL and the complementary bit line BLB. Among them, the voltage of the first power supply signal CS1 is the first pre-charge voltage V1.

[0114] S303. In the charge sharing stage S3, the second equalization signal EQOC and the third equalization signal EQ are at a low level, the fifth transistor M5 and the sixth transistor M6 are turned off, the isolation control signal ISO is at a high level, the third transistor M3 and the fourth transistor M4 are turned on, the voltage of the third power supply signal VOC can continue to remain unchanged, the voltages of the first power supply signal CS1 and the second power supply signal CS2 are the first pre-charge voltage V1, and the word line signal WL is at a high level. In this way, a charge sharing voltage is formed on the bit line BL and the complementary bit line BLB.

[0115] S304. During the sense amplification stage S4, the second equalization signal EQOC and the third equalization signal EQ are at low level, and the fifth transistor M5 and the sixth transistor M6 are cut off. The isolation control signal ISO is at high level, and the third transistor M3 and the fourth transistor M4 are turned on. The voltage of the first power supply signal CS1 is the power supply voltage VCC, the voltage of the second power supply signal CS2 is the ground voltage VSS, the voltage of the third power supply signal VOC can continue to remain unchanged, and the word line signal WL is at high level, thus realizing the amplification of the voltage difference between the bit line BL and the complementary bit line BLB.

[0116] S305. During the pre-charge stage, the second equalization signal EQOC and the third equalization signal EQ are at high level, the fifth transistor M5 and the sixth transistor M6 are turned on, the isolation control signal ISO is at high level, the third transistor M3 and the fourth transistor M4 are turned on, the voltage of the second power supply signal CS2 is the first pre-charge voltage V1, the third power supply signal VOC is the second pre-charge voltage V2, and the word line signal is at high level, thus realizing the pre-charge of the voltages on the bit line BL and the complementary bit line BLB to the second pre-charge voltage V2.

[0117] In some embodiments, during the pre-charge stage, the third equalization signal EQ is at high level first, and the sixth transistor M6 is turned on. Subsequently, the first power supply signal CS1 and the second power supply signal CS2 are adjusted to the first pre-charge voltage, and then the second equalization signal EQOC is adjusted to high level, and the fifth transistor M5 is turned on.

[0118] In the above technical solution, through the above timing control method, the mismatch noise on the seventh transistor M7 and the eighth transistor M8 is completely eliminated or partially eliminated, and the data on the storage unit is accurately amplified.

[0119] Figure 7 For Figure 5 The timing schematic diagram of the shown sense amplifier is as Figure 7 shown. The control method when the first transistor M1 and the second transistor M2 in the sense amplifier are P-type transistors and the seventh transistor M7 and the eighth transistor M8 are N-type transistors is similar to the control method when the first transistor M1 and the second transistor M2 in the sense amplifier are N-type transistors and the seventh transistor M7 and the eighth transistor M8 are P-type transistors. The difference lies in:

[0120] When the values of the first pre-charge voltage V1 are different and the values of the second pre-charge voltage V2 are different, and the first transistor M1 and the second transistor M2 in the sense amplifier are P-type transistors, and the seventh transistor M7 and the eighth transistor M8 are N-type transistors, the first pre-charge voltage V1 and the second pre-charge voltage V2 can both be 0.38V. When the first transistor M1 and the second transistor M2 in the sense amplifier are N-type transistors, and the seventh transistor M7 and the eighth transistor M8 are P-type transistors, the first pre-charge voltage V1 and the second pre-charge voltage V2 can both be 0.6V.

[0121] In the offset cancellation stage, the first equalization signal controls the first equalization circuit 130 to output the third power supply signal VOC, the isolation control signal ISO controls the first switch unit 110 and the second switch unit 120 to be cut off, the voltage of the second power supply signal CS2 is less than the first pre-charge voltage V1, the voltage of the third power supply signal VOC is less than the second pre-charge voltage V2, and the voltage of the second power supply signal CS2 is less than the voltage of the third power supply signal VOC. The voltage of the second power supply signal CS2 and the voltage of the third power supply signal VOC make the seventh transistor M7 and the eighth transistor M8 in the source follower mode, so that a compensation voltage is formed on the bit line BL and the complementary bit line BLB.

[0122] In the sense amplification stage, the equalization signal controls the equalization circuit to stop providing the third power supply signal VOC, and the isolation control signal ISO controls the first switch unit 110 and the second switch unit 120 to be turned on. The voltage of the first power supply signal CS1 is the ground voltage, and the voltage of the second power supply signal CS2 is the power supply voltage. With such settings, the voltage difference between the bit line BL and the complementary bit line BLB is amplified.

[0123] In some embodiments, as Figure 8 and Figure 9 shown, the sense amplifier includes a first transistor M1 and a second transistor M2. The first end of the first transistor M1 receives the first power supply signal CS1, the control end of the first transistor M1 is connected to the control end of the seventh transistor M7, and the second end of the first transistor M1 is connected to the bit line BL. The first end of the second transistor M2 receives the first power supply signal CS1, the control end of the second transistor M2 is connected to the control end of the eighth transistor M8, and the second end of the second transistor M2 is connected to the complementary bit line BLB.

[0124] The output terminal of the first equalization circuit 130 is connected to the control terminals of the seventh transistor M7 and the eighth transistor M8, and the output terminal of the first equalization circuit 130 is connected to the control terminals of the first transistor M1 and the second transistor M2. The first equalization circuit 130 also receives a first equalization signal and is configured to output a third power supply signal VOC based on the first equalization signal. By controlling the voltage of the third power supply signal VOC output by the first equalization circuit 130 and the time of the third power supply signal VOC output by the first equalization circuit 130, a compensation voltage is formed on the bit line BL and the complementary bit line BLB. The compensation voltage is used to completely eliminate or partially eliminate the noise caused by the mismatch between the overall formed by the first transistor M1 and the second transistor M2 and the overall formed by the seventh transistor M7 and the eighth transistor M8.

[0125] The first switch unit 110 and the second switch unit 120 receive an isolation control signal ISO and turn on or off based on the isolation control signal ISO, so as to control whether the control terminal of the first transistor M1 is connected to the second terminal of the second transistor M2, and control whether the control terminal of the second transistor M2 is connected to the second terminal of the first transistor M1, thereby controlling whether the first transistor M1 and the second transistor M2 perform voltage difference amplification. The first switch unit 110 and the second switch unit 120 receive an isolation control signal ISO and turn on or off based on the isolation control signal ISO, so as to control whether the control terminal of the seventh transistor M7 is connected to the first terminal of the eighth transistor M8, and control whether the control terminal of the eighth transistor M8 is connected to the first terminal of the seventh transistor M7, thereby controlling whether the seventh transistor M7 and the eighth transistor M8 perform voltage difference amplification.

[0126] In the above technical solution, by setting the output terminal of the first equalization circuit 130 to be connected to the control terminals of the seventh transistor M7 and the eighth transistor M8, and the output terminal of the first equalization circuit 130 to be connected to the control terminals of the first transistor M1 and the second transistor M2, a compensation voltage is formed on the bit line BL and the complementary bit line BLB. The compensation voltage is used to completely eliminate or partially eliminate the noise caused by the mismatch between the overall formed by the first transistor M1 and the second transistor M2 and the overall formed by the seventh transistor M7 and the eighth transistor M8. In this way, there is no need to additionally set transistors for completely eliminating or partially eliminating signal control, reducing the number of transistors in the sense amplifier and reducing the chip area of the sense amplifier. And, compared with Figure 4 and Figure 5The shown sense amplifier structure can simultaneously completely eliminate or partially eliminate the noise caused by the mismatch between the first transistor M1 and the second transistor M2, and completely eliminate or partially eliminate the noise caused by the mismatch between the seventh transistor M7 and the eighth transistor M8, avoiding reintroducing additional noise caused by separately completely eliminating or partially eliminating the noise caused by the mismatch between the seventh transistor M7 and the eighth transistor M8, and improving the accuracy of data amplification of the sense amplifier.

[0127] For example, assume that the threshold voltage of the first transistor M1 is larger than that of the second transistor M2, and the threshold voltage of the seventh transistor M7 is larger than that of the eighth transistor M8. The threshold voltages of the second transistor M2 and the eighth transistor M8 belong to a preset level. At this time, the mismatch between the first transistor M1 and the second transistor M2, and the mismatch between the seventh transistor M7 and the eighth transistor M8 may partially or even completely offset, avoiding separately eliminating the mismatch between the first transistor M1 and the second transistor M2, or separately eliminating the mismatch between the seventh transistor M7 and the eighth transistor M8, which instead causes a mismatch between the overall first inverter composed of the first transistor M1 and the seventh transistor M7 and the overall second inverter composed of the second transistor M2 and the eighth transistor M8.

[0128] In some embodiments, as Figure 8 shown, the first transistor M1 and the second transistor M2 are P-type transistors, and the seventh transistor M7 and the eighth transistor M8 are N-type transistors.

[0129] In some embodiments, as Figure 9 shown, the first transistor M1 and the second transistor M2 are N-type transistors, and the seventh transistor M7 and the eighth transistor M8 are P-type transistors.

[0130] In some embodiments, as Figure 8 and Figure 9 shown, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are all N-type transistors.

[0131] Here, taking the structure of the sense amplifier shown in Figure 8 as an example, some embodiments of the present application provide a control method for a sense amplifier. The control method includes the following steps:

[0132] S401. In the idle stage, the isolation control signal ISO controls the first switch unit 110 and the second switch unit 120 to conduct. The first equalization signal controls the first equalization circuit 130 to output the third power supply signal VOC. The voltages of the first power supply signal CS1 and the second power supply signal CS2 are the first pre-charge voltages, and the third power supply signal VOC is the second pre-charge voltage.

[0133] Among them, the isolation control signal ISO controls the conduction of the first switch unit 110 and the second switch unit 120. The control terminal of the seventh transistor M7 is connected to the first terminal of the eighth transistor M8, the control terminal of the eighth transistor M8 is connected to the first terminal of the seventh transistor M7, the control terminal of the first transistor M1 is connected to the second terminal of the second transistor M2, and the control terminal of the second transistor M2 is connected to the second terminal of the first transistor M1. The output terminal of the first equalization circuit 130 is connected to the control terminals of the seventh transistor M7 and the eighth transistor M8. The first equalization signal controls the first equalization circuit 130 to output the third power supply signal VOC. At the same time, the voltages of the first power supply signal CS1 and the second power supply signal CS2 are the first pre-charge voltage, so as to pre-charge the voltages on the bit line BL and the complementary bit line BLB to the second pre-charge voltage.

[0134] The first pre-charge voltage and the second pre-charge voltage can be the same or different, and there is no limitation in this regard.

[0135] S402. In the offset cancellation stage, the isolation control signal ISO controls the first switch unit 110 and the second switch unit 120 to be turned off. The first equalization signal controls the first equalization circuit 130 to output the third power supply signal VOC. The voltages of the first power supply signal CS1 and the third power supply signal VOC make the first transistor M1 and the second transistor M2 in the source follower mode, and the voltages of the second power supply signal CS2 and the third power supply signal VOC make the seventh transistor M7 and the eighth transistor M8 in the source follower mode.

[0136] Among them, the isolation control signal ISO controls the first switch unit 110 and the second switch unit 120 to turn off, the control end of the seventh transistor M7 is disconnected from the first end of the eighth transistor M8, the control end of the eighth transistor M8 is disconnected from the first end of the seventh transistor M7, the first equalization signal controls the first equalization circuit 130 to output the third power supply signal VOC, and the voltages of the second power supply signal CS2 and the third power supply signal VOC make the seventh transistor M7 and the eighth transistor M8 in the source follower mode. The isolation control signal ISO controls the first switch unit 110 and the second switch unit 120 to turn off, the control end of the first transistor M1 is disconnected from the first end of the second transistor M2, the control end of the second transistor M2 is disconnected from the first end of the first transistor M1, and the voltages of the first power supply signal CS1 and the third power supply signal VOC make the first transistor M1 and the second transistor M2 in the source follower mode. In this way, the voltages of the first power supply signal CS1 and the second power supply signal CS2 can be controlled to charge and discharge the second ends of the first transistor M1 and the second transistor M2 by adjusting the voltage of the third power supply signal VOC, and then a compensation voltage is formed on the bit line BL and the complementary bit line BLB, completely eliminating or partially eliminating the noise caused by the mismatch between the whole formed by the first transistor M1 and the second transistor M2 and the whole formed by the seventh transistor M7 and the eighth transistor M8.

[0137] In the above technical solution, in the idle stage, the isolation control signal ISO controls the first switch unit 110 and the second switch unit 120 to turn on, the first equalization signal controls the first equalization circuit 130 to output the third power supply signal VOC, the voltages of the first power supply signal CS1 and the second power supply signal CS2 are the first pre-charge voltage, and the third power supply signal VOC is the second pre-charge voltage, so as to pre-charge the bit line BL and the complementary bit line BLB to the second pre-charge voltage in the idle stage. In the offset cancellation stage, the isolation control signal ISO controls the first switch unit 110 and the second switch unit 120 to turn off, the equalization signal controls the first equalization circuit 130 to output the third power supply signal VOC, the voltages of the first power supply signal CS1 and the third power supply signal VOC make the first transistor M1 and the second transistor M2 in the source follower mode, and the voltages of the second power supply signal CS2 and the third power supply signal VOC make the seventh transistor M7 and the eighth transistor M8 in the source follower mode. Since the third power supply signal VOC is connected to the control ends of the first transistor M1, the second transistor M2, the third transistor M7 and the eighth transistor M8 at the same time, and the first transistor M1 and the seventh transistor M7 jointly generate the compensation voltage on the bit line BL, and the second transistor M2 and the eighth transistor M8 jointly generate the compensation voltage on the complementary bit line BLB, therefore, the actually eliminated mismatch is the mismatch between the first inverter as a whole formed by the first transistor M1 and the seventh transistor M7 and the second inverter as a whole formed by the second transistor M2 and the eighth transistor M8.

[0138] In some embodiments, during the offset cancellation phase, when the first transistor M1 and the second transistor M2 are P-type transistors, the seventh transistor M7 and the eighth transistor M8 are N-type transistors, the voltage of the first power supply signal is less than the first pre-charge voltage, the voltage of the second power supply signal is greater than the first pre-charge voltage, the voltage of the third power supply signal is the second pre-charge voltage, the voltage of the first power supply signal is less than the voltage of the third power supply signal, and the voltage of the second power supply signal is greater than the voltage of the third power supply signal. The voltages of the first power supply signal CS1 and the third power supply signal VOC make the first transistor M1 and the second transistor M2 in the source follower mode, and the voltages of the second power supply signal CS2 and the third power supply signal VOC make the seventh transistor M7 and the eighth transistor M8 in the source follower mode, thus forming a compensation voltage on the bit line BL and the complementary bit line BLB.

[0139] Here, taking the first transistor M1 and the second transistor M2 as P-type transistors and the seventh transistor M7 and the eighth transistor M8 as N-type transistors as an example, some embodiments of the present application provide a control method for a sense amplifier. The control method includes the following steps:

[0140] S501. During the idle phase, the first equalization signal controls the first equalization circuit 130 to output the third power supply signal VOC, the isolation control signal ISO controls the first switch unit 110 and the second switch unit 120 to conduct, the control word line signal is at a low level, the voltages of the first power supply signal CS1 and the second power supply signal CS2 are the first pre-charge voltage, and the third power supply signal VOC is the second pre-charge voltage. With such a setting, the voltages on the bit line BL and the complementary bit line BLB are maintained at the second pre-charge voltage.

[0141] S502. During the offset cancellation phase, the first equalization signal controls the first equalization circuit 130 to output the third power supply signal VOC, the isolation control signal ISO controls the first switch unit 110 and the second switch unit 120 to cut off, and the control word line signal is at a low level. The voltage of the third power supply signal VOC is the second pre-charge voltage, the voltage of the first power supply signal CS1 is less than the first pre-charge voltage, the voltage of the second power supply signal CS2 is greater than the first pre-charge voltage, the voltage of the second power supply signal CS2 is greater than the voltage of the third power supply signal VOC, and the voltage of the first power supply signal CS1 is less than the voltage of the third power supply signal VOC. The voltages of the first power supply signal CS1 and the third power supply signal VOC make the first transistor M1 and the second transistor M2 in the source follower mode, and the voltages of the second power supply signal CS2 and the third power supply signal VOC make the seventh transistor M7 and the eighth transistor M8 in the source follower mode, thus forming a compensation voltage on the bit line BL and the complementary bit line BLB.

[0142] S503. During the charge sharing stage, the equalization signal controls the equalization circuit to stop providing the third power supply signal VOC, the isolation control signal ISO controls the first switch unit 110 and the second switch unit 120 to conduct, the voltage of the first power supply signal CS1 and the voltage of the second power supply signal CS2 are the first pre-charge voltage, the voltage of the third power supply signal VOC is the second pre-charge voltage, and the control word line signal is at a high level. With such settings, charge sharing occurs between the memory cell and the bit line BL, and a charge sharing voltage is formed on the bit line BL and the complementary bit line BLB.

[0143] S504. During the sense amplification stage, the first equalization signal controls the first equalization circuit 130 to stop providing the third power supply signal VOC, the isolation control signal ISO controls the first switch unit 110 and the second switch unit 120 to conduct. The voltage of the first power supply signal CS1 is the power supply voltage, the voltage of the second power supply signal CS2 is the ground voltage, and the voltage of the third power supply signal VOC is the second pre-charge voltage. With such settings, the voltage difference between the bit line BL and the complementary bit line BLB is amplified.

[0144] S505. During the pre-charge stage, the first equalization signal controls the first equalization circuit 130 to provide the third power supply signal VOC, the isolation control signal ISO controls the first switch unit 110 and the second switch unit 120 to conduct, the voltage of the first power supply signal CS1 and the voltage of the second power supply signal CS2 are the first pre-charge voltage, the third power supply signal VOC is the second pre-charge voltage, and the word line signal is at a low level. With such settings, the voltages on the bit line BL and the complementary bit line BLB are pre-charged to the first pre-charge voltage.

[0145] In the above technical solution, through the above timing control method, the noise caused by the mismatch between the whole formed by the first transistor M1 and the second transistor M2 and the whole formed by the seventh transistor M7 and the eighth transistor M8 is completely eliminated or partially eliminated, and the data on the memory cell is accurately amplified.

[0146] Here, taking Figure 8 the circuit structure shown as an example, where the first transistor M1 and the second transistor M2 are P-type transistors, and the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are N-type transistors.

[0147] Figure 10 For Figure 8 the timing schematic diagram of the sense amplifier shown, as Figure 10 shown, some embodiments of the present application provide a control method for a sense amplifier, and the control method includes the following steps:

[0148] S601. During the idle stage S1, the second equalization signal EQOC and the third equalization signal EQ are at high level, and the fifth transistor M5 and the sixth transistor M6 are turned on. The isolation control signal ISO is at high level, and the third transistor M3 and the fourth transistor M4 are turned on. The third power supply signal VOC is the second pre-charge voltage V2, the voltages of the first power supply signal CS1 and the second power supply signal CS2 are the first pre-charge voltage V1, and the word line signal WL is at low level, thus maintaining the voltages on the bit line BL and the complementary bit line BLB at the second pre-charge voltage V2.

[0149] S602. During the offset cancellation stage S2, the second equalization signal EQOC and the third equalization signal EQ are at high level, and the fifth transistor M5 and the sixth transistor M6 are turned on. The isolation control signal ISO is at low level, and the third transistor M3 and the fourth transistor M4 are turned off. The voltage of the first power supply signal CS1 is less than the first pre-charge voltage, the voltage of the second power supply signal CS2 is greater than the first pre-charge voltage, the voltage of the third power supply signal VOC is the second pre-charge voltage, the voltage of the second power supply signal CS2 is greater than the voltage of the third power supply signal VOC, and the voltage of the first power supply signal CS1 is less than the voltage of the third power supply signal VOC. The voltages of the first power supply signal CS1 and the third power supply signal VOC make the first transistor M1 and the second transistor M2 in the source follower mode, and the voltages of the second power supply signal CS2 and the third power supply signal VOC make the seventh transistor M7 and the eighth transistor M8 in the source follower mode, thus forming a compensation voltage on the bit line BL and the complementary bit line BLB.

[0150] S603. During the charge sharing stage S3, the second equalization signal EQOC and the third equalization signal EQ are at low level, the fifth transistor M5 and the sixth transistor M6 are turned off, the isolation control signal ISO is at high level, the third transistor M3 and the fourth transistor M4 are turned on, the voltage of the third power supply signal VOC remains unchanged, the voltages of the first power supply signal CS1 and the second power supply signal CS2 are the first pre-charge voltage V1, and the word line signal WL is at high level, thus forming a charge sharing voltage on the bit line BL and the complementary bit line BLB.

[0151] S604. During the sense amplification stage S4, the second equalization signal EQOC and the third equalization signal EQ are at low level, the fifth transistor M5 and the sixth transistor M6 are turned off. The isolation control signal ISO is at high level, the third transistor M3 and the fourth transistor M4 are turned on. The voltage of the first power supply signal CS1 is the power supply voltage VCC, the voltage of the second power supply signal CS2 is the ground voltage VSS, the voltage of the third power supply signal VOC remains unchanged, and the word line signal WL is at high level, thus realizing the amplification of the voltage difference between the bit line BL and the complementary bit line BLB.

[0152] S605. In the pre-charging stage S5, the second equalization signal EQOC and the third equalization signal EQ are at high level, the fifth transistor M5 and the sixth transistor M6 are turned on, the isolation control signal ISO is at high level, the third transistor M3 and the fourth transistor M4 are turned on, the voltage of the second power supply signal CS2 is the first pre-charging voltage V1, the third power supply signal VOC is the second pre-charging voltage V2, and the word line signal is at high level. In this way, the voltages on the bit line BL and the complementary bit line BLB are pre-charged to the second pre-charging voltage V2.

[0153] In some embodiments, in the pre-charging stage, the third equalization signal EQ is at high level first, and the sixth transistor M6 is turned on. Subsequently, the first power supply signal CS1 and the second power supply signal CS2 are at the first pre-charging voltage, and then the second equalization signal EQOC is at high level, and the fifth transistor M5 is turned on.

[0154] It can be understood that when performing the offset cancellation operation based on the Figure 4 and Figure 5 shown circuit, the seventh transistor and the eighth transistor can be either in the linear region or in the saturation region; when performing the offset cancellation operation based on the Figure 8 and Figure 9 shown circuit, the first transistor, the second transistor, the seventh transistor and the eighth transistor are all in the linear region.

[0155] In the above technical solution, through the above timing control method, the noise caused by the mismatch between the overall formed by the first transistor M1 and the second transistor M2 and the overall formed by the seventh transistor M7 and the eighth transistor M8 is completely eliminated or partially eliminated, and the data on the storage unit is accurately amplified.

[0156] Figure 9 The control method of the circuit structure shown in Figure 8 is similar to the control method of the circuit structure shown in

[0157] The difference is that in the offset cancellation stage S2, the voltage of the first power supply signal CS1 is greater than the first pre-charging voltage, the voltage of the second power supply signal CS2 is less than the first pre-charging voltage, the voltage of the third power supply signal VOC is the second pre-charging voltage, the voltage of the second power supply signal CS2 is less than the voltage of the third power supply signal VOC, and the voltage of the first power supply signal CS1 is greater than the voltage of the third power supply signal VOC. Those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include the common general knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present application are pointed out by the following claims.

[0158] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. A sense amplifier, characterized in that, Including: A seventh transistor, an eighth transistor, a first switching unit, a second switching unit, and a first equalization circuit; A first end of the seventh transistor is connected to a bit line, a control end of the seventh transistor is connected to a first end of the first switching unit, a second end of the first switching unit is connected to a first end of the eighth transistor, and a second end of the seventh transistor receives a second power signal; A first end of the eighth transistor is connected to a complementary bit line, a control end of the eighth transistor is connected to a second end of the second switching unit, a first end of the second switching unit is connected to a first end of the seventh transistor, and a second end of the eighth transistor receives the second power signal; The first switching unit and the second switching unit receive an isolation control signal and conduct or cut off based on the isolation control signal; An output end of the first equalization circuit is connected to a control end of the seventh transistor and a control end of the eighth transistor, and is configured to output a third power signal based on a first equalization signal.

2. The sense amplifier according to claim 1, characterized in that, The sense amplifier further includes: a first transistor and a second transistor; A first end of the first transistor receives a first power signal, a second end is connected to a first end of the seventh transistor, and a control end is connected to a second end of the second transistor; A first end of the second transistor receives the first power signal, a second end is connected to a first end of the eighth transistor, and a control end is connected to a second end of the first transistor.

3. The sense amplifier according to claim 1, wherein The sense amplifier further includes: a first transistor and a second transistor; A first end of the first transistor receives a first power signal, a control end of the first transistor is connected to a control end of the seventh transistor, and a second end of the first transistor is connected to a bit line; A first end of the second transistor receives the first power signal, a control end of the second transistor is connected to a control end of the eighth transistor, and a second end of the second transistor is connected to a complementary bit line.

4. The sense amplifier according to any one of claims 1 to 3, characterized in that The first equalization circuit includes a fifth transistor and a sixth transistor, and the first equalization signal includes a second equalization signal and a third equalization signal; A first end of the fifth transistor is configured to receive the third power signal, a second end is connected to a control end of the seventh transistor or a control end of the eighth transistor, and a control end is configured to receive the second equalization signal; A first end of the sixth transistor is connected to a control end of the seventh transistor, a second end of the sixth transistor is connected to a control end of the eighth transistor, and a control end of the sixth transistor is configured to receive the third equalization signal.

5. The sense amplifier according to claim 2, wherein The first transistor and the second transistor are P-type transistors, and the seventh transistor and the eighth transistor are N-type transistors; or, The first transistor and the second transistor are N-type transistors, and the seventh transistor and the eighth transistor are P-type transistors.

6. A control method for a sense amplifier, characterized in that The sense amplifier includes a seventh transistor, an eighth transistor, a first switching unit, a second switching unit, and a first equalization circuit; The first end of the seventh transistor is connected to the bit line. The control end of the seventh transistor is connected to the first end of the first switch unit. The second end of the first switch unit is connected to the first end of the eighth transistor. The second end of the seventh transistor receives a second power signal; The first end of the eighth transistor is connected to the complementary bit line. The control end of the eighth transistor is connected to the second end of the second switch unit. The first end of the second switch unit is connected to the first end of the seventh transistor. The second end of the eighth transistor receives the second power signal; The control ends of the first switch unit and the second switch unit receive an isolation control signal; The output end of the first equalization circuit is connected to the control ends of the seventh transistor and the eighth transistor. The control method includes: In the idle stage, the isolation control signal controls the first switch unit and the second switch unit to conduct. The first equalization signal controls the first equalization circuit to output a third power signal. The voltage of the second power signal is a first pre-charge voltage, and the third power signal is a second pre-charge voltage; In the offset cancellation stage, the isolation control signal controls the first switch unit and the second switch unit to turn off. The first equalization signal controls the first equalization circuit to output the third power signal. The voltages of the second power signal and the third power signal make the seventh transistor and the eighth transistor operate in a source follower mode.

7. The control method of the sense amplifier according to claim 6, characterized in that The sense amplifier further includes: a first transistor and a second transistor. The first end of the first transistor receives a first power signal. The second end is connected to the first end of the seventh transistor. The control end is connected to the second end of the second transistor. The first end of the second transistor receives the first power signal. The second end is connected to the first end of the eighth transistor. The control end is connected to the second end of the first transistor; In the offset cancellation stage, if the first transistor and the second transistor are P-type transistors, the seventh transistor and the eighth transistor are N-type transistors. The voltage of the second power signal is greater than the first pre-charge voltage. The voltage of the third power signal is greater than the second pre-charge voltage. The voltage of the second power signal is greater than the voltage of the third power signal.

8. The control method of the sense amplifier according to claim 6, characterized in that, The sense amplifier further includes: a first transistor and a second transistor. The first end of the first transistor receives a first power signal. The second end is connected to the first end of the seventh transistor. The control end is connected to the second end of the second transistor. The first end of the second transistor receives the first power signal. The second end is connected to the first end of the eighth transistor. The control end is connected to the second end of the first transistor; In the offset cancellation stage, if the first transistor and the second transistor are N-type transistors, the seventh transistor and the eighth transistor are P-type transistors. The voltage of the second power signal is less than the first pre-charge voltage. The voltage of the third power signal is less than the second pre-charge voltage. And the voltage of the second power signal is less than the voltage of the third power signal.

9. A control method for a sense amplifier, characterized in that, The sense amplifier includes a first transistor, a second transistor, a seventh transistor, an eighth transistor, a first switch unit, a second switch unit, and a first equalization circuit; A first end of the first transistor receives a first power signal, a control end of the first transistor is connected to a control end of the seventh transistor, and a second end of the first transistor is connected to a bit line; a first end of the second transistor receives the first power signal, a control end of the second transistor is connected to a control end of the eighth transistor, and a second end of the second transistor is connected to a complementary bit line; A first end of the seventh transistor is connected to the bit line, a control end of the seventh transistor is connected to a first end of the first switch unit, a second end of the first switch unit is connected to a first end of the eighth transistor, and a second end of the seventh transistor receives a second power signal; A first end of the eighth transistor is connected to the complementary bit line, a control end of the eighth transistor is connected to a second end of the second switch unit, a first end of the second switch unit is connected to a first end of the seventh transistor, and a second end of the eighth transistor receives the second power signal; A control end of the first switch unit and a control end of the second switch unit receive an isolation control signal; An output end of the first equalization circuit is connected to a control end of the seventh transistor and a control end of the eighth transistor, and the control method includes: In an idle stage, the isolation control signal controls the first switch unit and the second switch unit to conduct, a first equalization signal controls the first equalization circuit to output a third power signal, a voltage of the first power signal and a voltage of the second power signal are a first pre-charge voltage, and the third power signal is a second pre-charge voltage; In an offset cancellation stage, the isolation control signal controls the first switch unit and the second switch unit to turn off, the first equalization signal controls the first equalization circuit to output the third power signal, a voltage of the first power signal and a voltage of the third power signal make the first transistor and the second transistor in a source follower mode, and a voltage of the second power signal and a voltage of the third power signal make the seventh transistor and the eighth transistor in a source follower mode.

10. The control method according to claim 9, characterized in that The first transistor and the second transistor are P-type transistors, the seventh transistor and the eighth transistor are N-type transistors, and in the offset cancellation stage, a voltage of the first power signal is less than the first pre-charge voltage, a voltage of the second power signal is greater than the first pre-charge voltage, and a voltage of the third power signal is the second pre-charge voltage.

11. The control method according to claim 9, wherein The first equalization circuit includes a fifth transistor and a sixth transistor, and the first equalization signal includes a second equalization signal and a third equalization signal; A first end of the fifth transistor is used to receive the third power signal, a second end is connected to a control end of the seventh transistor or a control end of the eighth transistor, and a control end is used to receive the second equalization signal; The first end of the sixth transistor is connected to the control end of the seventh transistor, the second end of the sixth transistor is connected to the control end of the eighth transistor, and the control end of the sixth transistor is configured to receive the third equalization signal. The method further includes: In a pre-charging stage, the third equalization signal is initially at a high level, and the sixth transistor is turned on; subsequently, the first power supply signal and the second power supply signal are at a first pre-charging voltage, and then the second equalization signal is at a high level, and the fifth transistor is turned on.

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