RRAM testing method, device and system

Abstract

The present application provides a method, device and system for testing RRAM. The RRAM testing method is used for a test board; the test board includes a memristor array arranged in rows B and columns W, and an FPGA. The method includes: a host computer displays a parameter setting interface for the current test of the RRAM; the parameter setting interface displays the parameters to be input; receiving parameter data input for the parameters to be input and the address of the memristor to be tested input by the user, generating and sending a host computer instruction; the memristor to be tested is one or more memristors in the memristor array; the FPGA generates a drive signal for the address of the memristor to be tested according to the register protocol agreed upon by the host computer and the FPGA and the host computer instruction received; the drive signal is sent to the memristor to be tested; the return signal of the memristor to be tested is received, and the current test is performed.

Description

Technical Field

[0001] The present application relates to the field of RRAM (Resistive Random-Access Memory, also known as memristor) testing technology, and in particular to a RRAM testing method, device, and system. Background Art

[0002] Existing memristors are resistors with a "memory" function. Their resistance changes with the magnitude and direction of the current flowing through them, and remains unchanged after power is removed. This property is highly similar to the plasticity of synapses between biological neurons. By changing their resistance, memristors simulate the dynamic adjustment and storage of synaptic weights, directly influencing the capacity of neural networks through their physical properties, such as the number of neurons, synaptic size, and complexity. The weights of the simulated synapses correspond to the weights of the neural network. Therefore, existing technology requires a chip with a capacity of 1024M. To handle larger neural networks, multiple chips must be spliced ​​and integrated. This requires more chips and occupies a large space. Summary of the Invention

[0003] The present application provides a method, device, and system for testing an RRAM.

[0004] The present application provides a RRAM testing method for a test board; the test board includes a memristor array arranged in B rows and W columns, and an FPGA. The RRAM testing method includes:

[0005] The host computer displays a parameter setting interface for the current test of the RRAM; the parameter setting interface displays parameters to be input; receives parameter data input for the parameters to be input and an address of the memristor to be tested input by the user, generates and sends a host computer instruction; the memristor to be tested is one or more memristors in the memristor array;

[0006] The FPGA generates a drive signal for the address of the memristor to be tested according to a register protocol agreed upon by the host computer and the FPGA and based on instructions received from the host computer; sends the drive signal to the memristor to be tested; and receives a return signal from the memristor to be tested to perform the current test.

[0007] Furthermore, the parameter setting interface displays a chart corresponding to a switch array arranged in rows B and columns W, corresponding to each memristor in the memristor array; the switch array is used to control the switches of the memristor to be tested;

[0008] The receiving of parameter data input for the parameters to be input and the address of the memristor to be tested input by the user includes: if the user's operation in the chart is detected, determining the address of the memristor to be tested; wherein, while the address of the memristor to be tested is framed in the chart, it is automatically filled in the memristor input position in the parameter setting interface.

[0009] Furthermore, if the user operation in the chart is detected, the address of the memristor to be tested is determined, including: detecting a first position selected by the user in the chart as the starting position of a framed area of ​​the memristor to be tested; detecting that the user moves along the selected first position and stops at a second position, as the ending position of the selected area of ​​the memristor to be tested; and using the address of the memristor in the framed area between the starting position and the end position as the address of the memristor to be tested;

[0010] or,

[0011] The positions selected one by one by the user in the chart are detected as the addresses of the memristor to be tested.

[0012] Furthermore, the parameter setting interface displays a chart corresponding to a switch array arranged in rows B and columns W, corresponding to each memristor in the memristor array; the switch array is used to control the switches of the memristor to be tested;

[0013] The receiving of parameter data input for the parameters to be input and the address of the memristor to be tested input by the user includes: obtaining the address of the memristor to be tested from a local location; automatically importing and filling the address of the memristor to be tested at the memristor input position in the parameter setting interface, and correspondingly displaying it in the selection area in the chart.

[0014] Furthermore, the parameter setting interface displays a chart arranged in rows B and columns W, corresponding to each memristor in the memristor array;

[0015] The receiving of parameter data for the parameters to be input and the address of the memristor to be tested input by the user includes: receiving the address of the memristor to be tested input by the user in the memristor input position in the parameter setting interface; the address of the memristor to be tested corresponds to the selection area displayed in the chart.

[0016] Furthermore, the host computer displays a parameter setting interface for the current test of the RRAM, including: the host computer receives a current test selected from a plurality of memristor tests and displays a parameter setting interface for the current test; the plurality of memristor tests include two or more of a read-write test, a weight modulation test, an identification test, and a multi-function test integrated in the host computer.

[0017] Furthermore, after the current test is performed, the method also includes: when receiving a parameter setting interface for switching to the next test as the parameter setting interface for this test, if it is detected that there is saved data from the previous test, the saved data that can be used in this test is extracted and automatically filled in the parameter setting interface for this test; wherein, the saved data refers to the data saved at the end of the previous test; the saved data used in this test includes the address of the memristor to be tested.

[0018] Furthermore, when the current test includes an identification test, the receiving of parameter data for the parameters to be input includes: receiving a batch import instruction; importing parameter data from the local according to the batch import instruction; the parameter data includes transverse pressure parameter data and pulse width parameter data.

[0019] Furthermore, the test board includes a control circuit; the control circuit includes a digital-to-analog converter DAC chip and an analog-to-digital converter ADC chip; the control circuit generates a drive signal for the address of the memristor to be tested according to the register protocol agreed upon by the host computer and the FPGA and based on the received host computer instruction; the drive signal is given to the memristor to be tested; the return signal of the memristor to be tested is received, and the current test is performed, including: generating arbitrary voltage data of the word line WL control line required by the user according to the host computer instruction; the arbitrary voltage data includes any voltage value or any voltage curve, and is given to the WL pin of the RRAM chip by driving the DAC chip; and generating bit line BL voltage data required by the user according to the host computer instruction; the voltage data includes a voltage value or a voltage curve, and is given to the BL pin and / or source line SL pin of the RRAM chip by driving the DAC chip and a switch; generating the voltage data of the BL pin and / or SL pin required by the user according to the host computer instruction, and reading back the current value by driving the switch and the ADC chip.

[0020] The present application provides a RRAM testing method, which is applied to a host computer in the RRAM testing method as described above, including: a parameter setting interface displaying the current RRAM test; the parameter setting interface displays parameters to be input;

[0021] Receive parameter data input for the parameter to be input and the address of the memristor to be tested input by the user, generate and send a host computer instruction; the memristor to be tested is one or more memristors in the memristor array arranged in B rows and W columns in the test board, so that the FPGA generates a drive signal for the address of the memristor to be tested according to the register protocol agreed upon by the host computer and the FPGA and based on the received host computer instruction; the drive signal is sent to the memristor to be tested; and a return signal from the memristor to be tested is received to perform the current test.

[0022] The present application provides an RRAM testing device for implementing the RRAM testing method as described above, wherein the RRAM testing device comprises: a parameter setting interface for displaying the current RRAM test; parameters to be input displayed on the parameter setting interface;

[0023] Receive parameter data input for the parameter to be input and the address of the memristor to be tested input by the user, generate and send a host computer instruction; the memristor to be tested is one or more memristors in the memristor array arranged in B rows and W columns in the test board, so that the FPGA generates a drive signal for the address of the memristor to be tested according to the register protocol agreed upon by the host computer and the FPGA and based on the received host computer instruction; the drive signal is sent to the memristor to be tested; and a return signal from the memristor to be tested is received to perform the current test.

[0024] The present application provides a RRAM test system, comprising: a test board including a memristor array arranged in B rows and W columns;

[0025] A host computer, configured to display a parameter setting interface for the current test of the RRAM; the parameter setting interface displays parameters to be input; receive parameter data input for the parameters to be input and an address of a memristor to be tested input by a user, and generate and send a host computer instruction; the memristor to be tested is one or more memristors in the memristor array;

[0026] The FPGA is configured to generate a drive signal for the address of the memristor to be tested according to a register protocol agreed upon by the host computer and the FPGA and based on instructions received from the host computer; transmit the drive signal to the memristor to be tested; and receive a return signal from the memristor to be tested to perform a current test.

[0027] Furthermore, the FPGA driver in the FPGA includes a processing system PS end and a programmable logic PL end connected to the PS end. The PS end is connected to the host computer and is used for the PS end to communicate with the host computer and store instructions in registers. Each module in the PL drives the corresponding hardware module by reading data in the RRAM.

[0028] Furthermore, the FPGA driver includes a programmable logic (PL) terminal, which is connected to the host computer and is used for the PL terminal to communicate with the host computer, the register to store instructions, and each module in the PL to drive the corresponding hardware module by reading data in the RRAM.

[0029] Furthermore, the FPGA driver in the FPGA includes a processing system PS end and a programmable logic PL end connected to the PS end. The host computer is also used to convert the input parameters into hexadecimal instructions according to the register protocol and transmit them to the PS end of the FPGA through the network port; the PS end stores the data in the RRAM and waits for the PL end to read it; the PL end reads the data stored in the RRAM by the PS end and returns the data to the host computer; after reading the data, the PL end drives the corresponding DAC chip and ADC chip according to the FPGA agreed register protocol contained in the host computer instruction, and stores the FPGA agreed register protocol in the RRAM array.

[0030] Furthermore, the memristor array has a memory function; the memory function is used to indicate that after the conductance value of the memristor array is successfully set, it will not be lost during a power outage; the FPGA is used to convert the image input by the user into a voltage signal, apply it to the target end of the memristor array, and obtain the current value read by the target end; the current value is used to reflect the calculation result; the calculation result is transmitted to the host computer or drives the braking device to respond.

[0031] The present application provides a computer-readable storage medium having a program stored thereon. When the program is executed by a processor, the method described in any one of the above items is implemented.

[0032] The present application provides a computer program product, comprising a computer program / instruction, which implements any of the above methods when executed by a processor.

[0033] In some embodiments, the RRAM testing method of the present application controls a host computer, an FPGA, and a test board comprising a memristor array arranged in rows B and columns W. The FPGA, in accordance with a register protocol agreed upon between the host computer and the FPGA and based on instructions received from the host computer, generates a drive signal for the address of the memristor to be tested; transmits the drive signal to the memristor to be tested; and receives a return signal from the memristor to perform the current test. Because the memristor array includes multiple memristors and has a large capacity, it can handle larger-scale neural networks. Furthermore, the memristor array is integrated into the test board, occupying less space. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1aA schematic structural diagram of an RRAM testing system used in the RRAM testing method provided in an embodiment of the present application;

[0035] Figure 1b for Figure 1a A schematic diagram of the specific structure of the RRAM test system shown;

[0036] Figure 1c for Figure 1a A schematic diagram of a preset memristor array in the RRAM test system is shown;

[0037] Figure 2 1 is a flow chart of a RRAM testing method provided in an embodiment of the present application;

[0038] Figure 3 Shown Figure 2 A schematic diagram of a host computer display identification test of the RRAM test method shown;

[0039] Figure 4 Shown Figure 2 The upper computer of the RRAM test method shown is a schematic diagram showing a read and write test;

[0040] Figure 5 Shown Figure 2 A schematic diagram of a host computer display weight modulation test of the RRAM test method shown;

[0041] Figure 6 Shown Figure 2 The upper computer of the RRAM test method shown is a schematic diagram showing a multi-function test;

[0042] Figure 7a Shown Figure 2 The logic flow chart of the read and write test in the RRAM test method shown;

[0043] Figure 7b Shown Figure 2 A logic flow chart of weight modulation in the RRAM test method shown;

[0044] Figure 7c Shown Figure 2 A logic flow chart of the identification test in the RRAM test method shown;

[0045] Figure 7d Shown Figure 2 A logic flow chart of a multi-function test in the RRAM test method shown;

[0046] Figure 8 Shown Figure 2 A schematic diagram of pulses displayed by a host computer in the RRAM testing method shown;

[0047] Figure 9a Shown Figure 2 The change of control voltage during the enhanced linear scan process in the RRAM testing method is shown;

[0048] Figure 9b Shown Figure 2 The RRAM test method shown suppresses the change of the control voltage during the linear scan process;

[0049] Figure 10 FIG2 is a flow chart showing the application of the RRAM testing method provided in an embodiment of the present application to a host computer;

[0050] Figure 11 Shown is a schematic diagram of the structure of the host computer provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with one or more embodiments of this specification. Rather, they are merely examples of apparatuses and methods consistent with certain aspects of one or more embodiments of this specification, as detailed in the appended claims.

[0052] It should be noted that in other embodiments, the steps of the corresponding method are not necessarily performed in the order shown and described in this specification. In some other embodiments, the method may include more or fewer steps than those described in this specification. In addition, a single step described in this specification may be broken down into multiple steps for description in other embodiments, and multiple steps described in this specification may be combined into a single step for description in other embodiments.

[0053] To address the aforementioned technical issues of a large number of chips and a large space footprint, an embodiment of the present application provides a method for testing RRAM, controlling a host computer, an FPGA (Field-Programmable Gate Array), and a test board comprising a memristor array arranged in B rows and W columns. The FPGA generates a drive signal for the address of the memristor to be tested based on instructions received from the host computer, in accordance with the register protocol agreed upon between the host computer and the FPGA. The drive signal is then transmitted to the memristor to be tested, and a return signal from the memristor to be tested is received to perform the current test. Because the memristor array (also known as an RRAM array) includes multiple memristors and has a large capacity, it can handle larger-scale neural networks. Furthermore, the memristor array is integrated into the test board, occupying less space.

[0054] Figure 1a A schematic structural diagram of an RRAM testing system applied to the RRAM testing method provided in an embodiment of the present application. Figure 1b for Figure 1a A schematic diagram of the specific structure of the RRAM test system is shown.

[0055] like Figure 1a As shown, the RRAM test system used in the RRAM test method may include but is not limited to a host computer and a test board. The test board includes an FPGA and a control circuit.

[0056] The test board includes a memristor array (also called a non-volatile memory array) arranged in B rows and W columns, and the memristor array of the test board is tested. B represents the row number, W represents the column number, and B and W are both greater than or equal to 1. For example, B rows can be 32 rows. W columns can be 32 columns. 32 rows and 32 columns are 1kb. Of course, B and W can also be greater than an integer multiple of 32. For example, B is 32. 4, W is 32 4 refers to 4kb, which is equivalent to four arrays spliced ​​together and selected by a chip select signal. Of course, the size of B and W depends on the design scale of the chip, and can also be 1 megabyte (M).

[0057] The input address of the memristor changes during user use. With the development of integrated circuits, mobile communications, and the Internet of Things, the demand for non-volatile memory is shifting increasingly toward high capacity, low power consumption, high density, and low cost. Metal oxide resistive switching devices (MORSDs) are a new type of non-volatile memory with great application potential. Their typical structure is a metal electrode-oxide-metal electrode. Under the influence of an external electric field, the non-volatile memory can reversibly switch between high and low resistance states, and these high and low resistance states remain even after the electric field is removed.

[0058] Continue as Figure 1b As shown, the control circuit may include, but is not limited to, a digital-to-analog conversion chip connected to the RRAM chip, an amplifier circuit, a clock generation chip, and a switching circuit. The switching circuit may include a switch matrix. The control circuit can be used in a series of memristor AI chips (with address select lines and WL (Word Line), BL (Bit Line), and SL (Source Line) read / write lines).

[0059] The FPGA transmits the hexadecimal code 8000, along with the chip's operating mode configuration, to the DAC chip. The DAC chip converts digital data used by the FPGA into analog data used by the hardware circuits, generating a corresponding voltage that is connected to the amplifier circuit as input. Because the DAC chip only has conversion capabilities, the resulting voltage and current are very small. Therefore, the amplifier circuit amplifies the voltage and current transmitted by the DAC chip and then supplies them to a specific terminal on the RRAM chip. The clock generation chip generates a high-precision clock for all chips, controlling the rhythm of all signals. Because the RRAM chip requires a high-precision clock (pulse width of 10ns), the ADC clock is calculated to be as high as 800MHz, requiring a separate clock generation chip. Furthermore, the switch circuit switches the chip connected to a specific terminal on the RRAM chip to control disconnected WL, BL, and SL devices, such as switching between read and write modes.

[0060] Figure 1c for Figure 1a Schematic diagram of a preset memristor array in an RRAM test system.

[0061] like Figure 1c As shown in the figure, a memristor and transistor integrated circuit multiplies the linear weight coefficient column in the linear velocity parameter matrix by the matrix consisting of each input variable, with the memristor array with j = 0 serving as the reference column. BL is the bit line of the memristor array, which controls the input voltage, and WL is the external control signal of the memristor array.

[0062] Based on this, continue as Figure 1a 、 Figure 1b and Figure 1c As shown, the host computer communicates with the FPGA via a fixed communication protocol, which may include but is not limited to TCP (Transmission Control Protocol) and / or UDP (User Datagram Protocol). The host computer's front-end interface is developed using Vue (pronounced / vjuː / , similar to view), a JavaScript framework for building user interfaces based on standard HTML, CSS, and JavaScript. It provides a declarative, component-based programming model for efficient user interface development, and the back-end is developed using Go (also known as Golang, an open-source programming language). The host computer's main functional interface includes four parts: read-write testing, weight modulation, recognition testing, and multi-function testing.

[0063] Each functional host computer implements the following tests through the following operating logic:

[0064] Read and write test: Supports single-device FORMING, SET, and RESET (restoring a system or state to the initial or default state) operations. Specifically, the voltage, pulse width, and number of pulses of BL, SL, and WL can be set, and the readback current data can be displayed and saved. Among them, the FORMING process refers to the process of RRAM jumping from the initial high-resistance state to the low-resistance state for the first time. Conversely, RRAM in the low-resistance state can be converted to the high-resistance state after applying a certain voltage stimulus. The process of jumping from the low-resistance state to the high-resistance state is called RESET. RRAM that enters the high-resistance state after the RESET process can also be converted to the low-resistance state by applying voltage stimulus. This process is different from the first high-resistance state to low-resistance state jump called the SET process.

[0065] Weight Modulation: While other pulse parameters remain unchanged, one parameter (WL, BL, SL voltage values, pulse width, or number of pulses) is increased or decreased by a certain amount. If the current resistance is smaller than the target resistance, the parameter value is changed and a SET cycle is performed; otherwise, the parameter value is changed and a RESET cycle is performed. If the target resistance value is not reached within the tolerance range after exceeding the modulation count, the modulation fails; otherwise, the modulation succeeds.

[0066] The gate voltage modulation in the weight modulation mentioned above means that while other pulse parameters remain unchanged, the RESET and SET gate voltages (SET gate voltage is the key) can be increased or decreased by a certain amount. If the current resistance is smaller than the target resistance, the RESET cycle is performed with increasing gate voltage; otherwise, the SET cycle is performed with increasing gate voltage.

[0067] Amplitude modulation in weight modulation means that while other pulse parameters remain unchanged, the BL and SL voltages of RESET and SET can be increased or decreased by a certain amount. If the current resistance is smaller than the target resistance, a RESET cycle is performed with the SL voltage increasing, and the BL voltage is 0V. Otherwise, a SET cycle is performed with the BL voltage increasing, and the SL voltage is 0V.

[0068] Pulse-width modulation in weighted modulation means that while other pulse parameters remain constant, the RESET and SET pulse widths can be increased or decreased in specific steps. If the current resistance is smaller than the target resistance, a RESET cycle with increasing pulse widths is performed, and the BL voltage is 0V. Otherwise, a SET cycle with increasing pulse widths is performed, and the SL voltage is 0V.

[0069] Pulse modulation in weight modulation means that the SET and RESET parameters remain unchanged during the cyclic modulation process, and only the number of SET and RESET pulses applied changes. If the current resistance value is smaller than the target resistance value, the RESET cycle is performed, and the BL voltage is 0V; otherwise, the SET cycle is performed, and the SL voltage is 0V.

[0070] Identification testing essentially involves simultaneously opening multiple rows and columns of devices to perform matrix multiplication and addition operations. The software interface allows you to control which rows and columns are open, allowing you to batch import 32 BL or SL voltage vectors. Current readings from the 32 BL or SL terminals are displayed as a bar graph, and the current data can be saved, with a selectable storage path.

[0071] Multifunctional tests include hold test, DC cycle test and yield test:

[0072] Retention testing involves performing read operations at intervals with identical pulse parameters for each read operation, saving the resistance data and observing device retention. A DC cycling test is essentially a pulsed operation, requiring a single device to undergo a RESET cycle with increasing SL voltage, followed by a RESET cycle with decreasing SL voltage, followed by a SET cycle with increasing BL voltage, and finally a SET cycle with decreasing BL voltage. This cycle is called a single cycle. The current change during RESET and SET cycles is measured from the SL terminal. The number of cycles can be set, as can the SET and RESET parameters. Yield testing measures the percentage of fully formed arrays that can successfully undergo SET and RESET cycles.

[0073] Continue as Figure 1a 、 Figure 1b and Figure 1c As shown in the figure, FPGA development is divided into two parts: PS (Processing System) and PL (Programmable Logic).

[0074] The PS side implements the communication with the host computer and the register storage instruction function. Each module in the PL side drives the corresponding hardware module by reading the data in the RRAM:

[0075] The WL control line voltage configuration module generates any voltage value or voltage curve required by the user for the WL control line according to the host computer instructions, and provides it to the WL pin of the RRAM chip by driving the DAC (Digital-to-Analog Converter) chip.

[0076] The BL / SL write voltage control module generates the user's required BL voltage value or voltage curve according to the host computer's instructions, and provides it to the BL / SL pin of the RRAM chip by driving the high-speed DAC chip and switch. Here, " / " represents "and / or".

[0077] The BL / SL voltage reader module generates the user's desired BL / SL voltage value or arbitrary voltage curve according to host computer instructions. It then reads back the current value by driving a switch and a high-speed ADC (Analog-to-Digital Converter) chip. It also requires the cooperation of a switch module to turn off switches on unused lines to reduce crosstalk between lines.

[0078] This article encapsulates the low-level control logic through the host computer to facilitate high-level development and expansion.

[0079] Figure 2 FIG2 is a flow chart of a RRAM testing method provided in an embodiment of the present application.

[0080] like Figure 2 As shown, the RRAM testing method is used for a test board; the test board includes a memristor array arranged in B rows and W columns, and may include but is not limited to the following steps 110 to 120:

[0081] Step 110: The host computer displays a parameter setting interface for the current RRAM test; the parameter setting interface displays the parameters to be input; receives parameter data for the parameters to be input and the address of the memristor to be tested input by the user; generates and sends a host computer command; the memristor to be tested is one or more memristors in the memristor array. Faulty memristors may not be displayed.

[0082] In this article, when the current test is a test, the parameter setting interface of this current test is directly displayed by default.

[0083] Figure 3 Shown Figure 2 A schematic diagram of a host computer display identification test of an RRAM testing method is shown.

[0084] like Figure 3 As shown, the test list may include multiple tests, including the current test such as identification test 111. The current test is also such as read-write test 112, which can be seen as follows Figure 4 As shown, the current test, for example, the weight test 113 can be seen as follows Figure 5 As shown, the current test, for example, multi-function test 114, can be seen as follows Figure 6 As shown. The options of multiple tests are displayed. By clicking on the options of each test, the options of the clicked test are switched. The options include the options of each test, such as the options of the read and write test, the options of the weight modulation, the options of the identification test or the options of the multi-function test. Figures 3 to 5 Only one option for "Multi-function Test" is indicated as an example. Figure 6Only one option, "Read and Write Test", is indicated as an example.

[0085] In step 120 , the FPGA generates a drive signal for the address of the memristor to be tested according to the register protocol agreed upon by the host computer and the FPGA and based on the host computer instruction received; sends the drive signal to the memristor to be tested; receives a return signal from the memristor to be tested, and performs the current test.

[0086] It should be noted that the register protocol (see Table 1 below) is the core of the communication between the host computer and the FPGA. By defining the format, rules, and timing of data exchange, it ensures that the two can interact efficiently and reliably.

[0087] like Figure 3 As shown, Figure 3 Select the option corresponding to the test category: Each test page displays four test categories: read and write test, weight modulation, identification test, and multi-function test. Test categories are displayed in tab format. When you first enter the test page, there is no data under each test category; the data of each test category is independent. Switching test categories will retain the data under each test category; only when the user clicks to close the device test page will the data be cleared the next time you open it. Figure 3 Device number 14 is in a normal state. As a user programming interface, the user's desired RRAM array address and conductance value can be sent to the FPGA according to the register protocol agreed upon between the host computer and the FPGA. Register instructions are formatted as 64-bit hexadecimal numbers, as shown in Table 1 below. These instructions include a 16-bit fixed instruction header (55d5), a 1-bit read / write bit (0 for writing to the FPGA register and 1 for reading back data), a 15-bit register address, and 32-bit register data. See Table 1 for register instruction information.

[0088] Table 1 Register instruction information

[0089]

[0090] In Table 1, the register instruction information includes fixed bits, register addresses, and data bits. The register information is in hexadecimal format, with the fixed bits being 55aa, the register address being 000C, and the remaining bits (000000001) being data bits. The FPGA design in this article specifies this register information.

[0091] Based on this, the above register protocol can have the following functions:

[0092] (1) Data Communication: The register protocol defines how data is exchanged between the FPGA and the host computer through registers. The host computer can access the FPGA's internal registers through specific addresses and write control commands or data; the FPGA can read or modify data through registers and return it to the host computer.

[0093] (2) Control and Configuration: The register protocol allows the host computer to control the behavior of the FPGA by writing to the FPGA registers. For example, the host computer can start or stop a module inside the FPGA, change the processing mode, or change the signal processing method by setting certain bits in the register.

[0094] (3) Status feedback: FPGA can report its current status, operation results or processing progress to the host computer by reading certain registers. In this way, the host computer can understand the working status of the FPGA in a timely manner and make corresponding processing. The register protocol between the host computer and FPGA instructions is shown in Table 2:

[0095] Table 2 Register protocol between host computer and FPGA instructions

[0096]

[0097] Next, it should be noted that the above-mentioned step 120 may include but is not limited to: generating an arbitrary voltage value or an arbitrary voltage curve of the word line WL control line required by the user according to the host computer instruction, and providing it to the WL pin of the RRAM chip by driving the digital-to-analog converter DAC chip; and generating a bit line BL voltage value or a voltage curve required by the user according to the host computer instruction, and providing it to the BL pin and / or source line SL pin of the RRAM chip by driving the DAC chip and a switch; generating the BL and / or SL voltage value or an arbitrary voltage curve required by the user according to the host computer instruction, and reading back the current value by driving the switch and the analog-to-digital converter ADC chip.

[0098] Continue as Figure 3 As shown, the parameter setting interface displays a chart corresponding to the switch array arranged in rows B and columns W, corresponding to each memristor in the memristor array. The chart corresponding to the switch array is pre-associated with the memristor array, so the switch array can be used to control the memristor to be tested. In this way, this article establishes a method for controlling each memristor in advance and integrates a chart 13 of the switch array corresponding to each memristor on the host computer. In this way, by selecting a switch in the switch array of the chart, each memristor can be controlled accordingly. Of course, one memristor can be selected at a time, or multiple memristors can be selected, depending on the actual situation and is not limited here.

[0099] Based on this, combined Figure 4 As shown, in step 110, if a user operation is detected in the chart, the address of the memristor to be tested is determined. When the address of the memristor to be tested is selected in the chart, it is automatically filled in the memristor input position 21 in the parameter setting interface. In this way, parameter data for the parameters to be input and the address of the memristor to be tested entered by the user can be received.

[0100] If the user's operation in the chart is detected, the address of the memristor to be tested may be determined by at least one of the following methods:

[0101] In one optional method, the first position selected by the user on the chart is detected as the starting position of the framed area for the memristors to be tested; the user's movement along the selected first position and stopping at the second position is detected as the ending position of the selected area for the memristors to be tested; and the addresses of the memristors within the framed area between the starting position and the ending position are used as the addresses of the memristors to be tested. For example, after the user clicks on the first position and then drags the mouse or the selection box to the second position, the framed area is obtained, and the addresses of the memristors within the framed area are used as the addresses of the memristors to be tested, so that after the parameters of the current test are set, these memristors to be tested can be turned on.

[0102] The “first” in the “first position” and the “second” in the “second position” are used to distinguish any two different positions of the switch array in the diagram, so as to facilitate the one-time determination of the memristor to be tested.

[0103] In the second alternative, the user's selected positions on the chart are detected and used as the addresses of the memristors to be tested. For example, the user clicks on the chart one by one, and the clicked positions are recorded as the addresses of the memristors to be tested. This allows the user to set parameters and then turn on these memristors to test.

[0104] Of course, the above selection method may include but is not limited to selecting adjacent ones one by one or selecting at any interval, so that the user can select the memristors to be tested one by one according to his or her own wishes.

[0105] Figure 4 Shown Figure 2 A schematic diagram of a host computer displaying a read and write test of an RRAM test method is shown.

[0106] like Figure 4 As shown, in the third optional method, the first step is to obtain the address of the memristor to be tested from the local. The second step is to automatically import and fill the address of the memristor to be tested into the memristor input position 21 in the parameter setting interface, and correspondingly display the selected area in the chart. Among them, the memristor input position 21 is Figure 4 Select coordinates as shown.

[0107] In a fourth optional method, the address of the memristor to be tested is received by the user in the memristor input position 21 in the parameter setting interface; the address of the memristor to be tested corresponds to the selection area displayed in the chart. In this way, the memristor to be tested can be directly input according to the user's needs, thereby meeting the user's needs.

[0108] When any memristor fails, the switch array in the corresponding diagram displays a fault indicator, which is different from the indicator indicating a normal memristor. The fault indicator is used to indicate a memristor failure. The normal indicator is used to indicate a normal memristor. Of course, the fault indicator and the normal indicator can be distinguished by color, text, etc., respectively, and this is not limited here. For example, the color of the indicator indicating a normal memristor is colorless in the diagram of the switch array. The color of the indicator indicating a memristor failure is gray. For another example, the character "f" (short for fault) is used to indicate a fault in the memristor.

[0109] Based on this, in a fifth optional method, the first position selected by the user on the chart is detected as the starting position of the framed area for the memristors to be tested; the user's movement along the selected first position to the second position is detected as the ending position of the selected area for the memristors to be tested; the switch array corresponding to the fault identifier in the addresses of the memristors in the framed area between the starting and ending positions is automatically deleted, and the addresses of the memristors in the framed area between the starting and ending positions after deletion are used as the addresses of the memristors to be tested. In this way, abnormal memristors can be eliminated and normal memristors can be batch tested.

[0110] Figure 5 Shown Figure 2 A schematic diagram of a host computer display weight modulation test of the RRAM test method is shown. Figure 6 Shown Figure 2 A schematic diagram of a host computer displaying a multi-function test of an RRAM test method is shown.

[0111] Combine Figures 2 to 4 ,as well as Figure 5 and Figure 6 As shown, the upper computer in the above step 110 displays the parameter setting interface of the current test of the RRAM in the following manner: the upper computer receives the current test selected from the multiple memristor tests and displays the parameter setting interface of the current test; the multiple memristor tests include two or more of the read and write tests, weight modulation, identification tests, and multi-function tests integrated in the upper computer.

[0112] As an embodiment, after performing the current test, the method may also include but is not limited to: when receiving a parameter setting interface for switching to the next test, which serves as the parameter setting interface for this test, if it is detected that there is saved data from the previous test, the saved data that can be used in this test is extracted and automatically filled in the parameter setting interface for this test; wherein, the saved data refers to the data saved at the end of the previous test; the saved data used in this test includes the address of the memristor to be tested.

[0113] It should be noted that detecting the existence of saved data from the previous test may include but is not limited to the following examples:

[0114] Example 1: receiving a user's instruction to save the address of the memristor to be tested that is currently being tested.

[0115] Example 2: receiving an instruction to save the default settings.

[0116] In the embodiment of the present application, the next test can be performed on the address of the same memristor to be tested, thereby realizing test data sharing without the need for the user to re-enter the test data.

[0117] Continue to see Figure 3 In the illustrated embodiment, the current test includes an identification test, wherein receiving parameter data for parameters to be input includes: receiving a batch import instruction; and importing the parameter data from a local computer according to the batch import instruction; the parameter data includes lateral pressure parameter data and pulse width parameter data. Thus, importing the parameter data from a local computer reduces user input operations and improves user efficiency.

[0118] In another embodiment, before the host computer displays the parameter setting interface of the current test of the RRAM, the method further includes: displaying a login interface of the current test of the RRAM; receiving login information input by the user for the login interface; verifying that the login information is passed, and the host computer displays the parameter setting interface of the current test of the RRAM.

[0119] In an embodiment of the present application, receiving an RRAM experimental deployment requirement input by a user on a host computer may include the following steps:

[0120] Step 1: The user maps the parameters of a network model, such as a fuzzy control algorithm or neural network algorithm (BNN, SNN, RNN, CNN, etc.), into a set of conductance values ​​within the RRAM conductance range according to a specific ratio and specifies the corresponding BL, SL, and WL voltage values. These values ​​are entered on the host computer, which then pre-processes the instructions and sends them to the FPGA. The DoReadTest processing logic checks whether the parameters are compliant. If not, an error is considered. If so, a message is sent to the client in an asynchronous loop. Operations are logged asynchronously, with the client performing the relevant operations and the server storing the data. In this way, the host computer acts as the server and the FPGA as the client. The stored parameters can be any data transmitted through the network port, such as the FPGA device number, the voltage value sent to the FPGA, the current value read back, and so on.

[0121] After the FPGA and hardware respond to the instructions and perform related operations, the host computer makes the next judgment based on the returned instructions and the test type selected by the user. This part is implemented by the back-end part of the host computer. The logical flow of the read and write test is as follows: Figure 7a The logic flow of weight modulation is as follows: Figure 7b , identify the logical flow of the test such as Figure 7c And the logic flow chart of multi-function test is as follows Figure 7d shown.

[0122] Referring to Kirchhoff's current law, according to the quantized voltage values ​​of each input variable, input the preset memristor array to obtain the current value of each column To determine the linear velocity output matrix as an example, as follows: ,in, Indicates the conductance value of each memristor in the array opened by the host computer, is the conductance value of each memristor in the reference column, Indicates the line, represents the integers from 0 to λ traversing one side, The value of is from 0 to λ, where λ represents the number of input variables. Represents a column, The product of the quantized conductance value of each linear weight coefficient in the j-th row of the linear velocity parameter matrix implemented by the memristor array and the quantized voltage value of each input variable, that is, the current value output by the j-th column, It is the voltage value corresponding to the input variable Vi obtained through the preset voltage quantization ratio.

[0123] The host computer user selects the identification test and enters as needed The host computer sends the parameters to the FPGA via the network UDP (User Datagram Protocol) according to the register protocol shown in Table 1. The register instruction consists of the following parts: 16-bit fixed instruction header hex55d5 + 1-bit read / write flag (0: read, 1: write) + 15-bit register address + 32-bit register data. After the host computer waits for the hardware response, it reads back The current value is displayed.

[0124] Step 2: After receiving the host computer instruction, the PS side of the FPGA writes it into the RRAM, and the PL side configures each module by reading the data in the RRAM.

[0125] like Figure 1b For example, the WL control line voltage configuration module corresponds to the AD5532 chip in the driver hardware circuit. It first initializes and configures the AD5532 using the SPI (Serial Peripheral Interface) protocol, then continuously sends voltage levels to the chip pins according to the data in the register and the counter's ticks. The BL / SL write voltage control module corresponds to the AD (Analog Devices) 9148 chip in the driver hardware circuit (this chip is a high-speed DAC chip and requires the FPGA to pre-program the driver for the AD9516 clock module. This patent uses a 100MHz configuration, resulting in a chip with 1ns control accuracy). It then continuously sends voltage levels to the chip pins according to the data in the register and the counter's ticks. The read voltage control configuration module corresponds to the LTM511 chip in the driver hardware circuit. An innovative feature of this module is its ability to automatically determine whether the data read back by the chip is correct, then perform a preliminary averaging of multiple reads and transmit the data to the host computer. The specific logic is as follows:

[0126] The FPGA first configures the ADC chip in test mode, reads the signals from the ADC chip's 16 pins, and compares them with the pattern specified in the chip's configuration. If the comparison is correct 1024 times, the current value and clock are considered accurate. The FPGA then switches to normal mode to read the current. Current averaging accumulates the four current readings, shifts the result left by 2 bits (dividing by 4), and writes it to a register for retrieval by the host computer.

[0127] The row and column selection module automatically turns on the corresponding switch according to the row and column given by the host computer. The signal transmission of all modules in step 2 is as follows Figure 1a 、 Figure 1b and Figure 1c As shown, in the cfg_main frame.

[0128] Step 3: FPGA transmits data to the host computer through the network port controlled by the phy (Physical Layer Chip) chip, and the host computer displays it. The pulse diagram is as follows Figure 8 The signals on the hardware circuit can be detected using an oscilloscope or a voltmeter.

[0129] Other embodiments of this application, such as implementation of write verification logic: Figure 9a The control voltage is varied for the enhanced linear scan process. Figure 9b To suppress the change of control voltage during the linear scan process. Figure 9a As shown, Vgs is the voltage difference between WL and SL, and Vbs is the voltage difference between BL and SL. Figure 9a It means that the SL voltage remains unchanged, the BL voltage remains unchanged, the WL voltage is increased, and the SET operation with increasing voltage is performed until the target conductance value is reached. Figure 9b As shown, a complete RESET is performed each time, followed by a SET, until the target conductance value is reached.

[0130] Generally, before performing write verification, the host computer first determines whether the device is within the target conductance value. If it is, the process ends. The target conductance range depends on the user-input parameters. For example, if the user enters: target conductance value is 100uS (target resistance value is 10kΩ, resistance and conductance values ​​are inversely proportional), and the tolerance range is: 1%, then the target conductance range is: 99.00uS to 101.00uS.

[0131] In this regard, the memristor is determined to have reached the target conductivity range. If so, it is considered successful and the process ends. If not, the SET or REST operation is continued until the maximum number of attempts is reached without success, at which point the process ends.

[0132] Specifically, the scanning process corresponding to SET is to apply a SET voltage to the memristor, then record the current write count n and the read conductance value to determine whether the read conductance value reaches the target conductivity value range. If so, the write is successful. If not, the voltage is increased or decreased, and the SET scanning is continued and the write count n+1 is updated until the maximum write count, i.e., N cycles, is reached. If the read conductance value does not reach the target conductivity value range, the write fails.

[0133] The RESET scan process involves applying a RESET voltage to the memristor followed by a SET voltage, alternating between RESET and SET voltages. The scan then records the current write count n and the read conductance value to determine whether the read conductance value falls within the target range. If so, the write is successful. If not, the voltage is increased or decreased, and the RESET scan is repeated, updating the write count n+1 until the maximum number of writes, or N cycles, is reached. If the read conductance value does not fall within the target range, the write fails. Each SET or RESET scan control curve represents one cycle. If the target value is still not reached after N cycles, the RRAM device is considered unable to reach the target conductance value.

[0134] Based on the same inventive concept as the above method, the embodiment of the present application also provides a RRAM testing method, such as Figure 10 As shown, the host computer used in the above RRAM test method may include but is not limited to the following steps 210 to 220:

[0135] Step 210 : Displaying a parameter setting interface for the current RRAM test; the parameter setting interface displays parameters to be input.

[0136] Step 220, receiving parameter data for the input parameters and the address of the memristor to be tested input by the user, generating and sending a host computer instruction; the memristor to be tested is one or more memristors in the memristor array arranged in B rows and W columns in the test board, so that the FPGA generates a drive signal for the address of the memristor to be tested according to the register protocol agreed upon by the host computer and the FPGA and the received host computer instruction; the drive signal is sent to the memristor to be tested; and a return signal of the memristor to be tested is received to perform the current test.

[0137] Based on the same inventive concept as the above method, an embodiment of the present application further provides an RRAM testing device, which is used to implement the above RRAM testing method. The RRAM testing device includes:

[0138] A display module is used to display the parameter setting interface of the current RRAM test; the parameter setting interface displays the parameters to be input;

[0139] The processing module is used to receive parameter data input for the parameters to be input and the address of the memristor to be tested input by the user, generate and send a host computer instruction; the memristor to be tested is one or more memristors in the memristor array arranged in B rows and W columns on the test board, so that the FPGA generates a drive signal for the address of the memristor to be tested according to the register protocol agreed upon by the host computer and the FPGA and the received host computer instruction; send the drive signal to the memristor to be tested; receive a return signal from the memristor to be tested, and perform the current test.

[0140] As an embodiment, the above-mentioned device also includes: a detection module, which is used to, after the current test is performed, when a parameter setting interface for switching to the next test is received as the parameter setting interface for this test, if it is detected that there is saved data in the previous test, extract the saved data that can be used in this test and automatically fill it in the parameter setting interface of this test; wherein, the saved data refers to the data saved at the end of the previous test; the saved data used in this test includes the address of the memristor to be tested.

[0141] Based on the same inventive concept as the above method, the embodiment of the present application further provides an RRAM test system which may include but is not limited to a test board, a host computer and an FPGA; wherein,

[0142] A test board, containing a memristor array arranged in B rows and W columns;

[0143] The host computer is used to display the parameter setting interface of the current test of the RRAM; the parameter setting interface displays the parameters to be input; receive parameter data input for the parameters to be input and the address of the memristor to be tested input by the user, generate and send the host computer command; the memristor to be tested is one or more memristors in the memristor array;

[0144] The FPGA is used to generate a drive signal for the address of the memristor to be tested according to the register protocol agreed upon by the host computer and the FPGA and based on the instructions received from the host computer; send the drive signal to the memristor to be tested; and receive a return signal from the memristor to perform the current test.

[0145] As an embodiment, the FPGA driver in the FPGA includes a processing system PS end and a programmable logic PL end connected to the PS end. The PS end is connected to the host computer and is used for communication between the PS end and the host computer and for register storage instructions. Each module in the PL drives the corresponding hardware module by reading data in the RRAM.

[0146] The FPGA multiplication and accumulation method of the related art involves a large number of multiplication and addition operations, which require a certain amount of logic resources in the FPGA. In particular, when the data bit width of the operation is large, the required resources will increase significantly.

[0147] In this embodiment, the user input sets the model weights, which are then quantized into memristor conductance values. The memristors at the corresponding coordinates are modulated to the corresponding conductance values. In this step, the host computer provides a visual representation of the correspondence between the memristors and the coordinates, allowing the user to select them.

[0148] As an example, the host computer converts the user input information into hexadecimal instructions according to the register protocol and transmits it to the PS side of the FPGA through the network port (for example: 55aa 0050 0000 0001). The PS side stores the data in RRAM and waits for the PL side to read it. Similarly, the data sent back to the host computer is also stored by the PL side in RRAM and waits for the PS side to read it, realizing data exchange between different clock domains. The data transmission protocol is AXI (Advanced eXtensible Interface) protocol (such as Figure 1b After receiving the data, the PL drives the corresponding DAC and ADC chips according to the information contained in the instruction (refer to the register protocol instruction table), and then stores the information in the RRAM array, without the need for additional storage space.

[0149] As an example, once the conductance value is successfully set, it will not be lost after the hardware device is powered off. When in use, the memristor array is activated upon power-up, converting the user's input image into a voltage signal and applying it to the target end of the memristor array, such as the BL / SL end. The current value read at the SL / BL end reflects the calculation result, which can then be transmitted to the host computer or the driving and braking device for response. This is used in scenarios such as low-power and fast-response edge computing. Driving and braking devices include traffic light recognition, robotic arm control, and robot navigation.

[0150] For example, FPGA development is divided into two parts: PS and PL. The PS side implements the communication with the host computer and the register storage instruction function. The PS side block diagram is as follows Figure 5As shown in the figure, after receiving the instruction, the host computer performs preliminary analysis. If it is a write instruction, the data is written to the RRAM according to the corresponding register address. If it is a read instruction, the data is retrieved from the register and transmitted to the host computer via Ethernet. Each module on the PL side drives the corresponding hardware module by reading the data in the RRAM: the WL control line voltage configuration module generates the user's desired WL control line voltage value or voltage curve according to the host computer instruction, and drives the DAC chip to the WL pin of the RRAM chip. The BL / SL write voltage control module generates the user's desired BL voltage value or voltage curve according to the host computer instruction, and drives the high-speed DAC chip and switch to the BL / SL pin of the RRAM chip. The SL / SL read voltage module generates the user's desired BL / SL voltage value or voltage curve according to the host computer instruction, and reads the current value by driving the switch and high-speed ADC chip. The switch module also cooperates to turn off the switch on unused lines to reduce crosstalk between lines.

[0151] In the embodiments of the present application, each module in PL is easy to transplant and expand.

[0152] As an example, the FPGA driver includes a programmable logic (PL) terminal, which is connected to a host computer. This terminal is used for communication between the PL and the host computer, registers for storing instructions, and each module in the PL drives the corresponding hardware module by reading data from RRAM. Thus, even without the PS terminal, using the PL terminal directly can achieve communication between the host computer and the FPGA.

[0153] The implementation process of the functions and effects of each module / sub-module / unit in the above-mentioned device and system is specifically described in the implementation process of the corresponding steps in the above-mentioned method, and the same technical effects can be achieved, so it will not be repeated here.

[0154] Specifically, the host computer may be a desktop computer, a portable computer, or a PDA (Personal Digital Assistant), etc. Any host computer that can implement the embodiments of the present application falls within the scope of protection of the present application and is not limited thereto.

[0155] Figure 11 Shown is a structural diagram of the host computer 50 provided in an embodiment of the present application.

[0156] like Figure 11 As shown, the host computer 50 includes one or more processors 51 for implementing the RRAM testing method as applied to the host computer.

[0157] In some embodiments, the host computer 50 may include a storage medium 59. For example, the computer-readable storage medium may store a program that can be called by the processor 51, and may include a non-volatile storage medium. In some embodiments, the host computer 50 may include a memory 58 and an interface 57. In some embodiments, the host computer 50 may also include other hardware depending on the actual application.

[0158] The computer-readable storage medium of the embodiment of the present application stores a program thereon, and when the program is executed by the processor 51, it is used to implement the RRAM testing method described above.

[0159] The present application provides a computer program product, comprising a computer program / instruction, which implements any of the above methods when executed by a processor.

[0160] The present application also provides a computer program, which is stored in a computer-readable storage medium, for example, Figure 11 The computer program is stored in a storage medium 59, and when the processor executes the computer program, the processor 51 is prompted to perform the method described above.

[0161] This application may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to magnetic disk storage, CD-ROMs, optical storage, etc.) containing program code. Computer-readable storage media include both permanent and non-permanent, removable and non-removable media, and may implement information storage using any method or technology. The information may be computer-readable instructions, data structures, program modules, or other data. Examples of computer-readable storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible by a computing device.

[0162] The above description is only a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this specification should be included in the scope of protection of this specification.

Claims

1. A method for testing RRAM, characterized in that: A test board for a memristor array arranged in rows B and columns W, and an FPGA, wherein the FPGA driver includes a PS terminal and a PL terminal; the PS terminal is used to communicate with a host computer and store instructions in a register; each module of the PL drives the corresponding hardware module by reading data in the RRAM; the host computer communicates with the FPGA via a fixed communication protocol; the fixed communication protocol includes TCP and / or UDP; the front-end interface of the host computer is developed using Vue, and the back-end is developed using the Go language; the host computer serves as a server, and the method includes: The host computer displays a login interface for the current test of the RRAM; receives login information input by the user for the login interface; verifies that the login information is passed, receives the current test selected from a plurality of memristor tests, and displays a parameter setting interface for the current test of the RRAM; the parameter setting interface displays parameters to be input; the parameter setting interface displays a chart corresponding to switches for controlling the memristors to be tested arranged in rows B and columns W, corresponding to each memristor in the memristor array; the first position selected by the user in the chart is detected as the starting position of a framed area for the memristor to be tested; the user is detected to move along the selected first position and drag to a second position and stop, which is used as the end position of the framed area; the address of the memristor in the framed area is used as the address of the memristor to be tested; while the address of the memristor to be tested is framed in the chart, the memristor input position in the parameter setting interface is automatically filled in, and a host computer instruction is generated and sent; the memristors to be tested are multiple memristors in the memristor array; The FPGA generates a drive signal for the address of the memristor to be tested according to a register protocol agreed upon by the host computer and the FPGA and a command received from the host computer; transmits the drive signal to the memristor to be tested; receives a return signal from the memristor to be tested, and performs a current test; When receiving the parameter setting interface for switching from the current test to the next test, which is used as the parameter setting interface for this test, if it is detected that there is saved data from the previous test, the saved data that can be used in this test is extracted and automatically filled in the parameter setting interface for this test; wherein, the saved data refers to the data saved at the end of the previous test; the saved data used in this test includes the address of the memristor to be tested.

2. The RRAM testing method according to claim 1, wherein: The parameter setting interface displays a chart corresponding to the switch array arranged in rows B and columns W, corresponding to each memristor in the memristor array; the switch array is used to control the switches of the memristor to be tested; Receiving parameter data input for the parameter to be input and an address of the memristor to be tested input by a user, comprising: Obtaining the address of the memristor to be tested from a local device; The address of the memristor to be tested is automatically imported and filled in the memristor input position in the parameter setting interface, and is correspondingly displayed in the selection area in the chart.

3. The RRAM testing method according to claim 1, wherein: The parameter setting interface is arranged in a chart with B rows and W columns, corresponding to each memristor in the memristor array; Receiving parameter data input for the parameter to be input and an address of the memristor to be tested input by a user, comprising: receiving an address of a memristor to be tested input by a user in a memristor input position in the parameter setting interface; The address of the memristor to be tested corresponds to the selected area displayed in the chart.

4. The RRAM testing method according to any one of claims 1 to 3, wherein: The multiple memristor tests include two or more of a read-write test, a weight modulation test, an identification test, and a multi-function test integrated in the host computer.

5. The RRAM testing method according to any one of claims 1 to 2, wherein: When the current test includes an identification test, the receiving of parameter data for the parameters to be input includes: receiving a batch import instruction; importing parameter data from the local according to the batch import instruction; the parameter data includes transverse pressure parameter data and pulse width parameter data.

6. The RRAM testing method according to any one of claims 1 to 2, wherein: The test board includes a control circuit; the control circuit includes a digital-to-analog converter DAC chip and an analog-to-digital converter ADC chip; generating a drive signal for the address of the memristor to be tested according to a register protocol agreed upon by the host computer and the FPGA and receiving an instruction from the host computer; Sending the driving signal to the memristor to be tested; Receiving a return signal of the memristor to be tested and performing a current test, including: Generate arbitrary voltage data of the word line WL control line required by the user according to the host computer instruction; the arbitrary voltage data includes an arbitrary voltage value or an arbitrary voltage curve, and is given to the WL pin of the RRAM chip by driving the DAC chip; Furthermore, the bit line BL voltage data required by the user is generated according to the host computer instruction; the voltage data includes a voltage value or a voltage curve, which is provided to the BL pin and / or the source line SL pin of the RRAM chip by driving the DAC chip and the switch; The voltage data of the BL pin and / or the SL pin required by the user is generated according to the host computer instruction, and the current value is read back by driving the switch and the ADC chip.

7. A method for testing RRAM, characterized in that: A host computer used in the RRAM testing method according to any one of claims 1 to 6 comprises: Displaying a login interface for the current RRAM test; receiving login information input by a user on the login interface; verifying that the login information is passed, receiving a current test selected from a plurality of memristor tests, and displaying a parameter setting interface for the current RRAM test; the parameter setting interface displays parameters to be input; the parameter setting interface displays a chart corresponding to switches for controlling the memristors to be tested arranged in rows B and columns W, corresponding to each memristor in the memristor array; The first position selected by the user in the chart is detected as the starting position of the frame selection area of ​​the memristor to be tested; the user is detected to move along the selected first position and drag to the second position and stop, which is used as the end position of the frame selection area; the address of the memristor in the framed area is used as the address of the memristor to be tested; when the address of the memristor to be tested is framed in the chart, the memristor input position in the parameter setting interface is automatically filled in, and a host computer instruction is generated and sent; the memristor to be tested is a plurality of memristors in the memristor array arranged in rows B and columns W in the test board, so that the FPGA is configured to operate according to the host computer and the FPGA. The device comprises an agreed register protocol, a drive signal for the address of the memristor to be tested, and a control signal receiving an instruction from the host computer; the drive signal is sent to the memristor to be tested; the return signal of the memristor to be tested is received, and the current test is performed; when the parameter setting interface for the current test is switched to the next test, the parameter setting interface for the current test is used as the parameter setting interface for the current test; if it is detected that there is saved data in the previous test, the saved data that can be used in the current test is extracted and automatically filled in the parameter setting interface for the current test; wherein the saved data refers to the data saved at the end of the previous test; the saved data used in the current test includes the address of the memristor to be tested; Among them, the FPGA driver of the FPGA includes a PS end and a PL end; the PS end is used to communicate with the host computer and store instructions in registers; each module of the PL drives the corresponding hardware module by reading data in the RRAM; the host computer communicates with the FPGA through a fixed communication protocol; the fixed communication protocol includes TCP and / or UDP, the front-end interface of the host computer is developed in Vue, and the back-end is developed in Go language, and the host computer serves as the server end.

8. A RRAM testing device, characterized in that: For implementing the RRAM testing method according to claim 7, the RRAM testing device comprises: Displaying a login interface for the current RRAM test; receiving login information input by a user on the login interface; verifying that the login information is passed, receiving a current test selected from a plurality of memristor tests, and displaying a parameter setting interface for the current RRAM test; the parameter setting interface displays parameters to be input; the parameter setting interface displays a chart corresponding to switches for controlling the memristors to be tested arranged in rows B and columns W, corresponding to each memristor in the memristor array; The first position selected by the user in the chart is detected as the starting position of the frame selection area of ​​the memristor to be tested; the user is detected to move along the selected first position and drag to the second position and stop, which is used as the end position of the frame selection area; the address of the memristor in the framed area is used as the address of the memristor to be tested; when the address of the memristor to be tested is framed in the chart, the memristor input position in the parameter setting interface is automatically filled in, and a host computer instruction is generated and sent; the memristor to be tested is a plurality of memristors in the memristor array arranged in rows B and columns W in the test board, so that the FPGA is configured to operate according to the host computer and the FPGA. The device comprises an agreed register protocol, a drive signal for the address of the memristor to be tested, and a control signal receiving an instruction from the host computer; the drive signal is sent to the memristor to be tested; the return signal of the memristor to be tested is received, and the current test is performed; when the parameter setting interface for the current test is switched to the next test, the parameter setting interface for the current test is used as the parameter setting interface for the current test; if it is detected that there is saved data in the previous test, the saved data that can be used in the current test is extracted and automatically filled in the parameter setting interface for the current test; wherein the saved data refers to the data saved at the end of the previous test; the saved data used in the current test includes the address of the memristor to be tested; Among them, the FPGA driver of the FPGA includes a PS end and a PL end; the PS end is used to communicate with the host computer and store instructions in registers; each module of the PL drives the corresponding hardware module by reading data in the RRAM; the host computer communicates with the FPGA through a fixed communication protocol; the fixed communication protocol includes TCP and / or UDP, the front-end interface of the host computer is developed in Vue, and the back-end is developed in Go language, and the host computer serves as the server end.

9. A RRAM testing system, characterized in that: include: A test board, containing a memristor array arranged in B rows and W columns; The host computer is used to display the login interface of the current test of RRAM; Receive login information entered by the user on the login interface; After the login information is verified, a current test selected from a plurality of memristor tests is received, and a parameter setting interface for the current RRAM test is displayed; the parameter setting interface displays parameters to be input; and the parameter setting interface displays a chart corresponding to switches for controlling the memristors to be tested arranged in rows B and columns W, corresponding to each memristor in the memristor array; detecting a first position selected by the user on the chart as a starting position of a framed area of ​​the memristor to be tested; Detecting that the user moves along the selected first position and stops at the second position as the end position of the framed area; using the address of the memristor in the framed area as the address of the memristor to be tested; while the address of the memristor to be tested is framed in the chart, automatically filling it in the memristor input position in the parameter setting interface, generating and sending a host computer command; the memristors to be tested are multiple memristors in the memristor array; FPGA, configured to generate a drive signal for the address of the memristor to be tested according to a register protocol agreed upon by the host computer and the FPGA and based on instructions received from the host computer; Sending the driving signal to the memristor to be tested; receiving a return signal of the memristor to be tested and performing a current test; Upon receiving a parameter setting interface for switching from the current test to the next test, which is used as the parameter setting interface for the current test, if it is detected that there is saved data from the previous test, the saved data that can be used in the current test is extracted and automatically filled in the parameter setting interface for the current test; wherein the saved data refers to the data saved at the end of the previous test; and the saved data used in the current test includes the address of the memristor to be tested; Among them, the FPGA driver of the FPGA includes a PS end and a PL end; the PS end is used to communicate with the host computer and store instructions in registers; each module of the PL drives the corresponding hardware module by reading data in the RRAM; the host computer communicates with the FPGA through a fixed communication protocol; the fixed communication protocol includes TCP and / or UDP, the front-end interface of the host computer is developed in Vue, and the back-end is developed in Go language, and the host computer serves as the server end.

10. The RRAM testing system according to claim 9, wherein: The FPGA driver includes a programmable logic PL terminal; The PL end is connected to the host computer, and is used for the PL end to communicate with the host computer, the register to store instructions, and each module in the PL to drive the corresponding hardware module by reading data in the RRAM.

11. The RRAM testing system according to claim 9, wherein: The FPGA driver in the FPGA includes a processing system PS end and a programmable logic PL end connected to the PS end; The host computer is further configured to convert the input parameters into hexadecimal instructions according to the register protocol and transmit the instructions to the PS end of the FPGA via the network port; The PS side stores the data in the RRAM and waits for the PL side to read the data; The PL terminal reads the data stored in the RRAM of the PS terminal and transmits the data back to the host computer; After the PL terminal reads the data, it drives the corresponding DAC chip and ADC chip according to the register protocol agreed upon by the FPGA contained in the host computer instruction, and stores the register protocol agreed upon by the FPGA in the RRAM array.

12. The RRAM testing system according to claim 9, wherein: The memristor array has a memory function; the memory function is used to indicate that after the conductance value of the memristor array is successfully set, it will not be lost when the power is turned off; The FPGA is used to convert the image input by the user into a voltage signal, apply it to the target end of the memristor array, and obtain the current value read by the target end; the current value is used to reflect the calculation result; The calculation result is transmitted to the host computer or the driving brake device to respond.

Images