Chip, manufacturing method thereof and digital isolator
By prefabing the key structure in digital isolator chip manufacturing and replacing part of the metal interconnect structure with interconnect columns, the problem of high manufacturing costs in the prior art is solved, and the effect of reducing costs and maintaining efficient isolation is achieved.
Patent Information
- Application Number
- CN202311814323.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-26
- Publication Date
- 2025-06-27
AI Technical Summary
The manufacturing cost of existing capacitive digital isolators is high, mainly due to the increase in the number of lithography plates and process steps.
By pre-made substrate, transmission circuit, dielectric layer, first metal interconnection structure and second metal interconnection structure during chip manufacturing, and forming an upper plate on the insulating material layer, the dielectric thickness between the upper plate and the lower plate of the capacitor is adjusted using an interconnect column instead of the part of the metal interconnection structure.
Reduces process flow and lithography steps, reduces manufacturing costs while still achieving efficient signal transmission and isolation.
Smart Images
Figure CN120221502A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit technology, and particularly to a chip, a manufacturing method thereof, and a digital isolator. Background Art
[0002] A digital isolator is a device that realizes signal transmission in an electrically isolated state and is widely used in various electronic system devices such as industrial control, power energy, communication networks, instrumentation, and consumer electronics. Digital isolators can be further divided into capacitive isolators and magnetic isolators according to the basic principle. Capacitive isolation uses a high-voltage capacitor inside the chip to isolate the high voltage on the left and right sides of the chip, and a high-dielectric material is used in the middle to block the voltage. A capacitor is an element that can store electric charges. It consists of two conductor plates and a dielectric, and its characteristic is to conduct high-frequency signals and block low-frequency signals. The middle dielectric layer can isolate low-frequency or DC high-voltage signals.
[0003] As Figure 1 shown is a circuit schematic diagram of a traditional capacitive isolation type digital isolator, which consists of two chips. One chip is a transmitting circuit chip 100, which includes a transmitting circuit 103 and a high-voltage capacitor 101 inside; the other is a receiving circuit chip 200, which includes a receiving circuit 203 and a high-voltage capacitor 201 inside. The high-voltage capacitors on the two chips are connected by bonding wires 300. The transmitting circuit 103 modulates the input signal Din and turns it into a high-frequency signal (as Figure 2 shown). Utilizing the characteristic of the capacitor to conduct high-frequency signals and block low-frequency signals, this high-frequency signal can be transmitted to the receiving circuit chip 200 through the high-voltage capacitor and reach the input end of the receiving circuit. Then, through the demodulation of the receiving circuit, the output signal Dout can be obtained. The timing of this Dout signal and the data information carried by it are the same as those of the Din signal.
[0004] Figure 3 is a cross-sectional schematic diagram of a traditional capacitive digital isolator chip. The key device for realizing high-voltage isolation and signal transmission is a high-voltage capacitor. The lower plate of the high-voltage capacitor is realized by the M4 (Metal-4) metal layer, and the upper plate of the high-voltage capacitor is realized by the M8 (Metal-8) metal layer. The thickness of the dielectric layer between the two plates of the capacitor determines the level of isolation that can be achieved. The thicker the dielectric layer, the higher the DC voltage that can be isolated, and the higher the isolation level. In order to achieve a higher isolation level, it is often necessary to make the dielectric layer between the two plates as thick as possible. For example, to achieve a reliable isolation of 5.7 - kVRMS, the thickness of the dielectric layer needs to reach 20 μm. In order to achieve a thicker dielectric layer, the existing technology currently is to adopt a special customized process: increasing the number of metal wiring layers and at the same time increasing the thickness of the dielectric layer between adjacent metal layers. The disadvantage of this processing scheme is that the cost is relatively high due to the increase in the number of photomasks and process steps.
[0005] It should be noted that the information disclosed in the background art part of this invention is only intended to deepen the understanding of the general background art of this invention, and should not be regarded as an admission or any form of implication that this information constitutes the prior art known to those skilled in the art. Summary of the Invention
[0006] The purpose of this invention is to provide a chip, its manufacturing method, and a digital isolator, so as to solve the problem that the chip manufacturing cost of the existing capacitive digital isolator is relatively high.
[0007] To solve the above technical problems, this invention provides a manufacturing method of a chip for manufacturing a transmitting circuit chip or a receiving circuit chip of a digital isolator, including the following steps:
[0008] S1: Provide a substrate with a transmission circuit, a dielectric layer is formed on the top of the substrate, and a first metal interconnect structure and a second metal interconnect structure respectively connected to the transmission circuit are arranged in the dielectric layer. Among them, a lower electrode plate is further connected to the top of the first metal interconnect structure, and at least part of the top of the second metal interconnect structure is exposed out of the dielectric layer;
[0009] S2: Form an insulating material layer with a required thickness on the top surface of the dielectric layer, and at least part of the second metal interconnect structure is exposed through a contact groove in the insulating material layer;
[0010] S3: Fill the contact groove to form an interconnect post connected to the second metal interconnect structure, and form an upper electrode plate corresponding to the lower electrode plate on the top of the insulating material layer.
[0011] Preferably, a passivation layer is further formed between the dielectric layer and the insulating material layer, wherein the interconnect post penetrates through the insulating material layer, the passivation layer and at least part of the dielectric layer to be connected to the second metal interconnect structure.
[0012] Preferably, in S2, an insulating material is coated on the top of the passivation layer to form the insulating material layer with a required thickness.
[0013] Preferably, in S2, after forming the insulating material layer, the insulating material layer is etched to form the contact groove, so that the top of the second metal interconnect structure is exposed through the contact groove.
[0014] Preferably, in S3, the steps of forming the interconnect post and the upper electrode plate include: forming a metal material layer in the contact groove and on the top of the insulating material layer, and patterning the metal material layer by photolithography to form the upper electrode plate and the interconnect post.
[0015] Preferably, after forming the upper electrode plate and the interconnecting posts, the method further includes: covering a protective layer on the sides and top of the upper electrode plate and the interconnecting posts, and then etching the protective layer to form a first bonding pad exposing the top of the upper electrode plate and a second bonding pad exposing the top of the interconnecting posts.
[0016] Preferably, the insulating material layer is a photoresist.
[0017] Preferably, the protective layer is made of the same material as the insulating material layer.
[0018] The present invention also provides a chip for modulating or demodulating an input signal, adopting the manufacturing method of the chip as described above:
[0019] The chip is a transmitting circuit chip, which is configured to modulate and shape the input signal to generate a modulation signal, or:
[0020] The chip is a receiving circuit chip, which is configured to demodulate the modulation signal to generate an output signal.
[0021] The present invention also provides a digital isolator, including:
[0022] The transmitting circuit chip as described above;
[0023] The receiving circuit chip as described above;
[0024] Wherein, the transmitting circuit chip and the receiving circuit chip are connected by a bonding wire.
[0025] In the manufacturing method of the chip provided by the present invention, the substrate, the transmission circuit, the dielectric layer, the first metal interconnecting structure and the second metal interconnecting structure can all be pre-fabricated and realized by conventional processes. By providing another insulating material layer and forming an upper electrode plate on the insulating material layer, the insulating material layer can not only be set with a thickness according to requirements, but also a material with a lower manufacturing cost can be selected, and interconnecting posts are provided to replace part of the metal interconnecting structure, which is convenient for adjusting the dielectric thickness between the upper and lower electrode plates of the capacitor, reducing the process flow and the manufacturing cost.
[0026] The chip provided by the present invention and the manufacturing method of the chip provided by the present invention belong to the same inventive concept. Therefore, the chip provided by the present invention has at least all the advantages of the manufacturing method of the chip provided by the present invention, which will not be elaborated herein. Further, the chip manufactured by the above manufacturing method of the chip can serve as the receiving / transmitting circuit chip of the digital isolator. The final digital isolator product can be formed by packaging the transmitting circuit chip and the receiving circuit chip together. The substrate, the dielectric layer, the first metal interconnect structure and the second metal interconnect structure can all be prefabricated and formed. The lower electrode plate can be embedded in the dielectric layer. Then, the thickness and material of the insulating material layer can be set according to requirements, and the interconnect posts can be set to realize the connection with the second metal interconnect structure and the transmission circuit. Therefore, compared with the traditional solution, it is convenient to set the thickness of the insulating material layer, and the insulating material layer can also be set with materials with lower manufacturing costs according to requirements, greatly reducing the manufacturing cost.
[0027] The digital isolator provided by the present invention and the manufacturing method of the chip provided by the present invention belong to the same inventive concept. Therefore, the digital isolator provided by the present invention has at least all the advantages of the manufacturing method of the chip provided by the present invention, which will not be elaborated herein. Description of the Drawings
[0028] Figure 1 is a schematic circuit connection diagram of a capacitive digital isolator in the prior art;
[0029] Figure 2 is a signal waveform diagram of a capacitive digital isolator in the prior art;
[0030] Figure 3 is a schematic cross-sectional view of a chip of a capacitive digital isolator in the prior art;
[0031] Figure 4 is a schematic cross-sectional view of a receiving chip of a capacitive digital isolator in the prior art;
[0032] Figure 5 is a schematic diagram of a high-voltage capacitor structure of a capacitive digital isolator in the prior art;
[0033] Figure 6 is a flowchart of the manufacturing method of the chip provided by the present invention;
[0034] Figure 7 is a schematic cross-sectional view of the chip provided by the present invention;
[0035] Figure 8 is a schematic cross-sectional view of the chip provided by the present invention after the insulating material layer is formed;
[0036] Figure 9 is a schematic cross-sectional view of the chip provided by the present invention after the contact grooves are formed;
[0037] Figure 10 It is a schematic cross-sectional view of the chip provided by the present invention after forming a metal layer;
[0038] Figure 11 It is a schematic cross-sectional view of the chip provided by the present invention after forming an upper electrode plate;
[0039] Figure 12 It is a schematic cross-sectional view of the chip provided by the present invention after forming a protective layer;
[0040] Figure 13 It is a schematic cross-sectional view of the chip provided by the present invention after forming a bonding pad.
[0041] Figures 1 - 5 In:
[0042] 100. Transmitting circuit chip; 101. High-voltage capacitor; 1011. First lower electrode plate; 1012. First upper electrode plate; 102. First substrate; 103. Transmitting circuit; 104. First metal interconnecting structure; 105. First passivation layer; 106. First gold wire; 107. First dielectric layer; 108. Second metal interconnecting structure; 200. Receiving circuit chip; 201. High-voltage capacitor; 2011. Second lower electrode plate; 2012. Second upper electrode plate; 202. Second substrate; 203. Receiving circuit; 204. Third metal interconnecting structure; 205. Second passivation layer; 206. Second gold wire; 207. Second dielectric layer; 208. Fourth metal interconnecting structure; 300. Bonding wire.
[0043] Figures 6 - 13 In:
[0044] 1. Substrate; 2. Transmission circuit; 3. Dielectric layer; 4. First metal interconnecting structure; 5. Lower electrode plate; 6. Second metal interconnecting structure; 61. First metal layer; 62. Second metal layer; 63. Third metal layer; 64. Fourth metal layer; 65. Contact hole; 7. Passivation layer; 8. Groove; 9. Insulating material layer; 10. Contact groove; 11. Metal material layer; 12. Upper electrode plate; 13. Interconnecting post; 14. Protective layer; 15. First bonding pad; 16. Second bonding pad. Detailed implementation manners
[0045] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments with respect to the chip, its manufacturing method, and the digital isolator. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to explain certain principles of the present invention in the drawings of the specification will also adopt a slightly simplified drawing method. The specific design features of the present invention disclosed herein, such as specific dimensions, directions, positions, and shapes, will be partially determined by the specific application and usage environment. Also, in the following described embodiments, sometimes the same reference numerals are used commonly between different drawings to represent the same or parts with the same functions, and the repeated description thereof is omitted. In this specification, similar reference numerals and letters are used to represent similar items. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.
[0046] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present invention, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined.
[0047] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.
[0048] The capacitance structures in existing capacitive digital isolators are often formed by fabricating metal layers, and reference can be made to Figures 3 - 5 , since the structures of the transmitting circuit chip 100 and the receiving circuit chip 200 are substantially the same, only the structure of the transmitting circuit chip 100 in Figure 4 will be described here.
[0049] The inventors' research found that during the process of manufacturing the capacitive structure of the transmitting circuit chip 100, to meet the isolation requirements, it is necessary to fill a certain thickness of insulating medium in the upper electrode plate 1012 and the lower electrode plate 1011 of the high-voltage capacitor (see Figure 5 ). Correspondingly, the first metal interconnect structure 104 also needs to be increased in height and expose the first dielectric layer 107 to connect the first gold wire 106 (see Figure 3 ) to connect the transmitting circuit 103. Increasing the height of the first metal interconnect structure 104 requires increasing the number of metal wiring layers, and the metal layers in the first metal interconnect structure 104 also need to be interconnected through contact holes, which undoubtedly increases the lithography process flow and raises the manufacturing cost.
[0050] Based on this, the core idea of the present invention is that the substrate, transmission circuit, dielectric layer, first metal interconnect structure, and second metal interconnect structure can all be pre-fabricated and realized through conventional processes. By setting another insulating material layer and forming an upper electrode plate on the insulating material layer, the insulating material layer can not only be set with a thickness according to requirements, but also select materials with lower manufacturing costs, and set interconnect posts to replace part of the metal interconnect structure, which is convenient for adjusting the dielectric thickness between the upper and lower electrode plates of the capacitor, reducing the process flow and lowering the manufacturing cost.
[0051] Please refer to Figures 6 - 13 , which is a schematic diagram of an embodiment of the present invention. As Figure 6 shown, a method for manufacturing a chip, used for manufacturing a transmitting circuit chip or a receiving circuit chip of a digital isolator, includes the following steps:
[0052] S1: Provide a substrate 1 having a transmission circuit 2, a dielectric layer 3 is formed on the top of the substrate 1, and a first metal interconnect structure 4 and a second metal interconnect structure 6 respectively connected to the transmission circuit 2 are provided in the dielectric layer 3. Among them, the top of the first metal interconnect structure 4 is also connected to a lower electrode plate 5, and at least part of the top of the second metal interconnect structure 6 is exposed from the dielectric layer 3;
[0053] S2: Form an insulating material layer 9 with a required thickness on the top surface of the dielectric layer 3, and at least part of the second metal interconnect structure 4 is exposed through the contact groove 10 in the insulating material layer 9;
[0054] S3: Fill the contact groove 10 to form an interconnect post 13 connected to the second metal interconnect structure 4, and form an upper electrode plate 12 corresponding to the lower electrode plate 5 on the top of the insulating material layer 9.
[0055] The substrate 1, the transmission circuit 2, the dielectric layer 3, the first metal interconnect structure 4, and the second metal interconnect structure 6 can all be prefabricated by conventional processes. The insulating material layer 9 and the upper electrode plate 12 can be processed using RDL technology in a packaging factory. The process is relatively mature and the cost is very low. Therefore, the insulating material layer 9 with the required thickness can be set on the lower electrode plate 5 according to requirements. The insulating material layer 9 can also be selected from materials with lower costs according to requirements, and the interconnect posts 13 are arranged to realize the interconnection between the second metal interconnect structure 4 and external signals.
[0056] During the manufacturing process, the substrate 1, the dielectric layer 3, the first metal interconnect structure 4, and the second metal interconnect structure 6 can all be prefabricated and formed. The lower electrode plate 5 can be embedded in the dielectric layer 3. Then, the thickness and material of the insulating material layer 9 can be set according to requirements, and the interconnect posts 13 are set to realize the connection with the second metal interconnect structure 6 and the transmission circuit 2. Therefore, compared with the traditional scheme, it is convenient to set the thickness of the insulating material layer 9, and the insulating material layer 9 can be set with materials with lower manufacturing costs according to requirements, greatly reducing the manufacturing cost.
[0057] In one embodiment, the insulating material layer 9 is a photoresist. More preferably, polyimide is selected as the insulating material layer 9. Polyimide is a polymer composed of imide monomers. It has excellent breakdown strength, thermal stability, mechanical stability, and chemical resistance. Moreover, it is compatible with the integrated circuit process and the manufacturing cost is very low. Only simple photolithography is required to form a relatively thick patterned polyimide film, which is very suitable for use as the insulating material between the two electrode plates of a high-voltage digital isolator. Therefore, in the present disclosure, polyimide is used to fabricate the insulating material layer 9 between the two electrode plates of the high-voltage capacitor.
[0058] As Figure 13 shown, it is a cross-sectional schematic diagram of the capacitive-coupled digital isolator chip proposed by the present invention. In this example, the passivation layer 7 and the part below the passivation layer 7 are the original wafer fabricated by the Foundry factory using standard processes. The total number of metal wiring layers in the second metal interconnect structure 6 is 4 layers, namely M1 (Metal-1, the first metal layer 61), M2 (Metal-2, the second metal layer 62), M3 (Metal-3, the third metal layer 63), and M4 (Metal-4, the fourth metal layer 64). Adjacent metal layers are connected by contact holes 65.
[0059] In one example, the first metal interconnect structure 4 is provided with three metal wiring layers, and another metal wiring layer is also connected thereto to serve as the lower electrode plate 5 of the high-voltage capacitor. The lower electrode plate 5 is connected to the transmission circuit 2 through the three metal wiring layers of the first metal interconnect structure 4. The transmission circuit 2 is the receiving or transmitting circuit used in a conventional digital isolator. The first metal interconnect structure 4 can be provided with two or one metal wiring layer, or can be not provided, and only the lower electrode plate 5 and the transmission circuit 2 are connected through contact holes. The polyimide dielectric layer in the figure and the upper electrode plate of the high-voltage capacitor can be processed by the RDL technology in a packaging factory, and the process is relatively mature and the cost is very low. The specific processing process is as Figures 7 - 13 shown.
[0060] The insulating material layer 9 can also be selected from other photoresists with insulating properties, such as benzocyclobutene (BCB: bis-BenzoCycloButene), poly(p-phenylene-2,6-benzobisoxazole) (PBO), etc. There is no limitation here.
[0061] As Figure 7 and Figure 12 shown, a passivation layer 7 is also formed between the dielectric layer 3 and the insulating material layer 9. Among them, the interconnect post 13 penetrates through the insulating material layer 9, the passivation layer 7 and at least part of the dielectric layer 3 to be connected to the second metal interconnect structure 6.
[0062] As Figure 7 is a schematic cross-sectional view of the original wafer produced by the foundry factory. This wafer is processed by a standard process and has a low cost. Inside the wafer, the lower electrode plate 5 of the high-voltage capacitor has been fabricated using a metal wiring layer, and the lower electrode plate 5 has been connected to the receiving circuit or the transmitting circuit. A groove 8 is also etched on the passivation layer 7, and the groove 8 exposes the top of the second metal interconnect structure 6.
[0063] As Figure 8 shown, in S2, an insulating material is coated on the top of the passivation layer 7 to form the insulating material layer 9 with a required thickness. In one example, the insulating material is polyimide, that is, polyimide photoresist is coated on the surface of the passivation layer 7 to form the insulating material layer 9, and its thickness can be set as required here.
[0064] As Figure 9 , after the insulating material layer is formed in S2, the insulating material layer 9 is also etched to form the contact groove 10 so that the top of the second metal interconnect structure 6 is exposed through the contact groove 10. The insulating material layer 9 of the polyimide photoresist coated in the previous step is lithographed and developed to expose the original bond pad area on the wafer.
[0065] As Figures 10 - 11 , in S3, the steps of forming the interconnecting posts 13 and the upper electrode plate 12 include: forming a metal material layer 11 in the contact groove 10 and on the top of the insulating material layer 9, and patterning the metal material layer 11 by photolithography to form the upper electrode plate 12 and the interconnecting posts 13.
[0066] Among them, a metal material layer 11 is fabricated on the entire wafer, or on the insulating material layer 9. In one example, copper is plated on the insulating material layer 9 by electroplating. The fabricated metal material layer 11 is patterned by photolithography technology, and the unnecessary areas are etched away, leaving the required areas to form the upper electrode plate 12, the interconnecting posts 13 of the high-voltage capacitor, and other patterns.
[0067] As Figures 12 - 13 , after forming the upper electrode plate 12 and the interconnecting posts 13, it further includes: covering a protective layer 14 on the sides and top of the upper electrode plate 12 and the interconnecting posts 13, and then etching the protective layer 14 to form a first bonding pad 15 exposing the top of the upper electrode plate 12 and a second bonding pad 16 exposing the top of the interconnecting posts 13. More preferably, the protective layer 14 is made of the same material as the insulating material layer 9. Both are polyimide photoresist.
[0068] The polyimide photoresist is coated for the second time to form the protective layer 14, and the second-coated polyimide photoresist is subjected to photolithography and development to form new bonding pads: the first bonding pad 15 and the second bonding pad 16. The top of the upper electrode plate 12 and the top of the interconnecting posts 13 are respectively exposed at the first bonding pad 15 and the second bonding pad 16. The first bonding pad 15 and the second bonding pad 16 are used to set gold wires to achieve interconnection with other structures.
[0069] As Figure 13 The formed chip can serve as a receiving / transmitting circuit chip of a digital isolator. Encapsulating the transmitting circuit chip and the receiving circuit chip together can form the final digital isolator product. Similar to Figure 3 the digital isolator, the upper electrode plate of the high-voltage capacitor in the transmitting circuit chip is connected to the upper electrode plate of the high-voltage capacitor in the receiving circuit chip by a gold wire, and other bonding pads are connected to the pins of the package case by gold wires.
[0070] Therefore, based on the same technical concept, the present disclosure also provides a chip for modulating or demodulating an input signal, adopting the manufacturing method of the chip as described above:
[0071] The chip is a transmitting circuit chip, which is configured to modulate and shape an input signal to generate a modulation signal, or:
[0072] The chip is a receiving circuit chip, which is configured to demodulate the modulated signal to generate an output signal.
[0073] The transmission circuit 2 of the transmitting circuit chip is configured as a transmitting circuit. In contrast, the transmission circuit 2 of the receiving circuit chip is configured as a receiving circuit.
[0074] Therefore, based on the same inventive concept, the present disclosure also provides a digital isolator, comprising:
[0075] The above-mentioned transmitting circuit chip, which is configured to modulate and shape an input signal to generate a modulated signal;
[0076] The above-mentioned receiving circuit chip, which is configured to demodulate the modulated signal to generate an output signal, and the transmitting circuit chip and the receiving circuit chip are connected by bonding wires.
[0077] In summary, in the chip, its manufacturing method, and the digital isolator provided in the embodiments of the present invention, during the manufacturing process, the substrate 1, the dielectric layer 3, the first metal interconnect structure 4, and the second metal interconnect structure 6 can all be prefabricated and formed. The lower electrode plate 5 can be embedded in the dielectric layer 3. Then, the thickness and material of the insulating material layer 9 can be set according to requirements, and then the interconnecting posts 13 can be set to achieve connection with the second metal interconnect structure 6 and the transmission circuit 2. Therefore, compared with the traditional solution, it is convenient to set the thickness of the insulating material layer 9, and a material with a lower manufacturing cost can be selected to set the insulating material layer 9 according to requirements, greatly reducing the manufacturing cost.
[0078] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure are within the protection scope of the claims.
Claims
1. A manufacturing method of a chip, used for manufacturing a transmitting circuit chip or a receiving circuit chip of a digital isolator, characterized in that, It includes the following steps: S1: Provide a substrate with a transmission circuit. A dielectric layer is formed on the top of the substrate. A first metal interconnect structure and a second metal interconnect structure respectively connected to the transmission circuit are arranged in the dielectric layer. Wherein, a lower electrode plate is further connected to the top of the first metal interconnect structure, and at least part of the top of the second metal interconnect structure is exposed out of the dielectric layer; S2: Form an insulating material layer with a required thickness on the top surface of the dielectric layer, and at least part of the second metal interconnect structure is exposed through a contact groove in the insulating material layer; S3: Fill the contact groove to form an interconnect pillar connected to the second metal interconnect structure, and form an upper electrode plate corresponding to the lower electrode plate on the top of the insulating material layer.
2. The manufacturing method of the chip according to claim 1, characterized in that, A passivation layer is further formed between the dielectric layer and the insulating material layer. Wherein, the interconnect pillar penetrates through the insulating material layer, the passivation layer and at least part of the dielectric layer to be connected to the second metal interconnect structure.
3. The manufacturing method of the chip according to claim 2, characterized in that, In S2, an insulating material is coated on the top of the passivation layer to form the insulating material layer with a required thickness.
4. The manufacturing method of the chip according to claim 2, characterized in that, In S2, after forming the insulating material layer, the insulating material layer is etched to form the contact groove, so that the top of the second metal interconnect structure is exposed through the contact groove.
5. The manufacturing method of the chip according to claim 1, characterized in that, In S3, the steps of forming the interconnect pillar and the upper electrode plate include: forming a metal material layer in the contact groove and on the top of the insulating material layer, and patterning the metal material layer by photolithography to form the upper electrode plate and the interconnect pillar.
6. The manufacturing method of the chip according to claim 2, characterized in that, After forming the upper electrode plate and the interconnect pillar, it further includes: covering a protective layer on the sides and the top of the upper electrode plate and the interconnect pillar, and then etching the protective layer to form a first bonding pad exposing the top of the upper electrode plate and a second bonding pad exposing the top of the interconnect pillar.
7. The manufacturing method of the chip according to claim 1, characterized in that, The insulating material layer is a photoresist.
8. The manufacturing method of the chip according to claim 6, characterized in that, The protective layer has the same material as the insulating material layer.
9. A chip for modulating or demodulating an input signal, characterized in that, Adopt the manufacturing method of the chip as described in any one of claims 1-8: The chip is a transmitting circuit chip, which is configured to modulate and shape an input signal to generate a modulated signal, or: The chip is a receiving circuit chip, which is configured to demodulate the modulated signal to generate an output signal.
10. A digital isolator, characterized in that, It includes: The transmitting circuit chip as described in claim 9; The receiving circuit chip as described in claim 9; Wherein, the transmitting circuit chip and the receiving circuit chip are connected by a bonding wire.