Multi-chip stacked packaging structure and packaging method for improving welding reliability

Abstract

The invention relates to the technical field of chip packaging, in particular to a multi-chip stacked packaging structure and packaging method capable of improving welding reliability. A plurality of packaging units are arranged on the substrate, each packaging unit comprises two chip sets stacked in a stepped mode, one chip set is bonded with the substrate through an arc-shaped lead, the other chip set is bonded with the substrate through a vertical lead, a plurality of grooves are formed in non-welding positions on the surface of the substrate, and filling glue is arranged in the grooves. Compared with the prior art, effective combination of vertical routing and traditional routing is realized by utilizing the sacrifice module through a close-up and staggered stacking packaging method, so that the requirement of packaging density is greatly improved, and the requirement of packaging layout area is reduced. And moreover, complete metal wrapping of the side surfaces and the surface is realized through chemical plating of NiAu, the contact effect is greatly improved, the substrate is slotted, the binding force between the underfill and the substrate is greatly increased, the chip failure risk is reduced, and the welding reliability is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and specifically to a multi-chip stacked packaging structure and packaging method for improving welding reliability. Background Art

[0002] In the current packaging field, especially in the field of memory chip packaging, in consideration of expanding the storage capacity of a single package, stacking is generally considered. After stacking multiple chips in sequence, wire bonding is performed to complete electrical connection, as Figure 3 shown. This solution does not adopt a special packaging process and can be completed by relying on conventional die bonding and wire bonding equipment.

[0003] With the development trend of high capacity and high density, although this packaging layout has been developed in the 3D direction, in order to avoid interference between the leads of adjacent stacked chips, there are certain requirements for the spacing between adjacent stacked chips, resulting in poor utilization of the overall space, thereby greatly increasing the 2D size in subsequent large chip packaging and high stacked structures. And currently, simply using underfill to increase the bonding force between the plastic package and the substrate is limited. Especially when the contact area of the exposed metal solder joints is limited, it is very easy to cause the welding to break during subsequent mounting on the substrate, resulting in product failure.

[0004] Therefore, new packaging methods are required. For example, methods such as HBM (High Bandwidth Memory) use TSV to achieve non-staggered interconnection between chips, greatly reducing space requirements. However, this packaging method has the disadvantages of low yield and high cost due to the use of TSV technology. Summary of the Invention

[0005] The present invention aims to overcome the deficiencies of the prior art and provides a multi-chip stacked packaging structure and packaging method for improving welding reliability.

[0006] To achieve the above object, a multi-chip stacked packaging structure for improving welding reliability is designed, including a substrate. A number of packaging units are provided on the substrate. Each packaging unit includes two chip groups stacked in a stepped manner. One chip group is bonded to the substrate through an arc-shaped lead, and the other chip group is bonded to the substrate through a vertical lead. A number of grooves are provided at non-welding positions on the surface of the substrate, and filling glue is provided in the grooves.

[0007] The gap between the two chip groups is 200 ± 50um.

[0008] Convex points are provided at one end of the arc-shaped lead and the vertical lead close to the substrate. The sides and surfaces of the convex points are wrapped with metal parts. Solder balls or bumps are provided on the surface of the substrate to cooperate with the metal parts.

[0009] To achieve the above object, a multi-chip stacked packaging method for improving welding reliability is designed, including the following steps: S1. Provide a chip group stacked in a stepped manner, and vertically wire at the pads of each chip. S2. Provide a sacrificial module. The surface of the sacrificial module is mounted to the chip group through a DAF film, and the vertical leads are in a suspended state. S3. Provide another chip group stacked in a stepped manner, and mount it to the surface of the sacrificial module through a DAF film. S4. Through plasma oxygen ashing treatment, remove the DAF film and organic matter exposed on the surface of the sacrificial module, and expose the pads of the sacrificial module. S5. Perform a wire bonding process on the chip group in step S3 through arc-shaped leads. S6. Encapsulate and wrap the two chip groups, arc-shaped leads, and vertical leads. S7. Grind and thin, remove the sacrificial module, and expose one end of the arc-shaped leads and vertical leads close to the sacrificial module. S8. Through dry etching of the surfaces of the exposed ends of the arc-shaped leads and vertical leads by oxygen plasma, expose the metal of the arc-shaped leads and vertical leads to form bumps, and then perform electroless plating of NiAu to completely wrap the sides and surfaces of the bumps with metal parts to form a packaging unit. S9. Provide a substrate, and solder balls or bumps are provided at corresponding positions on the surface of the substrate. The non-welding positions outside the solder balls or bumps are laser ablated to form several grooves. S10. Mount and weld the packaging unit to the substrate. S11. Clean the flux and perform underfill process, and fill the filling glue in the grooves. S12. Ball mounting and dicing to obtain the finished product.

[0010] In the step S1, one ends of several vertical leads away from the chip pads are flush, and are 100 ± 50 um higher than the surface of the chip corresponding to the shortest vertical lead.

[0011] The thickness of the sacrificial module is greater than the height of the vertical wire bonding above the outermost chip surface.

[0012] In the step S3, the gap between the two chip groups is 200 ± 50 um.

[0013] In the step S2, the thickness of the DAF film on the surface of the sacrificial module is 30 ± 10 um.

[0014] In the step S8, the height of the bump is 20 ± 10 um. In the step S9, the depth of the groove is 5 ± 5 um, the width is 100 ± 10 um, and the spacing between adjacent grooves is 200 - 1000 um.

[0015] The outer sides of the arc-shaped leads and the vertically arranged leads are wrapped with a metal part, and the metal part is further wrapped with a filling adhesive.

[0016] Compared with the prior art, the present invention realizes the effective combination of vertical wire bonding and traditional wire bonding by means of a close-packed and staggered stacking packaging method, utilizes a sacrificial module, greatly improves the requirement for packaging density, and thus reduces the requirement for packaging layout area. And by chemical plating NiAu, the side and the surface are completely wrapped with metal, greatly increasing the contact effect. Slots are made in the substrate, greatly increasing the bonding force between the underfill adhesive and the substrate, reducing the risk of chip failure, and improving the welding reliability. Description of the Drawings

[0017] Figure 1 It is a structural schematic diagram of the present invention.

[0018] Figure 2 It is a process schematic diagram of the present invention.

[0019] Figure 3 It is a structural schematic diagram of the prior art before the improvement of the present invention. Detailed Embodiments

[0020] The following further describes the present invention with reference to the drawings.

[0021] As Figure 1 shown, a plurality of packaging units are provided on a substrate 1. Each packaging unit includes two chip groups 2 stacked in a stepped manner. One chip group 2 is bonded to the substrate 1 through an arc-shaped lead 3, and the other chip group 2 is bonded to the substrate 1 through a vertical lead 4. A plurality of grooves are provided at non-welding positions on the surface of the substrate 1, and a filling adhesive 12 is provided in the grooves. By forming the grooves, the bonding force of the filling adhesive 12 is increased, and reliability problems such as the breaking of welding points caused by delamination are solved.

[0022] The gap between the two chip groups 2 is 200 ± 50 um. Through the bonding of the two wire bonding methods, the distance between adjacent chip groups realizes a close-packed packaging, improving the packaging density.

[0023] Convex points 6 are provided at one ends of the arc-shaped leads 3 and the vertical leads 4 close to the substrate 1. The sides and the surfaces of the convex points 6 are wrapped with metal, and solder balls or bumps 10 matched with the metal parts 9 are provided on the surface of the substrate 1. Electrical connection is formed through the metal parts 9 wrapped outside the convex points 6 and the solder balls or bumps 10 on the surface of the substrate 1.

[0024] During specific use, a plastic package layer 7 is provided outside the chip group 2 to protect the chip group 2, the arc-shaped leads 3, and the vertical leads 4. An electrical connector 8 is provided at one end of the substrate 1, and electrical connection is formed with other external components through the electrical connector 8.

[0025] To achieve the above object, a multi-chip stacked packaging method for improving welding reliability is designed, including the following steps: S1. Provide a chip group 2 stacked in a stepped manner, and perform vertical wire bonding at the pads of each chip. S2. Provide a sacrificial module 5. The surface of the sacrificial module 5 is mounted to the chip group 2 through a DAF film 11, and the vertical leads 4 are in a suspended state. S3. Provide another chip group 2 stacked in a stepped manner, and mount it to the surface of the sacrificial module 5 through a DAF film 11. S4. Through plasma oxygen ashing treatment, remove the DAF film and organic matter exposed on the surface of the sacrificial module 5, and expose the pads of the sacrificial module 5, which plays a positioning role in the subsequent wire bonding process. S5. Perform a wire bonding process on the chip group 2 in step S3 through an arc-shaped lead 3. S6. Encapsulate, wrap the two chip groups 2, the arc-shaped leads 3, and the vertical leads 4. Select the temperature when the encapsulant has the best fluidity, and adjust the pressure and temperature according to the actual situation to control the flow thrust, so as to avoid the encapsulant impacting and deforming the vertical leads 4. S7. Grind and thin, remove the sacrificial module 5, and expose the ends of the arc-shaped leads 3 and the vertical leads 4 close to the sacrificial module 5. S8. Through dry etching of the surfaces of the exposed ends of the arc-shaped leads 3 and the vertical leads 4 by oxygen plasma, expose the metal of the arc-shaped leads 3 and the vertical leads 4 to form bumps 6, and then perform chemical plating of NiAu so that the sides and surfaces of the bumps 6 are completely wrapped by the metal parts 9 to form a packaging unit. S9. Provide a substrate 1, and solder balls or bumps 10 are provided at corresponding positions on the surface of the substrate 1. Laser ablation is performed on the non-welding positions outside the solder balls or bumps 10 to form a number of grooves. S10. Mount and weld the packaging unit to the substrate 1. S11. Clean the flux, perform the underfill process, and fill the filling glue 12 in the grooves. S12. Ball mounting and dicing to obtain the finished product.

[0026] In step S1, the heights of a number of vertical leads 4 are different. It is necessary to keep the ends of each vertical lead 4 away from the chip pads flush, and be 100 ± 50 um higher than the surface of the chip corresponding to the shortest vertical lead 4. This height is denoted as the first height.

[0027] To avoid interference between the vertical lead 4 and the sacrificial module 5, an opening is provided on one side of the sacrificial module 5. After the chipset 2 is mounted on the sacrificial module 5, the vertical lead 4 can be in a suspended state, and the position of the vertical circuit will not be affected during the mounting process, so that it can be accurately mounted on the substrate in subsequent processes. The thickness of the sacrificial module 5 is greater than the height of the vertical wire bonding above the surface of the outermost chip, that is, the thickness of the sacrificial module 5 is greater than the first height.

[0028] In step S3, the gap between the two chipsets 2 is 200 ± 50 um, achieving a close-packed stack and reducing the volume of the finished package.

[0029] In step S2, the thickness of the DAF film on the surface of the sacrificial module 5 is 30 ± 10 um.

[0030] In step S7, after grinding, the exposed ends of the arc-shaped lead 3 and the vertical lead 4 are flush.

[0031] In the present invention, the chipset cannot be directly welded to the surface of the substrate through the vertical wire bonding 4. Different from the traditional arc-shaped wire bonding, the welding points of the chipset with vertical wire bonding and the substrate 1 are not on the same plane in the same direction, resulting in the inability of the wire bonding head to perform two-point displacement and the inability to achieve direct welding and interconnection between the chip and the substrate. Moreover, if the vertical wire bonding is in a suspended state and the substrate is directly welded, since the diameter of the lead is about 20 um and has a certain degree of extensibility, it is difficult to ensure that the position and shape of the metal wire do not deform during the welding process. Therefore, in the present invention, a sacrificial module is borrowed to first fix the chipset 2 with vertical wire bonding, and then the vertical lead 4 is wrapped and supported by plastic encapsulation. Moreover, a welding bump is formed at the exposed end of the vertical lead 4, and the vertical lead 4 is connected to the substrate 1 by welding the welding bump 6 to the solder ball or bump on the surface of the substrate 1, so as to complete the connection between the vertical lead 4 and the substrate, with high stability and not easily deformed.

[0032] In step S2, in the vertically wire-bonded chipset 2 after mounting, one end of the vertical lead 4 is suspended. Through the plastic encapsulation and curing in step S6, the position and shape of the vertical lead 4 are cured, so as to ensure that the position and shape are not easily changed during the subsequent welding process.

[0033] In step S2, one end of the vertical lead 4 is suspended, and one end of the arc-shaped lead 3 is directly welded to the sacrificial module 5. Using the thickness of the DAF film, the horizontal position of its welding point is lower than the bottom surface of the chip. Subsequently, through plastic encapsulation and thinning, the coplanarity of one end of the vertical lead 4 and one end of the arc-shaped lead 3 is achieved.

[0034] During specific use, the sacrificial module 5 is selected as the substrate.

[0035] In the step S8, the height of the bump 6 is 20±10um. The present invention uses the method of anisotropic etching. After the plastic package is thinned, the circuits exposed by the arc-shaped lead 3 and the vertical lead 4 are processed to expose the bump 6, and then NiAu is plated on it. The contact area of the welding point is increased, the welding force is improved, and the structural strength is greatly improved compared with the bump formed by directly plating NiAu, increasing the bonding force between the packaging unit and the substrate.

[0036] In the step S9, the depth of the groove is 5±5um, the width is 100±10um, and the spacing between adjacent grooves is 200-1000um. The outside of the metal wrapped by the arc-shaped lead 3 and the vertical lead 4 is further wrapped with the filling glue 12. The present invention forms a groove by digging the non-welding position of the substrate, increasing the contact area of the subsequent filling glue 12 and the bonding force of the filling glue 12, and solving the reliability problems such as the breaking of the welding point caused by delamination.

Claims

1. A multi-chip stacking package structure for improving welding reliability, comprising a substrate, characterized in that: The substrate (1) is provided with a plurality of packaging units, each packaging unit comprising two chip groups (2) stacked in a step-like manner, one chip group (2) being bonded to the substrate (1) via an arc lead (3), and the other chip group (2) being bonded to the substrate (1) via a vertical lead (4), and a plurality of grooves being provided at non-welding positions on the surface of the substrate (1), and filling glue (12) being provided in the grooves.

2. The multi-chip stacking packaging structure according to claim 1, characterized in that: The gap between the two chip groups (2) is 200±50 um.

3. The multi-chip stacking packaging structure according to claim 1, characterized in that: The arc lead (3) and the vertical lead (4) are provided with a bump (6) at one end close to the substrate (1); the side and surface of the bump (6) are wrapped with a metal part (9); and the surface of the substrate (1) is provided with a solder ball or a bump (10) that matches the metal part (9).

4. A multi-chip stacking packaging method for improving welding reliability, characterized in that: The steps include: S1, provides a stacked chip set (2) in a stepped manner, and vertically bonds wires at the pads of each chip. S2, providing a sacrificial module (5), wherein the surface of the sacrificial module (5) is mounted on the chipset (2) via a DAF film (11), and the vertical lead (4) is in a suspended state; S3, providing another chip set (2) stacked in a step-like manner, and mounting it on the surface of the sacrificial module (5) through a DAF film (11); S4, removing the DAF film and organic matter exposed on the surface of the sacrificial module (5) through plasma oxygen ashing treatment, thereby exposing the soldering pad of the sacrificial module (5); S5, performing a wire bonding process on the chip set (2) of step S3 through the arc lead (3); S6, plastic encapsulation, encapsulating the two chip groups (2), the curved leads (3), and the vertical leads (4); S7, grinding and thinning to remove the sacrificial module (5), so that the arc lead (3) and the vertical lead (4) are exposed at one end close to the sacrificial module (5); S8, dry etching the exposed end surfaces of the arc lead (3) and the vertical lead (4) by oxygen plasma to expose the metal of the arc lead (3) and the vertical lead (4) to form a bump (6), and then chemically plating NiAu to make the side and surface of the bump (6) completely wrapped by the metal part (9) to form a packaging unit; S9, providing a substrate (1), wherein solder balls or bumps (10) are provided at corresponding positions on the surface of the substrate (1), and non-soldering positions outside the solder balls or bumps (10) are laser ablated to form a plurality of grooves; S10, mounting and soldering the packaging unit onto the substrate (1); S11, cleaning flux, bottom filling process, filling the groove with filling glue (12); S12, ball planting and dicing to obtain the finished product.

5. The multi-chip stacking packaging method for improving welding reliability according to claim 4, characterized in that: In the step S1, the ends of the plurality of vertical leads (4) away from the chip pad are flush and 100±50 um higher than the chip surface corresponding to the shortest vertical lead (4).

6. The multi-chip stacking packaging method for improving welding reliability according to claim 4, characterized in that: The thickness of the sacrificial module (5) is greater than the height of the vertical bonding wire above the outermost chip surface.

7. The multi-chip stacking packaging method for improving welding reliability according to claim 4, characterized in that: In the step S3, the gap between the two chip groups (2) is 200±50 um.

8. The multi-chip stacking packaging method for improving welding reliability according to claim 4, characterized in that: In the step S2, the thickness of the DAF film on the surface of the sacrificial module (5) is 30±10 um.

9. The multi-chip stacking packaging method for improving welding reliability according to claim 4, characterized in that: In the step S8, the height of the bump (6) is 20±10 um, and in the step S9, the depth of the groove is 5±5 um, the width is 100±10 um, and the spacing between adjacent grooves is 200-1000 um.

10. The multi-chip stacking packaging method for improving welding reliability according to claim 4, characterized in that: The outer side of the metal piece (9) wrapped by the arc lead (3) and the vertical lead (4) is further wrapped with a filling glue (12).

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