A combined packet identification circuit and energy storage system

Abstract

The present application relates to a parallel pack identification circuit and energy storage system. The parallel pack identification circuit includes a quantity identification circuit, a type identification circuit, and a controller. The quantity identification circuit and the type identification circuit are respectively connected to the controller. When an external battery pack is incorporated into a host, the quantity identification circuit generates a first identification signal, wherein the level state of the first identification signal is related to the number of external battery packs, and the type identification circuit generates a second identification signal, wherein the voltage of the second identification signal is related to the type of the external battery pack. The controller calculates the number of external battery packs based on the level state of the first identification signal and identifies the type parameters of the external battery pack based on the voltage of the second identification signal, thereby realizing the identification of the number and type of external battery packs.

Description

Technical Field

[0001] The present application relates to the field of energy storage, and in particular to a combined identification circuit and energy storage system. Background Art

[0002] With the prevalence of electronic devices, the number of scenarios involving multiple battery packs working together to provide power is increasing. However, existing energy storage systems have the following drawbacks: First, they cannot accurately detect the number of battery packs. When multiple battery packs are connected in parallel, the lack of a detection mechanism can easily lead to misjudgments, affecting power distribution and charge and discharge control. Second, battery packs come in many types, and each type has different electrical characteristics. For example, lithium-ion and nickel-metal hydride battery packs have different electrical characteristics. If the type of battery pack being connected cannot be identified, it will lead to mismatched charge and discharge strategies, shortening battery life and even safety hazards. Therefore, a parallel pack identification circuit that can identify both the number and type of battery packs is urgently needed. Summary of the Invention

[0003] The embodiments of the present application aim to provide a battery pack identification circuit and energy storage system, which can identify the quantity and type parameters of external battery packs.

[0004] To solve the above technical problems, the embodiments of the present application provide the following technical solutions:

[0005] In a first aspect, an embodiment of the present application provides a parallel pack identification circuit, wherein the parallel pack identification circuit is applied to an energy storage system, the energy storage system including a host and i external battery packs for connecting to the host, the parallel pack identification circuit including: a quantity identification circuit, a type identification circuit, and a controller;

[0006] The quantity identification circuit is connected to the controller, and is configured to generate a first identification signal in response to the external battery pack being incorporated into the host, wherein a level of the first identification signal is related to the number of the external battery packs;

[0007] The type identification circuit is connected to the controller, and is configured to generate a second identification signal in response to the external battery pack being incorporated into the host, wherein a voltage of the second identification signal is related to the type of the external battery pack;

[0008] The controller is configured to calculate the number of the external battery packs according to the level state of the first identification signal, and identify the type parameter of the external battery pack according to the voltage of the second identification signal.

[0009] In a second aspect, an embodiment of the present application provides an energy storage system, comprising a host, i external battery packs, and a parallel pack identification circuit as described above, wherein each of the external battery packs is connected in parallel with the host, and the parallel pack identification circuit is used to identify the number and type parameters of the external battery packs.

[0010] In various embodiments of the present application, the parallel pack identification circuit includes a quantity identification circuit, a type identification circuit, and a controller. The quantity identification circuit and the type identification circuit are respectively connected to the controller. When an external battery pack is connected to the host, the quantity identification circuit generates a first identification signal, wherein the level state of the first identification signal is related to the number of external battery packs, and the type identification circuit generates a second identification signal, wherein the voltage of the second identification signal is related to the type of the external battery pack. The controller calculates the number of external battery packs based on the level state of the first identification signal, and identifies the type parameters of the external battery pack based on the voltage of the second identification signal. When different numbers of external battery packs are connected to the host, the level state of the first identification signal is different. When different types of external battery packs are connected to the host, the voltage of the second identification signal is different. Therefore, the parallel pack identification circuit can identify the number of external battery packs based on the level state of the first identification signal and identify the type of external battery pack based on the voltage of the second identification signal, thereby realizing the identification of the number and type of external battery packs. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0012] Figure 1 This is a schematic diagram of the structure of one of the energy storage systems provided in the embodiments of the present application;

[0013] Figure 2 This is a schematic structural diagram of one of the packet identification circuits provided in an embodiment of the present application;

[0014] Figure 3 This is a structural diagram of one of the packet identification circuits provided in an embodiment of the present application;

[0015] Figure 4 This is a schematic diagram of a circuit structure of one of the embodiments of the present application and includes an identification circuit;

[0016] Figure 5 This is a schematic diagram of a circuit structure of one of the embodiments of the present application and includes an identification circuit;

[0017] Figure 6This is a schematic diagram of a circuit structure of one of the embodiments of the present application and includes an identification circuit;

[0018] Figure 7 This is a schematic diagram of a circuit structure of one of the embodiments of the present application and includes an identification circuit;

[0019] Figure 8 This is a schematic diagram of the circuit structure of one of the embodiments of the present application and includes an identification circuit. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0021] When the energy storage system is expanded, the external battery pack is connected in parallel with the host in the energy storage system through a connector, such as Figure 1 As shown, the energy storage system includes a host 100 and N external battery packs 200, where N is an integer greater than or equal to 1, which can be three, four or more battery packs. The specific number of battery packs can be set as needed and is not limited here.

[0022] like Figure 1 As shown, when the first external battery pack 200 is incorporated into the host 100, the first external battery pack 200 and the host 100 are connected in parallel via the connector 300. When the second external battery pack 200 is incorporated into the host 100, the second external battery pack 200 is connected in parallel with the first external battery pack 200 via the connector 300. This continues in parallel until the Nth external battery pack 200 is incorporated. After each external battery pack 200 is incorporated into the host 100, the host 100 controls the charging, discharging, or balancing operations of the external battery pack 200.

[0023] The host 100 can be expanded in both the upper and lower directions ( Figure 1 (The example of expanding the capacity at the bottom of the host 100 is shown in the figure), but there is a limit on the number of expandable battery packs. The system needs to identify the number of incorporated expansion devices and operate within the limited number. Therefore, the energy storage system needs to identify the number of external battery packs to control operations such as charging and discharging.

[0024] At the same time, the external battery packs integrated into the host 100 are of the same type, for example, all i battery packs integrated into the host are of the first type, or all i battery packs integrated into the host are of the second type. The energy storage system also needs to identify the type of the external battery pack when controlling charging and discharging operations. This is because different types of external battery packs require different charging voltages or charging currents, and their discharge voltages or discharge currents also differ. Therefore, the energy storage system needs to identify the type of the external battery pack to enable rapid charging and discharging.

[0025] Based on the above problems, an embodiment of the present application provides a parallel pack identification circuit, which can identify the number and type of external battery packs so that the energy storage system can control operations such as fast charging and discharging.

[0026] like Figure 2 As shown, the package identification circuit includes a quantity identification circuit 20, a type identification circuit 10 and a controller 30, wherein the quantity identification circuit 20 is connected to the controller 30. When the external battery pack is incorporated into the host, the quantity identification circuit 20 generates a first identification signal, and the level state of the first identification signal is related to the number of external battery packs. The controller 30 samples the first identification signal and determines the number of external battery packs based on the level state of the first identification signal.

[0027] The type identification circuit is connected to the controller. When the external battery pack is integrated into the host, the type identification circuit generates a second identification signal. The voltage of the second identification signal is related to the type of the external battery pack. The controller samples the second identification signal and identifies the type parameters of the external battery pack based on the voltage of the second identification signal. The type parameters include parameters such as the type of the external battery pack, device ID, and charging voltage or current.

[0028] When different numbers of external battery packs are incorporated into the host, the level states of the first identification signal are different. When different types of external battery packs are incorporated into the host, the voltages of the second identification signal are different.

[0029] For example, when i external battery packs are incorporated into the host, the level state of the first identification signal is the first level state; when i+1 external battery packs are incorporated into the host, the level state of the first identification signal is the second level state. The controller then identifies the number of external battery packs based on the level state of the received first identification signal.

[0030] For example: when a first type of external battery pack is incorporated into the host, the voltage of the second identification signal generated by the type identification circuit is a first voltage; when a second type of external battery pack is incorporated into the host, the voltage of the second identification signal generated by the type identification circuit is a second voltage. The controller identifies the type of the external battery pack based on the voltage of the second identification signal, thereby identifying the number and type of the external battery packs.

[0031] See also Figure 3 , Figure 3 This is a schematic diagram of the structure of a packet identification circuit provided in an embodiment of the present application. Figure 3 As shown, the type identification circuit 10 includes a first reference resistor R 02 and i coding resistors (R 1B 、R 2B ...and R iB ), the first reference resistor R 02 The first end of the first reference resistor R is connected to the first power supply VSS, wherein the first reference resistor R 02 The controller 30 is disposed in the host, the coding resistor is disposed in the external battery pack, and the first end of the coding resistor is grounded.

[0032] The type identification circuit 10 also includes a non-sensing control circuit. Each non-sensing control circuit corresponds to an external battery pack. The non-sensing control circuit includes a microcontroller, an RFID switch, and an RFID tag. The microcontroller is connected to the control terminal of the RFID switch and the RFID tag respectively. The first terminal of the RFID switch is connected to the second terminal of the coding resistor belonging to the same external battery pack. Figure 3 As shown, the i microcontrollers are respectively microcontroller 1, microcontroller 2, ..., and microcontroller i; the i RFID switches are respectively switch S1, switch S2, ..., and switch Si; and the i RFID tags are respectively RFID tag 1, RFID tag 2, ..., and RFID tag i. Each sensorless control circuit can be disposed in an external battery pack.

[0033] It is worth noting that when the host and each external battery pack form a stacked structure through the connector 300, the coding resistor in each external battery pack and the first reference resistor R 02 , the first power supply VSS device located in the host and the non-sensing control circuit located in each battery pack can form Figure 3 and Figure 4 The connection relationship shown.

[0034] When the external battery pack is incorporated into the host, the second end of the RFID switch is connected to the second end of the first reference resistor, that is, the RFID switch controls the connection state between the second end of the coding resistor and the second end of the first reference resistor. When the RFID switch is closed, the second end of the coding resistor is connected to the second end of the first reference resistor. When the RFID switch is opened, the second end of the coding resistor is disconnected from the second end of the first reference resistor.

[0035] When i external battery packs are integrated into the host computer, the controller sequentially transmits radio frequency signals of varying frequencies. Each RFID tag in the external battery pack responds to the corresponding RFID signal. If the RFID tag responds, the microcontroller connected to the tag controls the RFID switch to close, establishing a connection between the second end of the coding resistor, which belongs to the same external battery pack as the RFID switch, and the second end of the first reference resistor.

[0036] It is understandable that each RFID tag is unique. When the controller sends a RFID signal, when the RFID tag of an external battery pack incorporated into the host responds to the RFID signal, the microcontroller of the external battery pack controls the corresponding RFID switch to close, thereby establishing a connection between the second end of the coding resistor in the external battery pack and the second end of the first reference resistor.

[0037] It is worth noting that, in order to enable type identification of different types of external battery packs, resistance coding is performed based on the analog-to-digital sampling range of the controller 30 before identification. Coding resistors of different values ​​are assigned to different types of external battery packs. Ideal resistors are then assigned to correspond one-to-one with the coding resistors, with each ideal resistor having the same value as the corresponding coding resistor. Coding resistors of different values ​​are assigned to different types of external battery packs, and ideal resistors with the same value as the coding resistors are mapped one-to-one with the type parameters of the corresponding external battery packs, establishing a mapping relationship to form a set of mapping relationships.

[0038] When performing the resistance coding allocation operation, resistance coding is performed based on the analog-to-digital sampling range of the controller 30 , and coding resistors of different resistance values ​​are allocated to the multiple external battery packs.

[0039] When performing the resistance coding assignment operation, an external battery pack is incorporated into the host to determine the resistance value of the coding resistor in the external battery pack.

[0040] First, the maximum and minimum resistance values ​​of the coding resistor are determined based on the analog-to-digital sampling range of the controller 30. In some embodiments, the controller 30 includes an ADC sampling unit that samples the voltage-dividing signal and performs analog-to-digital conversion on the voltage-dividing signal to obtain the voltage value of the voltage-dividing signal. Therefore, the analog-to-digital sampling range of the controller 30 is the range of the ADC sampling unit.

[0041] Then the first reference resistor R 02 The first power supply VSS is divided by the coding resistor, and the first divided voltage signal obtained must be within the range of the ADC sampling unit to achieve correct sampling. Based on this principle, the maximum resistance value and the minimum resistance value of the coding resistor can be obtained.

[0042] If the sampling range of the ADC sampling unit is [Vmin ,V max ], in order to meet the correct sampling, the voltage of the first divided voltage signal V ADC The following constraints must be met:

[0043] V min <V ADC <V max (1)

[0044] V again ADC =(R m × VSS) / (R 02 +R m ), where R m is the resistance of the coding resistor, R 02 is the resistance of the first reference resistor, then based on formula (1) we can get:

[0045] (V min ×R 02 ) / (VSS-V min )<R m <(V max ×R 02 ) / (VSS-V max )(2)

[0046] Therefore, in order to ensure the accuracy of sampling, the resistance value of the coding resistor R m The range is [R min , R max ], the minimum resistance value is R min , the maximum resistance value is R max , where R min =(V min ×R 02 ) / (VSS-V min ), R max =(V max ×R 02 ) / (VSS-V max ).

[0047] Then based on the minimum resistance value R min With the maximum resistance R max The resistor encoding operation is performed to obtain the resistance values ​​of multiple encoding resistors. When generating the resistance values ​​of each encoding resistor, if the resistance difference between the encoding resistors is small, measurement errors and other reasons may cause mismatching of the external battery pack type, resulting in confusion.

[0048] Based on the above problems, when performing a resistance coding operation to generate the resistance value of the coding resistor, differentiated resistance intervals are designed for the resistance values ​​of the various coding resistors to prevent confusion and reduce the risk of mismatching multiple external battery pack types.

[0049] In the embodiment of the present application, first, based on the analog-to-digital sampling range of the controller 30, the voltage of the first power supply VSS and the first reference resistor R 02 The median resistance value is determined based on the resistance value of the analog-to-digital sampling range, and the minimum allowable interval is then determined based on the median resistance value. Specifically, when the median voltage of the analog-to-digital sampling range is used as the voltage of the first voltage-divided signal, the corresponding resistance value of the coding resistor is determined as the median resistance value. The median voltage is determined based on the analog-to-digital sampling range of the controller 30, where the median voltage is the middle value of the analog-to-digital sampling range.

[0050] The median resistance value is determined by the following formula:

[0051] R base =V mid ×R 02 / (VSS-V mid )(3)

[0052] Among them, R base is the median resistance value, V mid is the mid-range voltage, R 02 is the resistance of the first reference resistor.

[0053] If the analog-to-digital sampling range is [V min ,V max ], then the median voltage V mid =(V max +V min ) / 2, when the resistance of the coding resistor is the middle resistance value, it is equal to the first reference resistor R 02 The voltage of the first voltage-divided signal generated by dividing the first power source VSS is a mid-voltage. Therefore, the corresponding mid-resistance value can be inferred based on the mid-voltage.

[0054] Then, the minimum allowable interval is determined based on the median resistance value. The minimum allowable interval can make the interval between the resistance values ​​of adjacent coding resistors large enough to avoid identification conflicts caused by measurement errors.

[0055] Specifically, first obtain the maximum measurement error, and then determine the minimum allowable interval using the following formula:

[0056] R gap =w×ε×R base (4)

[0057] Among them, R gap is the minimum allowed interval, w is the weight, ε is the maximum measurement error, R base is the median resistance value.

[0058] w can be set as needed. In the embodiment of the present application, w is 2. ε is the maximum measurement error, which refers to the maximum allowable error between the measured resistance value of the coding resistor and the assigned resistance value of the coding resistor. It can be set as needed. In the embodiment of the present application, ε is 5%. That is, if the error between the actual measured value and the assigned resistance value of the coding resistor is less than or equal to ε, it is considered that the actual measured value and the assigned resistance value of the coding resistor meet the error requirement or match.

[0059] In some embodiments, in order to take noise interference into account in the minimum allowable interval and further reduce the measurement error, the minimum allowable interval can also be set at the middle resistance value R gap Add a safety margin δ to the base to get the final minimum allowable interval. gap Multiply by the weight corresponding to the noise interference to obtain the safety margin δ, for example, safety margin δ = 2% × R base .

[0060] Finally, based on the minimum allowable interval, the resistance values ​​from the minimum resistance value to the maximum resistance value are divided to obtain the resistance values ​​of several coding resistors. min ,R max ] is split and the difference between the resistance values ​​obtained by splitting meets the minimum allowable interval. For example, the resistance values ​​of each coding resistor are R min , R min +R gap , R min +2.5×R gap ...and so on, until the resistance value of the last coding resistor is obtained.

[0061] It should be noted that in [R min ,R max ] When the resistance values ​​of the coding resistors are obtained by segmentation, they can be evenly split so that the differences between the resistance values ​​of the coding resistors are equal, or they can be unevenly split so that the differences between the resistance values ​​of the coding resistors are equal or unequal, as long as the difference between the resistance values ​​of two adjacent coding resistors meets the minimum allowable interval.

[0062] After obtaining the resistance value of each coding resistor, assign each coding resistor to different types of external battery packs. Each coding resistor corresponds to each type of external battery pack. For example, assign the resistance value to R min The coding resistor is assigned to the first type of external battery pack, and the resistance is R min +R gap The coding resistor is assigned to the second type of external battery pack, and the resistance is R min +2.5×R gapThe coding resistor is assigned to the third type of external battery pack, and so on, until the last coding resistor is assigned to an external battery pack of a different type from the aforementioned ones.

[0063] Among them, the coding resistor can be a single resistor or multiple resistors connected in parallel. For example, if the coding resistor is a single resistor, the resistance of the single resistor is the resistance of the coding resistor. If the coding resistor is multiple resistors, the resistance of the multiple resistors connected in parallel is the resistance of the coding resistor.

[0064] Then, a mapping relationship set is established, wherein the mapping relationship set includes multiple mapping data units. The multiple mapping data units are constructed as follows: an ideal resistor corresponding to the coding resistor is assigned to each mapping data unit, and the resistance value of each ideal resistor is equal to the resistance value of the corresponding coding resistor. Then, a mapping relationship is established between the ideal resistor of each mapping data unit and the type parameter of the external battery pack of the corresponding coding resistor.

[0065] That is, the coding resistor and the ideal resistor are mapped one by one, and the resistance value of the coding resistor is equal to the resistance value of the ideal resistor. Then, a mapping relationship is established between the ideal resistor and the type parameter of the corresponding external battery pack. For example, the type parameter includes the model and ID number of the external battery pack, as well as the target output voltage and maximum current of the external battery pack. The mapping relationship can be expressed as (M, R m , I DM , V _targetM , I _maxM ), where M is the device model of the external battery pack, R m is the resistance of the ideal resistor, I DM is the ID number of device M, V _targetM is the target output voltage of device M, I _maxM is the maximum current of device M.

[0066] Taking the allocation of coded resistors for two types of external battery packs and the construction of two mapping data units as an example, the process of establishing a set of resistance coding and mapping relationships is described.

[0067] Different resistance values ​​are assigned to the coding resistors in the two types of external battery packs. If the two types of external battery packs are respectively a first external battery pack and a second external battery pack, and the corresponding coding resistors are respectively a first coding resistor and a second coding resistor, then the first coding resistor is assigned to the first external battery pack, and its resistance value is the first resistance value, and the second coding resistor is assigned to the second external battery pack, and its resistance value is the second resistance value, and the first resistance value and the second resistance value are a pair of [R min ,R max ] is obtained by segmentation, and the difference between the first resistance value and the second resistance value meets the minimum allowable interval, for example: the first resistance value and the second resistance value are R min and Rmin +R gap .

[0068] Then, two mapping data units are constructed, and a first ideal resistor corresponding to the first resistance value is assigned to the first mapping data unit. The resistance value of the first ideal resistor is equal to the first resistance value. Then, a mapping relationship is established between the first ideal resistor and the type parameter of the first external battery pack. The mapping relationship is expressed as (M1, R m1 , I DM1 , V _targetM1 , I _maxM1 ), where M1 refers to the device model of the first external battery pack, R M1 Refers to the resistance of the first ideal resistor, I DM1 Refers to the ID number of device M1, V _targetM1 is the target output voltage of device M1, I _maxM1 Refers to the maximum current of the device M1. Assign a second ideal resistor corresponding to the second resistance value to the second mapping data unit. The resistance value of the second ideal resistor is equal to the second resistance value. Then, a mapping relationship is established between the second ideal resistor and the type parameter of the second external battery pack. The mapping relationship is expressed as (M2, R m2 , I DM2 , V _targetM2 , I _maxM2 ), where M2 refers to the device model of the second external battery pack, R M2 Refers to the resistance of the second ideal resistor, I DM2 Refers to the ID number of device M2, V _targetM2 is the target output voltage of device M2, I _maxM2 It refers to the maximum current of the device M2. Finally, the two mapping data units form a mapping relationship set.

[0069] Therefore, the mapping relationship set includes the mapping relationship between the type parameters of each external battery pack and the ideal resistor, and the resistance value of the ideal resistor is equal to the coding resistor of the external battery pack, and they correspond one to one.

[0070] In a first specific embodiment, during the sequential closing of i RFID switches, when the i-th RFID switch is closed, the connection between the i-th coding resistor, the first i-1 coding resistors, and the first reference resistor, after being connected in parallel, forms the i-th voltage-dividing node, and each of the i-th voltage-dividing nodes generates an i-th first voltage-dividing signal. When the number of first voltage-dividing signals reaches the number of external battery packs, the controller is further configured to stop transmitting the RF signal, and the i-th first voltage-dividing signals form the second identification signal. In this embodiment, once the RFID switch is closed, it remains closed without opening.

[0071] For example, if the controller transmits an RF signal at frequency f1, the RFID tag in the external battery pack corresponding to frequency f1 will respond to the RF signal, while other RFID tags will not. The microcontroller in the external battery pack then controls the corresponding RFID switch to close, thereby establishing a connection between the second end of the coding resistor in the external battery pack and the second end of the first reference resistor.

[0072] If the controller transmits an RF signal at frequency f2, the RFID tag in the external battery pack corresponding to frequency f2 responds to the signal, while other RFID tags do not. The microcontroller in the external battery pack then controls the corresponding RFID switch to close, thereby establishing a connection between the second end of the coding resistor in the external battery pack and the second end of the first reference resistor.

[0073] If the external battery packs are sorted according to the order in which the RFID switches are closed, for example, when the controller sends the first RF signal, the RFID switch corresponding to the first RF signal is closed, then the external battery pack corresponding to the RFID switch is called the first external battery pack, and the coding resistor in the first external battery pack is connected to the first reference resistor. The coding resistor and the first reference resistor divide the first power supply VSS to generate a first first divided voltage signal.

[0074] When the controller sends a second RF signal, the RFID switch corresponding to the second RF signal is closed, and the external battery pack corresponding to the RFID switch is the second external battery pack. The coding resistor in the second external battery pack is connected in parallel with the coding resistor in the first external battery pack, and then connected to the first reference resistor. The two parallel coding resistors and the first reference resistor divide the first power supply VSS to generate a second first divided voltage signal.

[0075] By analogy, when the controller transmits the i-th RF signal, the RFID switch corresponding to the i-th RF signal is closed. The external battery pack corresponding to the RFID switch is the i-th external battery pack. The coding resistor in the i-th external battery pack is then connected in parallel with the previous i-1 coding resistors and then connected to the first reference resistor. The i-th parallel coding resistors and the first reference resistor divide the first power supply VSS to generate the i-th first divided voltage signal. To prevent the controller from transmitting invalid RF signals, the controller determines the number of received first divided voltage signals and stops transmitting RF signals when the number of received first divided voltage signals reaches the number of external battery packs.

[0076] Specifically, if Figure 3 As shown, when the controller sends the first RF signal, the RFID switch S1 in the first external battery pack is closed, and the external battery pack corresponding to the RFID switch S1 is the first external battery pack, then the coding resistor R1B With the first reference resistor R 02 The connection forms the first voltage divider node, and the coding resistor R 1B With the first reference resistor R 02 The first power source VSS is voltage-divided to generate a first first voltage-divided signal at a first voltage-divided node, and the controller samples the first voltage-divided signal.

[0077] When the controller sends the second RF signal, the RFID switch S2 is closed. The external battery pack corresponding to the RFID switch S2 is the second external battery pack. The coding resistor R 2B With the first reference resistor R 02 Connect, and the coding resistor R 1B With the coding resistor R 2B Connect in parallel with the first reference resistor R 02 The connection forms a second voltage divider node, and the parallel coding resistor R 1B With the coding resistor R 2B , and the first reference resistor R 02 The first power source VSS is voltage-divided to generate a second first voltage-divided signal at both the first voltage-divided node and the second voltage-divided node, and the controller samples the second first voltage-divided signal.

[0078] By analogy, when the controller sends the ith RF signal, the RFID switch S i Closed, and the RFID switch S i The corresponding external battery pack is the i-th external battery pack, and the coding resistor R iB With the first reference resistor R 02 Connect, and the coding resistor R 1B , coding resistor R 2B Until the coding resistor R iB Connect in parallel with the first reference resistor R 02 Connect to form the i-th voltage divider node, and the parallel coding resistor R 1B , coding resistor R 2B Until the coding resistor R iB , and the first reference resistor R 02 The first power supply VSS is voltage-divided to generate an i-th first voltage-divided signal at each of i voltage-divided nodes, and the controller samples the i-th first voltage-divided signal. When the number of first voltage-divided signals reaches the number of external battery packs, the controller stops transmitting the RF signal, and the i-th first voltage-divided signals form a second identification signal.

[0079] In the first embodiment, the controller 30 identifies the types of i external battery packs according to the voltages of the i received first voltage-divided signals.

[0080] Specifically, first, a first parallel resistor is determined based on the i-1th first voltage-dividing signal, the voltage-dividing principle, and the first reference resistor, wherein the first parallel resistor is the total resistance of the first i-1 coding resistors connected in parallel. Then, a second parallel resistor is determined based on the i-th first voltage-dividing signal, the voltage-dividing principle, and the first reference resistor, wherein the second parallel resistor is the total resistance of the first i coding resistors connected in parallel. Then, based on the first parallel resistor, the second parallel resistor, and the parallel principle, the measured resistance value of the i-th coding resistor is determined. Finally, a resistance value search is performed in a mapping relationship set to obtain a target ideal resistor and a target type parameter, wherein the target ideal resistor is an ideal resistor that matches the numerical value of the measured resistance value, and the target type parameter is the type parameter of the i-th external battery pack. The mapping relationship set includes an ideal resistor that matches the coding resistor and a type parameter of the external battery pack that corresponds one-to-one to the ideal resistor.

[0081] For example: Figure 3 As shown, assuming that the RFID switches S1, S2...S i When the first RFID switch S1 is closed, if i is 1, the measured resistance value of the first coding resistor is determined by the following formula based on the first voltage division signal, the voltage division principle, and the first reference resistor:

[0082] R 并1 =R 1B =V1×R 02 / (VSS-V1)(5)

[0083] Among them, R 并1 is the total resistance of the first coding resistor in parallel, R 1B is the measured resistance value of the first coding resistor, V1 is the voltage of the first divided voltage signal, R 02 is the resistance of the first reference resistor, and VSS is the voltage of the first power supply.

[0084] When i is any integer from 2 to i, the second RFID switch S2 to the i-th RFID switch S i Close them in sequence and determine the first parallel resistance by the following formula:

[0085] R 并（i-1） =V i-1 ×R 02 / (VSS-V i-1 )(6)

[0086] Among them, R 并（i-1） is the total resistance of the first i-1 encoding resistors connected in parallel, V i-1 is the voltage of the (i-1)th first voltage-divided signal.

[0087] The second parallel resistance is determined by the following formula:

[0088] R 并i =V i ×R 02 / (VSS-V i )(7)

[0089] Among them, R 并i is the total resistance of the first i encoding resistors in parallel, V i is the voltage of the i-th first voltage-divided signal.

[0090] The measured resistance value of the i-th coding resistor is then determined by the following formula:

[0091] R iB =R 并（i-1） ×R 并i / (R 并（i-1） -R 并i )(8)

[0092] For the above formula (7), the resistance value of multiple external battery packs connected in parallel is calculated, rather than the corresponding measured value of the coded resistance of each external battery pack. In this way, when the switch is closed for the i-th time, it is necessary to follow the voltage of the first voltage-divided signal generated according to the previous i-1-th closing situation to obtain the current closed RFID switch S i Measured value of the coding resistor of the external battery pack.

[0093] The process of obtaining type parameters is described using the first and second external battery packs as examples. The first and second external battery packs are different types. When the first and second external battery packs are integrated into a host computer, the controller emits a first RF signal. The RFID tag within the first external battery pack responds to the RF signal. The microcontroller within the first external battery pack controls the corresponding RFID switch to close, connecting the first coding resistor within the first external battery pack to the first reference resistor. This connection forms a first voltage divider node, and a first first voltage divider signal is generated at the first voltage divider node. The controller then emits a second RF signal. The RFID tag within the second external battery pack responds to the RF signal. The microcontroller within the second external battery pack controls the corresponding RFID switch to close, connecting the second coding resistor within the second external battery pack to the first coding resistor in parallel. The parallel connection of the first and second coding resistors is then connected to the first reference resistor, forming a second voltage divider node. A second first voltage divider signal is generated at the second voltage divider node.

[0094] The measured resistance value of the first coding resistor is calculated by the following formula:

[0095] R 并1 =R 1B=V1×R 02 / (VSS-V1)(9)

[0096] Among them, R 并1 is the previous coding resistor (i.e. the first coding resistor R 1B ) total resistance after parallel connection, R 1B is the measured resistance value of the first coding resistor, V1 is the voltage of the first first voltage division signal, R 02 is the resistance of the first reference resistor, and VSS is the voltage of the first power supply.

[0097] In the embodiment of the present application, the first parallel resistor is equal to the measured resistance value of the first coding resistor, and then the second parallel resistor is calculated by the following formula:

[0098] R 并2 =V2×R 02 / (VSS-V2)(10)

[0099] Among them, R 并2 For the first two coding resistors (i.e. the first coding resistor R 1B With the second coding resistor R 2B ) is the total resistance after parallel connection, and V2 is the voltage of the second first divided voltage signal.

[0100] The measured resistance value of the second coding resistor is then determined by the following formula:

[0101] R 2B =R 并1 ×R 并2 / (R 并1 -R 并2 )=R 1B ×R 并2 / (R 1B -R 并2 )(11)

[0102] The measured resistance value of the first coding resistor and the measured resistance value of the second coding resistor can be calculated according to the voltage of the first first voltage-divided signal and the voltage of the second first voltage-divided signal.

[0103] Thus, based on the voltage of the i-1th first voltage-divided signal, the voltage of the i-th first voltage-divided signal can be used to obtain the measured resistance value of the i-th coding resistor. A mapping relationship set is then obtained, and a target ideal resistor corresponding to the measured resistance value is searched from the mapping relationship set to obtain the target ideal type parameter corresponding to the target ideal resistor, i.e., the type parameter of the i-th external battery pack.

[0104] When i external battery packs of different types are connected to the host, i first voltage-dividing signals are generated at the voltage-dividing node. The controller 30 can sequentially determine the measured resistance values ​​of i coding resistors (such as the above formulas (5) to (8)) through the i first voltage-dividing signals, and then determine the target ideal resistor that matches it from the mapping relationship set through the measured resistance value, and then determine the type parameter that matches it through the target ideal resistor.

[0105] The controller 30 traverses the ideal resistance in the mapping relationship. If the absolute value of the difference between the ideal resistance and the measured resistance value is less than the preset error, it is determined that the ideal resistance value matches the measured resistance value, and the ideal resistance value is the target ideal resistance value. Then, the type parameter of the external battery pack corresponding to the target ideal resistance is determined from the mapping relationship set.

[0106] In the second embodiment, after a preset time after the RFID switch is closed, the microcontroller controls the RFID switch to be opened, and the second end of the encoding resistor belonging to the same external battery pack as the RFID switch is disconnected from the second end of the first reference resistor.

[0107] In the process of sequentially closing the i RFID switches, when the i RFID switch is closed, the connection between the i encoding resistor and the first reference resistor forms the i th voltage dividing node, and the i th first voltage dividing signal is generated at the i th voltage dividing node. When the number of the first voltage dividing signals reaches the number of external battery packs, the controller stops sending the RF signal.

[0108] For example: Figure 3 As shown, when the controller 30 sends the first RF signal, the RFID switch S1 in the first external battery pack is closed, and the external battery pack corresponding to the RFID switch S1 is the first external battery pack, then the coding resistor R 1B With the first reference resistor R 02 The connection forms the first voltage divider node, and the coding resistor R 1B With the first reference resistor R 02 The first power source is voltage-divided to generate a first voltage-divided signal, and the controller 30 samples the first voltage-divided signal.

[0109] After the preset time, the microcontroller 1 controls the RFID switch S1 in the first external battery pack to be disconnected, and the first coding resistor R 1B With the first reference resistor R 02 The controller 30 sends a second RF signal, the RFID switch S2 is closed, and the external battery pack corresponding to the RFID switch S2 is the second external battery pack, then the coding resistor R 2B With the first reference resistor R 02 Connect, and the coding resistor R 2BWith the first reference resistor R 02 The connection forms a second voltage divider node, and the coding resistor R 2B With the first reference resistor R 02 The first power supply is voltage-divided to generate a second first voltage-divided signal, and the controller 30 samples the second first voltage-divided signal.

[0110] After the preset time, the microcontroller 2 controls the RFID switch S2 in the second external battery pack to be disconnected, and the second coding resistor R 2B With the first reference resistor R 02 The controller 30 sends a third RF signal, the RFID switch S3 is closed, and the external battery pack corresponding to the RFID switch S3 is the third external battery pack, then the coding resistor R 3B With the first reference resistor R 02 The connection forms the third voltage divider node, and the coding resistor R 3B With the first reference resistor R 02 The first power supply is voltage-divided to generate a third first voltage-divided signal, and the controller 30 samples the third first voltage-divided signal.

[0111] By analogy, after the preset time, the microcontroller i controls the RFID switch in the i-1th external battery pack to be disconnected, and the i-1th coding resistor R （i-1）B With the first reference resistor R 02 Disconnect. The controller 30 sends the ith RF signal, and the RFID switch S i Closed, the external battery pack corresponding to the RFID switch Si is the i-th external battery pack, then the coding resistor R iB With the first reference resistor R 02 The connection forms the i-th voltage divider node, and the coding resistor R iB With the first reference resistor R 02 The first power source VSS is voltage-divided to generate an i-th first voltage-divided signal, and the controller 30 samples the i-th first voltage-divided signal. When the number of the first voltage-divided signals reaches the number of external battery packs, the controller stops transmitting the RF signal, and the i-th first voltage-divided signals form a second identification signal.

[0112] The controller 30 identifies the types of the i external battery packs according to the voltages of the i received first voltage-divided signals.

[0113] Specifically, first, the measured resistance value of the i-th coding resistor is determined based on the i-th first voltage division signal, the voltage division principle and the first reference resistor, and then the resistance value is searched in the mapping relationship set to obtain the target ideal resistor and the target type parameter, wherein the target ideal resistor is an ideal resistor that matches the numerical value of the measured resistance value, the target type parameter is the type parameter of the i-th external battery pack, and the mapping relationship set includes the ideal resistor that matches the coding resistor and the type parameter of the external battery pack that corresponds one-to-one to the ideal resistor.

[0114] For example: Figure 3 As shown, based on the i-th first voltage division signal, the voltage division principle and the first reference resistor, the measured resistance value of the i-th coding resistor is determined by the following formula:

[0115] R iB =V i ×R 02 / (VSS-V i )(12)

[0116] Among them, R iB is the measured resistance value of the i-th coding resistor, V i is the voltage of the i-th first divided voltage signal, R 02 is the resistance of the first reference resistor, and VSS is the voltage of the first power supply.

[0117] Thus, the measured resistance value of the i-th coding resistor can be obtained based on the voltage of the i-th first voltage-divided signal. A mapping relationship set is then obtained, and a target ideal resistor corresponding to the measured resistance value is searched from the mapping relationship set to obtain the target ideal type parameter corresponding to the target ideal resistor, i.e., the type parameter of the i-th external battery pack.

[0118] In some embodiments, the controller 30 infers the measured resistance value from the voltage value of the first voltage-divided signal as the original resistance value of the coding resistor. To improve measurement accuracy, the original resistance value is temperature compensated to obtain the measured resistance value. The temperature-compensated measured resistance value is more accurate and more consistent with the actual resistance value of the coding resistor, thereby improving the resistance measurement accuracy of the coding resistor.

[0119] Due to measurement errors or measurement accuracy issues, the measured resistance value R iB The resistance value of the ideal resistor is not necessarily the same as that of the ideal resistor. Therefore, the ideal resistors in the mapping relationship set are traversed to determine the resistance value of each ideal resistor and the measured resistance value R iB Is the absolute value of the difference between the ideal resistor and the measured resistance value R less than the preset error? If so, the ideal resistor is confirmed to be the same as the measured resistance value R. iB Matches and will be measured with the resistance value R iBThe matched ideal resistance is determined as the target ideal resistance, and the type parameters of the external battery pack corresponding to the target ideal resistance are then determined.

[0120] In the above embodiment, if Figure 3 As shown, the type identification circuit 10 further includes a filter circuit, which includes a resistor R 03 With capacitor C1, resistor R 03 Connected between the controller and the voltage divider node, one end of the capacitor C1 is connected to the controller and the resistor R 03 The first voltage-divided signal is filtered by the filter circuit and then transmitted to the controller 30 .

[0121] In the above embodiment, in order to reduce the measurement error, in the above type identification circuit, the coding resistor assigned to the external battery pack can be formed by connecting the first resistor, the second resistor and the third resistor in parallel, that is, R iB It can be formed by connecting three resistors in parallel.

[0122] See also Figure 4 , Figure 4 This is a schematic diagram of the structure of a packet identification circuit provided in an embodiment of the present application. Figure 4 As shown, the quantity recognition circuit 20 includes: i matching resistors (resistance R 1A , resistor R 2A ...resistor R iA ), the second reference resistor R 01 and N comparison circuits 21 , wherein i is a positive integer from 0 to N, and N is a positive integer greater than or equal to 1.

[0123] It is worth noting that when the host and each external battery pack form a stacked structure through the connector 300, the matching resistors in each external battery pack and the second reference resistor R 01 , the second power supply VDD device located in the host can form Figure 4 and Figure 5 The connection relationship shown.

[0124] The second reference resistor R 01 The first end of is connected to the second power supply VDD, and the matching resistor is set in the external battery pack and corresponds to the external battery pack one by one. The resistance of the matching resistor is the same. When i external battery packs are incorporated into the host, i matching resistors are connected in parallel to form a parallel voltage divider module. The first end of the parallel voltage divider module is connected to the second reference resistor R 01 The second end of the parallel voltage divider module is connected to the ground GND, and the second reference resistor R 01 The parallel voltage dividing module divides the second power supply VDD to obtain a second voltage dividing signal. Thus, the first end of the parallel voltage dividing module can obtain the second voltage dividing signal about the second power supply.

[0125] For example: If the i matching resistors are resistors R 1A , resistor R 2A ...resistor R iA , when the first external battery pack is connected to the host, the resistor R 1A The first end and the second reference resistor R 01 The second end of the resistor R 1A With the second reference resistor R 01 The second power supply VDD is divided to obtain a second divided voltage signal. The voltage of the second divided voltage signal is Vin1=VDD×R 1A / (R 01 +R 1A ).

[0126] When the second external battery pack is connected to the host, the resistor R 1A With resistor R 2A Connect in parallel to form a voltage divider resistor module, resistor R 2A The first end and the second reference resistor R 01 The second end of the resistor R 1A , resistor R 2A and the second reference resistor R 01 The second power supply VDD is divided to obtain a second divided voltage signal. The voltage of the second divided voltage signal is Vin2=VDD×(R 1A ||R 2A ) / (R 01 +(R 1A ||R 2A )), where || is the parallel symbol, R 1A ||R 2A Represents R 1A With R 2A The total resistance after parallel connection.

[0127] By analogy, when the i-th external battery pack is connected to the host, the resistor R 1A , resistor R 2A Until the resistor R iA are connected in parallel to form a voltage divider resistor module, resistor R iA The first end and the second reference resistor R 01 The second end of the resistor R 1A , resistor R 2A Until the resistor R iA Common with the second reference resistor R 01 The second power supply VDD is divided to obtain a second divided voltage signal, and the voltage of the second divided voltage signal is Vin i =VDD×(R 1A ||R 2A||...||R iA ) / (R 01 +(R 1A ||R 2A ||...||R iA )), where || is the parallel symbol, R 1A ||R 2A ||...||R iA Represents R 1A 、R 2A , ... and R iA The total resistance after parallel connection.

[0128] Therefore, when different numbers of external battery packs are connected to the host, the voltage of the second divided voltage signal is different. The voltage of the second divided voltage signal decreases as the number of external battery packs increases, and is always lower than the voltage of the second power supply VDD.

[0129] The first input terminal of each comparison circuit 21 is connected to the second voltage-divided signal, and the second input terminal of each comparison circuit 21 is connected to a reference voltage. For example, the second input terminal of the first comparison circuit is connected to the first reference voltage Vref1, the second input terminal of the second comparison circuit is connected to the second reference voltage Vref2, and so on. The second input terminal of the Nth comparison circuit is connected to the Nth reference voltage Vref N , wherein the voltages of the reference voltages are different, for example, the voltages of the reference voltages are successively increased or decreased, that is, Vref1 <Vref2<...<Vref N , or, Vref1>Vref2>...>Vref N .

[0130] The voltage of the second power supply VDD is greater than the maximum value of the reference voltages. If the values ​​of the reference voltages increase in sequence, the voltage of the second power supply VDD is greater than Vref N If the values ​​of the reference voltages decrease in sequence, the voltage of the second power supply VDD is greater than Vref1.

[0131] The comparison circuit 21 compares the voltage of the second voltage-divided signal with a corresponding reference voltage and outputs a corresponding comparison signal. The N comparison signals reflect the number of external battery packs.

[0132] For example, if the reference voltage values ​​are increasing in sequence, that is, Vref1<Vref2<...<Vref N , and when the voltage at the first input terminal of the comparison circuit is less than the voltage at the second input terminal thereof, the comparison circuit outputs a high-level comparison signal.

[0133] When there is no external battery pack incorporated, the first input terminals of N comparison circuits are all connected to the second power supply VDD, and the voltage of the second power supply VDD is greater than any reference voltage. Then, all N comparison circuits output comparison signals of low level, determining that no external battery pack is incorporated.

[0134] When one external battery pack is incorporated, resistor R 1A and the second reference resistor R 01 divide the voltage of the second power supply VDD to obtain a second divided voltage signal, and the voltage of the second divided voltage signal is Vin1. Among them, Vin1 is transmitted to the first input terminals of N comparison circuits, and Vref N-1 <Vin1<Vref N , then the Nth comparison circuit outputs a comparison signal of high level, and other comparison circuits output comparison signals of low level. Then, it is determined that the number of external battery packs is one.

[0135] When two external battery packs are incorporated, resistor R 1A , resistor R 2A and the second reference resistor R 01 divide the voltage of the second power supply VDD to obtain a second divided voltage signal, and the voltage of the second divided voltage signal is Vin2. Among them, Vin2 is transmitted to the first input terminals of N comparison circuits, and Vref N-2 <Vin2<Vref N-1 , then the Nth comparison circuit outputs a comparison signal of high level, the (N - 1)th comparison circuit outputs a comparison signal of high level, and other comparison circuits output comparison signals of low level. Then, it is determined that the number of external battery packs is two.

[0136] And so on. When N external battery packs are incorporated, resistor R 1A to resistor R N and the second reference resistor R 01 divide the voltage of the second power supply VDD to obtain a second divided voltage signal, and the voltage of the second divided voltage signal is Vin N , among which, Vin N is transmitted to the first input terminals of N comparison circuits, and Vin N <Vref1. Then, the first comparison circuit outputs a comparison signal of high level, the second comparison circuit outputs a comparison signal of high level, and so on. The Nth comparison circuit also outputs a comparison signal of high level. Then, it is determined that the number of external battery packs is N.

[0137] For another example, if the values of the reference voltages decrease in sequence, that is, Vref N <Vref N-1 <...<Vref1, and when the voltage at the first input terminal of the comparison circuit is less than the voltage at its second input terminal, the comparison circuit outputs a comparison signal of high level.

[0138] When no external battery pack is incorporated, the first input terminals of N comparison circuits are all connected to the second power supply VDD, and the voltage of the second power supply VDD is greater than any reference voltage. Then, all N comparison circuits output comparison signals with low levels, determining that no external battery pack is incorporated.

[0139] When one external battery pack is incorporated, the resistor R 1A and the second reference resistor R 01 divide the voltage of the second power supply VDD to obtain a second divided voltage signal. The voltage of the second divided voltage signal is Vin1. Among them, Vin1 is transmitted to the first input terminals of N comparison circuits, and Vref2 < Vin1 < Vref1. Then, the first comparison circuit outputs a comparison signal with a high level, and other comparison circuits output comparison signals with low levels, determining that the number of external battery packs incorporated is one.

[0140] When two external battery packs are incorporated, the resistor R 1A , the resistor R 2A and the second reference resistor R 01 divide the voltage of the second power supply VDD to obtain a second divided voltage signal. The voltage of the second divided voltage signal is Vin2. Among them, Vin2 is transmitted to the first input terminals of N comparison circuits, and Vref3 < Vin2 < Vref2. Then, the first comparison circuit outputs a comparison signal with a high level, the second comparison circuit outputs a comparison signal with a high level, and other comparison circuits output comparison signals with low levels, determining that the number of external battery packs incorporated is two.

[0141] By analogy, when N external battery packs are incorporated, the resistors R 1A to the resistor R N and the second reference resistor R 01 divide the voltage of the second power supply VDD to obtain a second divided voltage signal. The voltage of the second divided voltage signal is Vin N , among which, Vin N is transmitted to the first input terminals of N comparison circuits, and Vin N < Vref N . Then, the first comparison circuit outputs a comparison signal with a high level, the second comparison circuit outputs a comparison signal with a high level, and by analogy, the Nth comparison circuit also outputs a comparison signal with a high level, determining that the number of external battery packs incorporated is N.

[0142] For another example, if the values of the reference voltages increase in sequence, that is, Vref1 < Vref2 <... < Vref N , and when the voltage at the first input terminal of the comparison circuit is greater than the voltage at its second input terminal, the comparison circuit outputs a comparison signal with a high level.

[0143] When no external battery pack is incorporated, the first input terminals of the N comparison circuits are all incorporated into the second power supply VDD, and the voltage of the second power supply VDD is greater than any reference voltage. Then, the N comparison circuits all output comparison signals of high level, determining that no external battery pack is incorporated.

[0144] When an external battery pack is incorporated, the resistor R 1A and the second reference resistor R 01 divide the voltage of the second power supply VDD to obtain a second divided voltage signal, and the voltage of the second divided voltage signal is Vin1. Among them, Vin1 is transmitted to the first input terminals of the N comparison circuits, and Vref N-1 <Vin1<Vref N , then the Nth comparison circuit outputs a comparison signal of low level, and the other comparison circuits output comparison signals of high level, determining that the number of external battery packs is one.

[0145] By analogy, when N external battery packs are incorporated, the resistors R 1A to the resistor R N and the second reference resistor R 01 divide the voltage of the second power supply VDD to obtain a second divided voltage signal, and the voltage of the second divided voltage signal is Vin N , among which, Vin N is transmitted to the first input terminals of the N comparison circuits, and Vin N <Vref1, then the first comparison circuit to the Nth comparison circuit all output comparison signals of low level, determining that the number of external battery packs is N.

[0146] For another example, if the values of the reference voltages decrease in sequence, that is, Vref N <Vref N-1 <...<Vref1, and when the voltage at the first input terminal of the comparison circuit is greater than the voltage at its second input terminal, the comparison circuit outputs a comparison signal of high level.

[0147] When no external battery pack is incorporated, the first input terminals of the N comparison circuits are all incorporated into the second power supply VDD, and the voltage of the second power supply VDD is greater than any reference voltage. Then, the N comparison circuits all output comparison signals of high level, determining that no external battery pack is incorporated.

[0148] When an external battery pack is incorporated, the resistor R 1A and the second reference resistor R 01The second power supply VDD is divided in voltage to obtain a second divided voltage signal, and the voltage of the second divided voltage signal is Vin1. Among them, Vin1 is transmitted to the first input ends of N comparison circuits, and Vref2 < Vin1 < Vref1, then the first comparison circuit outputs a comparison signal with a low level, and the other comparison circuits output comparison signals with a high level, and it is determined that the number of externally connected battery packs is one.

[0149] And so on, when N externally connected battery packs are incorporated, the resistor R 1A to the resistor R N and the second reference resistor R 01 divide the second power supply VDD in voltage to obtain a second divided voltage signal, and the voltage of the second divided voltage signal is Vin N , among which, Vin N is transmitted to the first input ends of N comparison circuits, and Vin N < Vref N , then the first comparison circuit to the Nth comparison circuit all output comparison signals with a low level, and it is determined that the number of externally connected battery packs is N.

[0150] In some embodiments, the second reference resistor R 01 and the N comparison circuits 21 are both arranged in the host. When an externally connected battery pack is incorporated, the externally connected battery pack is connected in parallel with the host through a connector, and the matching resistor in the externally connected battery pack is connected to the second end of the second reference resistor R 01 in the host. When multiple externally connected battery packs are incorporated, the multiple externally connected battery packs are connected in parallel through a connector, and then connected in parallel with the host through the connector. The matching resistors in each externally connected battery pack form a parallel voltage division module, and then are connected to the second end of the second reference resistor R 01 .

[0151] In some embodiments, in order to make the circuit design simpler, the resistance values of the N matching resistors can be set to the same resistance value, that is, the resistance values of the resistor R 1A to the resistor R iA are all the same, so that the voltage of the second divided voltage signal changes every time an externally connected battery pack is incorporated.

[0152] The output ends of the N comparison circuits are respectively connected to the controller 30. For example: the output end of the first comparison circuit is electrically connected to the first pin of the controller 30, the output end of the second comparison circuit is electrically connected to the second pin of the controller 30, and so on, the output end of the Nth comparison circuit is electrically connected to the Nth pin of the controller 30.

[0153] The controller 30 analyzes the N comparison signals to obtain an identification result. For example: if the values of the reference voltages increase in sequence, that is, Vref1 < Vref2 <... < Vref N, and when the voltage at the first input terminal of the comparison circuit is less than the voltage at the second input terminal thereof, the comparison circuit outputs a high-level comparison signal.

[0154] If the first to Nth pins of the controller 30 all receive low-level comparison signals, it is determined that no battery pack is incorporated.

[0155] If the Nth pin of the controller 30 receives a high-level comparison signal, and the first pin to the N-1th pin of the controller 30 all receive low-level comparison signals, it is determined that the number of the external battery pack is one.

[0156] If the Nth pin of the controller 30 receives a high-level comparison signal, the N-1th pin of the controller 30 receives a high-level comparison signal, and the first pin of the controller 30 to the N-2th pin of the controller 30 all receive low-level comparison signals, it is determined that the number of external battery packs is two.

[0157] If the first pin to the Nth pin of the controller 30 all receive high-level comparison signals, it is determined that the number of external battery packs is N.

[0158] For another example, if the reference voltage value is decreasing in sequence, that is, Vref N <Vref N-1 <...<Vref1, and when the voltage at the first input terminal of the comparison circuit is lower than the voltage at the second input terminal thereof, the comparison circuit outputs a high-level comparison signal.

[0159] If the controller 30 receives N low-level comparison signals, it determines that no external battery pack is connected.

[0160] If the first pin of the controller 30 receives a high-level comparison signal, and the second pin to the Nth pin of the controller 30 all receive low-level comparison signals, it is determined that the number of the external battery pack is one.

[0161] If the first pin of the controller 30 receives a high-level comparison signal, the second pin of the controller 30 receives a high-level comparison signal, and the third pin of the controller 30 to the Nth pin of the controller 30 all receive low-level comparison signals, it is determined that the number of external battery packs is two.

[0162] If the first pin to the Nth pin of the controller 30 all receive high-level comparison signals, it is determined that the number of external battery packs is N.

[0163] For another example, if the values ​​of the reference voltages are increasing in sequence, that is, Vref1<Vref2<...<Vref N, and when the voltage at the first input terminal of the comparison circuit is greater than the voltage at the second input terminal thereof, the comparison circuit outputs a high-level comparison signal.

[0164] If the controller 30 receives N high-level comparison signals, it determines that no external battery pack is connected.

[0165] If the first pin to the N-1th pin of the controller 30 all receive high-level comparison signals and the Nth pin of the controller 30 receives a low-level comparison signal, it is determined that the number of the external battery pack is one.

[0166] If the first pin to the Nth pin of the controller 30 all receive low-level comparison signals, it is determined that the number of external battery packs is N.

[0167] For another example, if the reference voltage value is decreasing in sequence, that is, Vref N <Vref N-1 <...<Vref1, and when the voltage at the first input terminal of the comparison circuit is greater than the voltage at the second input terminal thereof, the comparison circuit outputs a high-level comparison signal.

[0168] If the controller 30 receives N high-level comparison signals, it determines that no external battery pack is connected.

[0169] If the first pin of the controller 30 receives a low-level comparison signal, and the second pin to the Nth pin of the controller 30 all receive high-level comparison signals, it is determined that the number of the external battery pack is one.

[0170] If the first pin to the Nth pin of the controller 30 all receive low-level comparison signals, it is determined that the number of external battery packs is N.

[0171] In some embodiments, the controller 30 can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a single-chip microcomputer, an ARM (Acorn RiASC Machine) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. Furthermore, the controller 30 can also be any conventional processor, controller, microcontroller, or state machine. The controller 30 can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP, and / or any other such configuration. The controller 30 can also be a battery management unit for the host computer.

[0172] See also Figure 5 , Figure 5 This is a circuit structure diagram of a quantity recognition circuit provided by an embodiment of the present application, such as Figure 5 As shown, the comparison circuit 21 in the quantity identification circuit 20 includes a comparator, a first voltage-dividing resistor, and a second voltage-dividing resistor, wherein the first end of the first voltage-dividing resistor is electrically connected to the first end of the second voltage-dividing resistor and the second input end of the comparator, respectively, the second end of the first voltage-dividing resistor is used to access the third power supply VCC, and the second end of the second voltage-dividing resistor is grounded GND. The first voltage-dividing resistor and the second voltage-dividing resistor divide the third power supply VCC to obtain a reference voltage, the first input end of the comparator is used to access the second voltage-dividing signal, and the second input end of the comparator is used to access the corresponding reference voltage.

[0173] like Figure 5 As shown, the number of comparison circuits is N, the number of first voltage-dividing resistors is N, the number of second voltage-dividing resistors is N, and the first comparison circuit includes a comparator U1, a first voltage-dividing resistor R 11 And the second voltage divider resistor R 21 The second comparison circuit includes a comparator U2, a first voltage divider resistor R 12 And the second voltage divider resistor R 22 The third comparison circuit includes a comparator U3, a first voltage divider resistor R 13 And the second voltage divider resistor R 23 , and so on, the Nth comparison circuit includes comparator U N , the first voltage divider resistor R 1N And the second voltage divider resistor R 2N .

[0174] Furthermore, the first voltage divider resistor R 11 With the second voltage divider resistor R 21 Divide the third power supply VCC to obtain the first reference voltage Vref1, that is, Vref1=VCC×R 21 / (R 11 +R 21 ), the first voltage divider resistor R 12 With the second voltage divider resistor R 22 Divide the third power supply VCC to obtain the second reference voltage Vref2, that is, Vref2=VCC×R 22 / (R 12 +R 22 ), the first voltage divider resistor R 13 With the second voltage divider resistor R 23 Divide the third power supply VCC to obtain the third reference voltage Vref3, that is, Vref3=VCC×R 23 / (R 13 +R 23 ), and so on, the first voltage divider resistor R 1N With the second voltage divider resistor R 2NDivide the third power supply VCC to obtain a third reference voltage Vref N , that is, Vref N =VCC×R 2N / (R 1N +R 2N ).

[0175] If the reference voltage increases in sequence, that is, Vref1 <Vref2<...<Vref N , Vref1=VCC×R 21 / (R 11 +R 21 ) <Vref2=VCC×R 22 / (R 12 +R 22 )<... <Vref N =VCC×R 2N / (R 1N +R 2N ), then R 21 / (R 11 +R 21 ) <R 22 / (R 12 +R 22 )<... <R 2N / (R 1N +R 2N ), at the same time, the second power supply VDD is greater than the maximum value of the reference voltage, then VDD>Vref N =VCC×R 2N / (R 1N +R 2N ), that is, VDD>VCC×R 2N / (R 1N +R 2N ).

[0176] If the reference voltage value is decreasing in sequence, that is, Vref N <Vref N-1 <... <Vref1,Vref N =VCC×R 2N / (R 1N +R 2N ) <Vref N-1 =VCC×R 2(N-1) / (R 1(N-1) +R 2(N-1) )<... <Vref1=VCC×R 21 / (R 11 +R 21 ), then R 2N / (R 1N +R 2N)<R 2(N-1) / (R 1(N-1) +R 2(N-1) )<...<R 21 / (R 11 +R 21 ),simultaneously, when the voltage of the second power supply VDD is greater than the maximum value in the reference voltages, then VDD > Vref1 = VCC × R 21 / (R 11 +R 21 ), that is, VDD > VCC × R 21 / (R 11 +R 21 ). [[ID= / / ID=26]]

[0177] Thus, by configuring the ratio relationship of the first voltage-dividing resistor and the second voltage-dividing resistor in each comparison circuit, the voltages of the reference voltages can be made to satisfy the constraint conditions of increasing or decreasing in sequence. [[ID=2 / / ID=29]]

[0178] When i external battery packs are incorporated into the host, the i matching resistors are connected in parallel and then connected to the second terminal of the second reference resistor R 01 , and a second voltage-dividing signal is generated at the second terminal of the second reference resistor R 01 . The resistance values of each matching resistor are the same. If the resistance value of each matching resistor is R, the voltage of the second voltage-dividing signal is:

[0179] Vin<00… i = R / (R + i × R 01 [[ID=4 / / ID=41]]), (13)

[0180] where Vin i is the voltage of the second voltage-dividing signal when i external battery packs are incorporated into the host, R is the resistance value of the matching resistor, R 01 is the resistance value of the second reference resistor R 01 , and i is a positive integer from 0 to N.

[0181] In order to identify the number of external battery packs by comparing the level states of the signals, when each external battery pack is connected, the level states of the N comparison signals need to change bit by bit. If the voltages of the reference voltages are gradually increasing, the voltage of the second voltage-dividing signal and the voltages of each reference voltage need to satisfy the following first constraint condition:

[0182] When i = 0, Vin0 = VDD > Vref N , when i is a positive integer from 1 to N - 1, Vref N-i <Vin i < Vref N-i+1 , when i = N, Vin N < Vref1. Where VDD is the voltage of the second power supply, Vin iVref is the voltage of the second divided voltage signal when i external battery packs are connected to the host. i is the voltage of the i-th reference voltage.

[0183] Correspondingly, the first voltage-dividing resistor and the second voltage-dividing resistor satisfy the third constraint:

[0184] If i is 0, Vin0=VDD>VCC×R 2N / (R 1N +R 2N ), if i is a positive integer from 1 to N-1, VCC×R 2(N-i) / (R 1(N-i) +R 2(N-i) )<Vin i <VCC×R 2(N-i+1) / (R 1(N-i+1) +R 2(N-i+1) ), if i is N, Vin N <VCC×R 21 / (R 11 +R 21 ).

[0185] Among them, VCC is the voltage of the third power supply, R 1i is the first voltage divider resistor in the i-th comparison circuit, R 2i is the second voltage-dividing resistor in the i-th comparison circuit.

[0186] Similarly, if the reference voltage is gradually decreasing, the voltage of the second divided voltage signal and the voltage of each reference voltage must satisfy the second constraint:

[0187] If i is 0, Vin0=VDD>Vref1, if i is a positive integer from 1 to N-1, Vref i+1 <Vin i <Vref i , if i is N, Vin N <Vref N .

[0188] Correspondingly, the first voltage-dividing resistor and the second voltage-dividing resistor satisfy the fourth constraint:

[0189] If i is 0, Vin0=VDD>VCC×R 21 / (R 11 +R 21 ), if i is a positive integer from 1 to N-1, VCC×R 2(i+1) / (R 1(i+1) +R 2(i+1) )<Vin i <VCC×R 2i / (R 1i +R2i ), if i is N, Vin N <VCC×R 2N / (R 1N +R 2N ).

[0190] Therefore, by designing the size relationship between the first voltage-dividing resistor and the second voltage-dividing resistor, the voltages of the N reference voltages satisfy a relationship of increasing or decreasing in sequence, and the voltage of each second voltage-dividing signal satisfies the above-mentioned first constraint relationship or third constraint relationship.

[0191] In some embodiments, as Figure 5 As shown, the inverting input terminal of the comparator is the first input terminal of the comparator, and the non-inverting input terminal of the comparator is the second input terminal of the comparator.

[0192] The comparison circuit further includes a pull-up resistor R', which is connected in series between the third power supply VCC and the output terminal of the comparator. The pull-up resistor R' is an open-drain pull-up resistor of the comparator, which enables the comparator to output a high level.

[0193] Taking N as 4 as an example, the working principle of the quantity recognition circuit 20 is described. Figure 6 As shown, the inverting input terminal of the comparator is the first input terminal of the comparator, the non-inverting input terminal of the comparator is the second input terminal of the comparator, and the comparison signal output by the first comparator is Vout1, the comparison signal output by the second comparator is Vout2, the comparison signal output by the third comparator is Vout3, and the comparison signal output by the fourth comparator is Vout4.

[0194] If the reference voltage increases gradually, that is, Vref1 < Vref2 < Vref3 < Vref4, and Vref1 = 2.7V, Vref2 = 3.5V, Vref3 = 5.0V, Vref4 = 9.0V, VDD = 12.0V.

[0195] When no external battery pack is connected to the host, i is 0, the voltage of the second divided voltage signal is Vin0=VDD, VDD>Vref4, and the four comparators all output low-level comparison signals.

[0196] When an external battery pack is connected to the host, i is 1, and the voltage of the second divided voltage signal is Vin1=R / (R+1×R 01 )=6.0V, Vref3<Vin1<Vref4, then the comparison signal Vout1 output by the first comparator U1 is a high-level signal, and the other comparators output low-level signals.

[0197] When two external battery packs are connected to the host, i is 2, and the voltage of the second divided voltage signal is Vin2=R / (R+2×R 01 )=4.0V, Vref2<Vin2<Vref3, then the comparison signals Vout1 and Vout2 output by the first comparator U1 and the second comparator U2 are both high-level signals, and the other comparators output low-level signals.

[0198] When three external battery packs are connected to the host, i is 3, and the voltage of the second divided voltage signal is Vin3=R / (R+3×R 01 )=3.0V, Vref1<Vin3<Vref2, then the comparison signals Vout1, Vout2 and Vout3 output by the first comparator U1, the second comparator U2 and the third comparator U3 are all high-level signals, and the fourth comparator outputs a low-level signal.

[0199] When four external battery packs are connected to the host, i is 4, and the voltage of the second divided voltage signal is Vin4=R / (R+4×R 01 )=2.4V, Vin4<Vref1, then the comparison signals Vout1, Vout2, Vout3 and Vout4 output by the four comparators are all high-level signals.

[0200] The determination relationship comparison table of the quantity recognition circuit 20 can be shown in Table 1:

[0201] Table 1 Comparison table of determination relationships of quantity recognition circuit 20

[0202]

[0203] Thus, the controller 30 can identify the number of external battery packs according to the level states of the four comparison signals.

[0204] In some embodiments, if the reference voltage is gradually decreasing, ie, Vref4 < Vref3 < Vref2 < Vref1 , and Vref4 = 2.7V, Vref3 = 3.5V, Vref2 = 5.0V, Vref1 = 9.0V, VDD = 12.0V.

[0205] The working principle of the quantity recognition circuit 20 is similar to that of the above embodiment and will not be described in detail here. The determination relationship comparison table of the quantity recognition circuit 20 can be shown in Table 2:

[0206] Table 2 Comparison table of determination relationships of quantity recognition circuit 20

[0207]

[0208] Thus, the controller 30 can determine the number of external battery packs according to the level status of the four comparison signals. The controller 30 recognizes that the number of external battery packs is 4, and then infers the coding resistor R from the voltage of the four first voltage-divided signals. 1B The measured resistance value R m1 , coding resistor R 2B The measured resistance value R m2 , coding resistor R 3B The measured resistance value R m3 And the coding resistor R 4B The measured resistance value R m4 , and then determine the measured resistance value R from the mapping relationship set m1 The target ideal resistance that matches the target ideal resistance is obtained, and the type parameter of the first external battery pack corresponding to the target ideal resistance is determined from the mapping relationship set. m2 The target ideal resistance that matches the target ideal resistance is obtained, and the type parameter of the second external battery pack corresponding to the target ideal resistance is determined from the mapping relationship set. m3 The target ideal resistance that matches the target ideal resistance is obtained, and the type parameter of the third external battery pack corresponding to the target ideal resistance is determined from the mapping relationship set. m4 The target ideal resistance that matches the battery pack is determined, and the type parameters of the fourth external battery pack corresponding to the target ideal resistance are obtained.

[0209] See also Figure 7 , Figure 7 : is a circuit structure diagram of a quantity identification circuit 20 provided in an embodiment of the present application, Figure 7 and Figure 5 The difference is that the non-inverting input terminal of the comparator is the first input terminal of the comparator, and the inverting input terminal of the comparator is the second input terminal of the comparator. Figure 7 The constraints that each resistor and reference voltage must satisfy are Figure 4 The same, no longer repeated here.

[0210] Taking N as 4 as an example, the working principle of the quantity recognition circuit 20 is described. Figure 8 As shown, the non-inverting input terminal of the comparator is the first input terminal of the comparator, the inverting input terminal of the comparator is the second input terminal of the comparator, and the comparison signal output by the first comparator is Vout1, the comparison signal output by the second comparator is Vout2, the comparison signal output by the third comparator is Vout3, and the comparison signal output by the fourth comparator is Vout4.

[0211] If the reference voltage increases gradually, that is, Vref1 < Vref2 < Vref3 < Vref4, and Vref1 = 2.7V, Vref2 = 3.5V, Vref3 = 5.0V, Vref4 = 9.0V, VDD = 12.0V.

[0212] When no external battery pack is connected to the host, i is 0, the voltage of the second divided voltage signal is Vin0=VDD, VDD>Vref4, and the four comparators all output high-level comparison signals.

[0213] When an external battery pack is connected to the host, i is 1, and the voltage of the second divided voltage signal is Vin1=R / (R+1×R 01 )=6.0V, Vref3<Vin1<Vref4, then the comparison signals Vout1, Vout2 and Vout3 output by the first comparator U1, the second comparator U2 and the third comparator U3 are all high-level signals, and the fourth comparator U4 outputs a low-level signal.

[0214] When two external battery packs are connected to the host, i is 2, and the voltage of the second divided voltage signal is Vin2=R / (R+2×R 01 )=4.0V, Vref2<Vin2<Vref3, then the comparison signals Vout1 and Vout2 output by the first comparator U1 and the second comparator U2 are both high-level signals, and the other comparators output low-level signals.

[0215] When three external battery packs are connected to the host, i is 3, and the voltage of the second divided voltage signal is Vin3=R / (R+3×R 01 )=3.0V, Vref1<Vin3<Vref2, then the comparison signal Vout1 output by the first comparator U1 is a high-level signal, and the other comparators output low-level signals.

[0216] When four external battery packs are connected to the host, i is 4, and the voltage of the second divided voltage signal is Vin4=R / (R+4×R 01 )=2.4V, Vin4<Vref1, then the four comparators all output low-level signals.

[0217] Thus, the controller 30 can identify the number of external battery packs according to the level states of the four comparators.

[0218] The determination relationship comparison table of the quantity recognition circuit 20 can be shown in Table 3:

[0219] Table 3 Comparison table of determination relationships of quantity recognition circuit 20

[0220]

[0221] In some embodiments, if the reference voltage is gradually decreasing, ie, Vref4 < Vref3 < Vref2 < Vref1 , and Vref4 = 2.7V, Vref3 = 3.5V, Vref2 = 5.0V, Vref1 = 9.0V, VDD = 12.0V.

[0222] The working principle of the quantity recognition circuit 20 is similar to that of the above embodiment and will not be described in detail here. The determination relationship comparison table of the quantity recognition circuit 20 can be shown in Table 4:

[0223] Table 4 Comparison table of determination relationships of quantity recognition circuit 20

[0224]

[0225] Therefore, the controller 30 can determine the number of external battery packs according to the level states of the four comparison signals.

[0226] The controller 30 recognizes that the number of external battery packs is 4, and then infers the coding resistor R from the voltage of the four first divided voltage signals. 1B The measured resistance value R m1 , coding resistor R 2B The measured resistance value R m2 , coding resistor R 3B The measured resistance value R m3 And the coding resistor R 4B The measured resistance value R m4 , and then determine the measured resistance value R from the mapping relationship set m1 The target ideal resistance that matches the target ideal resistance is obtained, and the type parameter of the first external battery pack corresponding to the target ideal resistance is determined from the mapping relationship set. m2 The target ideal resistance that matches the target ideal resistance is obtained, and the type parameter of the second external battery pack corresponding to the target ideal resistance is determined from the mapping relationship set. m3 The target ideal resistance that matches the target ideal resistance is obtained, and the type parameter of the third external battery pack corresponding to the target ideal resistance is determined from the mapping relationship set. m4 The target ideal resistance that matches the battery pack is determined, and the type parameters of the fourth external battery pack corresponding to the target ideal resistance are obtained.

[0227] In summary, different numbers of external battery packs incorporated into the host correspond to different levels of the first identification signal. The controller identifies the number of external battery packs based on the different first identification signals. Different types of external battery packs incorporated into the host correspond to different voltages of the second identification signal. The controller identifies the type parameters of the external battery pack based on the voltage of the second identification signal. Thus, the pack identification circuit can identify the number and type of external battery packs incorporated into the host.

[0228] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Based on the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of the present application as described above. For the sake of simplicity, they are not provided in detail. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A packet identification circuit, characterized in that: Applied to an energy storage system, the energy storage system includes a host and i external battery packs for connecting to the host, the parallel pack identification circuit includes: a quantity identification circuit, a type identification circuit and a controller; The quantity identification circuit is connected to the controller, and is configured to generate a first identification signal in response to the external battery pack being incorporated into the host, wherein a level of the first identification signal is related to the number of the external battery packs; The type identification circuit is connected to the controller, and is configured to generate a second identification signal in response to the external battery pack being incorporated into the host, wherein a voltage of the second identification signal is related to the type of the external battery pack; The controller is configured to calculate the number of the external battery packs according to the level state of the first identification signal, and identify the type parameter of the external battery pack according to the voltage of the second identification signal; The type identification circuit includes: a first reference resistor disposed in the host, wherein a first end of the first reference resistor is connected to a first power supply; Coding resistors allocated to the external battery packs, each coding resistor corresponding to one of the external battery packs, wherein different types of external battery packs correspond to different resistance values ​​of the coding resistors, and a first end of the coding resistor is grounded; A non-sensing control circuit allocated to the external battery pack, each of the non-sensing control circuits corresponding to the external battery pack; The sensorless control circuit includes a microcontroller, an RFID switch, and an RFID tag. The RFID tag is configured to receive and identify RF signals transmitted by the controller. The microcontroller connects a control terminal of the RFID switch to the RFID tag. A first terminal of the RFID switch is connected to the second terminal of a coding resistor belonging to the same external battery pack. When the external battery pack is incorporated into the host device, the second terminal of the RFID switch is connected to the second terminal of the first reference resistor. The controller is further configured to sequentially transmit radio frequency signals of different frequencies, and each radio frequency identification tag within the external battery pack is configured to respond to the radio frequency signals. Each microcontroller is configured to control the radio frequency identification switch to close when the radio frequency identification tag connected thereto responds to the radio frequency signal, thereby establishing a connection between the second end of the encoding resistor, which belongs to the same external battery pack as the radio frequency identification switch, and the second end of the first reference resistor.

2. The packet identification circuit according to claim 1, characterized in that: During the process of sequentially closing the i-th RFID switches, when the i-th RFID switch is closed, the connection between the i-th coding resistor and the first reference resistor after being connected in parallel forms the i-th voltage dividing node, and the i-th first voltage dividing signal is generated at each of the i-th voltage dividing nodes; when the number of the first voltage dividing signals reaches the number of the external battery packs, the controller is further configured to stop sending the RF signal, and the i-th first voltage dividing signals form the second identification signal.

3. The packet identification circuit according to claim 2, characterized in that: The controller is configured to identify a type parameter of the external battery pack according to a voltage of the second identification signal, including: When i is 1, the measured resistance value of the first coding resistor is determined based on the first voltage division signal, the voltage division principle, and the first reference resistor; When i is greater than 1, a first parallel resistor is determined based on the (i-1)th first voltage division signal, the voltage division principle, and the first reference resistor, wherein the first parallel resistor is the total resistance of the first (i-1) coding resistors connected in parallel; Determine a second parallel resistor based on the i-th first voltage division signal, the voltage division principle, and the first reference resistor, wherein the second parallel resistor is the total resistance of the first i coding resistors connected in parallel; Determining a measured resistance value of the i-th coding resistor based on the first parallel resistor, the second parallel resistor, and a parallel connection principle; A resistance value search is performed in the mapping relationship set to obtain a target ideal resistance and a target type parameter, wherein the target ideal resistance is an ideal resistance that matches the numerical value of the measured resistance value, the target type parameter is the type parameter of the i-th external battery pack, and the mapping relationship set includes an ideal resistor that matches the coded resistor and a type parameter of the external battery pack that corresponds one-to-one to the ideal resistor.

4. The packet identification circuit according to claim 1, characterized in that: Each of the microcontrollers is further configured to control the RFID switch to open after a preset time period after the RFID switch is closed, so that the second end of the encoding resistor, which belongs to the same external battery pack as the RFID switch, is disconnected from the second end of the first reference resistor; In the process of sequentially closing the i-th RFID switches, when the i-th RFID switch is closed, the connection between the i-th coding resistor and the first reference resistor forms the i-th voltage dividing node, and the i-th first voltage dividing signal is generated at the i-th voltage dividing node; when the number of the first voltage dividing signals reaches the number of the external battery packs, the controller is used to stop sending the RF signal, and the i-th first voltage dividing signals form the second identification signal.

5. The packet identification circuit according to claim 4, characterized in that: The controller is configured to identify a type parameter of the external battery pack according to the number of the external battery packs and the voltage of the second identification signal, including: determining a measured resistance value of the i-th coding resistor based on the i-th first voltage-divided signal, the voltage-dividing principle, and the first reference resistor; A resistance value search is performed in the mapping relationship set to obtain a target ideal resistance and a target type parameter, wherein the target ideal resistance is an ideal resistance that matches the numerical value of the measured resistance value, the target type parameter is the type parameter of the i-th external battery pack, and the mapping relationship set includes an ideal resistor that matches the coded resistor and a type parameter of the external battery pack that corresponds one-to-one to the ideal resistor.

6. The packet identification circuit according to claim 1, characterized in that: The quantity recognition circuit includes: i matching resistors, each of the i matching resistors belongs to one of the i external battery packs and has the same resistance value; a second reference resistor and N comparison circuits, wherein the first end of the second reference resistor is connected to the second power supply. When i external battery packs are incorporated into the host, the i matching resistors are connected in parallel to form a parallel voltage divider module. The first end and the second end of the parallel voltage divider module are respectively connected to the second end of the second reference resistor and the ground. The first end of the parallel voltage divider module obtains a second voltage divided signal related to the second power supply, and the second voltage divided signal is connected to the first input ends of the N comparison circuits. The second input terminal of each comparison circuit is connected to a reference voltage, wherein the values ​​of the N reference voltages are different; The N comparison circuits are configured to output N comparison signals reflecting the number of the external battery packs according to the voltage of the second voltage-divided signal and the N reference voltages, wherein the N comparison signals together constitute the first identification signal; Wherein, i is a positive integer from 0 to N, and N is a positive integer greater than or equal to 1.

7. The packet identification circuit according to claim 6, characterized in that: Each of the comparison circuits includes a first voltage-dividing resistor, a second voltage-dividing resistor, and a comparator; The first end and the second end of the first voltage-dividing resistor are respectively connected to a third power supply and the first end of the second voltage-dividing resistor, the second end of the second voltage-dividing resistor is connected to a ground end, the connection point between the first voltage-dividing resistor and the second voltage-dividing resistor is connected to the second input terminal of the corresponding comparator, the first voltage-dividing resistor and the second voltage-dividing resistor divide the third power supply to obtain the reference voltages, and each of the reference voltages is connected to the second input terminal of the corresponding comparator; The first input terminal of the comparator is used to receive the second voltage-divided signal, and the N comparators are used to output N comparison signals according to the second voltage-divided signal and the N reference voltages.

8. The packet identification circuit according to claim 6, characterized in that: When the values ​​of the N reference voltages increase in sequence, the voltage of the second voltage-divided signal and the N reference voltages satisfy the first constraint condition: If i is 0, Vin0=VDD>Vref N ; If i is a positive integer from 1 to N-1, Vref N-i <Vin i <Vref N-i+1 ; If i is N, Vin N <Vref1; When the values ​​of the N reference voltages decrease in sequence, the voltage of the second voltage-divided signal and the N reference voltages satisfy the second constraint condition: If i is 0, Vin0=VDD>Vref1; If i is a positive integer from 1 to N-1, Vref i+1 <Vin i <Vref i ; If i is N, Vin N <Vref N ; Wherein, VDD is the voltage of the second power supply, Vin i is the voltage of the second divided voltage signal when i external battery packs are incorporated into the host, Vref i is the i-th reference voltage.

9. The packet identification circuit according to any one of claims 1 to 8, characterized in that: The resistance value of the coding resistor is obtained by performing resistance coding allocation based on the analog-to-digital sampling range of the controller, including: Determine the maximum resistance value and the minimum resistance value of the coding resistor based on the analog-to-digital sampling range of the controller; Determining a reference resistance value based on an analog-to-digital sampling range of the controller, a voltage of the first power supply, and a resistance value of the first reference resistor; determining a minimum allowable interval based on the reference resistance value; Based on the minimum allowable interval, dividing the resistance values ​​from the minimum resistance value to the maximum resistance value to obtain a plurality of resistance values ​​of the coding resistors, wherein a difference between the resistance values ​​of two adjacent coding resistors is greater than or equal to the minimum allowable interval; Allocating a plurality of the coding resistors to a plurality of different types of the external battery packs; Wherein, one of the coding resistors may be a single resistor or a plurality of resistors connected in parallel.

10. An energy storage system, characterized in that: The energy storage system includes a host, i external battery packs, and a parallel pack identification circuit as described in any one of claims 1 to 9, wherein each of the external battery packs is connected in parallel with the host, and the parallel pack identification circuit is used to identify the number and type parameters of the external battery packs.

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