Control method for reducing power consumption of power supply and power supply circuit applying method

Abstract

The invention discloses a control method for reducing power consumption of a power supply and a power supply circuit applying the method, and belongs to the technical field of switching power supplies. In order to solve the problems of high standby power consumption and slow dynamic response in the existing scheme, the invention proposes that a 220mu F electrolytic capacitor EC2 is bridged at + 5V and + 12V output ends, dummy load current is reduced through charge transfer during light load, the current is increased to 10K omega from 5K omega by matching with a bleeder resistor, and the static power consumption is reduced by more than 50%; the PWM duty ratio is adjusted in real time by adopting an optical coupled isolator and a PI algorithm, and + 12V ripples are suppressed to be below 500mV; an overcurrent protection mechanism is designed, and the thyristor cuts off overcurrent within 2 ms and executes graded recovery; dynamic load response is optimized, the voltage is rapidly stabilized through EC2 charge release and RC absorption circuits, and the duty ratio adjusting speed reaches five switching periods. The system is compatible with an original power supply framework, standby power consumption is smaller than or equal to 0.5 W, energy efficiency and transient performance are remarkably improved, and the system is suitable for energy-saving transformation of air conditioners and the like.

Description

Technical Field

[0001] The present invention specifically relates to a control method for reducing power consumption of a power supply and a power supply circuit applying this method. Background Art

[0002] With the rapid development of smart home appliances, the market's demand for low power consumption and high efficiency of home appliances such as air conditioners is becoming increasingly urgent. Currently, most of the switching power supplies of air conditioners adopt traditional design schemes. Although the chip schemes have high stability, there are problems such as large standby power consumption, slow dynamic response, and low energy efficiency. For example, in the existing scheme, the discharge resistor is fixed at 5KΩ, resulting in significant redundant power consumption under light load; in addition, the energy conversion efficiency across voltage domains is low, and there is a lack of a fast adjustment mechanism for load mutations. Especially in the scenario where the air conditioner is powered on for a long time, the traditional power supply scheme cannot effectively balance stability and energy-saving requirements, causing energy waste and being difficult to meet the green and low-carbon industry trend. Although attempts have been made to optimize the existing scheme, limited by problems such as fixed circuit structure and single feedback mechanism, it is difficult to achieve significant power consumption reduction without replacing core components. For example, in the existing technology, the discharge resistor is fixed at 5KΩ, resulting in a static power consumption ≥0.6W in the light load mode and a dynamic response time > 20ms. Therefore, there is an urgent need for an innovative solution that is compatible with the existing architecture and reduces power consumption through intelligent control strategies. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, an object of the present invention is to provide a control method for reducing power consumption of a power supply and a power supply circuit applying this method, which can reduce standby power consumption and the actual power used by the switching power supply.

[0004] The present invention also provides a control method for reducing power consumption of a power supply, including the following steps.

[0005] Step S1: Establish a dynamic charge transfer channel between the +5V output terminal and the +12V output terminal, and realize charge sharing across voltage domains by directly connecting a 220μF / 25V second electrolytic capacitor EC2.

[0006] Step S2: Configure a fake load adjustment strategy: increase the original 5KΩ discharge resistor to 10KΩ ± 5% accuracy, and compensate for the load current through the shunt effect of the second electrolytic capacitor EC2.

[0007] Step S3: Construct a dual-loop control including primary feedback and secondary feedback: Primary feedback: Real-time collect the +5V output voltage through an optocoupler isolator U2, and generate a first error signal through a voltage division network of the eighth resistor R8, the ninth resistor R9, and the sixth resistor R6; Secondary feedback: Monitor the ripple voltage amplitude at the +12V output terminal, and trigger duty cycle compensation when it exceeds 500mV.

[0008] Step S4: Implement overcurrent coordinated protection: When it is detected that the output current exceeds 20% of the rated value, the thyristor U4 is triggered to conduct within 2 ms, and at the same time, the PWM control chip U1 reduces the duty cycle to less than 5%.

[0009] Step S5: Execute dynamic load response: When the load changes suddenly, the time constant of the RC absorption circuit composed of the fifth resistor R5 and the third capacitor C3 is adjusted to 200 μs ± 10% accuracy to suppress the oscillation of the output voltage.

[0010] Specifically further, the specific implementation method of the duty cycle compensation in step S3 is as follows: When the +12V ripple voltage exceeds the threshold, the PWM control chip U1 dynamically adjusts the duty cycle according to the following formula: D(n)=D(n - 1)+Kp×ΔV+Ki×∫ΔV dt; where D(n) is the current duty cycle, Kp = 0.05% / mV, Ki = 0.2% / (mV·ms), ΔV is the ripple voltage deviation value, and the values of Kp and Ki are calibrated through experiments. Specifically: Apply a ±1A step load at the +12V output terminal, and adjust Kp and Ki to make the ripple voltage stabilization time ≤ 10 ms. And through multiple step load experiments (±1A perturbation), measure the ripple stabilization time and duty cycle adjustment accuracy during closed-loop debugging, and finally determine the values of Kp and Ki to ensure that the ripple suppression efficiency ≥ 90%.

[0011] Specifically further, after the overcurrent protection is triggered in step S4, a three-stage recovery mechanism is executed.

[0012] The first stage: Cut off the primary winding drive signal within 10 ms after triggering.

[0013] The second stage: Try to restart with a 10% duty cycle after 50 ms.

[0014] The third stage: If overcurrent is detected in three consecutive restarts, enter the permanent lock state.

[0015] Specifically further, the implementation of the dynamic load response in step S5 includes the following situations.

[0016] When the load steps up, the second electrolytic capacitor EC2 is preferentially used to release the stored charge to maintain voltage stability, and at the same time, the PWM control chip U1 linearly increases the duty cycle to the maximum value of 95% within 5 switching cycles.

[0017] When the load steps down, the RC absorption circuit composed of the fifth resistor R5 and the third capacitor C3 absorbs the excess energy, and reduces the duty cycle to 80% of the reference value within 10 switching cycles.

[0018] Specifically further, the operating modes of the dynamic charge transfer channel include: light load mode: when the +5V load current < 100 mA, the second electrolytic capacitor EC2 transfers charge through its low impedance characteristic and bears more than 80% of the dummy load current; heavy load mode: when the +5V load current ≥ 500 mA, the connection of the RC absorption circuit is automatically disconnected by the relay K1.

[0019] The present invention also discloses a power supply circuit applying the above control method for reducing power consumption of a power supply, including the following.

[0020] The main power module includes a bridge rectifier BD1 and a transformer T1; and a PWM control chip U1 connected to the primary side of the transformer.

[0021] The secondary output module includes: +12V branch: rectified by the first diode D1 and then connected in sequence to the fifth resistor R5, the fifth electrolytic capacitor EC5 and the second capacitor C2; +5V branch: rectified and output by the second diode D2 and the first diode D1.

[0022] In the cross-voltage domain coupling module, the positive electrode of the second electrolytic capacitor EC2 is connected to the +12V terminal, and the negative electrode is connected to the +5V terminal to achieve the transfer of charge from the +5V terminal to the +12V terminal in the light load mode, and an RC absorption unit composed of a fifth resistor R5 = 2 kΩ ± 5% accuracy and a third capacitor C3 = 100 nF is connected in parallel; The feedback protection module includes: an optocoupler isolator U2, whose input terminal samples the +5V output voltage through a voltage dividing network composed of the eighth resistor R8, the ninth resistor R9 and the sixth resistor R6; a thyristor U4, whose trigger electrode sets the overcurrent threshold through a voltage dividing circuit of the tenth resistor R10 and the eleventh resistor R11, and the anode of the thyristor U4 is connected to the +12V terminal and the cathode is grounded.

[0023] Specifically further, a fourth electrolytic capacitor EC4 with a capacitance value of 10 μF ± 20% is connected to the frequency control terminal of the PWM control chip U1 to set the switching frequency to 65 kHz ± 5% accuracy; the feedback input terminal of the PWM control chip U1 is connected to the output terminal of the optocoupler isolator U2 through a fifth capacitor C5 = 1 nF.

[0024] Specifically further, a magnetic bead FB1 is connected in series between the first inductor L1 and the +5V terminal, and its impedance characteristic is: the impedance ≥ 100 Ω at a frequency of 100 MHz; a fourth capacitor C4 with a capacitance of 47 nF is reversely connected in parallel between the cathode of the zener diode ZD1 and the +5V terminal.

[0025] Specifically further, the fifth resistor R5 in the RC absorption unit is a metal film resistor with a power tolerance value of 1W; the third capacitor C3 is a multilayer ceramic capacitor of X7R material with a withstand voltage value of 50V. The resistance ratio of the eighth resistor R8 and the ninth resistor R9 in the voltage division network is 1:2, and the adjustable end of the ninth resistor R9 is connected to the positive pole of the light-emitting diode of the optocoupler isolator U2, forming an output voltage fine-tuning mechanism. A double safety isolation structure is provided between the primary and secondary windings of the transformer T1, including: a first safety capacitor CY1 is connected in parallel between the primary ground PGND and the secondary ground SGND, with a capacitance value of 2.2nF ± 10% accuracy; a second safety capacitor CY2 is connected in parallel to the shielding layer pin of the transformer T1, with a capacitance value of 4.7nF ± 10% accuracy.

[0026] The present invention significantly improves the energy efficiency and stability of the power supply system through the following technical means, and the specific beneficial effects are as follows.

[0027] First, through the 220μF second electrolytic capacitor EC2 connected in parallel between the +5V and +12V output terminals, charge cross-domain transfer is achieved in the light load mode, reducing the false load current demand. The discharge resistor is increased from 5KΩ to 10KΩ ± 5% accuracy, directly reducing the static power consumption by more than 50%.

[0028] Second, an optocoupler isolator U2 and a voltage division network are used to monitor the +5V voltage in real time. Combining PI regulation triggered by the ripple amplitude (Kp = 0.05% / mV, Ki = 0.2% / (mV·ms) calibrated through experiments), the duty cycle is dynamically compensated to ensure that the output voltage accuracy is within ±2%. The specific method is: applying a step load disturbance to the +12V output terminal, and determining the optimal parameter combination through closed-loop debugging to make the ripple suppression efficiency reach more than 90%, achieving dynamic charge sharing to reduce redundant power consumption and achieving multi-level feedback precise control.

[0029] Third, the thyristor U4 and the PWM control chip U1 are linked to cut off the overcurrent and restore it in stages within 2ms to avoid hardware damage; the three-stage restoration mechanism (cut-off - soft start - lock) takes into account both safety and fault tolerance, serving as an overcurrent cooperative protection mechanism.

[0030] Fourth, by adjusting the time constant of the RC absorption circuit to 200μs ± 10% accuracy and combining the charge release / absorption function of EC2, when the load changes stepwise (such as the duty cycle rising to 95% within 5 cycles), the oscillation amplitude of the output voltage is reduced by more than 60%, improving the transient performance of the system and achieving fast dynamic load response.

[0031] V. Retain the core architectures of the original transformer T1 and the PWM control chip U1, and achieve energy efficiency optimization with low transformation costs by adding new modules (such as cross-domain coupling and RC absorption units). At the same time, the first safety capacitor CY1 and the second safety capacitor CY2 ensure EMI and isolation safety, enhancing compatibility and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and / or additional aspects and advantages of the present invention will become apparent and be readily understood from the description of the embodiments in conjunction with the following drawings.

[0033] Figure 1 is the circuit diagram of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] Embodiments of the present invention will be described in detail below. Examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

[0035] Reference will be made below to Figure 1 describe a control method for reducing power consumption of a power supply according to an embodiment of the present invention, including the following steps.

[0036] Step S1: Establish a dynamic charge transfer channel between the +5V output terminal and the +12V output terminal, and achieve charge sharing across voltage domains by directly connecting the 220 μF / 25V second electrolytic capacitor EC2.

[0037] Step S2: Configure a fake load adjustment strategy: increase the original 5KΩ discharge resistor to 10KΩ ± 5% accuracy, and compensate for the load current through the shunt effect of the second electrolytic capacitor EC2.

[0038] Step S3: Construct a dual-loop control including primary feedback and secondary feedback: Primary feedback: Real-time collect the +5V output voltage through the opto-isolator U2, and generate a first error signal through the voltage division network of the eighth resistor R8, the ninth resistor R9, and the sixth resistor R6; Secondary feedback: Monitor the ripple voltage amplitude at the +12V output terminal, and trigger duty cycle compensation when it exceeds 500 mV.

[0039] Step S4: Implement overcurrent cooperative protection: When it is detected that the output current exceeds 20% of the rated value, the thyristor U4 is triggered to conduct within 2 ms, and at the same time, the PWM control chip U1 reduces the duty cycle to less than 5%.

[0040] Step S5: Execute dynamic load response: When the load changes suddenly, adjust the time constant of the RC absorption circuit (the fifth resistor R5 and the third capacitor C3) to 200 μs ± 10% accuracy to suppress the output voltage oscillation.

[0041] Specifically further, the specific implementation method of the duty cycle compensation described in step S3 is as follows: when the +12V ripple voltage exceeds the threshold, the PWM control chip U1 dynamically adjusts the duty cycle according to the following formula: D(n)=D(n - 1)+Kp×ΔV+Ki×∫ΔV dt.

[0042] Where, D(n) is the current duty cycle, Kp = 0.05% / mV, Ki = 0.2% / (mV·ms), ΔV is the ripple voltage deviation value, and the values of Kp and Ki are calibrated through experiments. Specifically: by applying a ±1A step load, adjust Kp and Ki until the ripple stabilization time ≤ 10ms, and finally determine that Kp = 0.05% / mV and Ki = 0.2% / (mV·ms) are the optimal parameter combinations.

[0043] Specifically further, after the overcurrent protection is triggered in step S4, a three - level recovery mechanism is executed.

[0044] The first level: Cut off the primary winding drive signal within 10ms after triggering.

[0045] The second level: Try to restart with a 10% duty cycle after 50ms.

[0046] The third level: If overcurrent is detected during three consecutive restarts, enter the permanent lock - in state.

[0047] Specifically further, the implementation of the dynamic load response described in step S5 includes the following.

[0048] When the load step increases, first release the stored charge through the second electrolytic capacitor EC2 to maintain voltage stability, and at the same time, the PWM control chip U1 linearly increases the duty cycle to the maximum value of 95% within 5 switching cycles.

[0049] When the load step decreases, absorb the excess energy through the RC absorption circuit (the fifth resistor R5 and the third capacitor C3), and reduce the duty cycle to 80% of the reference value within 10 switching cycles.

[0050] The operating modes of the dynamic charge transfer channel include: Light load mode: When the +5V load current < 100 mA, the second electrolytic capacitor EC2 transfers charges through its low impedance characteristic and bears more than 80% of the dummy load current; Heavy load mode: When the +5V load current ≥ 500 mA, the connection of the RC absorption circuit is automatically disconnected by the relay K1. More specifically: When the +5V load current is 80 mA (light load mode), the charge transferred by EC2 is 12 mC, the current of the dummy load resistor drops from 1 mA to 0.4 mA, and the static power consumption drops from 0.6 W to 0.25 W; When the +5V load current is 600 mA (heavy load mode), the RC absorption circuit is automatically disconnected, EC2 stops charge transfer, and the main power path efficiency is increased to 92%.

[0051] A power supply circuit applying the above control method for reducing power consumption of a power supply includes the following.

[0052] The main power module includes a bridge rectifier BD1 and a transformer T1; and a PWM control chip U1 connected to the primary side of the transformer.

[0053] The secondary output module includes: +12V branch: After being rectified by the first diode D1, it is sequentially connected to the fifth resistor R5, the fifth electrolytic capacitor EC5, and the second capacitor C2; +5V branch: Rectified and output by the second diode D2 and the first diode D1.

[0054] In the cross-voltage domain coupling module, the positive electrode of the second electrolytic capacitor EC2 is connected to the +12V terminal, and the negative electrode is connected to the +5V terminal to achieve the transfer of charges from the +5V terminal to the +12V terminal in the light load mode, and an RC absorption unit composed of a fifth resistor R5 = 2 kΩ ± 5% accuracy and a third capacitor C3 = 100 nF is connected in parallel.

[0055] The feedback protection module includes: an optocoupler isolator U2, whose input terminal samples the +5V output voltage through a voltage dividing network composed of the eighth resistor R8, the ninth resistor R9, and the sixth resistor R6; a thyristor U4, whose trigger electrode sets the overcurrent threshold through a voltage dividing circuit of the tenth resistor R10 and the eleventh resistor R11, and the anode of the thyristor U4 is connected to the +12V terminal and the cathode is grounded.

[0056] Specifically further, a fourth electrolytic capacitor EC4 with a capacitance value of 10 μF ± 20% is connected to the frequency control terminal of the PWM control chip U1 for setting the switching frequency to 65 kHz ± 5% accuracy; the feedback input terminal of the PWM control chip U1 is connected to the output terminal of the optocoupler isolator U2 through a fifth capacitor C5 = 1 nF.

[0057] Specifically further, a bead FB1 is connected in series between the first inductor L1 and the +5V terminal, and its impedance characteristic is: the impedance ≥ 100Ω at a frequency of 100MHz; a fourth capacitor C4 with a capacitance value of 47nF is reversely connected in parallel between the cathode of the voltage stabilizing diode ZD1 and the +5V terminal. The bead FB1 is an electronic component mainly used to suppress high-frequency noise and spike interference on signal lines and power lines, and has the ability to absorb electrostatic pulses.

[0058] Specifically further, the fifth resistor R5 in the RC absorption unit is a metal film resistor with a power tolerance value of 1W; the third capacitor C3 is a multilayer ceramic capacitor of X7R material with a withstand voltage value of 50V. The resistance ratio of the eighth resistor R8 and the ninth resistor R9 in the voltage dividing network is 1:2, and the adjustable end of the ninth resistor R9 is connected to the anode of the light-emitting diode of the optocoupler isolator U2 to form an output voltage fine-tuning mechanism. A double safety isolation structure is provided between the primary and secondary windings of the transformer T1, including: a first safety capacitor CY1 is connected across the primary ground PGND and the secondary ground SGND with a capacitance value of 2.2nF ± 10% accuracy; a second safety capacitor CY2 is connected in parallel to the shield layer lead of the transformer T1 with a capacitance value of 4.7nF ± 10% accuracy.

[0059] The specific connections in the circuit are further described as follows: bridge rectifier group BD1, PWM control chip U1, transformer T1, optocoupler U2, +5V terminal, +12V terminal, and second electrolytic capacitor EC2. The bridge rectifier group BD1 is connected to the PWM control chip U1. The PWM control chip U1 is connected to the primary coil of the transformer T1. The secondary coil of the transformer T1 is respectively connected to the +5V terminal and the +12V terminal. The +5V terminal and the +12V terminal are connected through the second electrolytic capacitor EC2. The input terminal of the optocoupler U2 is connected to the secondary coil of the transformer T1, and the output terminal of the optocoupler U2 is connected to the PWM control chip U1.Pin 7 of the transformer T1 is connected to the +5V terminal through the fourth diode D4, and the +5V terminal and the fourth diode D4 are connected through the first inductor L1. The secondary coil of the transformer T1 is connected to the +12V terminal through the first diode D1 and the second diode D2. The +12V terminal is connected to the fifth resistor R5, and the fifth electrolytic capacitor EC5 and the second capacitor C2 are connected in parallel to the fifth resistor R5 in sequence. The primary coil and the secondary coil of the transformer T1 are connected with the first safety capacitor CY1 and the second safety capacitor CY2. The common terminal between the first safety capacitor CY1 and pin 4 of the transformer T1 is connected to the signal ground SGND. The second safety capacitor CY2 is connected to pin 6 of the transformer T1. A third electrolytic capacitor EC3 is connected between the fourth diode D4 and the first inductor L1, and the third electrolytic capacitor EC3 is connected to the second safety capacitor CY2. One end of the first inductor L1 is connected to the ninth resistor R9, and the other end of the first inductor L1 is connected to the eighth resistor R8. The other end of the ninth resistor R9 is connected to pin 1 of the optocoupler U2, and the eighth resistor R8 is connected to pin 2 of the optocoupler U2. A sixth resistor R6 is connected between pin 1 and pin 2 of the optocoupler U2. A fifth capacitor C5 and a tenth resistor R10 are also connected between the eighth resistor R8 and pin 2 of the optocoupler U2. The common terminal between the sixth resistor R6 and the fifth capacitor C5 is connected to the thyristor U4. The G pole of the thyristor U4 is connected to the common terminal between the tenth resistor R10 and the eighth resistor R8. The K pole of the thyristor U4 is connected to the eleventh resistor R11, and the other end of the eleventh resistor R11 is connected to the common terminal between the tenth resistor R10 and the eighth resistor R8. The second electrolytic capacitor EC2 is connected to the third capacitor C3, and the third capacitor C3 is connected in parallel with the fourth electrolytic capacitor EC4. The 3rd and 4th pins of the PWM control chip U1 are connected in parallel with the zener diode ZD1. Pin 4 of the filter inductor FL1 is connected to pin 3 of the bridge rectifier BD1, and pin 3 of the filter inductor FL1 is connected to pin 4 of the bridge rectifier BD1. A thermistor NTC is connected between pin 3 and pin 4 of the bridge rectifier BD1. The 4th and 3rd pins of the filter inductor FL1 are connected in parallel with the second high-voltage film capacitor CX2, and the 1st and 2nd pins of the filter inductor FL1 are connected in parallel with the first high-voltage film capacitor CX1. Among them, the seventh resistor R7, the thirteenth resistor R13 and the twelfth resistor R12 are connected in series. One end of the seventh resistor R7 is connected to the common terminal between pin 3 of the filter inductor FL1 and the thermistor NTC. One end of the twelfth resistor R12 is connected to the common terminal between pin 4 of the filter inductor FL1 and pin 3 of the bridge rectifier BD1. A varistor ZNR1 is connected in parallel with the first high-voltage film capacitor CX1. It also includes that pin 1 of the filter inductor FL is connected to the N terminal, and pin 2 of the filter inductor FL is connected to the fuse FS1, and the fuse FS1 is connected to the L terminal. Among them, the parameters of the thermistor NT (such as model MF72, resistance value 10KΩ±5% at 25°C), and its function is to limit the inrush current.In addition, the capacitance of the first safety capacitor CY1 and the second safety capacitor CY2 is 1000 pF, the error range is ±20%, and the working voltage is 400V AC (model JNA09F102ML02N). According to IEC standards, the safety distance needs to be large enough to avoid arcing during high-voltage power-on. Furthermore, the thermistor NTC is of model MF72, with a resistance value of 10KΩ ± 5% at 25°C, which is used to suppress the inrush current at startup.

[0060] The core of the present invention lies in realizing the low power consumption and high stability of the power supply system through strategies such as dynamic charge transfer, multi-stage feedback control, overcurrent cooperative protection, and dynamic load response, combined with an optimized circuit structure design. The following details its working principle from the technical details level: I. Dynamic charge transfer channel and fake load optimization mechanism. Cross-voltage domain charge sharing: A second electrolytic capacitor EC2 with a capacitance of 220μF / 25V is connected across the +5V output terminal and the +12V output terminal to construct a dynamic charge transfer channel.

[0061] Light load mode: When the +5V load current < 100mA, EC2 transfers the excess charge at the +5V terminal to the +12V terminal through its low impedance characteristic, assuming more than 80% of the fake load current. At this time, the discharge resistance is increased from the original 5KΩ to 10KΩ ± 5% accuracy, and the static power consumption is reduced by more than 50%. Heavy load mode: When the +5V load current ≥ 500mA, the RC absorption circuit composed of the fifth resistor R5 (2kΩ ± 5% accuracy) and the third capacitor C3 (100nF) is automatically disconnected to avoid energy loss caused by EC2 shunting and ensure the efficient output of the main power path.

[0062] Charge allocation and voltage balance: The capacitance value of the second electrolytic capacitor EC2 is 220μF and the withstand voltage is 25V. Through optimized design, it can achieve dynamic balance of charges under different load conditions and suppress voltage fluctuations across the voltage domain.

[0063] II. The precise regulation of the double-loop control including primary feedback and secondary feedback is as follows.

[0064] Primary feedback control: Voltage sampling and error generation: Through the input terminal of the optocoupler isolator U2, a voltage dividing network composed of the eighth resistor R8 (the lower end in the resistance ratio of 1:2), the ninth resistor R9 (the adjustable end connected to the positive electrode of the light-emitting diode of U2), and the sixth resistor R6 is used to collect the +5V output voltage in real time. The voltage signal generated after voltage division is compared with the reference value to form the first error signal. The optocoupler isolator U2 can adopt PC817 or an equivalent model, and its current transfer ratio (CTR) is 50% - 600%, ensuring the linearity and isolation performance of signal transmission.

[0065] Optocoupler transmission and duty cycle adjustment: The error signal is transmitted to the feedback input of the PWM control chip U1 through the optocoupler U2 (filtered by the fifth capacitor C5 = 1nF), driving the PWM control chip U1 to dynamically adjust the duty cycle of the primary winding drive signal to ensure that the +5V output accuracy is controlled within ±2%.

[0066] Secondary feedback control: ripple monitoring and PI compensation: real-time monitoring of the ripple voltage amplitude at the +12V output end. When it exceeds the threshold of 500mV, the proportional-integral (PI) algorithm is triggered to adjust the duty cycle.

[0067] The specific formula is: D(n)=D(n−1)+Kp×ΔV+Ki×∫ΔVdt, where Kp=0.05% / mV, Ki=0.2% / (mV⋅ms), and ΔV is the ripple voltage deviation value. This algorithm quickly suppresses high-frequency ripples to ensure the stability of the +12V output voltage.

[0068] 3. The overcurrent coordinated protection and graded recovery mechanism are as follows.

[0069] Overcurrent detection and fast response: When the output current exceeds the rated value by 20%, the voltage divider circuit composed of the tenth resistor R10 and the eleventh resistor R11 triggers the thyristor U4 to turn on (the anode is connected to the +12V terminal and the cathode is grounded), forcing the duty cycle of the PWM control chip U1 to drop below 5% within 2ms, cutting off the energy transmission path.

[0070] Three-level recovery strategy: Level 1 cutoff: Within 10ms after triggering, the PWM control chip U1 completely cuts off the primary winding drive signal to avoid continuous overcurrent causing device damage. Level 2 soft start: After 50ms, the PWM control chip U1 restarts with a 10% duty cycle to gradually restore energy supply. Level 3 lock: If overcurrent is detected after three consecutive restarts, it enters a permanent lock state and requires an external reset to ensure system safety.

[0071] 4. The transient optimization of dynamic load response is as follows.

[0072] Load sudden increase response: Charge release: When the load step increases, the second electrolytic capacitor EC2 releases the stored charge (capacity 220μF) first to maintain the +5V and +12V terminal voltages stable.

[0073] Rapid increase in duty cycle: The PWM control chip U1 linearly increases the duty cycle from the current value to the maximum value of 95% within 5 switching cycles (the switching frequency is set to 65kHz±5% accuracy by the fourth electrolytic capacitor EC4=10μF±20%), quickly replenishing the energy gap.

[0074] Load Sudden Drop Response: Energy Absorption: Excess energy is absorbed through an RC absorption circuit (the fifth resistor R5 is a 1W metal film resistor, and the third capacitor C3 is a multilayer ceramic capacitor of X7R material with a withstand voltage of 50V). The time constant is strictly controlled with an accuracy of 200μs ± 10%. Duty Cycle Gradual Decrease: The PWM control chip U1 reduces the duty cycle to 80% of the reference value within 10 switching cycles to avoid overshoot and oscillation of the output voltage, and the oscillation amplitude is reduced by more than 60%.

[0075] V. The collaborative design of the circuit modules is as follows.

[0076] Main Power Module: The bridge rectifier BD1 converts the AC input into DC, and is isolated and stepped down by the transformer T1 (a first safety capacitor CY1 = 2.2nF ± 10% accuracy and a second safety capacitor CY2 = 4.7nF ± 10% accuracy are provided between the primary and secondary windings). The PWM control chip U1 (the frequency is set by EC4) drives the primary side of the transformer to adjust the energy transfer efficiency.

[0077] Secondary Output Module: +12V Branch: After being rectified by the first diode D1, it outputs a stable voltage through the fifth resistor R5 for current limiting, the fifth electrolytic capacitor EC5 (for energy storage), and the second capacitor C2 (for high-frequency filtering). +5V Branch: After being rectified by the second diode D2 and the first diode D1.

[0078] The bridge is filtered by the first inductor L1 (series magnetic bead FB1, impedance ≥ 100Ω at 100MHz), and the voltage is clamped by the zener diode ZD1 (paralleled with the fourth capacitor C4 = 47nF).

[0079] VI. The cross-domain coupling and feedback protection module is as follows.

[0080] The cross-voltage-domain charge transfer is jointly completed by EC2 and the RC absorption unit (the fifth resistor R5 / the third capacitor C3) to achieve dynamic energy distribution. The optocoupler U2 and the thyristor U4 form a dual protection network, combined with a voltage division resistor network (the eighth resistor R8 / the ninth resistor R9 / the sixth resistor R6, the tenth resistor R10 / the eleventh resistor R11) to ensure accurate monitoring of voltage and current. Among them, the resistance value of the tenth resistor R10 is 1kΩ ± 1%, the resistance value of the eleventh resistor R11 is 470Ω ± 1%, the voltage division ratio is 1kΩ / (1kΩ + 470Ω) = 0.68, and the overcurrent threshold is set to 120% of the rated current.

[0081] VII. The safety regulations and EMI design are as follows.

[0082] Safety isolation: A first safety capacitor CY1 (connected across the primary ground PGND and the secondary ground SGND) and a second safety capacitor CY2 (connected in parallel to the shield pin) are provided between the primary and secondary windings of transformer T1, effectively suppressing common-mode noise and meeting the requirements of electrical isolation. EMI suppression: The magnetic bead FB1 (connected in series to the +5V branch) and the third capacitor C3 made of X7R material (with low ESR characteristics) work together to reduce high-frequency interference and ensure the electromagnetic compatibility of the system.

[0083] Through the above technical solutions, on the basis of retaining the original power supply architecture (such as transformer T1 and PWM control chip U1), the present invention realizes standby power consumption ≤ 0.5W (measured value) and shortens the dynamic response time to 5 switching cycles (about 77 μs) by adding dynamic charge transfer, multi-stage feedback control and intelligent protection mechanisms, while maintaining the output voltage accuracy at ±2% and the system reliability, significantly improving the energy efficiency ratio and meeting the low-carbon requirements of green household appliances. In addition, the comparison of measured data in light load / heavy load modes: First, the mode is light load (80 mA), the static power consumption is 0.25W, the ripple voltage is ≤ 500 mV, and the response time is 77 μs. Second, the mode is heavy load (600 mA), the static power consumption is 0.5W, the ripple voltage is ≤ 100 mV, and the response time is 100 μs.

[0084] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the claims and their equivalents.

Claims

1. A control method for reducing power consumption, characterized in that: The following steps are involved: Step S1: establishing a dynamic charge transfer channel between the +5V output terminal and the +12V output terminal, and directly connecting the 220μF / 25V second electrolytic capacitor EC2 to realize cross-voltage domain charge sharing; Step S2: configuring a dummy load regulation strategy: increasing the original 5KΩ discharge resistance to 10KΩ±5% accuracy, and compensating the load current through the shunt effect of the second electrolytic capacitor EC2; Step S3: construct a dual-loop control including primary feedback and secondary feedback: primary feedback: collect +5V output voltage in real time through the optocoupler isolator U2, and generate a first error signal through the eighth resistor R8, the ninth resistor R9 and the sixth resistor R6 voltage divider network; secondary feedback: monitor the ripple voltage amplitude of the +12V output end, and trigger duty cycle compensation when it exceeds 500mV; Step S4: Implement over-current coordinated protection: When it is detected that the output current exceeds the rated value by 20%, the thyristor U4 is triggered to turn on within 2ms, and the PWM control chip U1 reduces the duty cycle to below 5%; Step S5: Execute dynamic load response: When the load suddenly changes, the output voltage oscillation is suppressed by adjusting the time constant of the RC absorption circuit to an accuracy of 200μs±10%.

2. A control method for reducing power consumption according to claim 1, characterized in that: The specific implementation method of the duty cycle compensation in step S3 is: when the +12V ripple voltage exceeds the threshold, the PWM control chip U1 dynamically adjusts the duty cycle according to the following formula: D(n)=D(n-1)+Kp×ΔV+Ki×∫ΔV dt; Wherein, D(n) is the current duty cycle, Kp=0.05% / mV, Ki=0.2% / (mV·ms), ΔV is the ripple voltage deviation value, and the values ​​of Kp and Ki are calibrated through experiments, specifically: applying a ±1A step load at the +12V output end, and adjusting Kp and Ki so that the ripple voltage stabilization time is ≤10ms.

3. The control method for reducing power consumption according to claim 1, characterized in that: After the overcurrent protection in step S4 is triggered, a three-level recovery mechanism is executed: First stage: cut off the primary winding drive signal within 10ms after triggering; Level 2: Try to restart with a 10% duty cycle after 50ms; Level 3: If overcurrent is detected during three consecutive restarts, the system enters a permanent lock state.

4. The control method for reducing power consumption according to claim 1, characterized in that: The implementation of the dynamic load response in step S5 includes: When the load step increases, the second electrolytic capacitor EC2 is used to release the stored charge to maintain voltage stability. At the same time, the PWM control chip linearly increases the duty cycle to a maximum value of 95% within 5 switching cycles. When the load step decreases, the RC absorption circuit composed of the fifth resistor R5 and the third capacitor C3 absorbs the excess energy and reduces the duty cycle to 80% of the reference value within 10 switching cycles.

5. The control method for reducing power consumption according to claim 1, characterized in that: The working modes of the dynamic charge transfer channel include: light load mode: when the +5V load current is less than 100mA, the second electrolytic capacitor EC2 transfers charge through its low impedance characteristics and bears more than 80% of the false load current; heavy load mode: when the +5V load current is ≥500mA, the connection of the RC absorption circuit is automatically disconnected through the relay K1.

6. A power supply circuit using a control method for reducing power consumption as claimed in any one of claims 1 to 5, characterized in that: include: The main power module includes a bridge rectifier BD1 and a transformer T1, and a PWM control chip U1 connected to the primary side of the transformer; The secondary output module includes: a +12V branch: rectified by the first diode D1 and connected in sequence to the fifth resistor R5, the fifth electrolytic capacitor EC5 and the second capacitor C2; a +5V branch: rectified and output by the second diode D2 and the first diode D1; In the cross-voltage domain coupling module, the positive electrode of the second electrolytic capacitor EC2 is connected to the +12V terminal, and the negative electrode is connected to the +5V terminal to realize the transfer of charge from the +5V terminal to the +12V terminal in the light load mode, and an RC absorption unit consisting of a fifth resistor R5 with a resistance value of 2kΩ±5% accuracy and a third capacitor C3 with a capacitance value of 100nF is connected in parallel; The feedback protection module includes: an optocoupler isolator U2, whose input end samples the +5V output voltage through a voltage divider network composed of an eighth resistor R8, a ninth resistor R9 and a sixth resistor R6; a thyristor U4, whose trigger electrode sets the overcurrent threshold through a voltage divider circuit composed of a tenth resistor R10 and an eleventh resistor R11, and the anode of the thyristor U4 is connected to the +12V terminal and the cathode is grounded.

7. The power supply circuit according to claim 6, characterized in that: The frequency control end of the PWM control chip U1 is connected to a fourth electrolytic capacitor EC4 with a capacitance of 10μF±20%, which is used to set the switching frequency to 65kHz±5% accuracy; the feedback input end of the PWM control chip U1 is connected to the output end of the optocoupler isolator U2 through a fifth capacitor C5=1nF.

8. The power supply circuit according to claim 6, characterized in that: A magnetic bead FB1 is connected in series between the first inductor L1 and the +5V terminal, and its impedance characteristic is: impedance ≥ 100Ω at a frequency of 100MHz; a fourth capacitor C4 = 47nF is connected in reverse parallel between the cathode of the voltage zener diode ZD1 and the +5V terminal.

9. The power supply circuit according to claim 6, characterized in that: The fifth resistor R5 in the RC absorption unit is a metal film resistor with a power tolerance of 1W; the third capacitor C3 is a multilayer ceramic capacitor made of X7R material with a withstand voltage of 50V, and the resistance ratio of the eighth resistor R8 and the ninth resistor R9 in the voltage divider network is 1:2, and the adjustable end of the ninth resistor R9 is connected to the positive electrode of the light-emitting diode of the optocoupler isolator U2, forming an output voltage fine-tuning mechanism.

10. The power supply circuit according to claim 6, characterized in that: A double safety isolation structure is provided between the primary and secondary windings of the transformer T1, including: a first safety capacitor CY1 is connected between the primary ground PGND and the secondary ground SGND, with a capacitance of 2.2nF±10% accuracy; a second safety capacitor CY2 is connected in parallel to the shielding layer pin of the transformer T1, with a capacitance of 4.7nF±10% accuracy.

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